1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2010 Exar Corp.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explanation of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_max_pkts: This parameter defines maximum number of packets can be
42 * aggregated as a single large packet
43 * napi: This parameter used to enable/disable NAPI (polling Rx)
44 * Possible values '1' for enable and '0' for disable. Default is '1'
45 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
46 * Possible values '1' for enable , '0' for disable.
47 * Default is '2' - which means disable in promisc mode
48 * and enable in non-promiscuous mode.
49 * multiq: This parameter used to enable/disable MULTIQUEUE support.
50 * Possible values '1' for enable and '0' for disable. Default is '0'
51 ************************************************************************/
53 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
55 #include <linux/module.h>
56 #include <linux/types.h>
57 #include <linux/errno.h>
58 #include <linux/ioport.h>
59 #include <linux/pci.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/kernel.h>
62 #include <linux/netdevice.h>
63 #include <linux/etherdevice.h>
64 #include <linux/mdio.h>
65 #include <linux/skbuff.h>
66 #include <linux/init.h>
67 #include <linux/delay.h>
68 #include <linux/stddef.h>
69 #include <linux/ioctl.h>
70 #include <linux/timex.h>
71 #include <linux/ethtool.h>
72 #include <linux/workqueue.h>
73 #include <linux/if_vlan.h>
75 #include <linux/tcp.h>
76 #include <linux/uaccess.h>
78 #include <linux/io-64-nonatomic-lo-hi.h>
79 #include <linux/slab.h>
80 #include <linux/prefetch.h>
82 #include <net/checksum.h>
84 #include <asm/div64.h>
89 #include "s2io-regs.h"
91 #define DRV_VERSION "2.0.26.28"
93 /* S2io Driver name & version. */
94 static const char s2io_driver_name[] = "Neterion";
95 static const char s2io_driver_version[] = DRV_VERSION;
97 static const int rxd_size[2] = {32, 48};
98 static const int rxd_count[2] = {127, 85};
100 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
104 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
105 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
111 * Cards with following subsystem_id have a link state indication
112 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
113 * macro below identifies these cards given the subsystem_id.
115 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
116 (dev_type == XFRAME_I_DEVICE) ? \
117 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
118 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
120 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
121 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
123 static inline int is_s2io_card_up(const struct s2io_nic *sp)
125 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
128 /* Ethtool related variables and Macros. */
129 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
130 "Register test\t(offline)",
131 "Eeprom test\t(offline)",
132 "Link test\t(online)",
133 "RLDRAM test\t(offline)",
134 "BIST Test\t(offline)"
137 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
139 {"tmac_data_octets"},
143 {"tmac_pause_ctrl_frms"},
147 {"tmac_any_err_frms"},
148 {"tmac_ttl_less_fb_octets"},
149 {"tmac_vld_ip_octets"},
157 {"rmac_data_octets"},
158 {"rmac_fcs_err_frms"},
160 {"rmac_vld_mcst_frms"},
161 {"rmac_vld_bcst_frms"},
162 {"rmac_in_rng_len_err_frms"},
163 {"rmac_out_rng_len_err_frms"},
165 {"rmac_pause_ctrl_frms"},
166 {"rmac_unsup_ctrl_frms"},
168 {"rmac_accepted_ucst_frms"},
169 {"rmac_accepted_nucst_frms"},
170 {"rmac_discarded_frms"},
171 {"rmac_drop_events"},
172 {"rmac_ttl_less_fb_octets"},
174 {"rmac_usized_frms"},
175 {"rmac_osized_frms"},
177 {"rmac_jabber_frms"},
178 {"rmac_ttl_64_frms"},
179 {"rmac_ttl_65_127_frms"},
180 {"rmac_ttl_128_255_frms"},
181 {"rmac_ttl_256_511_frms"},
182 {"rmac_ttl_512_1023_frms"},
183 {"rmac_ttl_1024_1518_frms"},
191 {"rmac_err_drp_udp"},
192 {"rmac_xgmii_err_sym"},
210 {"rmac_xgmii_data_err_cnt"},
211 {"rmac_xgmii_ctrl_err_cnt"},
212 {"rmac_accepted_ip"},
216 {"new_rd_req_rtry_cnt"},
218 {"wr_rtry_rd_ack_cnt"},
221 {"new_wr_req_rtry_cnt"},
224 {"rd_rtry_wr_ack_cnt"},
234 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
235 {"rmac_ttl_1519_4095_frms"},
236 {"rmac_ttl_4096_8191_frms"},
237 {"rmac_ttl_8192_max_frms"},
238 {"rmac_ttl_gt_max_frms"},
239 {"rmac_osized_alt_frms"},
240 {"rmac_jabber_alt_frms"},
241 {"rmac_gt_max_alt_frms"},
243 {"rmac_len_discard"},
244 {"rmac_fcs_discard"},
247 {"rmac_red_discard"},
248 {"rmac_rts_discard"},
249 {"rmac_ingm_full_discard"},
253 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
254 {"\n DRIVER STATISTICS"},
255 {"single_bit_ecc_errs"},
256 {"double_bit_ecc_errs"},
269 {"alarm_transceiver_temp_high"},
270 {"alarm_transceiver_temp_low"},
271 {"alarm_laser_bias_current_high"},
272 {"alarm_laser_bias_current_low"},
273 {"alarm_laser_output_power_high"},
274 {"alarm_laser_output_power_low"},
275 {"warn_transceiver_temp_high"},
276 {"warn_transceiver_temp_low"},
277 {"warn_laser_bias_current_high"},
278 {"warn_laser_bias_current_low"},
279 {"warn_laser_output_power_high"},
280 {"warn_laser_output_power_low"},
281 {"lro_aggregated_pkts"},
282 {"lro_flush_both_count"},
283 {"lro_out_of_sequence_pkts"},
284 {"lro_flush_due_to_max_pkts"},
285 {"lro_avg_aggr_pkts"},
286 {"mem_alloc_fail_cnt"},
287 {"pci_map_fail_cnt"},
288 {"watchdog_timer_cnt"},
295 {"tx_tcode_buf_abort_cnt"},
296 {"tx_tcode_desc_abort_cnt"},
297 {"tx_tcode_parity_err_cnt"},
298 {"tx_tcode_link_loss_cnt"},
299 {"tx_tcode_list_proc_err_cnt"},
300 {"rx_tcode_parity_err_cnt"},
301 {"rx_tcode_abort_cnt"},
302 {"rx_tcode_parity_abort_cnt"},
303 {"rx_tcode_rda_fail_cnt"},
304 {"rx_tcode_unkn_prot_cnt"},
305 {"rx_tcode_fcs_err_cnt"},
306 {"rx_tcode_buf_size_err_cnt"},
307 {"rx_tcode_rxd_corrupt_cnt"},
308 {"rx_tcode_unkn_err_cnt"},
316 {"mac_tmac_err_cnt"},
317 {"mac_rmac_err_cnt"},
318 {"xgxs_txgxs_err_cnt"},
319 {"xgxs_rxgxs_err_cnt"},
321 {"prc_pcix_err_cnt"},
328 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
329 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
330 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
332 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
333 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
335 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
336 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
338 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
339 #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
341 /* copy mac addr to def_mac_addr array */
342 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
344 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
345 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
346 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
347 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
348 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
349 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
353 * Constants to be programmed into the Xena's registers, to configure
358 static const u64 herc_act_dtx_cfg[] = {
360 0x8000051536750000ULL, 0x80000515367500E0ULL,
362 0x8000051536750004ULL, 0x80000515367500E4ULL,
364 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
366 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
368 0x801205150D440000ULL, 0x801205150D4400E0ULL,
370 0x801205150D440004ULL, 0x801205150D4400E4ULL,
372 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
374 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
379 static const u64 xena_dtx_cfg[] = {
381 0x8000051500000000ULL, 0x80000515000000E0ULL,
383 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
385 0x8001051500000000ULL, 0x80010515000000E0ULL,
387 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
389 0x8002051500000000ULL, 0x80020515000000E0ULL,
391 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
396 * Constants for Fixing the MacAddress problem seen mostly on
399 static const u64 fix_mac[] = {
400 0x0060000000000000ULL, 0x0060600000000000ULL,
401 0x0040600000000000ULL, 0x0000600000000000ULL,
402 0x0020600000000000ULL, 0x0060600000000000ULL,
403 0x0020600000000000ULL, 0x0060600000000000ULL,
404 0x0020600000000000ULL, 0x0060600000000000ULL,
405 0x0020600000000000ULL, 0x0060600000000000ULL,
406 0x0020600000000000ULL, 0x0060600000000000ULL,
407 0x0020600000000000ULL, 0x0060600000000000ULL,
408 0x0020600000000000ULL, 0x0060600000000000ULL,
409 0x0020600000000000ULL, 0x0060600000000000ULL,
410 0x0020600000000000ULL, 0x0060600000000000ULL,
411 0x0020600000000000ULL, 0x0060600000000000ULL,
412 0x0020600000000000ULL, 0x0000600000000000ULL,
413 0x0040600000000000ULL, 0x0060600000000000ULL,
417 MODULE_LICENSE("GPL");
418 MODULE_VERSION(DRV_VERSION);
421 /* Module Loadable parameters. */
422 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
423 S2IO_PARM_INT(rx_ring_num, 1);
424 S2IO_PARM_INT(multiq, 0);
425 S2IO_PARM_INT(rx_ring_mode, 1);
426 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
427 S2IO_PARM_INT(rmac_pause_time, 0x100);
428 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
429 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
430 S2IO_PARM_INT(shared_splits, 0);
431 S2IO_PARM_INT(tmac_util_period, 5);
432 S2IO_PARM_INT(rmac_util_period, 5);
433 S2IO_PARM_INT(l3l4hdr_size, 128);
434 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
435 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
436 /* Frequency of Rx desc syncs expressed as power of 2 */
437 S2IO_PARM_INT(rxsync_frequency, 3);
438 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
439 S2IO_PARM_INT(intr_type, 2);
440 /* Large receive offload feature */
442 /* Max pkts to be aggregated by LRO at one time. If not specified,
443 * aggregation happens until we hit max IP pkt size(64K)
445 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
446 S2IO_PARM_INT(indicate_max_pkts, 0);
448 S2IO_PARM_INT(napi, 1);
449 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
451 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
452 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
453 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
454 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
455 static unsigned int rts_frm_len[MAX_RX_RINGS] =
456 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
458 module_param_array(tx_fifo_len, uint, NULL, 0);
459 module_param_array(rx_ring_sz, uint, NULL, 0);
460 module_param_array(rts_frm_len, uint, NULL, 0);
464 * This table lists all the devices that this driver supports.
466 static const struct pci_device_id s2io_tbl[] = {
467 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
468 PCI_ANY_ID, PCI_ANY_ID},
469 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
470 PCI_ANY_ID, PCI_ANY_ID},
471 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
472 PCI_ANY_ID, PCI_ANY_ID},
473 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
474 PCI_ANY_ID, PCI_ANY_ID},
478 MODULE_DEVICE_TABLE(pci, s2io_tbl);
480 static const struct pci_error_handlers s2io_err_handler = {
481 .error_detected = s2io_io_error_detected,
482 .slot_reset = s2io_io_slot_reset,
483 .resume = s2io_io_resume,
486 static struct pci_driver s2io_driver = {
488 .id_table = s2io_tbl,
489 .probe = s2io_init_nic,
490 .remove = s2io_rem_nic,
491 .err_handler = &s2io_err_handler,
494 /* A simplifier macro used both by init and free shared_mem Fns(). */
495 #define TXD_MEM_PAGE_CNT(len, per_each) DIV_ROUND_UP(len, per_each)
497 /* netqueue manipulation helper functions */
498 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
500 if (!sp->config.multiq) {
503 for (i = 0; i < sp->config.tx_fifo_num; i++)
504 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
506 netif_tx_stop_all_queues(sp->dev);
509 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
511 if (!sp->config.multiq)
512 sp->mac_control.fifos[fifo_no].queue_state =
515 netif_tx_stop_all_queues(sp->dev);
518 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
520 if (!sp->config.multiq) {
523 for (i = 0; i < sp->config.tx_fifo_num; i++)
524 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
526 netif_tx_start_all_queues(sp->dev);
529 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
531 if (!sp->config.multiq) {
534 for (i = 0; i < sp->config.tx_fifo_num; i++)
535 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
537 netif_tx_wake_all_queues(sp->dev);
540 static inline void s2io_wake_tx_queue(
541 struct fifo_info *fifo, int cnt, u8 multiq)
545 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
546 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
547 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
548 if (netif_queue_stopped(fifo->dev)) {
549 fifo->queue_state = FIFO_QUEUE_START;
550 netif_wake_queue(fifo->dev);
556 * init_shared_mem - Allocation and Initialization of Memory
557 * @nic: Device private variable.
558 * Description: The function allocates all the memory areas shared
559 * between the NIC and the driver. This includes Tx descriptors,
560 * Rx descriptors and the statistics block.
563 static int init_shared_mem(struct s2io_nic *nic)
566 void *tmp_v_addr, *tmp_v_addr_next;
567 dma_addr_t tmp_p_addr, tmp_p_addr_next;
568 struct RxD_block *pre_rxd_blk = NULL;
570 int lst_size, lst_per_page;
571 struct net_device *dev = nic->dev;
574 struct config_param *config = &nic->config;
575 struct mac_info *mac_control = &nic->mac_control;
576 unsigned long long mem_allocated = 0;
578 /* Allocation and initialization of TXDLs in FIFOs */
580 for (i = 0; i < config->tx_fifo_num; i++) {
581 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
583 size += tx_cfg->fifo_len;
585 if (size > MAX_AVAILABLE_TXDS) {
587 "Too many TxDs requested: %d, max supported: %d\n",
588 size, MAX_AVAILABLE_TXDS);
593 for (i = 0; i < config->tx_fifo_num; i++) {
594 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
596 size = tx_cfg->fifo_len;
598 * Legal values are from 2 to 8192
601 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
602 "Valid lengths are 2 through 8192\n",
608 lst_size = (sizeof(struct TxD) * config->max_txds);
609 lst_per_page = PAGE_SIZE / lst_size;
611 for (i = 0; i < config->tx_fifo_num; i++) {
612 struct fifo_info *fifo = &mac_control->fifos[i];
613 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
614 int fifo_len = tx_cfg->fifo_len;
615 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
617 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
618 if (!fifo->list_info) {
619 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
622 mem_allocated += list_holder_size;
624 for (i = 0; i < config->tx_fifo_num; i++) {
625 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
627 struct fifo_info *fifo = &mac_control->fifos[i];
628 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
630 fifo->tx_curr_put_info.offset = 0;
631 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
632 fifo->tx_curr_get_info.offset = 0;
633 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
636 fifo->max_txds = MAX_SKB_FRAGS + 2;
639 for (j = 0; j < page_num; j++) {
643 tmp_v = dma_alloc_coherent(&nic->pdev->dev, PAGE_SIZE,
647 "dma_alloc_coherent failed for TxDL\n");
650 /* If we got a zero DMA address(can happen on
651 * certain platforms like PPC), reallocate.
652 * Store virtual address of page we don't want,
656 mac_control->zerodma_virt_addr = tmp_v;
658 "%s: Zero DMA address for TxDL. "
659 "Virtual address %p\n",
661 tmp_v = dma_alloc_coherent(&nic->pdev->dev,
666 "dma_alloc_coherent failed for TxDL\n");
669 mem_allocated += PAGE_SIZE;
671 while (k < lst_per_page) {
672 int l = (j * lst_per_page) + k;
673 if (l == tx_cfg->fifo_len)
675 fifo->list_info[l].list_virt_addr =
676 tmp_v + (k * lst_size);
677 fifo->list_info[l].list_phy_addr =
678 tmp_p + (k * lst_size);
684 for (i = 0; i < config->tx_fifo_num; i++) {
685 struct fifo_info *fifo = &mac_control->fifos[i];
686 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
688 size = tx_cfg->fifo_len;
689 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
690 if (!fifo->ufo_in_band_v)
692 mem_allocated += (size * sizeof(u64));
695 /* Allocation and initialization of RXDs in Rings */
697 for (i = 0; i < config->rx_ring_num; i++) {
698 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
699 struct ring_info *ring = &mac_control->rings[i];
701 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
702 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
703 "multiple of RxDs per Block\n",
707 size += rx_cfg->num_rxd;
708 ring->block_count = rx_cfg->num_rxd /
709 (rxd_count[nic->rxd_mode] + 1);
710 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
712 if (nic->rxd_mode == RXD_MODE_1)
713 size = (size * (sizeof(struct RxD1)));
715 size = (size * (sizeof(struct RxD3)));
717 for (i = 0; i < config->rx_ring_num; i++) {
718 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
719 struct ring_info *ring = &mac_control->rings[i];
721 ring->rx_curr_get_info.block_index = 0;
722 ring->rx_curr_get_info.offset = 0;
723 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
724 ring->rx_curr_put_info.block_index = 0;
725 ring->rx_curr_put_info.offset = 0;
726 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
730 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
731 /* Allocating all the Rx blocks */
732 for (j = 0; j < blk_cnt; j++) {
733 struct rx_block_info *rx_blocks;
736 rx_blocks = &ring->rx_blocks[j];
737 size = SIZE_OF_BLOCK; /* size is always page size */
738 tmp_v_addr = dma_alloc_coherent(&nic->pdev->dev, size,
739 &tmp_p_addr, GFP_KERNEL);
740 if (tmp_v_addr == NULL) {
742 * In case of failure, free_shared_mem()
743 * is called, which should free any
744 * memory that was alloced till the
747 rx_blocks->block_virt_addr = tmp_v_addr;
750 mem_allocated += size;
752 size = sizeof(struct rxd_info) *
753 rxd_count[nic->rxd_mode];
754 rx_blocks->block_virt_addr = tmp_v_addr;
755 rx_blocks->block_dma_addr = tmp_p_addr;
756 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
757 if (!rx_blocks->rxds)
759 mem_allocated += size;
760 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
761 rx_blocks->rxds[l].virt_addr =
762 rx_blocks->block_virt_addr +
763 (rxd_size[nic->rxd_mode] * l);
764 rx_blocks->rxds[l].dma_addr =
765 rx_blocks->block_dma_addr +
766 (rxd_size[nic->rxd_mode] * l);
769 /* Interlinking all Rx Blocks */
770 for (j = 0; j < blk_cnt; j++) {
771 int next = (j + 1) % blk_cnt;
772 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
773 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
774 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
775 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
777 pre_rxd_blk = tmp_v_addr;
778 pre_rxd_blk->reserved_2_pNext_RxD_block =
779 (unsigned long)tmp_v_addr_next;
780 pre_rxd_blk->pNext_RxD_Blk_physical =
781 (u64)tmp_p_addr_next;
784 if (nic->rxd_mode == RXD_MODE_3B) {
786 * Allocation of Storages for buffer addresses in 2BUFF mode
787 * and the buffers as well.
789 for (i = 0; i < config->rx_ring_num; i++) {
790 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
791 struct ring_info *ring = &mac_control->rings[i];
793 blk_cnt = rx_cfg->num_rxd /
794 (rxd_count[nic->rxd_mode] + 1);
795 size = sizeof(struct buffAdd *) * blk_cnt;
796 ring->ba = kmalloc(size, GFP_KERNEL);
799 mem_allocated += size;
800 for (j = 0; j < blk_cnt; j++) {
803 size = sizeof(struct buffAdd) *
804 (rxd_count[nic->rxd_mode] + 1);
805 ring->ba[j] = kmalloc(size, GFP_KERNEL);
808 mem_allocated += size;
809 while (k != rxd_count[nic->rxd_mode]) {
810 ba = &ring->ba[j][k];
811 size = BUF0_LEN + ALIGN_SIZE;
812 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
815 mem_allocated += size;
816 tmp = (unsigned long)ba->ba_0_org;
818 tmp &= ~((unsigned long)ALIGN_SIZE);
819 ba->ba_0 = (void *)tmp;
821 size = BUF1_LEN + ALIGN_SIZE;
822 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
825 mem_allocated += size;
826 tmp = (unsigned long)ba->ba_1_org;
828 tmp &= ~((unsigned long)ALIGN_SIZE);
829 ba->ba_1 = (void *)tmp;
836 /* Allocation and initialization of Statistics block */
837 size = sizeof(struct stat_block);
838 mac_control->stats_mem =
839 dma_alloc_coherent(&nic->pdev->dev, size,
840 &mac_control->stats_mem_phy, GFP_KERNEL);
842 if (!mac_control->stats_mem) {
844 * In case of failure, free_shared_mem() is called, which
845 * should free any memory that was alloced till the
850 mem_allocated += size;
851 mac_control->stats_mem_sz = size;
853 tmp_v_addr = mac_control->stats_mem;
854 mac_control->stats_info = tmp_v_addr;
855 memset(tmp_v_addr, 0, size);
856 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
857 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
858 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
863 * free_shared_mem - Free the allocated Memory
864 * @nic: Device private variable.
865 * Description: This function is to free all memory locations allocated by
866 * the init_shared_mem() function and return it to the kernel.
869 static void free_shared_mem(struct s2io_nic *nic)
871 int i, j, blk_cnt, size;
873 dma_addr_t tmp_p_addr;
874 int lst_size, lst_per_page;
875 struct net_device *dev;
877 struct config_param *config;
878 struct mac_info *mac_control;
879 struct stat_block *stats;
880 struct swStat *swstats;
887 config = &nic->config;
888 mac_control = &nic->mac_control;
889 stats = mac_control->stats_info;
890 swstats = &stats->sw_stat;
892 lst_size = sizeof(struct TxD) * config->max_txds;
893 lst_per_page = PAGE_SIZE / lst_size;
895 for (i = 0; i < config->tx_fifo_num; i++) {
896 struct fifo_info *fifo = &mac_control->fifos[i];
897 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
899 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
900 for (j = 0; j < page_num; j++) {
901 int mem_blks = (j * lst_per_page);
902 struct list_info_hold *fli;
904 if (!fifo->list_info)
907 fli = &fifo->list_info[mem_blks];
908 if (!fli->list_virt_addr)
910 dma_free_coherent(&nic->pdev->dev, PAGE_SIZE,
913 swstats->mem_freed += PAGE_SIZE;
915 /* If we got a zero DMA address during allocation,
918 if (mac_control->zerodma_virt_addr) {
919 dma_free_coherent(&nic->pdev->dev, PAGE_SIZE,
920 mac_control->zerodma_virt_addr,
923 "%s: Freeing TxDL with zero DMA address. "
924 "Virtual address %p\n",
925 dev->name, mac_control->zerodma_virt_addr);
926 swstats->mem_freed += PAGE_SIZE;
928 kfree(fifo->list_info);
929 swstats->mem_freed += tx_cfg->fifo_len *
930 sizeof(struct list_info_hold);
933 size = SIZE_OF_BLOCK;
934 for (i = 0; i < config->rx_ring_num; i++) {
935 struct ring_info *ring = &mac_control->rings[i];
937 blk_cnt = ring->block_count;
938 for (j = 0; j < blk_cnt; j++) {
939 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
940 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
941 if (tmp_v_addr == NULL)
943 dma_free_coherent(&nic->pdev->dev, size, tmp_v_addr,
945 swstats->mem_freed += size;
946 kfree(ring->rx_blocks[j].rxds);
947 swstats->mem_freed += sizeof(struct rxd_info) *
948 rxd_count[nic->rxd_mode];
952 if (nic->rxd_mode == RXD_MODE_3B) {
953 /* Freeing buffer storage addresses in 2BUFF mode. */
954 for (i = 0; i < config->rx_ring_num; i++) {
955 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
956 struct ring_info *ring = &mac_control->rings[i];
958 blk_cnt = rx_cfg->num_rxd /
959 (rxd_count[nic->rxd_mode] + 1);
960 for (j = 0; j < blk_cnt; j++) {
964 while (k != rxd_count[nic->rxd_mode]) {
965 struct buffAdd *ba = &ring->ba[j][k];
967 swstats->mem_freed +=
968 BUF0_LEN + ALIGN_SIZE;
970 swstats->mem_freed +=
971 BUF1_LEN + ALIGN_SIZE;
975 swstats->mem_freed += sizeof(struct buffAdd) *
976 (rxd_count[nic->rxd_mode] + 1);
979 swstats->mem_freed += sizeof(struct buffAdd *) *
984 for (i = 0; i < nic->config.tx_fifo_num; i++) {
985 struct fifo_info *fifo = &mac_control->fifos[i];
986 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
988 if (fifo->ufo_in_band_v) {
989 swstats->mem_freed += tx_cfg->fifo_len *
991 kfree(fifo->ufo_in_band_v);
995 if (mac_control->stats_mem) {
996 swstats->mem_freed += mac_control->stats_mem_sz;
997 dma_free_coherent(&nic->pdev->dev, mac_control->stats_mem_sz,
998 mac_control->stats_mem,
999 mac_control->stats_mem_phy);
1004 * s2io_verify_pci_mode -
1007 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1009 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1010 register u64 val64 = 0;
1013 val64 = readq(&bar0->pci_mode);
1014 mode = (u8)GET_PCI_MODE(val64);
1016 if (val64 & PCI_MODE_UNKNOWN_MODE)
1017 return -1; /* Unknown PCI mode */
1021 #define NEC_VENID 0x1033
1022 #define NEC_DEVID 0x0125
1023 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1025 struct pci_dev *tdev = NULL;
1026 for_each_pci_dev(tdev) {
1027 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1028 if (tdev->bus == s2io_pdev->bus->parent) {
1037 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1039 * s2io_print_pci_mode -
1041 static int s2io_print_pci_mode(struct s2io_nic *nic)
1043 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1044 register u64 val64 = 0;
1046 struct config_param *config = &nic->config;
1047 const char *pcimode;
1049 val64 = readq(&bar0->pci_mode);
1050 mode = (u8)GET_PCI_MODE(val64);
1052 if (val64 & PCI_MODE_UNKNOWN_MODE)
1053 return -1; /* Unknown PCI mode */
1055 config->bus_speed = bus_speed[mode];
1057 if (s2io_on_nec_bridge(nic->pdev)) {
1058 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1064 case PCI_MODE_PCI_33:
1065 pcimode = "33MHz PCI bus";
1067 case PCI_MODE_PCI_66:
1068 pcimode = "66MHz PCI bus";
1070 case PCI_MODE_PCIX_M1_66:
1071 pcimode = "66MHz PCIX(M1) bus";
1073 case PCI_MODE_PCIX_M1_100:
1074 pcimode = "100MHz PCIX(M1) bus";
1076 case PCI_MODE_PCIX_M1_133:
1077 pcimode = "133MHz PCIX(M1) bus";
1079 case PCI_MODE_PCIX_M2_66:
1080 pcimode = "133MHz PCIX(M2) bus";
1082 case PCI_MODE_PCIX_M2_100:
1083 pcimode = "200MHz PCIX(M2) bus";
1085 case PCI_MODE_PCIX_M2_133:
1086 pcimode = "266MHz PCIX(M2) bus";
1089 pcimode = "unsupported bus!";
1093 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1094 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1100 * init_tti - Initialization transmit traffic interrupt scheme
1101 * @nic: device private variable
1102 * @link: link status (UP/DOWN) used to enable/disable continuous
1103 * transmit interrupts
1104 * Description: The function configures transmit traffic interrupts
1105 * Return Value: SUCCESS on success and
1109 static int init_tti(struct s2io_nic *nic, int link)
1111 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1112 register u64 val64 = 0;
1114 struct config_param *config = &nic->config;
1116 for (i = 0; i < config->tx_fifo_num; i++) {
1118 * TTI Initialization. Default Tx timer gets us about
1119 * 250 interrupts per sec. Continuous interrupts are enabled
1122 if (nic->device_type == XFRAME_II_DEVICE) {
1123 int count = (nic->config.bus_speed * 125)/2;
1124 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1126 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1128 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1129 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1130 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1131 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1133 if (use_continuous_tx_intrs && (link == LINK_UP))
1134 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1135 writeq(val64, &bar0->tti_data1_mem);
1137 if (nic->config.intr_type == MSI_X) {
1138 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1139 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1140 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1141 TTI_DATA2_MEM_TX_UFC_D(0x300);
1143 if ((nic->config.tx_steering_type ==
1144 TX_DEFAULT_STEERING) &&
1145 (config->tx_fifo_num > 1) &&
1146 (i >= nic->udp_fifo_idx) &&
1147 (i < (nic->udp_fifo_idx +
1148 nic->total_udp_fifos)))
1149 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1150 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1151 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1152 TTI_DATA2_MEM_TX_UFC_D(0x120);
1154 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1155 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1156 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1157 TTI_DATA2_MEM_TX_UFC_D(0x80);
1160 writeq(val64, &bar0->tti_data2_mem);
1162 val64 = TTI_CMD_MEM_WE |
1163 TTI_CMD_MEM_STROBE_NEW_CMD |
1164 TTI_CMD_MEM_OFFSET(i);
1165 writeq(val64, &bar0->tti_command_mem);
1167 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1168 TTI_CMD_MEM_STROBE_NEW_CMD,
1169 S2IO_BIT_RESET) != SUCCESS)
1177 * init_nic - Initialization of hardware
1178 * @nic: device private variable
1179 * Description: The function sequentially configures every block
1180 * of the H/W from their reset values.
1181 * Return Value: SUCCESS on success and
1182 * '-1' on failure (endian settings incorrect).
1185 static int init_nic(struct s2io_nic *nic)
1187 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1188 struct net_device *dev = nic->dev;
1189 register u64 val64 = 0;
1194 unsigned long long mem_share;
1196 struct config_param *config = &nic->config;
1197 struct mac_info *mac_control = &nic->mac_control;
1199 /* to set the swapper controle on the card */
1200 if (s2io_set_swapper(nic)) {
1201 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1206 * Herc requires EOI to be removed from reset before XGXS, so..
1208 if (nic->device_type & XFRAME_II_DEVICE) {
1209 val64 = 0xA500000000ULL;
1210 writeq(val64, &bar0->sw_reset);
1212 val64 = readq(&bar0->sw_reset);
1215 /* Remove XGXS from reset state */
1217 writeq(val64, &bar0->sw_reset);
1219 val64 = readq(&bar0->sw_reset);
1221 /* Ensure that it's safe to access registers by checking
1222 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1224 if (nic->device_type == XFRAME_II_DEVICE) {
1225 for (i = 0; i < 50; i++) {
1226 val64 = readq(&bar0->adapter_status);
1227 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1235 /* Enable Receiving broadcasts */
1236 add = &bar0->mac_cfg;
1237 val64 = readq(&bar0->mac_cfg);
1238 val64 |= MAC_RMAC_BCAST_ENABLE;
1239 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1240 writel((u32)val64, add);
1241 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1242 writel((u32) (val64 >> 32), (add + 4));
1244 /* Read registers in all blocks */
1245 val64 = readq(&bar0->mac_int_mask);
1246 val64 = readq(&bar0->mc_int_mask);
1247 val64 = readq(&bar0->xgxs_int_mask);
1251 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1253 if (nic->device_type & XFRAME_II_DEVICE) {
1254 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1255 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1256 &bar0->dtx_control, UF);
1258 msleep(1); /* Necessary!! */
1262 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1263 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1264 &bar0->dtx_control, UF);
1265 val64 = readq(&bar0->dtx_control);
1270 /* Tx DMA Initialization */
1272 writeq(val64, &bar0->tx_fifo_partition_0);
1273 writeq(val64, &bar0->tx_fifo_partition_1);
1274 writeq(val64, &bar0->tx_fifo_partition_2);
1275 writeq(val64, &bar0->tx_fifo_partition_3);
1277 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1278 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1280 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1281 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1283 if (i == (config->tx_fifo_num - 1)) {
1290 writeq(val64, &bar0->tx_fifo_partition_0);
1295 writeq(val64, &bar0->tx_fifo_partition_1);
1300 writeq(val64, &bar0->tx_fifo_partition_2);
1305 writeq(val64, &bar0->tx_fifo_partition_3);
1316 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1317 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1319 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1320 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1322 val64 = readq(&bar0->tx_fifo_partition_0);
1323 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1324 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1327 * Initialization of Tx_PA_CONFIG register to ignore packet
1328 * integrity checking.
1330 val64 = readq(&bar0->tx_pa_cfg);
1331 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1332 TX_PA_CFG_IGNORE_SNAP_OUI |
1333 TX_PA_CFG_IGNORE_LLC_CTRL |
1334 TX_PA_CFG_IGNORE_L2_ERR;
1335 writeq(val64, &bar0->tx_pa_cfg);
1337 /* Rx DMA initialization. */
1339 for (i = 0; i < config->rx_ring_num; i++) {
1340 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1342 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1344 writeq(val64, &bar0->rx_queue_priority);
1347 * Allocating equal share of memory to all the
1351 if (nic->device_type & XFRAME_II_DEVICE)
1356 for (i = 0; i < config->rx_ring_num; i++) {
1359 mem_share = (mem_size / config->rx_ring_num +
1360 mem_size % config->rx_ring_num);
1361 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1364 mem_share = (mem_size / config->rx_ring_num);
1365 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1368 mem_share = (mem_size / config->rx_ring_num);
1369 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1372 mem_share = (mem_size / config->rx_ring_num);
1373 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1376 mem_share = (mem_size / config->rx_ring_num);
1377 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1380 mem_share = (mem_size / config->rx_ring_num);
1381 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1384 mem_share = (mem_size / config->rx_ring_num);
1385 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1388 mem_share = (mem_size / config->rx_ring_num);
1389 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1393 writeq(val64, &bar0->rx_queue_cfg);
1396 * Filling Tx round robin registers
1397 * as per the number of FIFOs for equal scheduling priority
1399 switch (config->tx_fifo_num) {
1402 writeq(val64, &bar0->tx_w_round_robin_0);
1403 writeq(val64, &bar0->tx_w_round_robin_1);
1404 writeq(val64, &bar0->tx_w_round_robin_2);
1405 writeq(val64, &bar0->tx_w_round_robin_3);
1406 writeq(val64, &bar0->tx_w_round_robin_4);
1409 val64 = 0x0001000100010001ULL;
1410 writeq(val64, &bar0->tx_w_round_robin_0);
1411 writeq(val64, &bar0->tx_w_round_robin_1);
1412 writeq(val64, &bar0->tx_w_round_robin_2);
1413 writeq(val64, &bar0->tx_w_round_robin_3);
1414 val64 = 0x0001000100000000ULL;
1415 writeq(val64, &bar0->tx_w_round_robin_4);
1418 val64 = 0x0001020001020001ULL;
1419 writeq(val64, &bar0->tx_w_round_robin_0);
1420 val64 = 0x0200010200010200ULL;
1421 writeq(val64, &bar0->tx_w_round_robin_1);
1422 val64 = 0x0102000102000102ULL;
1423 writeq(val64, &bar0->tx_w_round_robin_2);
1424 val64 = 0x0001020001020001ULL;
1425 writeq(val64, &bar0->tx_w_round_robin_3);
1426 val64 = 0x0200010200000000ULL;
1427 writeq(val64, &bar0->tx_w_round_robin_4);
1430 val64 = 0x0001020300010203ULL;
1431 writeq(val64, &bar0->tx_w_round_robin_0);
1432 writeq(val64, &bar0->tx_w_round_robin_1);
1433 writeq(val64, &bar0->tx_w_round_robin_2);
1434 writeq(val64, &bar0->tx_w_round_robin_3);
1435 val64 = 0x0001020300000000ULL;
1436 writeq(val64, &bar0->tx_w_round_robin_4);
1439 val64 = 0x0001020304000102ULL;
1440 writeq(val64, &bar0->tx_w_round_robin_0);
1441 val64 = 0x0304000102030400ULL;
1442 writeq(val64, &bar0->tx_w_round_robin_1);
1443 val64 = 0x0102030400010203ULL;
1444 writeq(val64, &bar0->tx_w_round_robin_2);
1445 val64 = 0x0400010203040001ULL;
1446 writeq(val64, &bar0->tx_w_round_robin_3);
1447 val64 = 0x0203040000000000ULL;
1448 writeq(val64, &bar0->tx_w_round_robin_4);
1451 val64 = 0x0001020304050001ULL;
1452 writeq(val64, &bar0->tx_w_round_robin_0);
1453 val64 = 0x0203040500010203ULL;
1454 writeq(val64, &bar0->tx_w_round_robin_1);
1455 val64 = 0x0405000102030405ULL;
1456 writeq(val64, &bar0->tx_w_round_robin_2);
1457 val64 = 0x0001020304050001ULL;
1458 writeq(val64, &bar0->tx_w_round_robin_3);
1459 val64 = 0x0203040500000000ULL;
1460 writeq(val64, &bar0->tx_w_round_robin_4);
1463 val64 = 0x0001020304050600ULL;
1464 writeq(val64, &bar0->tx_w_round_robin_0);
1465 val64 = 0x0102030405060001ULL;
1466 writeq(val64, &bar0->tx_w_round_robin_1);
1467 val64 = 0x0203040506000102ULL;
1468 writeq(val64, &bar0->tx_w_round_robin_2);
1469 val64 = 0x0304050600010203ULL;
1470 writeq(val64, &bar0->tx_w_round_robin_3);
1471 val64 = 0x0405060000000000ULL;
1472 writeq(val64, &bar0->tx_w_round_robin_4);
1475 val64 = 0x0001020304050607ULL;
1476 writeq(val64, &bar0->tx_w_round_robin_0);
1477 writeq(val64, &bar0->tx_w_round_robin_1);
1478 writeq(val64, &bar0->tx_w_round_robin_2);
1479 writeq(val64, &bar0->tx_w_round_robin_3);
1480 val64 = 0x0001020300000000ULL;
1481 writeq(val64, &bar0->tx_w_round_robin_4);
1485 /* Enable all configured Tx FIFO partitions */
1486 val64 = readq(&bar0->tx_fifo_partition_0);
1487 val64 |= (TX_FIFO_PARTITION_EN);
1488 writeq(val64, &bar0->tx_fifo_partition_0);
1490 /* Filling the Rx round robin registers as per the
1491 * number of Rings and steering based on QoS with
1494 switch (config->rx_ring_num) {
1497 writeq(val64, &bar0->rx_w_round_robin_0);
1498 writeq(val64, &bar0->rx_w_round_robin_1);
1499 writeq(val64, &bar0->rx_w_round_robin_2);
1500 writeq(val64, &bar0->rx_w_round_robin_3);
1501 writeq(val64, &bar0->rx_w_round_robin_4);
1503 val64 = 0x8080808080808080ULL;
1504 writeq(val64, &bar0->rts_qos_steering);
1507 val64 = 0x0001000100010001ULL;
1508 writeq(val64, &bar0->rx_w_round_robin_0);
1509 writeq(val64, &bar0->rx_w_round_robin_1);
1510 writeq(val64, &bar0->rx_w_round_robin_2);
1511 writeq(val64, &bar0->rx_w_round_robin_3);
1512 val64 = 0x0001000100000000ULL;
1513 writeq(val64, &bar0->rx_w_round_robin_4);
1515 val64 = 0x8080808040404040ULL;
1516 writeq(val64, &bar0->rts_qos_steering);
1519 val64 = 0x0001020001020001ULL;
1520 writeq(val64, &bar0->rx_w_round_robin_0);
1521 val64 = 0x0200010200010200ULL;
1522 writeq(val64, &bar0->rx_w_round_robin_1);
1523 val64 = 0x0102000102000102ULL;
1524 writeq(val64, &bar0->rx_w_round_robin_2);
1525 val64 = 0x0001020001020001ULL;
1526 writeq(val64, &bar0->rx_w_round_robin_3);
1527 val64 = 0x0200010200000000ULL;
1528 writeq(val64, &bar0->rx_w_round_robin_4);
1530 val64 = 0x8080804040402020ULL;
1531 writeq(val64, &bar0->rts_qos_steering);
1534 val64 = 0x0001020300010203ULL;
1535 writeq(val64, &bar0->rx_w_round_robin_0);
1536 writeq(val64, &bar0->rx_w_round_robin_1);
1537 writeq(val64, &bar0->rx_w_round_robin_2);
1538 writeq(val64, &bar0->rx_w_round_robin_3);
1539 val64 = 0x0001020300000000ULL;
1540 writeq(val64, &bar0->rx_w_round_robin_4);
1542 val64 = 0x8080404020201010ULL;
1543 writeq(val64, &bar0->rts_qos_steering);
1546 val64 = 0x0001020304000102ULL;
1547 writeq(val64, &bar0->rx_w_round_robin_0);
1548 val64 = 0x0304000102030400ULL;
1549 writeq(val64, &bar0->rx_w_round_robin_1);
1550 val64 = 0x0102030400010203ULL;
1551 writeq(val64, &bar0->rx_w_round_robin_2);
1552 val64 = 0x0400010203040001ULL;
1553 writeq(val64, &bar0->rx_w_round_robin_3);
1554 val64 = 0x0203040000000000ULL;
1555 writeq(val64, &bar0->rx_w_round_robin_4);
1557 val64 = 0x8080404020201008ULL;
1558 writeq(val64, &bar0->rts_qos_steering);
1561 val64 = 0x0001020304050001ULL;
1562 writeq(val64, &bar0->rx_w_round_robin_0);
1563 val64 = 0x0203040500010203ULL;
1564 writeq(val64, &bar0->rx_w_round_robin_1);
1565 val64 = 0x0405000102030405ULL;
1566 writeq(val64, &bar0->rx_w_round_robin_2);
1567 val64 = 0x0001020304050001ULL;
1568 writeq(val64, &bar0->rx_w_round_robin_3);
1569 val64 = 0x0203040500000000ULL;
1570 writeq(val64, &bar0->rx_w_round_robin_4);
1572 val64 = 0x8080404020100804ULL;
1573 writeq(val64, &bar0->rts_qos_steering);
1576 val64 = 0x0001020304050600ULL;
1577 writeq(val64, &bar0->rx_w_round_robin_0);
1578 val64 = 0x0102030405060001ULL;
1579 writeq(val64, &bar0->rx_w_round_robin_1);
1580 val64 = 0x0203040506000102ULL;
1581 writeq(val64, &bar0->rx_w_round_robin_2);
1582 val64 = 0x0304050600010203ULL;
1583 writeq(val64, &bar0->rx_w_round_robin_3);
1584 val64 = 0x0405060000000000ULL;
1585 writeq(val64, &bar0->rx_w_round_robin_4);
1587 val64 = 0x8080402010080402ULL;
1588 writeq(val64, &bar0->rts_qos_steering);
1591 val64 = 0x0001020304050607ULL;
1592 writeq(val64, &bar0->rx_w_round_robin_0);
1593 writeq(val64, &bar0->rx_w_round_robin_1);
1594 writeq(val64, &bar0->rx_w_round_robin_2);
1595 writeq(val64, &bar0->rx_w_round_robin_3);
1596 val64 = 0x0001020300000000ULL;
1597 writeq(val64, &bar0->rx_w_round_robin_4);
1599 val64 = 0x8040201008040201ULL;
1600 writeq(val64, &bar0->rts_qos_steering);
1606 for (i = 0; i < 8; i++)
1607 writeq(val64, &bar0->rts_frm_len_n[i]);
1609 /* Set the default rts frame length for the rings configured */
1610 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1611 for (i = 0 ; i < config->rx_ring_num ; i++)
1612 writeq(val64, &bar0->rts_frm_len_n[i]);
1614 /* Set the frame length for the configured rings
1615 * desired by the user
1617 for (i = 0; i < config->rx_ring_num; i++) {
1618 /* If rts_frm_len[i] == 0 then it is assumed that user not
1619 * specified frame length steering.
1620 * If the user provides the frame length then program
1621 * the rts_frm_len register for those values or else
1622 * leave it as it is.
1624 if (rts_frm_len[i] != 0) {
1625 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1626 &bar0->rts_frm_len_n[i]);
1630 /* Disable differentiated services steering logic */
1631 for (i = 0; i < 64; i++) {
1632 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1634 "%s: rts_ds_steer failed on codepoint %d\n",
1640 /* Program statistics memory */
1641 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1643 if (nic->device_type == XFRAME_II_DEVICE) {
1644 val64 = STAT_BC(0x320);
1645 writeq(val64, &bar0->stat_byte_cnt);
1649 * Initializing the sampling rate for the device to calculate the
1650 * bandwidth utilization.
1652 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1653 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1654 writeq(val64, &bar0->mac_link_util);
1657 * Initializing the Transmit and Receive Traffic Interrupt
1661 /* Initialize TTI */
1662 if (SUCCESS != init_tti(nic, nic->last_link_state))
1665 /* RTI Initialization */
1666 if (nic->device_type == XFRAME_II_DEVICE) {
1668 * Programmed to generate Apprx 500 Intrs per
1671 int count = (nic->config.bus_speed * 125)/4;
1672 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1674 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1675 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1676 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1677 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1678 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1680 writeq(val64, &bar0->rti_data1_mem);
1682 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1683 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1684 if (nic->config.intr_type == MSI_X)
1685 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1686 RTI_DATA2_MEM_RX_UFC_D(0x40));
1688 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1689 RTI_DATA2_MEM_RX_UFC_D(0x80));
1690 writeq(val64, &bar0->rti_data2_mem);
1692 for (i = 0; i < config->rx_ring_num; i++) {
1693 val64 = RTI_CMD_MEM_WE |
1694 RTI_CMD_MEM_STROBE_NEW_CMD |
1695 RTI_CMD_MEM_OFFSET(i);
1696 writeq(val64, &bar0->rti_command_mem);
1699 * Once the operation completes, the Strobe bit of the
1700 * command register will be reset. We poll for this
1701 * particular condition. We wait for a maximum of 500ms
1702 * for the operation to complete, if it's not complete
1703 * by then we return error.
1707 val64 = readq(&bar0->rti_command_mem);
1708 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1712 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1722 * Initializing proper values as Pause threshold into all
1723 * the 8 Queues on Rx side.
1725 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1726 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1728 /* Disable RMAC PAD STRIPPING */
1729 add = &bar0->mac_cfg;
1730 val64 = readq(&bar0->mac_cfg);
1731 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1732 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1733 writel((u32) (val64), add);
1734 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1735 writel((u32) (val64 >> 32), (add + 4));
1736 val64 = readq(&bar0->mac_cfg);
1738 /* Enable FCS stripping by adapter */
1739 add = &bar0->mac_cfg;
1740 val64 = readq(&bar0->mac_cfg);
1741 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1742 if (nic->device_type == XFRAME_II_DEVICE)
1743 writeq(val64, &bar0->mac_cfg);
1745 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1746 writel((u32) (val64), add);
1747 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1748 writel((u32) (val64 >> 32), (add + 4));
1752 * Set the time value to be inserted in the pause frame
1753 * generated by xena.
1755 val64 = readq(&bar0->rmac_pause_cfg);
1756 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1757 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1758 writeq(val64, &bar0->rmac_pause_cfg);
1761 * Set the Threshold Limit for Generating the pause frame
1762 * If the amount of data in any Queue exceeds ratio of
1763 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1764 * pause frame is generated
1767 for (i = 0; i < 4; i++) {
1768 val64 |= (((u64)0xFF00 |
1769 nic->mac_control.mc_pause_threshold_q0q3)
1772 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1775 for (i = 0; i < 4; i++) {
1776 val64 |= (((u64)0xFF00 |
1777 nic->mac_control.mc_pause_threshold_q4q7)
1780 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1783 * TxDMA will stop Read request if the number of read split has
1784 * exceeded the limit pointed by shared_splits
1786 val64 = readq(&bar0->pic_control);
1787 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1788 writeq(val64, &bar0->pic_control);
1790 if (nic->config.bus_speed == 266) {
1791 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1792 writeq(0x0, &bar0->read_retry_delay);
1793 writeq(0x0, &bar0->write_retry_delay);
1797 * Programming the Herc to split every write transaction
1798 * that does not start on an ADB to reduce disconnects.
1800 if (nic->device_type == XFRAME_II_DEVICE) {
1801 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1802 MISC_LINK_STABILITY_PRD(3);
1803 writeq(val64, &bar0->misc_control);
1804 val64 = readq(&bar0->pic_control2);
1805 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1806 writeq(val64, &bar0->pic_control2);
1808 if (strstr(nic->product_name, "CX4")) {
1809 val64 = TMAC_AVG_IPG(0x17);
1810 writeq(val64, &bar0->tmac_avg_ipg);
1815 #define LINK_UP_DOWN_INTERRUPT 1
1816 #define MAC_RMAC_ERR_TIMER 2
1818 static int s2io_link_fault_indication(struct s2io_nic *nic)
1820 if (nic->device_type == XFRAME_II_DEVICE)
1821 return LINK_UP_DOWN_INTERRUPT;
1823 return MAC_RMAC_ERR_TIMER;
1827 * do_s2io_write_bits - update alarm bits in alarm register
1828 * @value: alarm bits
1829 * @flag: interrupt status
1830 * @addr: address value
1831 * Description: update alarm bits in alarm register
1835 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1839 temp64 = readq(addr);
1841 if (flag == ENABLE_INTRS)
1842 temp64 &= ~((u64)value);
1844 temp64 |= ((u64)value);
1845 writeq(temp64, addr);
1848 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1850 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1851 register u64 gen_int_mask = 0;
1854 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1855 if (mask & TX_DMA_INTR) {
1856 gen_int_mask |= TXDMA_INT_M;
1858 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1859 TXDMA_PCC_INT | TXDMA_TTI_INT |
1860 TXDMA_LSO_INT | TXDMA_TPA_INT |
1861 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1863 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1864 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1865 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1866 &bar0->pfc_err_mask);
1868 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1869 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1870 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1872 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1873 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1874 PCC_N_SERR | PCC_6_COF_OV_ERR |
1875 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1876 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1878 flag, &bar0->pcc_err_mask);
1880 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1881 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1883 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1884 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1885 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1886 flag, &bar0->lso_err_mask);
1888 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1889 flag, &bar0->tpa_err_mask);
1891 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1894 if (mask & TX_MAC_INTR) {
1895 gen_int_mask |= TXMAC_INT_M;
1896 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1897 &bar0->mac_int_mask);
1898 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1899 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1900 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1901 flag, &bar0->mac_tmac_err_mask);
1904 if (mask & TX_XGXS_INTR) {
1905 gen_int_mask |= TXXGXS_INT_M;
1906 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1907 &bar0->xgxs_int_mask);
1908 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1909 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1910 flag, &bar0->xgxs_txgxs_err_mask);
1913 if (mask & RX_DMA_INTR) {
1914 gen_int_mask |= RXDMA_INT_M;
1915 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1916 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1917 flag, &bar0->rxdma_int_mask);
1918 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1919 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1920 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1921 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1922 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1923 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1924 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1925 &bar0->prc_pcix_err_mask);
1926 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1927 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1928 &bar0->rpa_err_mask);
1929 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1930 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1931 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1932 RDA_FRM_ECC_SG_ERR |
1933 RDA_MISC_ERR|RDA_PCIX_ERR,
1934 flag, &bar0->rda_err_mask);
1935 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1936 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1937 flag, &bar0->rti_err_mask);
1940 if (mask & RX_MAC_INTR) {
1941 gen_int_mask |= RXMAC_INT_M;
1942 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1943 &bar0->mac_int_mask);
1944 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1945 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1946 RMAC_DOUBLE_ECC_ERR);
1947 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
1948 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
1949 do_s2io_write_bits(interruptible,
1950 flag, &bar0->mac_rmac_err_mask);
1953 if (mask & RX_XGXS_INTR) {
1954 gen_int_mask |= RXXGXS_INT_M;
1955 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1956 &bar0->xgxs_int_mask);
1957 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1958 &bar0->xgxs_rxgxs_err_mask);
1961 if (mask & MC_INTR) {
1962 gen_int_mask |= MC_INT_M;
1963 do_s2io_write_bits(MC_INT_MASK_MC_INT,
1964 flag, &bar0->mc_int_mask);
1965 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1966 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1967 &bar0->mc_err_mask);
1969 nic->general_int_mask = gen_int_mask;
1971 /* Remove this line when alarm interrupts are enabled */
1972 nic->general_int_mask = 0;
1976 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1977 * @nic: device private variable,
1978 * @mask: A mask indicating which Intr block must be modified and,
1979 * @flag: A flag indicating whether to enable or disable the Intrs.
1980 * Description: This function will either disable or enable the interrupts
1981 * depending on the flag argument. The mask argument can be used to
1982 * enable/disable any Intr block.
1983 * Return Value: NONE.
1986 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1988 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1989 register u64 temp64 = 0, intr_mask = 0;
1991 intr_mask = nic->general_int_mask;
1993 /* Top level interrupt classification */
1994 /* PIC Interrupts */
1995 if (mask & TX_PIC_INTR) {
1996 /* Enable PIC Intrs in the general intr mask register */
1997 intr_mask |= TXPIC_INT_M;
1998 if (flag == ENABLE_INTRS) {
2000 * If Hercules adapter enable GPIO otherwise
2001 * disable all PCIX, Flash, MDIO, IIC and GPIO
2002 * interrupts for now.
2005 if (s2io_link_fault_indication(nic) ==
2006 LINK_UP_DOWN_INTERRUPT) {
2007 do_s2io_write_bits(PIC_INT_GPIO, flag,
2008 &bar0->pic_int_mask);
2009 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2010 &bar0->gpio_int_mask);
2012 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2013 } else if (flag == DISABLE_INTRS) {
2015 * Disable PIC Intrs in the general
2016 * intr mask register
2018 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2022 /* Tx traffic interrupts */
2023 if (mask & TX_TRAFFIC_INTR) {
2024 intr_mask |= TXTRAFFIC_INT_M;
2025 if (flag == ENABLE_INTRS) {
2027 * Enable all the Tx side interrupts
2028 * writing 0 Enables all 64 TX interrupt levels
2030 writeq(0x0, &bar0->tx_traffic_mask);
2031 } else if (flag == DISABLE_INTRS) {
2033 * Disable Tx Traffic Intrs in the general intr mask
2036 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2040 /* Rx traffic interrupts */
2041 if (mask & RX_TRAFFIC_INTR) {
2042 intr_mask |= RXTRAFFIC_INT_M;
2043 if (flag == ENABLE_INTRS) {
2044 /* writing 0 Enables all 8 RX interrupt levels */
2045 writeq(0x0, &bar0->rx_traffic_mask);
2046 } else if (flag == DISABLE_INTRS) {
2048 * Disable Rx Traffic Intrs in the general intr mask
2051 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2055 temp64 = readq(&bar0->general_int_mask);
2056 if (flag == ENABLE_INTRS)
2057 temp64 &= ~((u64)intr_mask);
2059 temp64 = DISABLE_ALL_INTRS;
2060 writeq(temp64, &bar0->general_int_mask);
2062 nic->general_int_mask = readq(&bar0->general_int_mask);
2066 * verify_pcc_quiescent- Checks for PCC quiescent state
2067 * Return: 1 If PCC is quiescence
2068 * 0 If PCC is not quiescence
2070 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2073 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2074 u64 val64 = readq(&bar0->adapter_status);
2076 herc = (sp->device_type == XFRAME_II_DEVICE);
2078 if (flag == false) {
2079 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2080 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2083 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2087 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2088 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2089 ADAPTER_STATUS_RMAC_PCC_IDLE))
2092 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2093 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2101 * verify_xena_quiescence - Checks whether the H/W is ready
2102 * Description: Returns whether the H/W is ready to go or not. Depending
2103 * on whether adapter enable bit was written or not the comparison
2104 * differs and the calling function passes the input argument flag to
2106 * Return: 1 If xena is quiescence
2107 * 0 If Xena is not quiescence
2110 static int verify_xena_quiescence(struct s2io_nic *sp)
2113 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2114 u64 val64 = readq(&bar0->adapter_status);
2115 mode = s2io_verify_pci_mode(sp);
2117 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2118 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2121 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2122 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2125 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2126 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2129 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2130 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2133 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2134 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2137 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2138 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2141 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2142 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2145 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2146 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2151 * In PCI 33 mode, the P_PLL is not used, and therefore,
2152 * the the P_PLL_LOCK bit in the adapter_status register will
2155 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2156 sp->device_type == XFRAME_II_DEVICE &&
2157 mode != PCI_MODE_PCI_33) {
2158 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2161 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2162 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2163 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2170 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2171 * @sp: Pointer to device specifc structure
2173 * New procedure to clear mac address reading problems on Alpha platforms
2177 static void fix_mac_address(struct s2io_nic *sp)
2179 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2182 while (fix_mac[i] != END_SIGN) {
2183 writeq(fix_mac[i++], &bar0->gpio_control);
2185 (void) readq(&bar0->gpio_control);
2190 * start_nic - Turns the device on
2191 * @nic : device private variable.
2193 * This function actually turns the device on. Before this function is
2194 * called,all Registers are configured from their reset states
2195 * and shared memory is allocated but the NIC is still quiescent. On
2196 * calling this function, the device interrupts are cleared and the NIC is
2197 * literally switched on by writing into the adapter control register.
2199 * SUCCESS on success and -1 on failure.
2202 static int start_nic(struct s2io_nic *nic)
2204 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2205 struct net_device *dev = nic->dev;
2206 register u64 val64 = 0;
2208 struct config_param *config = &nic->config;
2209 struct mac_info *mac_control = &nic->mac_control;
2211 /* PRC Initialization and configuration */
2212 for (i = 0; i < config->rx_ring_num; i++) {
2213 struct ring_info *ring = &mac_control->rings[i];
2215 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2216 &bar0->prc_rxd0_n[i]);
2218 val64 = readq(&bar0->prc_ctrl_n[i]);
2219 if (nic->rxd_mode == RXD_MODE_1)
2220 val64 |= PRC_CTRL_RC_ENABLED;
2222 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2223 if (nic->device_type == XFRAME_II_DEVICE)
2224 val64 |= PRC_CTRL_GROUP_READS;
2225 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2226 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2227 writeq(val64, &bar0->prc_ctrl_n[i]);
2230 if (nic->rxd_mode == RXD_MODE_3B) {
2231 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2232 val64 = readq(&bar0->rx_pa_cfg);
2233 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2234 writeq(val64, &bar0->rx_pa_cfg);
2237 if (vlan_tag_strip == 0) {
2238 val64 = readq(&bar0->rx_pa_cfg);
2239 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2240 writeq(val64, &bar0->rx_pa_cfg);
2241 nic->vlan_strip_flag = 0;
2245 * Enabling MC-RLDRAM. After enabling the device, we timeout
2246 * for around 100ms, which is approximately the time required
2247 * for the device to be ready for operation.
2249 val64 = readq(&bar0->mc_rldram_mrs);
2250 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2251 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2252 val64 = readq(&bar0->mc_rldram_mrs);
2254 msleep(100); /* Delay by around 100 ms. */
2256 /* Enabling ECC Protection. */
2257 val64 = readq(&bar0->adapter_control);
2258 val64 &= ~ADAPTER_ECC_EN;
2259 writeq(val64, &bar0->adapter_control);
2262 * Verify if the device is ready to be enabled, if so enable
2265 val64 = readq(&bar0->adapter_status);
2266 if (!verify_xena_quiescence(nic)) {
2267 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2268 "Adapter status reads: 0x%llx\n",
2269 dev->name, (unsigned long long)val64);
2274 * With some switches, link might be already up at this point.
2275 * Because of this weird behavior, when we enable laser,
2276 * we may not get link. We need to handle this. We cannot
2277 * figure out which switch is misbehaving. So we are forced to
2278 * make a global change.
2281 /* Enabling Laser. */
2282 val64 = readq(&bar0->adapter_control);
2283 val64 |= ADAPTER_EOI_TX_ON;
2284 writeq(val64, &bar0->adapter_control);
2286 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2288 * Dont see link state interrupts initially on some switches,
2289 * so directly scheduling the link state task here.
2291 schedule_work(&nic->set_link_task);
2293 /* SXE-002: Initialize link and activity LED */
2294 subid = nic->pdev->subsystem_device;
2295 if (((subid & 0xFF) >= 0x07) &&
2296 (nic->device_type == XFRAME_I_DEVICE)) {
2297 val64 = readq(&bar0->gpio_control);
2298 val64 |= 0x0000800000000000ULL;
2299 writeq(val64, &bar0->gpio_control);
2300 val64 = 0x0411040400000000ULL;
2301 writeq(val64, (void __iomem *)bar0 + 0x2700);
2307 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2309 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2310 struct TxD *txdlp, int get_off)
2312 struct s2io_nic *nic = fifo_data->nic;
2313 struct sk_buff *skb;
2318 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2319 dma_unmap_single(&nic->pdev->dev,
2320 (dma_addr_t)txds->Buffer_Pointer,
2321 sizeof(u64), DMA_TO_DEVICE);
2325 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2327 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2330 dma_unmap_single(&nic->pdev->dev, (dma_addr_t)txds->Buffer_Pointer,
2331 skb_headlen(skb), DMA_TO_DEVICE);
2332 frg_cnt = skb_shinfo(skb)->nr_frags;
2335 for (j = 0; j < frg_cnt; j++, txds++) {
2336 const skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2337 if (!txds->Buffer_Pointer)
2339 dma_unmap_page(&nic->pdev->dev,
2340 (dma_addr_t)txds->Buffer_Pointer,
2341 skb_frag_size(frag), DMA_TO_DEVICE);
2344 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2349 * free_tx_buffers - Free all queued Tx buffers
2350 * @nic : device private variable.
2352 * Free all queued Tx buffers.
2353 * Return Value: void
2356 static void free_tx_buffers(struct s2io_nic *nic)
2358 struct net_device *dev = nic->dev;
2359 struct sk_buff *skb;
2363 struct config_param *config = &nic->config;
2364 struct mac_info *mac_control = &nic->mac_control;
2365 struct stat_block *stats = mac_control->stats_info;
2366 struct swStat *swstats = &stats->sw_stat;
2368 for (i = 0; i < config->tx_fifo_num; i++) {
2369 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2370 struct fifo_info *fifo = &mac_control->fifos[i];
2371 unsigned long flags;
2373 spin_lock_irqsave(&fifo->tx_lock, flags);
2374 for (j = 0; j < tx_cfg->fifo_len; j++) {
2375 txdp = fifo->list_info[j].list_virt_addr;
2376 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2378 swstats->mem_freed += skb->truesize;
2384 "%s: forcibly freeing %d skbs on FIFO%d\n",
2386 fifo->tx_curr_get_info.offset = 0;
2387 fifo->tx_curr_put_info.offset = 0;
2388 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2393 * stop_nic - To stop the nic
2394 * @nic ; device private variable.
2396 * This function does exactly the opposite of what the start_nic()
2397 * function does. This function is called to stop the device.
2402 static void stop_nic(struct s2io_nic *nic)
2404 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2405 register u64 val64 = 0;
2408 /* Disable all interrupts */
2409 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2410 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2411 interruptible |= TX_PIC_INTR;
2412 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2414 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2415 val64 = readq(&bar0->adapter_control);
2416 val64 &= ~(ADAPTER_CNTL_EN);
2417 writeq(val64, &bar0->adapter_control);
2421 * fill_rx_buffers - Allocates the Rx side skbs
2422 * @ring_info: per ring structure
2423 * @from_card_up: If this is true, we will map the buffer to get
2424 * the dma address for buf0 and buf1 to give it to the card.
2425 * Else we will sync the already mapped buffer to give it to the card.
2427 * The function allocates Rx side skbs and puts the physical
2428 * address of these buffers into the RxD buffer pointers, so that the NIC
2429 * can DMA the received frame into these locations.
2430 * The NIC supports 3 receive modes, viz
2432 * 2. three buffer and
2433 * 3. Five buffer modes.
2434 * Each mode defines how many fragments the received frame will be split
2435 * up into by the NIC. The frame is split into L3 header, L4 Header,
2436 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2437 * is split into 3 fragments. As of now only single buffer mode is
2440 * SUCCESS on success or an appropriate -ve value on failure.
2442 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2445 struct sk_buff *skb;
2447 int off, size, block_no, block_no1;
2452 struct RxD_t *first_rxdp = NULL;
2453 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2456 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2458 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2460 block_no1 = ring->rx_curr_get_info.block_index;
2461 while (alloc_tab < alloc_cnt) {
2462 block_no = ring->rx_curr_put_info.block_index;
2464 off = ring->rx_curr_put_info.offset;
2466 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2468 if ((block_no == block_no1) &&
2469 (off == ring->rx_curr_get_info.offset) &&
2470 (rxdp->Host_Control)) {
2471 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2475 if (off && (off == ring->rxd_count)) {
2476 ring->rx_curr_put_info.block_index++;
2477 if (ring->rx_curr_put_info.block_index ==
2479 ring->rx_curr_put_info.block_index = 0;
2480 block_no = ring->rx_curr_put_info.block_index;
2482 ring->rx_curr_put_info.offset = off;
2483 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2484 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2485 ring->dev->name, rxdp);
2489 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2490 ((ring->rxd_mode == RXD_MODE_3B) &&
2491 (rxdp->Control_2 & s2BIT(0)))) {
2492 ring->rx_curr_put_info.offset = off;
2495 /* calculate size of skb based on ring mode */
2497 HEADER_ETHERNET_II_802_3_SIZE +
2498 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2499 if (ring->rxd_mode == RXD_MODE_1)
2500 size += NET_IP_ALIGN;
2502 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2505 skb = netdev_alloc_skb(nic->dev, size);
2507 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2511 first_rxdp->Control_1 |= RXD_OWN_XENA;
2513 swstats->mem_alloc_fail_cnt++;
2517 swstats->mem_allocated += skb->truesize;
2519 if (ring->rxd_mode == RXD_MODE_1) {
2520 /* 1 buffer mode - normal operation mode */
2521 rxdp1 = (struct RxD1 *)rxdp;
2522 memset(rxdp, 0, sizeof(struct RxD1));
2523 skb_reserve(skb, NET_IP_ALIGN);
2524 rxdp1->Buffer0_ptr =
2525 dma_map_single(&ring->pdev->dev, skb->data,
2526 size - NET_IP_ALIGN,
2528 if (dma_mapping_error(&nic->pdev->dev, rxdp1->Buffer0_ptr))
2529 goto pci_map_failed;
2532 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2533 rxdp->Host_Control = (unsigned long)skb;
2534 } else if (ring->rxd_mode == RXD_MODE_3B) {
2537 * 2 buffer mode provides 128
2538 * byte aligned receive buffers.
2541 rxdp3 = (struct RxD3 *)rxdp;
2542 /* save buffer pointers to avoid frequent dma mapping */
2543 Buffer0_ptr = rxdp3->Buffer0_ptr;
2544 Buffer1_ptr = rxdp3->Buffer1_ptr;
2545 memset(rxdp, 0, sizeof(struct RxD3));
2546 /* restore the buffer pointers for dma sync*/
2547 rxdp3->Buffer0_ptr = Buffer0_ptr;
2548 rxdp3->Buffer1_ptr = Buffer1_ptr;
2550 ba = &ring->ba[block_no][off];
2551 skb_reserve(skb, BUF0_LEN);
2552 tmp = (u64)(unsigned long)skb->data;
2555 skb->data = (void *) (unsigned long)tmp;
2556 skb_reset_tail_pointer(skb);
2559 rxdp3->Buffer0_ptr =
2560 dma_map_single(&ring->pdev->dev,
2563 if (dma_mapping_error(&nic->pdev->dev, rxdp3->Buffer0_ptr))
2564 goto pci_map_failed;
2566 dma_sync_single_for_device(&ring->pdev->dev,
2567 (dma_addr_t)rxdp3->Buffer0_ptr,
2571 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2572 if (ring->rxd_mode == RXD_MODE_3B) {
2573 /* Two buffer mode */
2576 * Buffer2 will have L3/L4 header plus
2579 rxdp3->Buffer2_ptr = dma_map_single(&ring->pdev->dev,
2584 if (dma_mapping_error(&nic->pdev->dev, rxdp3->Buffer2_ptr))
2585 goto pci_map_failed;
2588 rxdp3->Buffer1_ptr =
2589 dma_map_single(&ring->pdev->dev,
2594 if (dma_mapping_error(&nic->pdev->dev,
2595 rxdp3->Buffer1_ptr)) {
2596 dma_unmap_single(&ring->pdev->dev,
2597 (dma_addr_t)(unsigned long)
2601 goto pci_map_failed;
2604 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2605 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2608 rxdp->Control_2 |= s2BIT(0);
2609 rxdp->Host_Control = (unsigned long) (skb);
2611 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2612 rxdp->Control_1 |= RXD_OWN_XENA;
2614 if (off == (ring->rxd_count + 1))
2616 ring->rx_curr_put_info.offset = off;
2618 rxdp->Control_2 |= SET_RXD_MARKER;
2619 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2622 first_rxdp->Control_1 |= RXD_OWN_XENA;
2626 ring->rx_bufs_left += 1;
2631 /* Transfer ownership of first descriptor to adapter just before
2632 * exiting. Before that, use memory barrier so that ownership
2633 * and other fields are seen by adapter correctly.
2637 first_rxdp->Control_1 |= RXD_OWN_XENA;
2643 swstats->pci_map_fail_cnt++;
2644 swstats->mem_freed += skb->truesize;
2645 dev_kfree_skb_irq(skb);
2649 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2651 struct net_device *dev = sp->dev;
2653 struct sk_buff *skb;
2657 struct mac_info *mac_control = &sp->mac_control;
2658 struct stat_block *stats = mac_control->stats_info;
2659 struct swStat *swstats = &stats->sw_stat;
2661 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2662 rxdp = mac_control->rings[ring_no].
2663 rx_blocks[blk].rxds[j].virt_addr;
2664 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2667 if (sp->rxd_mode == RXD_MODE_1) {
2668 rxdp1 = (struct RxD1 *)rxdp;
2669 dma_unmap_single(&sp->pdev->dev,
2670 (dma_addr_t)rxdp1->Buffer0_ptr,
2672 HEADER_ETHERNET_II_802_3_SIZE +
2673 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2675 memset(rxdp, 0, sizeof(struct RxD1));
2676 } else if (sp->rxd_mode == RXD_MODE_3B) {
2677 rxdp3 = (struct RxD3 *)rxdp;
2678 dma_unmap_single(&sp->pdev->dev,
2679 (dma_addr_t)rxdp3->Buffer0_ptr,
2680 BUF0_LEN, DMA_FROM_DEVICE);
2681 dma_unmap_single(&sp->pdev->dev,
2682 (dma_addr_t)rxdp3->Buffer1_ptr,
2683 BUF1_LEN, DMA_FROM_DEVICE);
2684 dma_unmap_single(&sp->pdev->dev,
2685 (dma_addr_t)rxdp3->Buffer2_ptr,
2686 dev->mtu + 4, DMA_FROM_DEVICE);
2687 memset(rxdp, 0, sizeof(struct RxD3));
2689 swstats->mem_freed += skb->truesize;
2691 mac_control->rings[ring_no].rx_bufs_left -= 1;
2696 * free_rx_buffers - Frees all Rx buffers
2697 * @sp: device private variable.
2699 * This function will free all Rx buffers allocated by host.
2704 static void free_rx_buffers(struct s2io_nic *sp)
2706 struct net_device *dev = sp->dev;
2707 int i, blk = 0, buf_cnt = 0;
2708 struct config_param *config = &sp->config;
2709 struct mac_info *mac_control = &sp->mac_control;
2711 for (i = 0; i < config->rx_ring_num; i++) {
2712 struct ring_info *ring = &mac_control->rings[i];
2714 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2715 free_rxd_blk(sp, i, blk);
2717 ring->rx_curr_put_info.block_index = 0;
2718 ring->rx_curr_get_info.block_index = 0;
2719 ring->rx_curr_put_info.offset = 0;
2720 ring->rx_curr_get_info.offset = 0;
2721 ring->rx_bufs_left = 0;
2722 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2723 dev->name, buf_cnt, i);
2727 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2729 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2730 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2737 * s2io_poll - Rx interrupt handler for NAPI support
2738 * @napi : pointer to the napi structure.
2739 * @budget : The number of packets that were budgeted to be processed
2740 * during one pass through the 'Poll" function.
2742 * Comes into picture only if NAPI support has been incorporated. It does
2743 * the same thing that rx_intr_handler does, but not in a interrupt context
2744 * also It will process only a given number of packets.
2746 * 0 on success and 1 if there are No Rx packets to be processed.
2749 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2751 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2752 struct net_device *dev = ring->dev;
2753 int pkts_processed = 0;
2754 u8 __iomem *addr = NULL;
2756 struct s2io_nic *nic = netdev_priv(dev);
2757 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2758 int budget_org = budget;
2760 if (unlikely(!is_s2io_card_up(nic)))
2763 pkts_processed = rx_intr_handler(ring, budget);
2764 s2io_chk_rx_buffers(nic, ring);
2766 if (pkts_processed < budget_org) {
2767 napi_complete_done(napi, pkts_processed);
2768 /*Re Enable MSI-Rx Vector*/
2769 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2770 addr += 7 - ring->ring_no;
2771 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2775 return pkts_processed;
2778 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2780 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2781 int pkts_processed = 0;
2782 int ring_pkts_processed, i;
2783 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2784 int budget_org = budget;
2785 struct config_param *config = &nic->config;
2786 struct mac_info *mac_control = &nic->mac_control;
2788 if (unlikely(!is_s2io_card_up(nic)))
2791 for (i = 0; i < config->rx_ring_num; i++) {
2792 struct ring_info *ring = &mac_control->rings[i];
2793 ring_pkts_processed = rx_intr_handler(ring, budget);
2794 s2io_chk_rx_buffers(nic, ring);
2795 pkts_processed += ring_pkts_processed;
2796 budget -= ring_pkts_processed;
2800 if (pkts_processed < budget_org) {
2801 napi_complete_done(napi, pkts_processed);
2802 /* Re enable the Rx interrupts for the ring */
2803 writeq(0, &bar0->rx_traffic_mask);
2804 readl(&bar0->rx_traffic_mask);
2806 return pkts_processed;
2809 #ifdef CONFIG_NET_POLL_CONTROLLER
2811 * s2io_netpoll - netpoll event handler entry point
2812 * @dev : pointer to the device structure.
2814 * This function will be called by upper layer to check for events on the
2815 * interface in situations where interrupts are disabled. It is used for
2816 * specific in-kernel networking tasks, such as remote consoles and kernel
2817 * debugging over the network (example netdump in RedHat).
2819 static void s2io_netpoll(struct net_device *dev)
2821 struct s2io_nic *nic = netdev_priv(dev);
2822 const int irq = nic->pdev->irq;
2823 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2824 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2826 struct config_param *config = &nic->config;
2827 struct mac_info *mac_control = &nic->mac_control;
2829 if (pci_channel_offline(nic->pdev))
2834 writeq(val64, &bar0->rx_traffic_int);
2835 writeq(val64, &bar0->tx_traffic_int);
2837 /* we need to free up the transmitted skbufs or else netpoll will
2838 * run out of skbs and will fail and eventually netpoll application such
2839 * as netdump will fail.
2841 for (i = 0; i < config->tx_fifo_num; i++)
2842 tx_intr_handler(&mac_control->fifos[i]);
2844 /* check for received packet and indicate up to network */
2845 for (i = 0; i < config->rx_ring_num; i++) {
2846 struct ring_info *ring = &mac_control->rings[i];
2848 rx_intr_handler(ring, 0);
2851 for (i = 0; i < config->rx_ring_num; i++) {
2852 struct ring_info *ring = &mac_control->rings[i];
2854 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2856 "%s: Out of memory in Rx Netpoll!!\n",
2866 * rx_intr_handler - Rx interrupt handler
2867 * @ring_info: per ring structure.
2868 * @budget: budget for napi processing.
2870 * If the interrupt is because of a received frame or if the
2871 * receive ring contains fresh as yet un-processed frames,this function is
2872 * called. It picks out the RxD at which place the last Rx processing had
2873 * stopped and sends the skb to the OSM's Rx handler and then increments
2876 * No. of napi packets processed.
2878 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2880 int get_block, put_block;
2881 struct rx_curr_get_info get_info, put_info;
2883 struct sk_buff *skb;
2884 int pkt_cnt = 0, napi_pkts = 0;
2892 get_info = ring_data->rx_curr_get_info;
2893 get_block = get_info.block_index;
2894 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2895 put_block = put_info.block_index;
2896 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2898 while (RXD_IS_UP2DT(rxdp)) {
2900 * If your are next to put index then it's
2901 * FIFO full condition
2903 if ((get_block == put_block) &&
2904 (get_info.offset + 1) == put_info.offset) {
2905 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2906 ring_data->dev->name);
2909 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2911 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2912 ring_data->dev->name);
2915 if (ring_data->rxd_mode == RXD_MODE_1) {
2916 rxdp1 = (struct RxD1 *)rxdp;
2917 dma_unmap_single(&ring_data->pdev->dev,
2918 (dma_addr_t)rxdp1->Buffer0_ptr,
2920 HEADER_ETHERNET_II_802_3_SIZE +
2924 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
2925 rxdp3 = (struct RxD3 *)rxdp;
2926 dma_sync_single_for_cpu(&ring_data->pdev->dev,
2927 (dma_addr_t)rxdp3->Buffer0_ptr,
2928 BUF0_LEN, DMA_FROM_DEVICE);
2929 dma_unmap_single(&ring_data->pdev->dev,
2930 (dma_addr_t)rxdp3->Buffer2_ptr,
2931 ring_data->mtu + 4, DMA_FROM_DEVICE);
2933 prefetch(skb->data);
2934 rx_osm_handler(ring_data, rxdp);
2936 ring_data->rx_curr_get_info.offset = get_info.offset;
2937 rxdp = ring_data->rx_blocks[get_block].
2938 rxds[get_info.offset].virt_addr;
2939 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
2940 get_info.offset = 0;
2941 ring_data->rx_curr_get_info.offset = get_info.offset;
2943 if (get_block == ring_data->block_count)
2945 ring_data->rx_curr_get_info.block_index = get_block;
2946 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2949 if (ring_data->nic->config.napi) {
2956 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2959 if (ring_data->lro) {
2960 /* Clear all LRO sessions before exiting */
2961 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
2962 struct lro *lro = &ring_data->lro0_n[i];
2964 update_L3L4_header(ring_data->nic, lro);
2965 queue_rx_frame(lro->parent, lro->vlan_tag);
2966 clear_lro_session(lro);
2974 * tx_intr_handler - Transmit interrupt handler
2975 * @nic : device private variable
2977 * If an interrupt was raised to indicate DMA complete of the
2978 * Tx packet, this function is called. It identifies the last TxD
2979 * whose buffer was freed and frees all skbs whose data have already
2980 * DMA'ed into the NICs internal memory.
2985 static void tx_intr_handler(struct fifo_info *fifo_data)
2987 struct s2io_nic *nic = fifo_data->nic;
2988 struct tx_curr_get_info get_info, put_info;
2989 struct sk_buff *skb = NULL;
2992 unsigned long flags = 0;
2994 struct stat_block *stats = nic->mac_control.stats_info;
2995 struct swStat *swstats = &stats->sw_stat;
2997 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3000 get_info = fifo_data->tx_curr_get_info;
3001 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3002 txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3003 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3004 (get_info.offset != put_info.offset) &&
3005 (txdlp->Host_Control)) {
3006 /* Check for TxD errors */
3007 if (txdlp->Control_1 & TXD_T_CODE) {
3008 unsigned long long err;
3009 err = txdlp->Control_1 & TXD_T_CODE;
3011 swstats->parity_err_cnt++;
3014 /* update t_code statistics */
3015 err_mask = err >> 48;
3018 swstats->tx_buf_abort_cnt++;
3022 swstats->tx_desc_abort_cnt++;
3026 swstats->tx_parity_err_cnt++;
3030 swstats->tx_link_loss_cnt++;
3034 swstats->tx_list_proc_err_cnt++;
3039 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3041 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3042 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3048 /* Updating the statistics block */
3049 swstats->mem_freed += skb->truesize;
3050 dev_consume_skb_irq(skb);
3053 if (get_info.offset == get_info.fifo_len + 1)
3054 get_info.offset = 0;
3055 txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3056 fifo_data->tx_curr_get_info.offset = get_info.offset;
3059 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3061 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3065 * s2io_mdio_write - Function to write in to MDIO registers
3066 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3067 * @addr : address value
3068 * @value : data value
3069 * @dev : pointer to net_device structure
3071 * This function is used to write values to the MDIO registers
3074 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3075 struct net_device *dev)
3078 struct s2io_nic *sp = netdev_priv(dev);
3079 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3081 /* address transaction */
3082 val64 = MDIO_MMD_INDX_ADDR(addr) |
3083 MDIO_MMD_DEV_ADDR(mmd_type) |
3084 MDIO_MMS_PRT_ADDR(0x0);
3085 writeq(val64, &bar0->mdio_control);
3086 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3087 writeq(val64, &bar0->mdio_control);
3090 /* Data transaction */
3091 val64 = MDIO_MMD_INDX_ADDR(addr) |
3092 MDIO_MMD_DEV_ADDR(mmd_type) |
3093 MDIO_MMS_PRT_ADDR(0x0) |
3094 MDIO_MDIO_DATA(value) |
3095 MDIO_OP(MDIO_OP_WRITE_TRANS);
3096 writeq(val64, &bar0->mdio_control);
3097 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3098 writeq(val64, &bar0->mdio_control);
3101 val64 = MDIO_MMD_INDX_ADDR(addr) |
3102 MDIO_MMD_DEV_ADDR(mmd_type) |
3103 MDIO_MMS_PRT_ADDR(0x0) |
3104 MDIO_OP(MDIO_OP_READ_TRANS);
3105 writeq(val64, &bar0->mdio_control);
3106 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3107 writeq(val64, &bar0->mdio_control);
3112 * s2io_mdio_read - Function to write in to MDIO registers
3113 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3114 * @addr : address value
3115 * @dev : pointer to net_device structure
3117 * This function is used to read values to the MDIO registers
3120 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3124 struct s2io_nic *sp = netdev_priv(dev);
3125 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3127 /* address transaction */
3128 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3129 | MDIO_MMD_DEV_ADDR(mmd_type)
3130 | MDIO_MMS_PRT_ADDR(0x0));
3131 writeq(val64, &bar0->mdio_control);
3132 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3133 writeq(val64, &bar0->mdio_control);
3136 /* Data transaction */
3137 val64 = MDIO_MMD_INDX_ADDR(addr) |
3138 MDIO_MMD_DEV_ADDR(mmd_type) |
3139 MDIO_MMS_PRT_ADDR(0x0) |
3140 MDIO_OP(MDIO_OP_READ_TRANS);
3141 writeq(val64, &bar0->mdio_control);
3142 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3143 writeq(val64, &bar0->mdio_control);
3146 /* Read the value from regs */
3147 rval64 = readq(&bar0->mdio_control);
3148 rval64 = rval64 & 0xFFFF0000;
3149 rval64 = rval64 >> 16;
3154 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3155 * @counter : counter value to be updated
3156 * @flag : flag to indicate the status
3157 * @type : counter type
3159 * This function is to check the status of the xpak counters value
3163 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3169 for (i = 0; i < index; i++)
3173 *counter = *counter + 1;
3174 val64 = *regs_stat & mask;
3175 val64 = val64 >> (index * 0x2);
3181 "Take Xframe NIC out of service.\n");
3183 "Excessive temperatures may result in premature transceiver failure.\n");
3187 "Take Xframe NIC out of service.\n");
3189 "Excessive bias currents may indicate imminent laser diode failure.\n");
3193 "Take Xframe NIC out of service.\n");
3195 "Excessive laser output power may saturate far-end receiver.\n");
3199 "Incorrect XPAK Alarm type\n");
3203 val64 = val64 << (index * 0x2);
3204 *regs_stat = (*regs_stat & (~mask)) | (val64);
3207 *regs_stat = *regs_stat & (~mask);
3212 * s2io_updt_xpak_counter - Function to update the xpak counters
3213 * @dev : pointer to net_device struct
3215 * This function is to upate the status of the xpak counters value
3218 static void s2io_updt_xpak_counter(struct net_device *dev)
3226 struct s2io_nic *sp = netdev_priv(dev);
3227 struct stat_block *stats = sp->mac_control.stats_info;
3228 struct xpakStat *xstats = &stats->xpak_stat;
3230 /* Check the communication with the MDIO slave */
3233 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3234 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3236 "ERR: MDIO slave access failed - Returned %llx\n",
3237 (unsigned long long)val64);
3241 /* Check for the expected value of control reg 1 */
3242 if (val64 != MDIO_CTRL1_SPEED10G) {
3243 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3244 "Returned: %llx- Expected: 0x%x\n",
3245 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3249 /* Loading the DOM register to MDIO register */
3251 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3252 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3254 /* Reading the Alarm flags */
3257 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3259 flag = CHECKBIT(val64, 0x7);
3261 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3262 &xstats->xpak_regs_stat,
3265 if (CHECKBIT(val64, 0x6))
3266 xstats->alarm_transceiver_temp_low++;
3268 flag = CHECKBIT(val64, 0x3);
3270 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3271 &xstats->xpak_regs_stat,
3274 if (CHECKBIT(val64, 0x2))
3275 xstats->alarm_laser_bias_current_low++;
3277 flag = CHECKBIT(val64, 0x1);
3279 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3280 &xstats->xpak_regs_stat,
3283 if (CHECKBIT(val64, 0x0))
3284 xstats->alarm_laser_output_power_low++;
3286 /* Reading the Warning flags */
3289 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3291 if (CHECKBIT(val64, 0x7))
3292 xstats->warn_transceiver_temp_high++;
3294 if (CHECKBIT(val64, 0x6))
3295 xstats->warn_transceiver_temp_low++;
3297 if (CHECKBIT(val64, 0x3))
3298 xstats->warn_laser_bias_current_high++;
3300 if (CHECKBIT(val64, 0x2))
3301 xstats->warn_laser_bias_current_low++;
3303 if (CHECKBIT(val64, 0x1))
3304 xstats->warn_laser_output_power_high++;
3306 if (CHECKBIT(val64, 0x0))
3307 xstats->warn_laser_output_power_low++;
3311 * wait_for_cmd_complete - waits for a command to complete.
3312 * @sp : private member of the device structure, which is a pointer to the
3313 * s2io_nic structure.
3314 * Description: Function that waits for a command to Write into RMAC
3315 * ADDR DATA registers to be completed and returns either success or
3316 * error depending on whether the command was complete or not.
3318 * SUCCESS on success and FAILURE on failure.
3321 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3324 int ret = FAILURE, cnt = 0, delay = 1;
3327 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3331 val64 = readq(addr);
3332 if (bit_state == S2IO_BIT_RESET) {
3333 if (!(val64 & busy_bit)) {
3338 if (val64 & busy_bit) {
3355 * check_pci_device_id - Checks if the device id is supported
3357 * Description: Function to check if the pci device id is supported by driver.
3358 * Return value: Actual device id if supported else PCI_ANY_ID
3360 static u16 check_pci_device_id(u16 id)
3363 case PCI_DEVICE_ID_HERC_WIN:
3364 case PCI_DEVICE_ID_HERC_UNI:
3365 return XFRAME_II_DEVICE;
3366 case PCI_DEVICE_ID_S2IO_UNI:
3367 case PCI_DEVICE_ID_S2IO_WIN:
3368 return XFRAME_I_DEVICE;
3375 * s2io_reset - Resets the card.
3376 * @sp : private member of the device structure.
3377 * Description: Function to Reset the card. This function then also
3378 * restores the previously saved PCI configuration space registers as
3379 * the card reset also resets the configuration space.
3384 static void s2io_reset(struct s2io_nic *sp)
3386 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3391 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3392 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3393 struct stat_block *stats;
3394 struct swStat *swstats;
3396 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3397 __func__, pci_name(sp->pdev));
3399 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3400 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3402 val64 = SW_RESET_ALL;
3403 writeq(val64, &bar0->sw_reset);
3404 if (strstr(sp->product_name, "CX4"))
3407 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3409 /* Restore the PCI state saved during initialization. */
3410 pci_restore_state(sp->pdev);
3411 pci_save_state(sp->pdev);
3412 pci_read_config_word(sp->pdev, 0x2, &val16);
3413 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3418 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3419 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3421 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3425 /* Set swapper to enable I/O register access */
3426 s2io_set_swapper(sp);
3428 /* restore mac_addr entries */
3429 do_s2io_restore_unicast_mc(sp);
3431 /* Restore the MSIX table entries from local variables */
3432 restore_xmsi_data(sp);
3434 /* Clear certain PCI/PCI-X fields after reset */
3435 if (sp->device_type == XFRAME_II_DEVICE) {
3436 /* Clear "detected parity error" bit */
3437 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3439 /* Clearing PCIX Ecc status register */
3440 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3442 /* Clearing PCI_STATUS error reflected here */
3443 writeq(s2BIT(62), &bar0->txpic_int_reg);
3446 /* Reset device statistics maintained by OS */
3447 memset(&sp->stats, 0, sizeof(struct net_device_stats));
3449 stats = sp->mac_control.stats_info;
3450 swstats = &stats->sw_stat;
3452 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3453 up_cnt = swstats->link_up_cnt;
3454 down_cnt = swstats->link_down_cnt;
3455 up_time = swstats->link_up_time;
3456 down_time = swstats->link_down_time;
3457 reset_cnt = swstats->soft_reset_cnt;
3458 mem_alloc_cnt = swstats->mem_allocated;
3459 mem_free_cnt = swstats->mem_freed;
3460 watchdog_cnt = swstats->watchdog_timer_cnt;
3462 memset(stats, 0, sizeof(struct stat_block));
3464 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3465 swstats->link_up_cnt = up_cnt;
3466 swstats->link_down_cnt = down_cnt;
3467 swstats->link_up_time = up_time;
3468 swstats->link_down_time = down_time;
3469 swstats->soft_reset_cnt = reset_cnt;
3470 swstats->mem_allocated = mem_alloc_cnt;
3471 swstats->mem_freed = mem_free_cnt;
3472 swstats->watchdog_timer_cnt = watchdog_cnt;
3474 /* SXE-002: Configure link and activity LED to turn it off */
3475 subid = sp->pdev->subsystem_device;
3476 if (((subid & 0xFF) >= 0x07) &&
3477 (sp->device_type == XFRAME_I_DEVICE)) {
3478 val64 = readq(&bar0->gpio_control);
3479 val64 |= 0x0000800000000000ULL;
3480 writeq(val64, &bar0->gpio_control);
3481 val64 = 0x0411040400000000ULL;
3482 writeq(val64, (void __iomem *)bar0 + 0x2700);
3486 * Clear spurious ECC interrupts that would have occurred on
3487 * XFRAME II cards after reset.
3489 if (sp->device_type == XFRAME_II_DEVICE) {
3490 val64 = readq(&bar0->pcc_err_reg);
3491 writeq(val64, &bar0->pcc_err_reg);
3494 sp->device_enabled_once = false;
3498 * s2io_set_swapper - to set the swapper controle on the card
3499 * @sp : private member of the device structure,
3500 * pointer to the s2io_nic structure.
3501 * Description: Function to set the swapper control on the card
3502 * correctly depending on the 'endianness' of the system.
3504 * SUCCESS on success and FAILURE on failure.
3507 static int s2io_set_swapper(struct s2io_nic *sp)
3509 struct net_device *dev = sp->dev;
3510 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3511 u64 val64, valt, valr;
3514 * Set proper endian settings and verify the same by reading
3515 * the PIF Feed-back register.
3518 val64 = readq(&bar0->pif_rd_swapper_fb);
3519 if (val64 != 0x0123456789ABCDEFULL) {
3521 static const u64 value[] = {
3522 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3523 0x8100008181000081ULL, /* FE=1, SE=0 */
3524 0x4200004242000042ULL, /* FE=0, SE=1 */
3529 writeq(value[i], &bar0->swapper_ctrl);
3530 val64 = readq(&bar0->pif_rd_swapper_fb);
3531 if (val64 == 0x0123456789ABCDEFULL)
3536 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3537 "feedback read %llx\n",
3538 dev->name, (unsigned long long)val64);
3543 valr = readq(&bar0->swapper_ctrl);
3546 valt = 0x0123456789ABCDEFULL;
3547 writeq(valt, &bar0->xmsi_address);
3548 val64 = readq(&bar0->xmsi_address);
3550 if (val64 != valt) {
3552 static const u64 value[] = {
3553 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3554 0x0081810000818100ULL, /* FE=1, SE=0 */
3555 0x0042420000424200ULL, /* FE=0, SE=1 */
3560 writeq((value[i] | valr), &bar0->swapper_ctrl);
3561 writeq(valt, &bar0->xmsi_address);
3562 val64 = readq(&bar0->xmsi_address);
3568 unsigned long long x = val64;
3570 "Write failed, Xmsi_addr reads:0x%llx\n", x);
3574 val64 = readq(&bar0->swapper_ctrl);
3575 val64 &= 0xFFFF000000000000ULL;
3579 * The device by default set to a big endian format, so a
3580 * big endian driver need not set anything.
3582 val64 |= (SWAPPER_CTRL_TXP_FE |
3583 SWAPPER_CTRL_TXP_SE |
3584 SWAPPER_CTRL_TXD_R_FE |
3585 SWAPPER_CTRL_TXD_W_FE |
3586 SWAPPER_CTRL_TXF_R_FE |
3587 SWAPPER_CTRL_RXD_R_FE |
3588 SWAPPER_CTRL_RXD_W_FE |
3589 SWAPPER_CTRL_RXF_W_FE |
3590 SWAPPER_CTRL_XMSI_FE |
3591 SWAPPER_CTRL_STATS_FE |
3592 SWAPPER_CTRL_STATS_SE);
3593 if (sp->config.intr_type == INTA)
3594 val64 |= SWAPPER_CTRL_XMSI_SE;
3595 writeq(val64, &bar0->swapper_ctrl);
3598 * Initially we enable all bits to make it accessible by the
3599 * driver, then we selectively enable only those bits that
3602 val64 |= (SWAPPER_CTRL_TXP_FE |
3603 SWAPPER_CTRL_TXP_SE |
3604 SWAPPER_CTRL_TXD_R_FE |
3605 SWAPPER_CTRL_TXD_R_SE |
3606 SWAPPER_CTRL_TXD_W_FE |
3607 SWAPPER_CTRL_TXD_W_SE |
3608 SWAPPER_CTRL_TXF_R_FE |
3609 SWAPPER_CTRL_RXD_R_FE |
3610 SWAPPER_CTRL_RXD_R_SE |
3611 SWAPPER_CTRL_RXD_W_FE |
3612 SWAPPER_CTRL_RXD_W_SE |
3613 SWAPPER_CTRL_RXF_W_FE |
3614 SWAPPER_CTRL_XMSI_FE |
3615 SWAPPER_CTRL_STATS_FE |
3616 SWAPPER_CTRL_STATS_SE);
3617 if (sp->config.intr_type == INTA)
3618 val64 |= SWAPPER_CTRL_XMSI_SE;
3619 writeq(val64, &bar0->swapper_ctrl);
3621 val64 = readq(&bar0->swapper_ctrl);
3624 * Verifying if endian settings are accurate by reading a
3625 * feedback register.
3627 val64 = readq(&bar0->pif_rd_swapper_fb);
3628 if (val64 != 0x0123456789ABCDEFULL) {
3629 /* Endian settings are incorrect, calls for another dekko. */
3631 "%s: Endian settings are wrong, feedback read %llx\n",
3632 dev->name, (unsigned long long)val64);
3639 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3641 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3643 int ret = 0, cnt = 0;
3646 val64 = readq(&bar0->xmsi_access);
3647 if (!(val64 & s2BIT(15)))
3653 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3660 static void restore_xmsi_data(struct s2io_nic *nic)
3662 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3666 if (nic->device_type == XFRAME_I_DEVICE)
3669 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3670 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3671 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3672 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3673 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3674 writeq(val64, &bar0->xmsi_access);
3675 if (wait_for_msix_trans(nic, msix_index))
3676 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3677 __func__, msix_index);
3681 static void store_xmsi_data(struct s2io_nic *nic)
3683 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3684 u64 val64, addr, data;
3687 if (nic->device_type == XFRAME_I_DEVICE)
3690 /* Store and display */
3691 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3692 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3693 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3694 writeq(val64, &bar0->xmsi_access);
3695 if (wait_for_msix_trans(nic, msix_index)) {
3696 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3697 __func__, msix_index);
3700 addr = readq(&bar0->xmsi_address);
3701 data = readq(&bar0->xmsi_data);
3703 nic->msix_info[i].addr = addr;
3704 nic->msix_info[i].data = data;
3709 static int s2io_enable_msi_x(struct s2io_nic *nic)
3711 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3713 u16 msi_control; /* Temp variable */
3714 int ret, i, j, msix_indx = 1;
3716 struct stat_block *stats = nic->mac_control.stats_info;
3717 struct swStat *swstats = &stats->sw_stat;
3719 size = nic->num_entries * sizeof(struct msix_entry);
3720 nic->entries = kzalloc(size, GFP_KERNEL);
3721 if (!nic->entries) {
3722 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3724 swstats->mem_alloc_fail_cnt++;
3727 swstats->mem_allocated += size;
3729 size = nic->num_entries * sizeof(struct s2io_msix_entry);
3730 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3731 if (!nic->s2io_entries) {
3732 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3734 swstats->mem_alloc_fail_cnt++;
3735 kfree(nic->entries);
3737 += (nic->num_entries * sizeof(struct msix_entry));
3740 swstats->mem_allocated += size;
3742 nic->entries[0].entry = 0;
3743 nic->s2io_entries[0].entry = 0;
3744 nic->s2io_entries[0].in_use = MSIX_FLG;
3745 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3746 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3748 for (i = 1; i < nic->num_entries; i++) {
3749 nic->entries[i].entry = ((i - 1) * 8) + 1;
3750 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3751 nic->s2io_entries[i].arg = NULL;
3752 nic->s2io_entries[i].in_use = 0;
3755 rx_mat = readq(&bar0->rx_mat);
3756 for (j = 0; j < nic->config.rx_ring_num; j++) {
3757 rx_mat |= RX_MAT_SET(j, msix_indx);
3758 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3759 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3760 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3763 writeq(rx_mat, &bar0->rx_mat);
3764 readq(&bar0->rx_mat);
3766 ret = pci_enable_msix_range(nic->pdev, nic->entries,
3767 nic->num_entries, nic->num_entries);
3768 /* We fail init if error or we get less vectors than min required */
3770 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3771 kfree(nic->entries);
3772 swstats->mem_freed += nic->num_entries *
3773 sizeof(struct msix_entry);
3774 kfree(nic->s2io_entries);
3775 swstats->mem_freed += nic->num_entries *
3776 sizeof(struct s2io_msix_entry);
3777 nic->entries = NULL;
3778 nic->s2io_entries = NULL;
3783 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3784 * in the herc NIC. (Temp change, needs to be removed later)
3786 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3787 msi_control |= 0x1; /* Enable MSI */
3788 pci_write_config_word(nic->pdev, 0x42, msi_control);
3793 /* Handle software interrupt used during MSI(X) test */
3794 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3796 struct s2io_nic *sp = dev_id;
3798 sp->msi_detected = 1;
3799 wake_up(&sp->msi_wait);
3804 /* Test interrupt path by forcing a a software IRQ */
3805 static int s2io_test_msi(struct s2io_nic *sp)
3807 struct pci_dev *pdev = sp->pdev;
3808 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3812 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3815 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3816 sp->dev->name, pci_name(pdev), pdev->irq);
3820 init_waitqueue_head(&sp->msi_wait);
3821 sp->msi_detected = 0;
3823 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3824 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3825 val64 |= SCHED_INT_CTRL_TIMER_EN;
3826 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3827 writeq(val64, &bar0->scheduled_int_ctrl);
3829 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3831 if (!sp->msi_detected) {
3832 /* MSI(X) test failed, go back to INTx mode */
3833 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3834 "using MSI(X) during test\n",
3835 sp->dev->name, pci_name(pdev));
3840 free_irq(sp->entries[1].vector, sp);
3842 writeq(saved64, &bar0->scheduled_int_ctrl);
3847 static void remove_msix_isr(struct s2io_nic *sp)
3852 for (i = 0; i < sp->num_entries; i++) {
3853 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3854 int vector = sp->entries[i].vector;
3855 void *arg = sp->s2io_entries[i].arg;
3856 free_irq(vector, arg);
3861 kfree(sp->s2io_entries);
3863 sp->s2io_entries = NULL;
3865 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3866 msi_control &= 0xFFFE; /* Disable MSI */
3867 pci_write_config_word(sp->pdev, 0x42, msi_control);
3869 pci_disable_msix(sp->pdev);
3872 static void remove_inta_isr(struct s2io_nic *sp)
3874 free_irq(sp->pdev->irq, sp->dev);
3877 /* ********************************************************* *
3878 * Functions defined below concern the OS part of the driver *
3879 * ********************************************************* */
3882 * s2io_open - open entry point of the driver
3883 * @dev : pointer to the device structure.
3885 * This function is the open entry point of the driver. It mainly calls a
3886 * function to allocate Rx buffers and inserts them into the buffer
3887 * descriptors and then enables the Rx part of the NIC.
3889 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3893 static int s2io_open(struct net_device *dev)
3895 struct s2io_nic *sp = netdev_priv(dev);
3896 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3900 * Make sure you have link off by default every time
3901 * Nic is initialized
3903 netif_carrier_off(dev);
3904 sp->last_link_state = 0;
3906 /* Initialize H/W and enable interrupts */
3907 err = s2io_card_up(sp);
3909 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3911 goto hw_init_failed;
3914 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3915 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3918 goto hw_init_failed;
3920 s2io_start_all_tx_queue(sp);
3924 if (sp->config.intr_type == MSI_X) {
3927 swstats->mem_freed += sp->num_entries *
3928 sizeof(struct msix_entry);
3930 if (sp->s2io_entries) {
3931 kfree(sp->s2io_entries);
3932 swstats->mem_freed += sp->num_entries *
3933 sizeof(struct s2io_msix_entry);
3940 * s2io_close -close entry point of the driver
3941 * @dev : device pointer.
3943 * This is the stop entry point of the driver. It needs to undo exactly
3944 * whatever was done by the open entry point,thus it's usually referred to
3945 * as the close function.Among other things this function mainly stops the
3946 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3948 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3952 static int s2io_close(struct net_device *dev)
3954 struct s2io_nic *sp = netdev_priv(dev);
3955 struct config_param *config = &sp->config;
3959 /* Return if the device is already closed *
3960 * Can happen when s2io_card_up failed in change_mtu *
3962 if (!is_s2io_card_up(sp))
3965 s2io_stop_all_tx_queue(sp);
3966 /* delete all populated mac entries */
3967 for (offset = 1; offset < config->max_mc_addr; offset++) {
3968 tmp64 = do_s2io_read_unicast_mc(sp, offset);
3969 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
3970 do_s2io_delete_unicast_mc(sp, tmp64);
3979 * s2io_xmit - Tx entry point of te driver
3980 * @skb : the socket buffer containing the Tx data.
3981 * @dev : device pointer.
3983 * This function is the Tx entry point of the driver. S2IO NIC supports
3984 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3985 * NOTE: when device can't queue the pkt,just the trans_start variable will
3988 * 0 on success & 1 on failure.
3991 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3993 struct s2io_nic *sp = netdev_priv(dev);
3994 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3997 struct TxFIFO_element __iomem *tx_fifo;
3998 unsigned long flags = 0;
4000 struct fifo_info *fifo = NULL;
4002 int enable_per_list_interrupt = 0;
4003 struct config_param *config = &sp->config;
4004 struct mac_info *mac_control = &sp->mac_control;
4005 struct stat_block *stats = mac_control->stats_info;
4006 struct swStat *swstats = &stats->sw_stat;
4008 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4010 if (unlikely(skb->len <= 0)) {
4011 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4012 dev_kfree_skb_any(skb);
4013 return NETDEV_TX_OK;
4016 if (!is_s2io_card_up(sp)) {
4017 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4019 dev_kfree_skb_any(skb);
4020 return NETDEV_TX_OK;
4024 if (skb_vlan_tag_present(skb))
4025 vlan_tag = skb_vlan_tag_get(skb);
4026 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4027 if (skb->protocol == htons(ETH_P_IP)) {
4032 if (!ip_is_fragment(ip)) {
4033 th = (struct tcphdr *)(((unsigned char *)ip) +
4036 if (ip->protocol == IPPROTO_TCP) {
4037 queue_len = sp->total_tcp_fifos;
4038 queue = (ntohs(th->source) +
4040 sp->fifo_selector[queue_len - 1];
4041 if (queue >= queue_len)
4042 queue = queue_len - 1;
4043 } else if (ip->protocol == IPPROTO_UDP) {
4044 queue_len = sp->total_udp_fifos;
4045 queue = (ntohs(th->source) +
4047 sp->fifo_selector[queue_len - 1];
4048 if (queue >= queue_len)
4049 queue = queue_len - 1;
4050 queue += sp->udp_fifo_idx;
4051 if (skb->len > 1024)
4052 enable_per_list_interrupt = 1;
4056 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4057 /* get fifo number based on skb->priority value */
4058 queue = config->fifo_mapping
4059 [skb->priority & (MAX_TX_FIFOS - 1)];
4060 fifo = &mac_control->fifos[queue];
4062 spin_lock_irqsave(&fifo->tx_lock, flags);
4064 if (sp->config.multiq) {
4065 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4066 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4067 return NETDEV_TX_BUSY;
4069 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4070 if (netif_queue_stopped(dev)) {
4071 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4072 return NETDEV_TX_BUSY;
4076 put_off = (u16)fifo->tx_curr_put_info.offset;
4077 get_off = (u16)fifo->tx_curr_get_info.offset;
4078 txdp = fifo->list_info[put_off].list_virt_addr;
4080 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4081 /* Avoid "put" pointer going beyond "get" pointer */
4082 if (txdp->Host_Control ||
4083 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4084 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4085 s2io_stop_tx_queue(sp, fifo->fifo_no);
4086 dev_kfree_skb_any(skb);
4087 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4088 return NETDEV_TX_OK;
4091 offload_type = s2io_offload_type(skb);
4092 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4093 txdp->Control_1 |= TXD_TCP_LSO_EN;
4094 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4096 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4097 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4101 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4102 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4103 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4104 if (enable_per_list_interrupt)
4105 if (put_off & (queue_len >> 5))
4106 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4108 txdp->Control_2 |= TXD_VLAN_ENABLE;
4109 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4112 frg_len = skb_headlen(skb);
4113 txdp->Buffer_Pointer = dma_map_single(&sp->pdev->dev, skb->data,
4114 frg_len, DMA_TO_DEVICE);
4115 if (dma_mapping_error(&sp->pdev->dev, txdp->Buffer_Pointer))
4116 goto pci_map_failed;
4118 txdp->Host_Control = (unsigned long)skb;
4119 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4121 frg_cnt = skb_shinfo(skb)->nr_frags;
4122 /* For fragmented SKB. */
4123 for (i = 0; i < frg_cnt; i++) {
4124 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4125 /* A '0' length fragment will be ignored */
4126 if (!skb_frag_size(frag))
4129 txdp->Buffer_Pointer = (u64)skb_frag_dma_map(&sp->pdev->dev,
4131 skb_frag_size(frag),
4133 txdp->Control_1 = TXD_BUFFER0_SIZE(skb_frag_size(frag));
4135 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4137 tx_fifo = mac_control->tx_FIFO_start[queue];
4138 val64 = fifo->list_info[put_off].list_phy_addr;
4139 writeq(val64, &tx_fifo->TxDL_Pointer);
4141 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4144 val64 |= TX_FIFO_SPECIAL_FUNC;
4146 writeq(val64, &tx_fifo->List_Control);
4149 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4151 fifo->tx_curr_put_info.offset = put_off;
4153 /* Avoid "put" pointer going beyond "get" pointer */
4154 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4155 swstats->fifo_full_cnt++;
4157 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4159 s2io_stop_tx_queue(sp, fifo->fifo_no);
4161 swstats->mem_allocated += skb->truesize;
4162 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4164 if (sp->config.intr_type == MSI_X)
4165 tx_intr_handler(fifo);
4167 return NETDEV_TX_OK;
4170 swstats->pci_map_fail_cnt++;
4171 s2io_stop_tx_queue(sp, fifo->fifo_no);
4172 swstats->mem_freed += skb->truesize;
4173 dev_kfree_skb_any(skb);
4174 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4175 return NETDEV_TX_OK;
4179 s2io_alarm_handle(struct timer_list *t)
4181 struct s2io_nic *sp = from_timer(sp, t, alarm_timer);
4182 struct net_device *dev = sp->dev;
4184 s2io_handle_errors(dev);
4185 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4188 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4190 struct ring_info *ring = (struct ring_info *)dev_id;
4191 struct s2io_nic *sp = ring->nic;
4192 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4194 if (unlikely(!is_s2io_card_up(sp)))
4197 if (sp->config.napi) {
4198 u8 __iomem *addr = NULL;
4201 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4202 addr += (7 - ring->ring_no);
4203 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4206 napi_schedule(&ring->napi);
4208 rx_intr_handler(ring, 0);
4209 s2io_chk_rx_buffers(sp, ring);
4215 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4218 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4219 struct s2io_nic *sp = fifos->nic;
4220 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4221 struct config_param *config = &sp->config;
4224 if (unlikely(!is_s2io_card_up(sp)))
4227 reason = readq(&bar0->general_int_status);
4228 if (unlikely(reason == S2IO_MINUS_ONE))
4229 /* Nothing much can be done. Get out */
4232 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4233 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4235 if (reason & GEN_INTR_TXPIC)
4236 s2io_txpic_intr_handle(sp);
4238 if (reason & GEN_INTR_TXTRAFFIC)
4239 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4241 for (i = 0; i < config->tx_fifo_num; i++)
4242 tx_intr_handler(&fifos[i]);
4244 writeq(sp->general_int_mask, &bar0->general_int_mask);
4245 readl(&bar0->general_int_status);
4248 /* The interrupt was not raised by us */
4252 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4254 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4257 val64 = readq(&bar0->pic_int_status);
4258 if (val64 & PIC_INT_GPIO) {
4259 val64 = readq(&bar0->gpio_int_reg);
4260 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4261 (val64 & GPIO_INT_REG_LINK_UP)) {
4263 * This is unstable state so clear both up/down
4264 * interrupt and adapter to re-evaluate the link state.
4266 val64 |= GPIO_INT_REG_LINK_DOWN;
4267 val64 |= GPIO_INT_REG_LINK_UP;
4268 writeq(val64, &bar0->gpio_int_reg);
4269 val64 = readq(&bar0->gpio_int_mask);
4270 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4271 GPIO_INT_MASK_LINK_DOWN);
4272 writeq(val64, &bar0->gpio_int_mask);
4273 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4274 val64 = readq(&bar0->adapter_status);
4275 /* Enable Adapter */
4276 val64 = readq(&bar0->adapter_control);
4277 val64 |= ADAPTER_CNTL_EN;
4278 writeq(val64, &bar0->adapter_control);
4279 val64 |= ADAPTER_LED_ON;
4280 writeq(val64, &bar0->adapter_control);
4281 if (!sp->device_enabled_once)
4282 sp->device_enabled_once = 1;
4284 s2io_link(sp, LINK_UP);
4286 * unmask link down interrupt and mask link-up
4289 val64 = readq(&bar0->gpio_int_mask);
4290 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4291 val64 |= GPIO_INT_MASK_LINK_UP;
4292 writeq(val64, &bar0->gpio_int_mask);
4294 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4295 val64 = readq(&bar0->adapter_status);
4296 s2io_link(sp, LINK_DOWN);
4297 /* Link is down so unmaks link up interrupt */
4298 val64 = readq(&bar0->gpio_int_mask);
4299 val64 &= ~GPIO_INT_MASK_LINK_UP;
4300 val64 |= GPIO_INT_MASK_LINK_DOWN;
4301 writeq(val64, &bar0->gpio_int_mask);
4304 val64 = readq(&bar0->adapter_control);
4305 val64 = val64 & (~ADAPTER_LED_ON);
4306 writeq(val64, &bar0->adapter_control);
4309 val64 = readq(&bar0->gpio_int_mask);
4313 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4314 * @value: alarm bits
4315 * @addr: address value
4316 * @cnt: counter variable
4317 * Description: Check for alarm and increment the counter
4319 * 1 - if alarm bit set
4320 * 0 - if alarm bit is not set
4322 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4323 unsigned long long *cnt)
4326 val64 = readq(addr);
4327 if (val64 & value) {
4328 writeq(val64, addr);
4337 * s2io_handle_errors - Xframe error indication handler
4338 * @nic: device private variable
4339 * Description: Handle alarms such as loss of link, single or
4340 * double ECC errors, critical and serious errors.
4344 static void s2io_handle_errors(void *dev_id)
4346 struct net_device *dev = (struct net_device *)dev_id;
4347 struct s2io_nic *sp = netdev_priv(dev);
4348 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4349 u64 temp64 = 0, val64 = 0;
4352 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4353 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4355 if (!is_s2io_card_up(sp))
4358 if (pci_channel_offline(sp->pdev))
4361 memset(&sw_stat->ring_full_cnt, 0,
4362 sizeof(sw_stat->ring_full_cnt));
4364 /* Handling the XPAK counters update */
4365 if (stats->xpak_timer_count < 72000) {
4366 /* waiting for an hour */
4367 stats->xpak_timer_count++;
4369 s2io_updt_xpak_counter(dev);
4370 /* reset the count to zero */
4371 stats->xpak_timer_count = 0;
4374 /* Handling link status change error Intr */
4375 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4376 val64 = readq(&bar0->mac_rmac_err_reg);
4377 writeq(val64, &bar0->mac_rmac_err_reg);
4378 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4379 schedule_work(&sp->set_link_task);
4382 /* In case of a serious error, the device will be Reset. */
4383 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4384 &sw_stat->serious_err_cnt))
4387 /* Check for data parity error */
4388 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4389 &sw_stat->parity_err_cnt))
4392 /* Check for ring full counter */
4393 if (sp->device_type == XFRAME_II_DEVICE) {
4394 val64 = readq(&bar0->ring_bump_counter1);
4395 for (i = 0; i < 4; i++) {
4396 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4397 temp64 >>= 64 - ((i+1)*16);
4398 sw_stat->ring_full_cnt[i] += temp64;
4401 val64 = readq(&bar0->ring_bump_counter2);
4402 for (i = 0; i < 4; i++) {
4403 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4404 temp64 >>= 64 - ((i+1)*16);
4405 sw_stat->ring_full_cnt[i+4] += temp64;
4409 val64 = readq(&bar0->txdma_int_status);
4410 /*check for pfc_err*/
4411 if (val64 & TXDMA_PFC_INT) {
4412 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4413 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4416 &sw_stat->pfc_err_cnt))
4418 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4420 &sw_stat->pfc_err_cnt);
4423 /*check for tda_err*/
4424 if (val64 & TXDMA_TDA_INT) {
4425 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4429 &sw_stat->tda_err_cnt))
4431 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4433 &sw_stat->tda_err_cnt);
4435 /*check for pcc_err*/
4436 if (val64 & TXDMA_PCC_INT) {
4437 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4438 PCC_N_SERR | PCC_6_COF_OV_ERR |
4439 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4440 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4443 &sw_stat->pcc_err_cnt))
4445 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4447 &sw_stat->pcc_err_cnt);
4450 /*check for tti_err*/
4451 if (val64 & TXDMA_TTI_INT) {
4452 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4454 &sw_stat->tti_err_cnt))
4456 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4458 &sw_stat->tti_err_cnt);
4461 /*check for lso_err*/
4462 if (val64 & TXDMA_LSO_INT) {
4463 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4464 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4466 &sw_stat->lso_err_cnt))
4468 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4470 &sw_stat->lso_err_cnt);
4473 /*check for tpa_err*/
4474 if (val64 & TXDMA_TPA_INT) {
4475 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4477 &sw_stat->tpa_err_cnt))
4479 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4481 &sw_stat->tpa_err_cnt);
4484 /*check for sm_err*/
4485 if (val64 & TXDMA_SM_INT) {
4486 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4488 &sw_stat->sm_err_cnt))
4492 val64 = readq(&bar0->mac_int_status);
4493 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4494 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4495 &bar0->mac_tmac_err_reg,
4496 &sw_stat->mac_tmac_err_cnt))
4498 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4499 TMAC_DESC_ECC_SG_ERR |
4500 TMAC_DESC_ECC_DB_ERR,
4501 &bar0->mac_tmac_err_reg,
4502 &sw_stat->mac_tmac_err_cnt);
4505 val64 = readq(&bar0->xgxs_int_status);
4506 if (val64 & XGXS_INT_STATUS_TXGXS) {
4507 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4508 &bar0->xgxs_txgxs_err_reg,
4509 &sw_stat->xgxs_txgxs_err_cnt))
4511 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4512 &bar0->xgxs_txgxs_err_reg,
4513 &sw_stat->xgxs_txgxs_err_cnt);
4516 val64 = readq(&bar0->rxdma_int_status);
4517 if (val64 & RXDMA_INT_RC_INT_M) {
4518 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4520 RC_PRCn_SM_ERR_ALARM |
4521 RC_FTC_SM_ERR_ALARM,
4523 &sw_stat->rc_err_cnt))
4525 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4527 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4528 &sw_stat->rc_err_cnt);
4529 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4532 &bar0->prc_pcix_err_reg,
4533 &sw_stat->prc_pcix_err_cnt))
4535 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4538 &bar0->prc_pcix_err_reg,
4539 &sw_stat->prc_pcix_err_cnt);
4542 if (val64 & RXDMA_INT_RPA_INT_M) {
4543 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4545 &sw_stat->rpa_err_cnt))
4547 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4549 &sw_stat->rpa_err_cnt);
4552 if (val64 & RXDMA_INT_RDA_INT_M) {
4553 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4554 RDA_FRM_ECC_DB_N_AERR |
4557 RDA_RXD_ECC_DB_SERR,
4559 &sw_stat->rda_err_cnt))
4561 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4562 RDA_FRM_ECC_SG_ERR |
4566 &sw_stat->rda_err_cnt);
4569 if (val64 & RXDMA_INT_RTI_INT_M) {
4570 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4572 &sw_stat->rti_err_cnt))
4574 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4576 &sw_stat->rti_err_cnt);
4579 val64 = readq(&bar0->mac_int_status);
4580 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4581 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4582 &bar0->mac_rmac_err_reg,
4583 &sw_stat->mac_rmac_err_cnt))
4585 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4586 RMAC_SINGLE_ECC_ERR |
4587 RMAC_DOUBLE_ECC_ERR,
4588 &bar0->mac_rmac_err_reg,
4589 &sw_stat->mac_rmac_err_cnt);
4592 val64 = readq(&bar0->xgxs_int_status);
4593 if (val64 & XGXS_INT_STATUS_RXGXS) {
4594 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4595 &bar0->xgxs_rxgxs_err_reg,
4596 &sw_stat->xgxs_rxgxs_err_cnt))
4600 val64 = readq(&bar0->mc_int_status);
4601 if (val64 & MC_INT_STATUS_MC_INT) {
4602 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4604 &sw_stat->mc_err_cnt))
4607 /* Handling Ecc errors */
4608 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4609 writeq(val64, &bar0->mc_err_reg);
4610 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4611 sw_stat->double_ecc_errs++;
4612 if (sp->device_type != XFRAME_II_DEVICE) {
4614 * Reset XframeI only if critical error
4617 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4618 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4622 sw_stat->single_ecc_errs++;
4628 s2io_stop_all_tx_queue(sp);
4629 schedule_work(&sp->rst_timer_task);
4630 sw_stat->soft_reset_cnt++;
4634 * s2io_isr - ISR handler of the device .
4635 * @irq: the irq of the device.
4636 * @dev_id: a void pointer to the dev structure of the NIC.
4637 * Description: This function is the ISR handler of the device. It
4638 * identifies the reason for the interrupt and calls the relevant
4639 * service routines. As a contongency measure, this ISR allocates the
4640 * recv buffers, if their numbers are below the panic value which is
4641 * presently set to 25% of the original number of rcv buffers allocated.
4643 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4644 * IRQ_NONE: will be returned if interrupt is not from our device
4646 static irqreturn_t s2io_isr(int irq, void *dev_id)
4648 struct net_device *dev = (struct net_device *)dev_id;
4649 struct s2io_nic *sp = netdev_priv(dev);
4650 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4653 struct mac_info *mac_control;
4654 struct config_param *config;
4656 /* Pretend we handled any irq's from a disconnected card */
4657 if (pci_channel_offline(sp->pdev))
4660 if (!is_s2io_card_up(sp))
4663 config = &sp->config;
4664 mac_control = &sp->mac_control;
4667 * Identify the cause for interrupt and call the appropriate
4668 * interrupt handler. Causes for the interrupt could be;
4673 reason = readq(&bar0->general_int_status);
4675 if (unlikely(reason == S2IO_MINUS_ONE))
4676 return IRQ_HANDLED; /* Nothing much can be done. Get out */
4679 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4680 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4683 if (reason & GEN_INTR_RXTRAFFIC) {
4684 napi_schedule(&sp->napi);
4685 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4686 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4687 readl(&bar0->rx_traffic_int);
4691 * rx_traffic_int reg is an R1 register, writing all 1's
4692 * will ensure that the actual interrupt causing bit
4693 * get's cleared and hence a read can be avoided.
4695 if (reason & GEN_INTR_RXTRAFFIC)
4696 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4698 for (i = 0; i < config->rx_ring_num; i++) {
4699 struct ring_info *ring = &mac_control->rings[i];
4701 rx_intr_handler(ring, 0);
4706 * tx_traffic_int reg is an R1 register, writing all 1's
4707 * will ensure that the actual interrupt causing bit get's
4708 * cleared and hence a read can be avoided.
4710 if (reason & GEN_INTR_TXTRAFFIC)
4711 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4713 for (i = 0; i < config->tx_fifo_num; i++)
4714 tx_intr_handler(&mac_control->fifos[i]);
4716 if (reason & GEN_INTR_TXPIC)
4717 s2io_txpic_intr_handle(sp);
4720 * Reallocate the buffers from the interrupt handler itself.
4722 if (!config->napi) {
4723 for (i = 0; i < config->rx_ring_num; i++) {
4724 struct ring_info *ring = &mac_control->rings[i];
4726 s2io_chk_rx_buffers(sp, ring);
4729 writeq(sp->general_int_mask, &bar0->general_int_mask);
4730 readl(&bar0->general_int_status);
4734 } else if (!reason) {
4735 /* The interrupt was not raised by us */
4745 static void s2io_updt_stats(struct s2io_nic *sp)
4747 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4751 if (is_s2io_card_up(sp)) {
4752 /* Apprx 30us on a 133 MHz bus */
4753 val64 = SET_UPDT_CLICKS(10) |
4754 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4755 writeq(val64, &bar0->stat_cfg);
4758 val64 = readq(&bar0->stat_cfg);
4759 if (!(val64 & s2BIT(0)))
4763 break; /* Updt failed */
4769 * s2io_get_stats - Updates the device statistics structure.
4770 * @dev : pointer to the device structure.
4772 * This function updates the device statistics structure in the s2io_nic
4773 * structure and returns a pointer to the same.
4775 * pointer to the updated net_device_stats structure.
4777 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4779 struct s2io_nic *sp = netdev_priv(dev);
4780 struct mac_info *mac_control = &sp->mac_control;
4781 struct stat_block *stats = mac_control->stats_info;
4784 /* Configure Stats for immediate updt */
4785 s2io_updt_stats(sp);
4787 /* A device reset will cause the on-adapter statistics to be zero'ed.
4788 * This can be done while running by changing the MTU. To prevent the
4789 * system from having the stats zero'ed, the driver keeps a copy of the
4790 * last update to the system (which is also zero'ed on reset). This
4791 * enables the driver to accurately know the delta between the last
4792 * update and the current update.
4794 delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4795 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4796 sp->stats.rx_packets += delta;
4797 dev->stats.rx_packets += delta;
4799 delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4800 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4801 sp->stats.tx_packets += delta;
4802 dev->stats.tx_packets += delta;
4804 delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4805 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4806 sp->stats.rx_bytes += delta;
4807 dev->stats.rx_bytes += delta;
4809 delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4810 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4811 sp->stats.tx_bytes += delta;
4812 dev->stats.tx_bytes += delta;
4814 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4815 sp->stats.rx_errors += delta;
4816 dev->stats.rx_errors += delta;
4818 delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4819 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4820 sp->stats.tx_errors += delta;
4821 dev->stats.tx_errors += delta;
4823 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4824 sp->stats.rx_dropped += delta;
4825 dev->stats.rx_dropped += delta;
4827 delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4828 sp->stats.tx_dropped += delta;
4829 dev->stats.tx_dropped += delta;
4831 /* The adapter MAC interprets pause frames as multicast packets, but
4832 * does not pass them up. This erroneously increases the multicast
4833 * packet count and needs to be deducted when the multicast frame count
4836 delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4837 le32_to_cpu(stats->rmac_vld_mcst_frms);
4838 delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4839 delta -= sp->stats.multicast;
4840 sp->stats.multicast += delta;
4841 dev->stats.multicast += delta;
4843 delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4844 le32_to_cpu(stats->rmac_usized_frms)) +
4845 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4846 sp->stats.rx_length_errors += delta;
4847 dev->stats.rx_length_errors += delta;
4849 delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4850 sp->stats.rx_crc_errors += delta;
4851 dev->stats.rx_crc_errors += delta;
4857 * s2io_set_multicast - entry point for multicast address enable/disable.
4858 * @dev : pointer to the device structure
4860 * This function is a driver entry point which gets called by the kernel
4861 * whenever multicast addresses must be enabled/disabled. This also gets
4862 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4863 * determine, if multicast address must be enabled or if promiscuous mode
4864 * is to be disabled etc.
4869 static void s2io_set_multicast(struct net_device *dev)
4872 struct netdev_hw_addr *ha;
4873 struct s2io_nic *sp = netdev_priv(dev);
4874 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4875 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4877 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4879 struct config_param *config = &sp->config;
4881 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4882 /* Enable all Multicast addresses */
4883 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4884 &bar0->rmac_addr_data0_mem);
4885 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4886 &bar0->rmac_addr_data1_mem);
4887 val64 = RMAC_ADDR_CMD_MEM_WE |
4888 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4889 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4890 writeq(val64, &bar0->rmac_addr_cmd_mem);
4891 /* Wait till command completes */
4892 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4893 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4897 sp->all_multi_pos = config->max_mc_addr - 1;
4898 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4899 /* Disable all Multicast addresses */
4900 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4901 &bar0->rmac_addr_data0_mem);
4902 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4903 &bar0->rmac_addr_data1_mem);
4904 val64 = RMAC_ADDR_CMD_MEM_WE |
4905 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4906 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4907 writeq(val64, &bar0->rmac_addr_cmd_mem);
4908 /* Wait till command completes */
4909 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4910 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4914 sp->all_multi_pos = 0;
4917 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4918 /* Put the NIC into promiscuous mode */
4919 add = &bar0->mac_cfg;
4920 val64 = readq(&bar0->mac_cfg);
4921 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4923 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4924 writel((u32)val64, add);
4925 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4926 writel((u32) (val64 >> 32), (add + 4));
4928 if (vlan_tag_strip != 1) {
4929 val64 = readq(&bar0->rx_pa_cfg);
4930 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4931 writeq(val64, &bar0->rx_pa_cfg);
4932 sp->vlan_strip_flag = 0;
4935 val64 = readq(&bar0->mac_cfg);
4936 sp->promisc_flg = 1;
4937 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4939 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4940 /* Remove the NIC from promiscuous mode */
4941 add = &bar0->mac_cfg;
4942 val64 = readq(&bar0->mac_cfg);
4943 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4945 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4946 writel((u32)val64, add);
4947 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4948 writel((u32) (val64 >> 32), (add + 4));
4950 if (vlan_tag_strip != 0) {
4951 val64 = readq(&bar0->rx_pa_cfg);
4952 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4953 writeq(val64, &bar0->rx_pa_cfg);
4954 sp->vlan_strip_flag = 1;
4957 val64 = readq(&bar0->mac_cfg);
4958 sp->promisc_flg = 0;
4959 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
4962 /* Update individual M_CAST address list */
4963 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
4964 if (netdev_mc_count(dev) >
4965 (config->max_mc_addr - config->max_mac_addr)) {
4967 "%s: No more Rx filters can be added - "
4968 "please enable ALL_MULTI instead\n",
4973 prev_cnt = sp->mc_addr_count;
4974 sp->mc_addr_count = netdev_mc_count(dev);
4976 /* Clear out the previous list of Mc in the H/W. */
4977 for (i = 0; i < prev_cnt; i++) {
4978 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4979 &bar0->rmac_addr_data0_mem);
4980 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4981 &bar0->rmac_addr_data1_mem);
4982 val64 = RMAC_ADDR_CMD_MEM_WE |
4983 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4984 RMAC_ADDR_CMD_MEM_OFFSET
4985 (config->mc_start_offset + i);
4986 writeq(val64, &bar0->rmac_addr_cmd_mem);
4988 /* Wait for command completes */
4989 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4990 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4993 "%s: Adding Multicasts failed\n",
4999 /* Create the new Rx filter list and update the same in H/W. */
5001 netdev_for_each_mc_addr(ha, dev) {
5003 for (j = 0; j < ETH_ALEN; j++) {
5004 mac_addr |= ha->addr[j];
5008 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5009 &bar0->rmac_addr_data0_mem);
5010 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5011 &bar0->rmac_addr_data1_mem);
5012 val64 = RMAC_ADDR_CMD_MEM_WE |
5013 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5014 RMAC_ADDR_CMD_MEM_OFFSET
5015 (i + config->mc_start_offset);
5016 writeq(val64, &bar0->rmac_addr_cmd_mem);
5018 /* Wait for command completes */
5019 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5020 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5023 "%s: Adding Multicasts failed\n",
5032 /* read from CAM unicast & multicast addresses and store it in
5033 * def_mac_addr structure
5035 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5039 struct config_param *config = &sp->config;
5041 /* store unicast & multicast mac addresses */
5042 for (offset = 0; offset < config->max_mc_addr; offset++) {
5043 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5044 /* if read fails disable the entry */
5045 if (mac_addr == FAILURE)
5046 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5047 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5051 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5052 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5055 struct config_param *config = &sp->config;
5056 /* restore unicast mac address */
5057 for (offset = 0; offset < config->max_mac_addr; offset++)
5058 do_s2io_prog_unicast(sp->dev,
5059 sp->def_mac_addr[offset].mac_addr);
5061 /* restore multicast mac address */
5062 for (offset = config->mc_start_offset;
5063 offset < config->max_mc_addr; offset++)
5064 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5067 /* add a multicast MAC address to CAM */
5068 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5072 struct config_param *config = &sp->config;
5074 for (i = 0; i < ETH_ALEN; i++) {
5076 mac_addr |= addr[i];
5078 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5081 /* check if the multicast mac already preset in CAM */
5082 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5084 tmp64 = do_s2io_read_unicast_mc(sp, i);
5085 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5088 if (tmp64 == mac_addr)
5091 if (i == config->max_mc_addr) {
5093 "CAM full no space left for multicast MAC\n");
5096 /* Update the internal structure with this new mac address */
5097 do_s2io_copy_mac_addr(sp, i, mac_addr);
5099 return do_s2io_add_mac(sp, mac_addr, i);
5102 /* add MAC address to CAM */
5103 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5106 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5108 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5109 &bar0->rmac_addr_data0_mem);
5111 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5112 RMAC_ADDR_CMD_MEM_OFFSET(off);
5113 writeq(val64, &bar0->rmac_addr_cmd_mem);
5115 /* Wait till command completes */
5116 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5117 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5119 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5124 /* deletes a specified unicast/multicast mac entry from CAM */
5125 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5128 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5129 struct config_param *config = &sp->config;
5132 offset < config->max_mc_addr; offset++) {
5133 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5134 if (tmp64 == addr) {
5135 /* disable the entry by writing 0xffffffffffffULL */
5136 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5138 /* store the new mac list from CAM */
5139 do_s2io_store_unicast_mc(sp);
5143 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5144 (unsigned long long)addr);
5148 /* read mac entries from CAM */
5149 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5152 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5155 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5156 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5157 writeq(val64, &bar0->rmac_addr_cmd_mem);
5159 /* Wait till command completes */
5160 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5161 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5163 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5166 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5172 * s2io_set_mac_addr - driver entry point
5175 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5177 struct sockaddr *addr = p;
5179 if (!is_valid_ether_addr(addr->sa_data))
5180 return -EADDRNOTAVAIL;
5182 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5184 /* store the MAC address in CAM */
5185 return do_s2io_prog_unicast(dev, dev->dev_addr);
5188 * do_s2io_prog_unicast - Programs the Xframe mac address
5189 * @dev : pointer to the device structure.
5190 * @addr: a uchar pointer to the new mac address which is to be set.
5191 * Description : This procedure will program the Xframe to receive
5192 * frames with new Mac Address
5193 * Return value: SUCCESS on success and an appropriate (-)ve integer
5194 * as defined in errno.h file on failure.
5197 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5199 struct s2io_nic *sp = netdev_priv(dev);
5200 register u64 mac_addr = 0, perm_addr = 0;
5203 struct config_param *config = &sp->config;
5206 * Set the new MAC address as the new unicast filter and reflect this
5207 * change on the device address registered with the OS. It will be
5210 for (i = 0; i < ETH_ALEN; i++) {
5212 mac_addr |= addr[i];
5214 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5217 /* check if the dev_addr is different than perm_addr */
5218 if (mac_addr == perm_addr)
5221 /* check if the mac already preset in CAM */
5222 for (i = 1; i < config->max_mac_addr; i++) {
5223 tmp64 = do_s2io_read_unicast_mc(sp, i);
5224 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5227 if (tmp64 == mac_addr) {
5229 "MAC addr:0x%llx already present in CAM\n",
5230 (unsigned long long)mac_addr);
5234 if (i == config->max_mac_addr) {
5235 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5238 /* Update the internal structure with this new mac address */
5239 do_s2io_copy_mac_addr(sp, i, mac_addr);
5241 return do_s2io_add_mac(sp, mac_addr, i);
5245 * s2io_ethtool_set_link_ksettings - Sets different link parameters.
5246 * @sp : private member of the device structure, which is a pointer to the
5247 * s2io_nic structure.
5248 * @cmd: pointer to the structure with parameters given by ethtool to set
5251 * The function sets different link parameters provided by the user onto
5258 s2io_ethtool_set_link_ksettings(struct net_device *dev,
5259 const struct ethtool_link_ksettings *cmd)
5261 struct s2io_nic *sp = netdev_priv(dev);
5262 if ((cmd->base.autoneg == AUTONEG_ENABLE) ||
5263 (cmd->base.speed != SPEED_10000) ||
5264 (cmd->base.duplex != DUPLEX_FULL))
5267 s2io_close(sp->dev);
5275 * s2io_ethtol_get_link_ksettings - Return link specific information.
5276 * @sp : private member of the device structure, pointer to the
5277 * s2io_nic structure.
5278 * @cmd : pointer to the structure with parameters given by ethtool
5279 * to return link information.
5281 * Returns link specific information like speed, duplex etc.. to ethtool.
5283 * return 0 on success.
5287 s2io_ethtool_get_link_ksettings(struct net_device *dev,
5288 struct ethtool_link_ksettings *cmd)
5290 struct s2io_nic *sp = netdev_priv(dev);
5292 ethtool_link_ksettings_zero_link_mode(cmd, supported);
5293 ethtool_link_ksettings_add_link_mode(cmd, supported, 10000baseT_Full);
5294 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
5296 ethtool_link_ksettings_zero_link_mode(cmd, advertising);
5297 ethtool_link_ksettings_add_link_mode(cmd, advertising, 10000baseT_Full);
5298 ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
5300 cmd->base.port = PORT_FIBRE;
5302 if (netif_carrier_ok(sp->dev)) {
5303 cmd->base.speed = SPEED_10000;
5304 cmd->base.duplex = DUPLEX_FULL;
5306 cmd->base.speed = SPEED_UNKNOWN;
5307 cmd->base.duplex = DUPLEX_UNKNOWN;
5310 cmd->base.autoneg = AUTONEG_DISABLE;
5315 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5316 * @sp : private member of the device structure, which is a pointer to the
5317 * s2io_nic structure.
5318 * @info : pointer to the structure with parameters given by ethtool to
5319 * return driver information.
5321 * Returns driver specefic information like name, version etc.. to ethtool.
5326 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5327 struct ethtool_drvinfo *info)
5329 struct s2io_nic *sp = netdev_priv(dev);
5331 strlcpy(info->driver, s2io_driver_name, sizeof(info->driver));
5332 strlcpy(info->version, s2io_driver_version, sizeof(info->version));
5333 strlcpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5337 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5338 * @sp: private member of the device structure, which is a pointer to the
5339 * s2io_nic structure.
5340 * @regs : pointer to the structure with parameters given by ethtool for
5341 * dumping the registers.
5342 * @reg_space: The input argument into which all the registers are dumped.
5344 * Dumps the entire register space of xFrame NIC into the user given
5350 static void s2io_ethtool_gregs(struct net_device *dev,
5351 struct ethtool_regs *regs, void *space)
5355 u8 *reg_space = (u8 *)space;
5356 struct s2io_nic *sp = netdev_priv(dev);
5358 regs->len = XENA_REG_SPACE;
5359 regs->version = sp->pdev->subsystem_device;
5361 for (i = 0; i < regs->len; i += 8) {
5362 reg = readq(sp->bar0 + i);
5363 memcpy((reg_space + i), ®, 8);
5368 * s2io_set_led - control NIC led
5370 static void s2io_set_led(struct s2io_nic *sp, bool on)
5372 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5373 u16 subid = sp->pdev->subsystem_device;
5376 if ((sp->device_type == XFRAME_II_DEVICE) ||
5377 ((subid & 0xFF) >= 0x07)) {
5378 val64 = readq(&bar0->gpio_control);
5380 val64 |= GPIO_CTRL_GPIO_0;
5382 val64 &= ~GPIO_CTRL_GPIO_0;
5384 writeq(val64, &bar0->gpio_control);
5386 val64 = readq(&bar0->adapter_control);
5388 val64 |= ADAPTER_LED_ON;
5390 val64 &= ~ADAPTER_LED_ON;
5392 writeq(val64, &bar0->adapter_control);
5398 * s2io_ethtool_set_led - To physically identify the nic on the system.
5399 * @dev : network device
5400 * @state: led setting
5402 * Description: Used to physically identify the NIC on the system.
5403 * The Link LED will blink for a time specified by the user for
5405 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5406 * identification is possible only if it's link is up.
5409 static int s2io_ethtool_set_led(struct net_device *dev,
5410 enum ethtool_phys_id_state state)
5412 struct s2io_nic *sp = netdev_priv(dev);
5413 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5414 u16 subid = sp->pdev->subsystem_device;
5416 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5417 u64 val64 = readq(&bar0->adapter_control);
5418 if (!(val64 & ADAPTER_CNTL_EN)) {
5419 pr_err("Adapter Link down, cannot blink LED\n");
5425 case ETHTOOL_ID_ACTIVE:
5426 sp->adapt_ctrl_org = readq(&bar0->gpio_control);
5427 return 1; /* cycle on/off once per second */
5430 s2io_set_led(sp, true);
5433 case ETHTOOL_ID_OFF:
5434 s2io_set_led(sp, false);
5437 case ETHTOOL_ID_INACTIVE:
5438 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid))
5439 writeq(sp->adapt_ctrl_org, &bar0->gpio_control);
5445 static void s2io_ethtool_gringparam(struct net_device *dev,
5446 struct ethtool_ringparam *ering)
5448 struct s2io_nic *sp = netdev_priv(dev);
5449 int i, tx_desc_count = 0, rx_desc_count = 0;
5451 if (sp->rxd_mode == RXD_MODE_1) {
5452 ering->rx_max_pending = MAX_RX_DESC_1;
5453 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5455 ering->rx_max_pending = MAX_RX_DESC_2;
5456 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5459 ering->tx_max_pending = MAX_TX_DESC;
5461 for (i = 0; i < sp->config.rx_ring_num; i++)
5462 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5463 ering->rx_pending = rx_desc_count;
5464 ering->rx_jumbo_pending = rx_desc_count;
5466 for (i = 0; i < sp->config.tx_fifo_num; i++)
5467 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5468 ering->tx_pending = tx_desc_count;
5469 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5473 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5474 * @sp : private member of the device structure, which is a pointer to the
5475 * s2io_nic structure.
5476 * @ep : pointer to the structure with pause parameters given by ethtool.
5478 * Returns the Pause frame generation and reception capability of the NIC.
5482 static void s2io_ethtool_getpause_data(struct net_device *dev,
5483 struct ethtool_pauseparam *ep)
5486 struct s2io_nic *sp = netdev_priv(dev);
5487 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5489 val64 = readq(&bar0->rmac_pause_cfg);
5490 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5491 ep->tx_pause = true;
5492 if (val64 & RMAC_PAUSE_RX_ENABLE)
5493 ep->rx_pause = true;
5494 ep->autoneg = false;
5498 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5499 * @sp : private member of the device structure, which is a pointer to the
5500 * s2io_nic structure.
5501 * @ep : pointer to the structure with pause parameters given by ethtool.
5503 * It can be used to set or reset Pause frame generation or reception
5504 * support of the NIC.
5506 * int, returns 0 on Success
5509 static int s2io_ethtool_setpause_data(struct net_device *dev,
5510 struct ethtool_pauseparam *ep)
5513 struct s2io_nic *sp = netdev_priv(dev);
5514 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5516 val64 = readq(&bar0->rmac_pause_cfg);
5518 val64 |= RMAC_PAUSE_GEN_ENABLE;
5520 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5522 val64 |= RMAC_PAUSE_RX_ENABLE;
5524 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5525 writeq(val64, &bar0->rmac_pause_cfg);
5530 * read_eeprom - reads 4 bytes of data from user given offset.
5531 * @sp : private member of the device structure, which is a pointer to the
5532 * s2io_nic structure.
5533 * @off : offset at which the data must be written
5534 * @data : Its an output parameter where the data read at the given
5537 * Will read 4 bytes of data from the user given offset and return the
5539 * NOTE: Will allow to read only part of the EEPROM visible through the
5542 * -1 on failure and 0 on success.
5545 #define S2IO_DEV_ID 5
5546 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5551 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5553 if (sp->device_type == XFRAME_I_DEVICE) {
5554 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5555 I2C_CONTROL_ADDR(off) |
5556 I2C_CONTROL_BYTE_CNT(0x3) |
5558 I2C_CONTROL_CNTL_START;
5559 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5561 while (exit_cnt < 5) {
5562 val64 = readq(&bar0->i2c_control);
5563 if (I2C_CONTROL_CNTL_END(val64)) {
5564 *data = I2C_CONTROL_GET_DATA(val64);
5573 if (sp->device_type == XFRAME_II_DEVICE) {
5574 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5575 SPI_CONTROL_BYTECNT(0x3) |
5576 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5577 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5578 val64 |= SPI_CONTROL_REQ;
5579 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5580 while (exit_cnt < 5) {
5581 val64 = readq(&bar0->spi_control);
5582 if (val64 & SPI_CONTROL_NACK) {
5585 } else if (val64 & SPI_CONTROL_DONE) {
5586 *data = readq(&bar0->spi_data);
5599 * write_eeprom - actually writes the relevant part of the data value.
5600 * @sp : private member of the device structure, which is a pointer to the
5601 * s2io_nic structure.
5602 * @off : offset at which the data must be written
5603 * @data : The data that is to be written
5604 * @cnt : Number of bytes of the data that are actually to be written into
5605 * the Eeprom. (max of 3)
5607 * Actually writes the relevant part of the data value into the Eeprom
5608 * through the I2C bus.
5610 * 0 on success, -1 on failure.
5613 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5615 int exit_cnt = 0, ret = -1;
5617 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5619 if (sp->device_type == XFRAME_I_DEVICE) {
5620 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5621 I2C_CONTROL_ADDR(off) |
5622 I2C_CONTROL_BYTE_CNT(cnt) |
5623 I2C_CONTROL_SET_DATA((u32)data) |
5624 I2C_CONTROL_CNTL_START;
5625 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5627 while (exit_cnt < 5) {
5628 val64 = readq(&bar0->i2c_control);
5629 if (I2C_CONTROL_CNTL_END(val64)) {
5630 if (!(val64 & I2C_CONTROL_NACK))
5639 if (sp->device_type == XFRAME_II_DEVICE) {
5640 int write_cnt = (cnt == 8) ? 0 : cnt;
5641 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5643 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5644 SPI_CONTROL_BYTECNT(write_cnt) |
5645 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5646 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5647 val64 |= SPI_CONTROL_REQ;
5648 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5649 while (exit_cnt < 5) {
5650 val64 = readq(&bar0->spi_control);
5651 if (val64 & SPI_CONTROL_NACK) {
5654 } else if (val64 & SPI_CONTROL_DONE) {
5664 static void s2io_vpd_read(struct s2io_nic *nic)
5668 int i = 0, cnt, len, fail = 0;
5669 int vpd_addr = 0x80;
5670 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5672 if (nic->device_type == XFRAME_II_DEVICE) {
5673 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5676 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5679 strcpy(nic->serial_num, "NOT AVAILABLE");
5681 vpd_data = kmalloc(256, GFP_KERNEL);
5683 swstats->mem_alloc_fail_cnt++;
5686 swstats->mem_allocated += 256;
5688 for (i = 0; i < 256; i += 4) {
5689 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5690 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5691 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5692 for (cnt = 0; cnt < 5; cnt++) {
5694 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5699 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5703 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5704 (u32 *)&vpd_data[i]);
5708 /* read serial number of adapter */
5709 for (cnt = 0; cnt < 252; cnt++) {
5710 if ((vpd_data[cnt] == 'S') &&
5711 (vpd_data[cnt+1] == 'N')) {
5712 len = vpd_data[cnt+2];
5713 if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5714 memcpy(nic->serial_num,
5717 memset(nic->serial_num+len,
5719 VPD_STRING_LEN-len);
5726 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5728 memcpy(nic->product_name, &vpd_data[3], len);
5729 nic->product_name[len] = 0;
5732 swstats->mem_freed += 256;
5736 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5737 * @sp : private member of the device structure, which is a pointer to the
5738 * s2io_nic structure.
5739 * @eeprom : pointer to the user level structure provided by ethtool,
5740 * containing all relevant information.
5741 * @data_buf : user defined value to be written into Eeprom.
5742 * Description: Reads the values stored in the Eeprom at given offset
5743 * for a given length. Stores these values int the input argument data
5744 * buffer 'data_buf' and returns these to the caller (ethtool.)
5749 static int s2io_ethtool_geeprom(struct net_device *dev,
5750 struct ethtool_eeprom *eeprom, u8 * data_buf)
5754 struct s2io_nic *sp = netdev_priv(dev);
5756 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5758 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5759 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5761 for (i = 0; i < eeprom->len; i += 4) {
5762 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5763 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5767 memcpy((data_buf + i), &valid, 4);
5773 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5774 * @sp : private member of the device structure, which is a pointer to the
5775 * s2io_nic structure.
5776 * @eeprom : pointer to the user level structure provided by ethtool,
5777 * containing all relevant information.
5778 * @data_buf ; user defined value to be written into Eeprom.
5780 * Tries to write the user provided value in the Eeprom, at the offset
5781 * given by the user.
5783 * 0 on success, -EFAULT on failure.
5786 static int s2io_ethtool_seeprom(struct net_device *dev,
5787 struct ethtool_eeprom *eeprom,
5790 int len = eeprom->len, cnt = 0;
5791 u64 valid = 0, data;
5792 struct s2io_nic *sp = netdev_priv(dev);
5794 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5796 "ETHTOOL_WRITE_EEPROM Err: "
5797 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5798 (sp->pdev->vendor | (sp->pdev->device << 16)),
5804 data = (u32)data_buf[cnt] & 0x000000FF;
5806 valid = (u32)(data << 24);
5810 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5812 "ETHTOOL_WRITE_EEPROM Err: "
5813 "Cannot write into the specified offset\n");
5824 * s2io_register_test - reads and writes into all clock domains.
5825 * @sp : private member of the device structure, which is a pointer to the
5826 * s2io_nic structure.
5827 * @data : variable that returns the result of each of the test conducted b
5830 * Read and write into all clock domains. The NIC has 3 clock domains,
5831 * see that registers in all the three regions are accessible.
5836 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5838 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5839 u64 val64 = 0, exp_val;
5842 val64 = readq(&bar0->pif_rd_swapper_fb);
5843 if (val64 != 0x123456789abcdefULL) {
5845 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5848 val64 = readq(&bar0->rmac_pause_cfg);
5849 if (val64 != 0xc000ffff00000000ULL) {
5851 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5854 val64 = readq(&bar0->rx_queue_cfg);
5855 if (sp->device_type == XFRAME_II_DEVICE)
5856 exp_val = 0x0404040404040404ULL;
5858 exp_val = 0x0808080808080808ULL;
5859 if (val64 != exp_val) {
5861 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5864 val64 = readq(&bar0->xgxs_efifo_cfg);
5865 if (val64 != 0x000000001923141EULL) {
5867 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5870 val64 = 0x5A5A5A5A5A5A5A5AULL;
5871 writeq(val64, &bar0->xmsi_data);
5872 val64 = readq(&bar0->xmsi_data);
5873 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5875 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
5878 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5879 writeq(val64, &bar0->xmsi_data);
5880 val64 = readq(&bar0->xmsi_data);
5881 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5883 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
5891 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5892 * @sp : private member of the device structure, which is a pointer to the
5893 * s2io_nic structure.
5894 * @data:variable that returns the result of each of the test conducted by
5897 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5903 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
5906 u64 ret_data, org_4F0, org_7F0;
5907 u8 saved_4F0 = 0, saved_7F0 = 0;
5908 struct net_device *dev = sp->dev;
5910 /* Test Write Error at offset 0 */
5911 /* Note that SPI interface allows write access to all areas
5912 * of EEPROM. Hence doing all negative testing only for Xframe I.
5914 if (sp->device_type == XFRAME_I_DEVICE)
5915 if (!write_eeprom(sp, 0, 0, 3))
5918 /* Save current values at offsets 0x4F0 and 0x7F0 */
5919 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5921 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5924 /* Test Write at offset 4f0 */
5925 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5927 if (read_eeprom(sp, 0x4F0, &ret_data))
5930 if (ret_data != 0x012345) {
5931 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5932 "Data written %llx Data read %llx\n",
5933 dev->name, (unsigned long long)0x12345,
5934 (unsigned long long)ret_data);
5938 /* Reset the EEPROM data go FFFF */
5939 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5941 /* Test Write Request Error at offset 0x7c */
5942 if (sp->device_type == XFRAME_I_DEVICE)
5943 if (!write_eeprom(sp, 0x07C, 0, 3))
5946 /* Test Write Request at offset 0x7f0 */
5947 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5949 if (read_eeprom(sp, 0x7F0, &ret_data))
5952 if (ret_data != 0x012345) {
5953 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5954 "Data written %llx Data read %llx\n",
5955 dev->name, (unsigned long long)0x12345,
5956 (unsigned long long)ret_data);
5960 /* Reset the EEPROM data go FFFF */
5961 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5963 if (sp->device_type == XFRAME_I_DEVICE) {
5964 /* Test Write Error at offset 0x80 */
5965 if (!write_eeprom(sp, 0x080, 0, 3))
5968 /* Test Write Error at offset 0xfc */
5969 if (!write_eeprom(sp, 0x0FC, 0, 3))
5972 /* Test Write Error at offset 0x100 */
5973 if (!write_eeprom(sp, 0x100, 0, 3))
5976 /* Test Write Error at offset 4ec */
5977 if (!write_eeprom(sp, 0x4EC, 0, 3))
5981 /* Restore values at offsets 0x4F0 and 0x7F0 */
5983 write_eeprom(sp, 0x4F0, org_4F0, 3);
5985 write_eeprom(sp, 0x7F0, org_7F0, 3);
5992 * s2io_bist_test - invokes the MemBist test of the card .
5993 * @sp : private member of the device structure, which is a pointer to the
5994 * s2io_nic structure.
5995 * @data:variable that returns the result of each of the test conducted by
5998 * This invokes the MemBist test of the card. We give around
5999 * 2 secs time for the Test to complete. If it's still not complete
6000 * within this peiod, we consider that the test failed.
6002 * 0 on success and -1 on failure.
6005 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6008 int cnt = 0, ret = -1;
6010 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6011 bist |= PCI_BIST_START;
6012 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6015 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6016 if (!(bist & PCI_BIST_START)) {
6017 *data = (bist & PCI_BIST_CODE_MASK);
6029 * s2io_link_test - verifies the link state of the nic
6030 * @sp ; private member of the device structure, which is a pointer to the
6031 * s2io_nic structure.
6032 * @data: variable that returns the result of each of the test conducted by
6035 * The function verifies the link state of the NIC and updates the input
6036 * argument 'data' appropriately.
6041 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6043 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6046 val64 = readq(&bar0->adapter_status);
6047 if (!(LINK_IS_UP(val64)))
6056 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6057 * @sp: private member of the device structure, which is a pointer to the
6058 * s2io_nic structure.
6059 * @data: variable that returns the result of each of the test
6060 * conducted by the driver.
6062 * This is one of the offline test that tests the read and write
6063 * access to the RldRam chip on the NIC.
6068 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6070 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6072 int cnt, iteration = 0, test_fail = 0;
6074 val64 = readq(&bar0->adapter_control);
6075 val64 &= ~ADAPTER_ECC_EN;
6076 writeq(val64, &bar0->adapter_control);
6078 val64 = readq(&bar0->mc_rldram_test_ctrl);
6079 val64 |= MC_RLDRAM_TEST_MODE;
6080 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6082 val64 = readq(&bar0->mc_rldram_mrs);
6083 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6084 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6086 val64 |= MC_RLDRAM_MRS_ENABLE;
6087 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6089 while (iteration < 2) {
6090 val64 = 0x55555555aaaa0000ULL;
6092 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6093 writeq(val64, &bar0->mc_rldram_test_d0);
6095 val64 = 0xaaaa5a5555550000ULL;
6097 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6098 writeq(val64, &bar0->mc_rldram_test_d1);
6100 val64 = 0x55aaaaaaaa5a0000ULL;
6102 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6103 writeq(val64, &bar0->mc_rldram_test_d2);
6105 val64 = (u64) (0x0000003ffffe0100ULL);
6106 writeq(val64, &bar0->mc_rldram_test_add);
6108 val64 = MC_RLDRAM_TEST_MODE |
6109 MC_RLDRAM_TEST_WRITE |
6111 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6113 for (cnt = 0; cnt < 5; cnt++) {
6114 val64 = readq(&bar0->mc_rldram_test_ctrl);
6115 if (val64 & MC_RLDRAM_TEST_DONE)
6123 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6124 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6126 for (cnt = 0; cnt < 5; cnt++) {
6127 val64 = readq(&bar0->mc_rldram_test_ctrl);
6128 if (val64 & MC_RLDRAM_TEST_DONE)
6136 val64 = readq(&bar0->mc_rldram_test_ctrl);
6137 if (!(val64 & MC_RLDRAM_TEST_PASS))
6145 /* Bring the adapter out of test mode */
6146 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6152 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6153 * @sp : private member of the device structure, which is a pointer to the
6154 * s2io_nic structure.
6155 * @ethtest : pointer to a ethtool command specific structure that will be
6156 * returned to the user.
6157 * @data : variable that returns the result of each of the test
6158 * conducted by the driver.
6160 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6161 * the health of the card.
6166 static void s2io_ethtool_test(struct net_device *dev,
6167 struct ethtool_test *ethtest,
6170 struct s2io_nic *sp = netdev_priv(dev);
6171 int orig_state = netif_running(sp->dev);
6173 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6174 /* Offline Tests. */
6176 s2io_close(sp->dev);
6178 if (s2io_register_test(sp, &data[0]))
6179 ethtest->flags |= ETH_TEST_FL_FAILED;
6183 if (s2io_rldram_test(sp, &data[3]))
6184 ethtest->flags |= ETH_TEST_FL_FAILED;
6188 if (s2io_eeprom_test(sp, &data[1]))
6189 ethtest->flags |= ETH_TEST_FL_FAILED;
6191 if (s2io_bist_test(sp, &data[4]))
6192 ethtest->flags |= ETH_TEST_FL_FAILED;
6201 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6210 if (s2io_link_test(sp, &data[2]))
6211 ethtest->flags |= ETH_TEST_FL_FAILED;
6220 static void s2io_get_ethtool_stats(struct net_device *dev,
6221 struct ethtool_stats *estats,
6225 struct s2io_nic *sp = netdev_priv(dev);
6226 struct stat_block *stats = sp->mac_control.stats_info;
6227 struct swStat *swstats = &stats->sw_stat;
6228 struct xpakStat *xstats = &stats->xpak_stat;
6230 s2io_updt_stats(sp);
6232 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6233 le32_to_cpu(stats->tmac_frms);
6235 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6236 le32_to_cpu(stats->tmac_data_octets);
6237 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6239 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6240 le32_to_cpu(stats->tmac_mcst_frms);
6242 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6243 le32_to_cpu(stats->tmac_bcst_frms);
6244 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6246 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6247 le32_to_cpu(stats->tmac_ttl_octets);
6249 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6250 le32_to_cpu(stats->tmac_ucst_frms);
6252 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6253 le32_to_cpu(stats->tmac_nucst_frms);
6255 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6256 le32_to_cpu(stats->tmac_any_err_frms);
6257 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6258 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6260 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6261 le32_to_cpu(stats->tmac_vld_ip);
6263 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6264 le32_to_cpu(stats->tmac_drop_ip);
6266 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6267 le32_to_cpu(stats->tmac_icmp);
6269 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6270 le32_to_cpu(stats->tmac_rst_tcp);
6271 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6272 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6273 le32_to_cpu(stats->tmac_udp);
6275 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6276 le32_to_cpu(stats->rmac_vld_frms);
6278 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6279 le32_to_cpu(stats->rmac_data_octets);
6280 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6281 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6283 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6284 le32_to_cpu(stats->rmac_vld_mcst_frms);
6286 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6287 le32_to_cpu(stats->rmac_vld_bcst_frms);
6288 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6289 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6290 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6291 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6292 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6294 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6295 le32_to_cpu(stats->rmac_ttl_octets);
6297 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6298 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
6300 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6301 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6303 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6304 le32_to_cpu(stats->rmac_discarded_frms);
6306 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6307 << 32 | le32_to_cpu(stats->rmac_drop_events);
6308 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6309 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6311 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6312 le32_to_cpu(stats->rmac_usized_frms);
6314 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6315 le32_to_cpu(stats->rmac_osized_frms);
6317 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6318 le32_to_cpu(stats->rmac_frag_frms);
6320 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6321 le32_to_cpu(stats->rmac_jabber_frms);
6322 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6323 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6324 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6325 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6326 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6327 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6329 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6330 le32_to_cpu(stats->rmac_ip);
6331 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6332 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6334 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6335 le32_to_cpu(stats->rmac_drop_ip);
6337 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6338 le32_to_cpu(stats->rmac_icmp);
6339 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6341 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6342 le32_to_cpu(stats->rmac_udp);
6344 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6345 le32_to_cpu(stats->rmac_err_drp_udp);
6346 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6347 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6348 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6349 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6350 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6351 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6352 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6353 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6354 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6355 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6356 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6357 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6358 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6359 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6360 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6361 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6362 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6364 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6365 le32_to_cpu(stats->rmac_pause_cnt);
6366 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6367 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6369 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6370 le32_to_cpu(stats->rmac_accepted_ip);
6371 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6372 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6373 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6374 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6375 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6376 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6377 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6378 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6379 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6380 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6381 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6382 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6383 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6384 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6385 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6386 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6387 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6388 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6389 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6391 /* Enhanced statistics exist only for Hercules */
6392 if (sp->device_type == XFRAME_II_DEVICE) {
6394 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6396 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6398 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6399 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6400 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6401 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6402 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6403 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6404 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6405 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6406 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6407 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6408 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6409 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6410 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6411 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6415 tmp_stats[i++] = swstats->single_ecc_errs;
6416 tmp_stats[i++] = swstats->double_ecc_errs;
6417 tmp_stats[i++] = swstats->parity_err_cnt;
6418 tmp_stats[i++] = swstats->serious_err_cnt;
6419 tmp_stats[i++] = swstats->soft_reset_cnt;
6420 tmp_stats[i++] = swstats->fifo_full_cnt;
6421 for (k = 0; k < MAX_RX_RINGS; k++)
6422 tmp_stats[i++] = swstats->ring_full_cnt[k];
6423 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6424 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6425 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6426 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6427 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6428 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6429 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6430 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6431 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6432 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6433 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6434 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6435 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6436 tmp_stats[i++] = swstats->sending_both;
6437 tmp_stats[i++] = swstats->outof_sequence_pkts;
6438 tmp_stats[i++] = swstats->flush_max_pkts;
6439 if (swstats->num_aggregations) {
6440 u64 tmp = swstats->sum_avg_pkts_aggregated;
6443 * Since 64-bit divide does not work on all platforms,
6444 * do repeated subtraction.
6446 while (tmp >= swstats->num_aggregations) {
6447 tmp -= swstats->num_aggregations;
6450 tmp_stats[i++] = count;
6453 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6454 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6455 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6456 tmp_stats[i++] = swstats->mem_allocated;
6457 tmp_stats[i++] = swstats->mem_freed;
6458 tmp_stats[i++] = swstats->link_up_cnt;
6459 tmp_stats[i++] = swstats->link_down_cnt;
6460 tmp_stats[i++] = swstats->link_up_time;
6461 tmp_stats[i++] = swstats->link_down_time;
6463 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6464 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6465 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6466 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6467 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6469 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6470 tmp_stats[i++] = swstats->rx_abort_cnt;
6471 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6472 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6473 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6474 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6475 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6476 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6477 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6478 tmp_stats[i++] = swstats->tda_err_cnt;
6479 tmp_stats[i++] = swstats->pfc_err_cnt;
6480 tmp_stats[i++] = swstats->pcc_err_cnt;
6481 tmp_stats[i++] = swstats->tti_err_cnt;
6482 tmp_stats[i++] = swstats->tpa_err_cnt;
6483 tmp_stats[i++] = swstats->sm_err_cnt;
6484 tmp_stats[i++] = swstats->lso_err_cnt;
6485 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6486 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6487 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6488 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6489 tmp_stats[i++] = swstats->rc_err_cnt;
6490 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6491 tmp_stats[i++] = swstats->rpa_err_cnt;
6492 tmp_stats[i++] = swstats->rda_err_cnt;
6493 tmp_stats[i++] = swstats->rti_err_cnt;
6494 tmp_stats[i++] = swstats->mc_err_cnt;
6497 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6499 return XENA_REG_SPACE;
6503 static int s2io_get_eeprom_len(struct net_device *dev)
6505 return XENA_EEPROM_SPACE;
6508 static int s2io_get_sset_count(struct net_device *dev, int sset)
6510 struct s2io_nic *sp = netdev_priv(dev);
6514 return S2IO_TEST_LEN;
6516 switch (sp->device_type) {
6517 case XFRAME_I_DEVICE:
6518 return XFRAME_I_STAT_LEN;
6519 case XFRAME_II_DEVICE:
6520 return XFRAME_II_STAT_LEN;
6529 static void s2io_ethtool_get_strings(struct net_device *dev,
6530 u32 stringset, u8 *data)
6533 struct s2io_nic *sp = netdev_priv(dev);
6535 switch (stringset) {
6537 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6540 stat_size = sizeof(ethtool_xena_stats_keys);
6541 memcpy(data, ðtool_xena_stats_keys, stat_size);
6542 if (sp->device_type == XFRAME_II_DEVICE) {
6543 memcpy(data + stat_size,
6544 ðtool_enhanced_stats_keys,
6545 sizeof(ethtool_enhanced_stats_keys));
6546 stat_size += sizeof(ethtool_enhanced_stats_keys);
6549 memcpy(data + stat_size, ðtool_driver_stats_keys,
6550 sizeof(ethtool_driver_stats_keys));
6554 static int s2io_set_features(struct net_device *dev, netdev_features_t features)
6556 struct s2io_nic *sp = netdev_priv(dev);
6557 netdev_features_t changed = (features ^ dev->features) & NETIF_F_LRO;
6559 if (changed && netif_running(dev)) {
6562 s2io_stop_all_tx_queue(sp);
6564 dev->features = features;
6565 rc = s2io_card_up(sp);
6569 s2io_start_all_tx_queue(sp);
6577 static const struct ethtool_ops netdev_ethtool_ops = {
6578 .get_drvinfo = s2io_ethtool_gdrvinfo,
6579 .get_regs_len = s2io_ethtool_get_regs_len,
6580 .get_regs = s2io_ethtool_gregs,
6581 .get_link = ethtool_op_get_link,
6582 .get_eeprom_len = s2io_get_eeprom_len,
6583 .get_eeprom = s2io_ethtool_geeprom,
6584 .set_eeprom = s2io_ethtool_seeprom,
6585 .get_ringparam = s2io_ethtool_gringparam,
6586 .get_pauseparam = s2io_ethtool_getpause_data,
6587 .set_pauseparam = s2io_ethtool_setpause_data,
6588 .self_test = s2io_ethtool_test,
6589 .get_strings = s2io_ethtool_get_strings,
6590 .set_phys_id = s2io_ethtool_set_led,
6591 .get_ethtool_stats = s2io_get_ethtool_stats,
6592 .get_sset_count = s2io_get_sset_count,
6593 .get_link_ksettings = s2io_ethtool_get_link_ksettings,
6594 .set_link_ksettings = s2io_ethtool_set_link_ksettings,
6598 * s2io_ioctl - Entry point for the Ioctl
6599 * @dev : Device pointer.
6600 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6601 * a proprietary structure used to pass information to the driver.
6602 * @cmd : This is used to distinguish between the different commands that
6603 * can be passed to the IOCTL functions.
6605 * Currently there are no special functionality supported in IOCTL, hence
6606 * function always return EOPNOTSUPPORTED
6609 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6615 * s2io_change_mtu - entry point to change MTU size for the device.
6616 * @dev : device pointer.
6617 * @new_mtu : the new MTU size for the device.
6618 * Description: A driver entry point to change MTU size for the device.
6619 * Before changing the MTU the device must be stopped.
6621 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6625 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6627 struct s2io_nic *sp = netdev_priv(dev);
6631 if (netif_running(dev)) {
6632 s2io_stop_all_tx_queue(sp);
6634 ret = s2io_card_up(sp);
6636 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6640 s2io_wake_all_tx_queue(sp);
6641 } else { /* Device is down */
6642 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6643 u64 val64 = new_mtu;
6645 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6652 * s2io_set_link - Set the LInk status
6653 * @data: long pointer to device private structue
6654 * Description: Sets the link status for the adapter
6657 static void s2io_set_link(struct work_struct *work)
6659 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6661 struct net_device *dev = nic->dev;
6662 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6668 if (!netif_running(dev))
6671 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6672 /* The card is being reset, no point doing anything */
6676 subid = nic->pdev->subsystem_device;
6677 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6679 * Allow a small delay for the NICs self initiated
6680 * cleanup to complete.
6685 val64 = readq(&bar0->adapter_status);
6686 if (LINK_IS_UP(val64)) {
6687 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6688 if (verify_xena_quiescence(nic)) {
6689 val64 = readq(&bar0->adapter_control);
6690 val64 |= ADAPTER_CNTL_EN;
6691 writeq(val64, &bar0->adapter_control);
6692 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6693 nic->device_type, subid)) {
6694 val64 = readq(&bar0->gpio_control);
6695 val64 |= GPIO_CTRL_GPIO_0;
6696 writeq(val64, &bar0->gpio_control);
6697 val64 = readq(&bar0->gpio_control);
6699 val64 |= ADAPTER_LED_ON;
6700 writeq(val64, &bar0->adapter_control);
6702 nic->device_enabled_once = true;
6705 "%s: Error: device is not Quiescent\n",
6707 s2io_stop_all_tx_queue(nic);
6710 val64 = readq(&bar0->adapter_control);
6711 val64 |= ADAPTER_LED_ON;
6712 writeq(val64, &bar0->adapter_control);
6713 s2io_link(nic, LINK_UP);
6715 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6717 val64 = readq(&bar0->gpio_control);
6718 val64 &= ~GPIO_CTRL_GPIO_0;
6719 writeq(val64, &bar0->gpio_control);
6720 val64 = readq(&bar0->gpio_control);
6723 val64 = readq(&bar0->adapter_control);
6724 val64 = val64 & (~ADAPTER_LED_ON);
6725 writeq(val64, &bar0->adapter_control);
6726 s2io_link(nic, LINK_DOWN);
6728 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6734 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6736 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6737 u64 *temp2, int size)
6739 struct net_device *dev = sp->dev;
6740 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6742 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6743 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6746 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6748 * As Rx frame are not going to be processed,
6749 * using same mapped address for the Rxd
6752 rxdp1->Buffer0_ptr = *temp0;
6754 *skb = netdev_alloc_skb(dev, size);
6757 "%s: Out of memory to allocate %s\n",
6758 dev->name, "1 buf mode SKBs");
6759 stats->mem_alloc_fail_cnt++;
6762 stats->mem_allocated += (*skb)->truesize;
6763 /* storing the mapped addr in a temp variable
6764 * such it will be used for next rxd whose
6765 * Host Control is NULL
6767 rxdp1->Buffer0_ptr = *temp0 =
6768 dma_map_single(&sp->pdev->dev, (*skb)->data,
6769 size - NET_IP_ALIGN,
6771 if (dma_mapping_error(&sp->pdev->dev, rxdp1->Buffer0_ptr))
6772 goto memalloc_failed;
6773 rxdp->Host_Control = (unsigned long) (*skb);
6775 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6776 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6777 /* Two buffer Mode */
6779 rxdp3->Buffer2_ptr = *temp2;
6780 rxdp3->Buffer0_ptr = *temp0;
6781 rxdp3->Buffer1_ptr = *temp1;
6783 *skb = netdev_alloc_skb(dev, size);
6786 "%s: Out of memory to allocate %s\n",
6789 stats->mem_alloc_fail_cnt++;
6792 stats->mem_allocated += (*skb)->truesize;
6793 rxdp3->Buffer2_ptr = *temp2 =
6794 dma_map_single(&sp->pdev->dev, (*skb)->data,
6795 dev->mtu + 4, DMA_FROM_DEVICE);
6796 if (dma_mapping_error(&sp->pdev->dev, rxdp3->Buffer2_ptr))
6797 goto memalloc_failed;
6798 rxdp3->Buffer0_ptr = *temp0 =
6799 dma_map_single(&sp->pdev->dev, ba->ba_0,
6800 BUF0_LEN, DMA_FROM_DEVICE);
6801 if (dma_mapping_error(&sp->pdev->dev, rxdp3->Buffer0_ptr)) {
6802 dma_unmap_single(&sp->pdev->dev,
6803 (dma_addr_t)rxdp3->Buffer2_ptr,
6806 goto memalloc_failed;
6808 rxdp->Host_Control = (unsigned long) (*skb);
6810 /* Buffer-1 will be dummy buffer not used */
6811 rxdp3->Buffer1_ptr = *temp1 =
6812 dma_map_single(&sp->pdev->dev, ba->ba_1,
6813 BUF1_LEN, DMA_FROM_DEVICE);
6814 if (dma_mapping_error(&sp->pdev->dev, rxdp3->Buffer1_ptr)) {
6815 dma_unmap_single(&sp->pdev->dev,
6816 (dma_addr_t)rxdp3->Buffer0_ptr,
6817 BUF0_LEN, DMA_FROM_DEVICE);
6818 dma_unmap_single(&sp->pdev->dev,
6819 (dma_addr_t)rxdp3->Buffer2_ptr,
6822 goto memalloc_failed;
6829 stats->pci_map_fail_cnt++;
6830 stats->mem_freed += (*skb)->truesize;
6831 dev_kfree_skb(*skb);
6835 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6838 struct net_device *dev = sp->dev;
6839 if (sp->rxd_mode == RXD_MODE_1) {
6840 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
6841 } else if (sp->rxd_mode == RXD_MODE_3B) {
6842 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6843 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6844 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
6848 static int rxd_owner_bit_reset(struct s2io_nic *sp)
6850 int i, j, k, blk_cnt = 0, size;
6851 struct config_param *config = &sp->config;
6852 struct mac_info *mac_control = &sp->mac_control;
6853 struct net_device *dev = sp->dev;
6854 struct RxD_t *rxdp = NULL;
6855 struct sk_buff *skb = NULL;
6856 struct buffAdd *ba = NULL;
6857 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6859 /* Calculate the size based on ring mode */
6860 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6861 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6862 if (sp->rxd_mode == RXD_MODE_1)
6863 size += NET_IP_ALIGN;
6864 else if (sp->rxd_mode == RXD_MODE_3B)
6865 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6867 for (i = 0; i < config->rx_ring_num; i++) {
6868 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6869 struct ring_info *ring = &mac_control->rings[i];
6871 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
6873 for (j = 0; j < blk_cnt; j++) {
6874 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6875 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
6876 if (sp->rxd_mode == RXD_MODE_3B)
6877 ba = &ring->ba[j][k];
6878 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
6886 set_rxd_buffer_size(sp, rxdp, size);
6888 /* flip the Ownership bit to Hardware */
6889 rxdp->Control_1 |= RXD_OWN_XENA;
6897 static int s2io_add_isr(struct s2io_nic *sp)
6900 struct net_device *dev = sp->dev;
6903 if (sp->config.intr_type == MSI_X)
6904 ret = s2io_enable_msi_x(sp);
6906 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6907 sp->config.intr_type = INTA;
6911 * Store the values of the MSIX table in
6912 * the struct s2io_nic structure
6914 store_xmsi_data(sp);
6916 /* After proper initialization of H/W, register ISR */
6917 if (sp->config.intr_type == MSI_X) {
6918 int i, msix_rx_cnt = 0;
6920 for (i = 0; i < sp->num_entries; i++) {
6921 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
6922 if (sp->s2io_entries[i].type ==
6924 snprintf(sp->desc[i],
6925 sizeof(sp->desc[i]),
6928 err = request_irq(sp->entries[i].vector,
6929 s2io_msix_ring_handle,
6932 sp->s2io_entries[i].arg);
6933 } else if (sp->s2io_entries[i].type ==
6935 snprintf(sp->desc[i],
6936 sizeof(sp->desc[i]),
6939 err = request_irq(sp->entries[i].vector,
6940 s2io_msix_fifo_handle,
6943 sp->s2io_entries[i].arg);
6946 /* if either data or addr is zero print it. */
6947 if (!(sp->msix_info[i].addr &&
6948 sp->msix_info[i].data)) {
6950 "%s @Addr:0x%llx Data:0x%llx\n",
6952 (unsigned long long)
6953 sp->msix_info[i].addr,
6954 (unsigned long long)
6955 ntohl(sp->msix_info[i].data));
6959 remove_msix_isr(sp);
6962 "%s:MSI-X-%d registration "
6963 "failed\n", dev->name, i);
6966 "%s: Defaulting to INTA\n",
6968 sp->config.intr_type = INTA;
6971 sp->s2io_entries[i].in_use =
6972 MSIX_REGISTERED_SUCCESS;
6976 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
6978 "MSI-X-TX entries enabled through alarm vector\n");
6981 if (sp->config.intr_type == INTA) {
6982 err = request_irq(sp->pdev->irq, s2io_isr, IRQF_SHARED,
6985 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6993 static void s2io_rem_isr(struct s2io_nic *sp)
6995 if (sp->config.intr_type == MSI_X)
6996 remove_msix_isr(sp);
6998 remove_inta_isr(sp);
7001 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7004 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7005 register u64 val64 = 0;
7006 struct config_param *config;
7007 config = &sp->config;
7009 if (!is_s2io_card_up(sp))
7012 del_timer_sync(&sp->alarm_timer);
7013 /* If s2io_set_link task is executing, wait till it completes. */
7014 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7016 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7019 if (sp->config.napi) {
7021 if (config->intr_type == MSI_X) {
7022 for (; off < sp->config.rx_ring_num; off++)
7023 napi_disable(&sp->mac_control.rings[off].napi);
7026 napi_disable(&sp->napi);
7029 /* disable Tx and Rx traffic on the NIC */
7035 /* stop the tx queue, indicate link down */
7036 s2io_link(sp, LINK_DOWN);
7038 /* Check if the device is Quiescent and then Reset the NIC */
7040 /* As per the HW requirement we need to replenish the
7041 * receive buffer to avoid the ring bump. Since there is
7042 * no intention of processing the Rx frame at this pointwe are
7043 * just setting the ownership bit of rxd in Each Rx
7044 * ring to HW and set the appropriate buffer size
7045 * based on the ring mode
7047 rxd_owner_bit_reset(sp);
7049 val64 = readq(&bar0->adapter_status);
7050 if (verify_xena_quiescence(sp)) {
7051 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7058 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7059 "adapter status reads 0x%llx\n",
7060 (unsigned long long)val64);
7067 /* Free all Tx buffers */
7068 free_tx_buffers(sp);
7070 /* Free all Rx buffers */
7071 free_rx_buffers(sp);
7073 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7076 static void s2io_card_down(struct s2io_nic *sp)
7078 do_s2io_card_down(sp, 1);
7081 static int s2io_card_up(struct s2io_nic *sp)
7084 struct config_param *config;
7085 struct mac_info *mac_control;
7086 struct net_device *dev = sp->dev;
7089 /* Initialize the H/W I/O registers */
7092 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7100 * Initializing the Rx buffers. For now we are considering only 1
7101 * Rx ring and initializing buffers into 30 Rx blocks
7103 config = &sp->config;
7104 mac_control = &sp->mac_control;
7106 for (i = 0; i < config->rx_ring_num; i++) {
7107 struct ring_info *ring = &mac_control->rings[i];
7109 ring->mtu = dev->mtu;
7110 ring->lro = !!(dev->features & NETIF_F_LRO);
7111 ret = fill_rx_buffers(sp, ring, 1);
7113 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7116 free_rx_buffers(sp);
7119 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7120 ring->rx_bufs_left);
7123 /* Initialise napi */
7125 if (config->intr_type == MSI_X) {
7126 for (i = 0; i < sp->config.rx_ring_num; i++)
7127 napi_enable(&sp->mac_control.rings[i].napi);
7129 napi_enable(&sp->napi);
7133 /* Maintain the state prior to the open */
7134 if (sp->promisc_flg)
7135 sp->promisc_flg = 0;
7136 if (sp->m_cast_flg) {
7138 sp->all_multi_pos = 0;
7141 /* Setting its receive mode */
7142 s2io_set_multicast(dev);
7144 if (dev->features & NETIF_F_LRO) {
7145 /* Initialize max aggregatable pkts per session based on MTU */
7146 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7147 /* Check if we can use (if specified) user provided value */
7148 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7149 sp->lro_max_aggr_per_sess = lro_max_pkts;
7152 /* Enable Rx Traffic and interrupts on the NIC */
7153 if (start_nic(sp)) {
7154 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7156 free_rx_buffers(sp);
7160 /* Add interrupt service routine */
7161 if (s2io_add_isr(sp) != 0) {
7162 if (sp->config.intr_type == MSI_X)
7165 free_rx_buffers(sp);
7169 timer_setup(&sp->alarm_timer, s2io_alarm_handle, 0);
7170 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
7172 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7174 /* Enable select interrupts */
7175 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7176 if (sp->config.intr_type != INTA) {
7177 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7178 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7180 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7181 interruptible |= TX_PIC_INTR;
7182 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7189 * s2io_restart_nic - Resets the NIC.
7190 * @data : long pointer to the device private structure
7192 * This function is scheduled to be run by the s2io_tx_watchdog
7193 * function after 0.5 secs to reset the NIC. The idea is to reduce
7194 * the run time of the watch dog routine which is run holding a
7198 static void s2io_restart_nic(struct work_struct *work)
7200 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7201 struct net_device *dev = sp->dev;
7205 if (!netif_running(dev))
7209 if (s2io_card_up(sp)) {
7210 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7212 s2io_wake_all_tx_queue(sp);
7213 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7219 * s2io_tx_watchdog - Watchdog for transmit side.
7220 * @dev : Pointer to net device structure
7222 * This function is triggered if the Tx Queue is stopped
7223 * for a pre-defined amount of time when the Interface is still up.
7224 * If the Interface is jammed in such a situation, the hardware is
7225 * reset (by s2io_close) and restarted again (by s2io_open) to
7226 * overcome any problem that might have been caused in the hardware.
7231 static void s2io_tx_watchdog(struct net_device *dev, unsigned int txqueue)
7233 struct s2io_nic *sp = netdev_priv(dev);
7234 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7236 if (netif_carrier_ok(dev)) {
7237 swstats->watchdog_timer_cnt++;
7238 schedule_work(&sp->rst_timer_task);
7239 swstats->soft_reset_cnt++;
7244 * rx_osm_handler - To perform some OS related operations on SKB.
7245 * @sp: private member of the device structure,pointer to s2io_nic structure.
7246 * @skb : the socket buffer pointer.
7247 * @len : length of the packet
7248 * @cksum : FCS checksum of the frame.
7249 * @ring_no : the ring from which this RxD was extracted.
7251 * This function is called by the Rx interrupt serivce routine to perform
7252 * some OS related operations on the SKB before passing it to the upper
7253 * layers. It mainly checks if the checksum is OK, if so adds it to the
7254 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7255 * to the upper layer. If the checksum is wrong, it increments the Rx
7256 * packet error count, frees the SKB and returns error.
7258 * SUCCESS on success and -1 on failure.
7260 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7262 struct s2io_nic *sp = ring_data->nic;
7263 struct net_device *dev = ring_data->dev;
7264 struct sk_buff *skb = (struct sk_buff *)
7265 ((unsigned long)rxdp->Host_Control);
7266 int ring_no = ring_data->ring_no;
7267 u16 l3_csum, l4_csum;
7268 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7271 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7276 /* Check for parity error */
7278 swstats->parity_err_cnt++;
7280 err_mask = err >> 48;
7283 swstats->rx_parity_err_cnt++;
7287 swstats->rx_abort_cnt++;
7291 swstats->rx_parity_abort_cnt++;
7295 swstats->rx_rda_fail_cnt++;
7299 swstats->rx_unkn_prot_cnt++;
7303 swstats->rx_fcs_err_cnt++;
7307 swstats->rx_buf_size_err_cnt++;
7311 swstats->rx_rxd_corrupt_cnt++;
7315 swstats->rx_unkn_err_cnt++;
7319 * Drop the packet if bad transfer code. Exception being
7320 * 0x5, which could be due to unsupported IPv6 extension header.
7321 * In this case, we let stack handle the packet.
7322 * Note that in this case, since checksum will be incorrect,
7323 * stack will validate the same.
7325 if (err_mask != 0x5) {
7326 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7327 dev->name, err_mask);
7328 dev->stats.rx_crc_errors++;
7332 ring_data->rx_bufs_left -= 1;
7333 rxdp->Host_Control = 0;
7338 rxdp->Host_Control = 0;
7339 if (sp->rxd_mode == RXD_MODE_1) {
7340 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7343 } else if (sp->rxd_mode == RXD_MODE_3B) {
7344 int get_block = ring_data->rx_curr_get_info.block_index;
7345 int get_off = ring_data->rx_curr_get_info.offset;
7346 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7347 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7348 unsigned char *buff = skb_push(skb, buf0_len);
7350 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7351 memcpy(buff, ba->ba_0, buf0_len);
7352 skb_put(skb, buf2_len);
7355 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7356 ((!ring_data->lro) ||
7357 (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG))) &&
7358 (dev->features & NETIF_F_RXCSUM)) {
7359 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7360 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7361 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7363 * NIC verifies if the Checksum of the received
7364 * frame is Ok or not and accordingly returns
7365 * a flag in the RxD.
7367 skb->ip_summed = CHECKSUM_UNNECESSARY;
7368 if (ring_data->lro) {
7373 ret = s2io_club_tcp_session(ring_data,
7378 case 3: /* Begin anew */
7381 case 1: /* Aggregate */
7382 lro_append_pkt(sp, lro, skb, tcp_len);
7384 case 4: /* Flush session */
7385 lro_append_pkt(sp, lro, skb, tcp_len);
7386 queue_rx_frame(lro->parent,
7388 clear_lro_session(lro);
7389 swstats->flush_max_pkts++;
7391 case 2: /* Flush both */
7392 lro->parent->data_len = lro->frags_len;
7393 swstats->sending_both++;
7394 queue_rx_frame(lro->parent,
7396 clear_lro_session(lro);
7398 case 0: /* sessions exceeded */
7399 case -1: /* non-TCP or not L2 aggregatable */
7401 * First pkt in session not
7402 * L3/L4 aggregatable
7407 "%s: Samadhana!!\n",
7414 * Packet with erroneous checksum, let the
7415 * upper layers deal with it.
7417 skb_checksum_none_assert(skb);
7420 skb_checksum_none_assert(skb);
7422 swstats->mem_freed += skb->truesize;
7424 skb_record_rx_queue(skb, ring_no);
7425 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7427 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7432 * s2io_link - stops/starts the Tx queue.
7433 * @sp : private member of the device structure, which is a pointer to the
7434 * s2io_nic structure.
7435 * @link : inidicates whether link is UP/DOWN.
7437 * This function stops/starts the Tx queue depending on whether the link
7438 * status of the NIC is is down or up. This is called by the Alarm
7439 * interrupt handler whenever a link change interrupt comes up.
7444 static void s2io_link(struct s2io_nic *sp, int link)
7446 struct net_device *dev = sp->dev;
7447 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7449 if (link != sp->last_link_state) {
7451 if (link == LINK_DOWN) {
7452 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7453 s2io_stop_all_tx_queue(sp);
7454 netif_carrier_off(dev);
7455 if (swstats->link_up_cnt)
7456 swstats->link_up_time =
7457 jiffies - sp->start_time;
7458 swstats->link_down_cnt++;
7460 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7461 if (swstats->link_down_cnt)
7462 swstats->link_down_time =
7463 jiffies - sp->start_time;
7464 swstats->link_up_cnt++;
7465 netif_carrier_on(dev);
7466 s2io_wake_all_tx_queue(sp);
7469 sp->last_link_state = link;
7470 sp->start_time = jiffies;
7474 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7475 * @sp : private member of the device structure, which is a pointer to the
7476 * s2io_nic structure.
7478 * This function initializes a few of the PCI and PCI-X configuration registers
7479 * with recommended values.
7484 static void s2io_init_pci(struct s2io_nic *sp)
7486 u16 pci_cmd = 0, pcix_cmd = 0;
7488 /* Enable Data Parity Error Recovery in PCI-X command register. */
7489 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7491 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7493 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7496 /* Set the PErr Response bit in PCI command register. */
7497 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7498 pci_write_config_word(sp->pdev, PCI_COMMAND,
7499 (pci_cmd | PCI_COMMAND_PARITY));
7500 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7503 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7508 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7509 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7510 "(%d) not supported\n", tx_fifo_num);
7512 if (tx_fifo_num < 1)
7515 tx_fifo_num = MAX_TX_FIFOS;
7517 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7521 *dev_multiq = multiq;
7523 if (tx_steering_type && (1 == tx_fifo_num)) {
7524 if (tx_steering_type != TX_DEFAULT_STEERING)
7526 "Tx steering is not supported with "
7527 "one fifo. Disabling Tx steering.\n");
7528 tx_steering_type = NO_STEERING;
7531 if ((tx_steering_type < NO_STEERING) ||
7532 (tx_steering_type > TX_DEFAULT_STEERING)) {
7534 "Requested transmit steering not supported\n");
7535 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7536 tx_steering_type = NO_STEERING;
7539 if (rx_ring_num > MAX_RX_RINGS) {
7541 "Requested number of rx rings not supported\n");
7542 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7544 rx_ring_num = MAX_RX_RINGS;
7547 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7548 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7549 "Defaulting to INTA\n");
7550 *dev_intr_type = INTA;
7553 if ((*dev_intr_type == MSI_X) &&
7554 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7555 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7556 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7557 "Defaulting to INTA\n");
7558 *dev_intr_type = INTA;
7561 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7562 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7563 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7567 for (i = 0; i < MAX_RX_RINGS; i++)
7568 if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) {
7569 DBG_PRINT(ERR_DBG, "Requested rx ring size not "
7570 "supported\nDefaulting to %d\n",
7571 MAX_RX_BLOCKS_PER_RING);
7572 rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING;
7579 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7580 * or Traffic class respectively.
7581 * @nic: device private variable
7582 * Description: The function configures the receive steering to
7583 * desired receive ring.
7584 * Return Value: SUCCESS on success and
7585 * '-1' on failure (endian settings incorrect).
7587 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7589 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7590 register u64 val64 = 0;
7592 if (ds_codepoint > 63)
7595 val64 = RTS_DS_MEM_DATA(ring);
7596 writeq(val64, &bar0->rts_ds_mem_data);
7598 val64 = RTS_DS_MEM_CTRL_WE |
7599 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7600 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7602 writeq(val64, &bar0->rts_ds_mem_ctrl);
7604 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7605 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7609 static const struct net_device_ops s2io_netdev_ops = {
7610 .ndo_open = s2io_open,
7611 .ndo_stop = s2io_close,
7612 .ndo_get_stats = s2io_get_stats,
7613 .ndo_start_xmit = s2io_xmit,
7614 .ndo_validate_addr = eth_validate_addr,
7615 .ndo_set_rx_mode = s2io_set_multicast,
7616 .ndo_do_ioctl = s2io_ioctl,
7617 .ndo_set_mac_address = s2io_set_mac_addr,
7618 .ndo_change_mtu = s2io_change_mtu,
7619 .ndo_set_features = s2io_set_features,
7620 .ndo_tx_timeout = s2io_tx_watchdog,
7621 #ifdef CONFIG_NET_POLL_CONTROLLER
7622 .ndo_poll_controller = s2io_netpoll,
7627 * s2io_init_nic - Initialization of the adapter .
7628 * @pdev : structure containing the PCI related information of the device.
7629 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7631 * The function initializes an adapter identified by the pci_dec structure.
7632 * All OS related initialization including memory and device structure and
7633 * initlaization of the device private variable is done. Also the swapper
7634 * control register is initialized to enable read and write into the I/O
7635 * registers of the device.
7637 * returns 0 on success and negative on failure.
7641 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7643 struct s2io_nic *sp;
7644 struct net_device *dev;
7646 int dma_flag = false;
7647 u32 mac_up, mac_down;
7648 u64 val64 = 0, tmp64 = 0;
7649 struct XENA_dev_config __iomem *bar0 = NULL;
7651 struct config_param *config;
7652 struct mac_info *mac_control;
7654 u8 dev_intr_type = intr_type;
7657 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7661 ret = pci_enable_device(pdev);
7664 "%s: pci_enable_device failed\n", __func__);
7668 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7669 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7671 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7673 "Unable to obtain 64bit DMA for coherent allocations\n");
7674 pci_disable_device(pdev);
7677 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
7678 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
7680 pci_disable_device(pdev);
7683 ret = pci_request_regions(pdev, s2io_driver_name);
7685 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7687 pci_disable_device(pdev);
7691 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7693 dev = alloc_etherdev(sizeof(struct s2io_nic));
7695 pci_disable_device(pdev);
7696 pci_release_regions(pdev);
7700 pci_set_master(pdev);
7701 pci_set_drvdata(pdev, dev);
7702 SET_NETDEV_DEV(dev, &pdev->dev);
7704 /* Private member variable initialized to s2io NIC structure */
7705 sp = netdev_priv(dev);
7708 sp->high_dma_flag = dma_flag;
7709 sp->device_enabled_once = false;
7710 if (rx_ring_mode == 1)
7711 sp->rxd_mode = RXD_MODE_1;
7712 if (rx_ring_mode == 2)
7713 sp->rxd_mode = RXD_MODE_3B;
7715 sp->config.intr_type = dev_intr_type;
7717 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7718 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7719 sp->device_type = XFRAME_II_DEVICE;
7721 sp->device_type = XFRAME_I_DEVICE;
7724 /* Initialize some PCI/PCI-X fields of the NIC. */
7728 * Setting the device configuration parameters.
7729 * Most of these parameters can be specified by the user during
7730 * module insertion as they are module loadable parameters. If
7731 * these parameters are not not specified during load time, they
7732 * are initialized with default values.
7734 config = &sp->config;
7735 mac_control = &sp->mac_control;
7737 config->napi = napi;
7738 config->tx_steering_type = tx_steering_type;
7740 /* Tx side parameters. */
7741 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7742 config->tx_fifo_num = MAX_TX_FIFOS;
7744 config->tx_fifo_num = tx_fifo_num;
7746 /* Initialize the fifos used for tx steering */
7747 if (config->tx_fifo_num < 5) {
7748 if (config->tx_fifo_num == 1)
7749 sp->total_tcp_fifos = 1;
7751 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7752 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7753 sp->total_udp_fifos = 1;
7754 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7756 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7757 FIFO_OTHER_MAX_NUM);
7758 sp->udp_fifo_idx = sp->total_tcp_fifos;
7759 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7760 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7763 config->multiq = dev_multiq;
7764 for (i = 0; i < config->tx_fifo_num; i++) {
7765 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7767 tx_cfg->fifo_len = tx_fifo_len[i];
7768 tx_cfg->fifo_priority = i;
7771 /* mapping the QoS priority to the configured fifos */
7772 for (i = 0; i < MAX_TX_FIFOS; i++)
7773 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7775 /* map the hashing selector table to the configured fifos */
7776 for (i = 0; i < config->tx_fifo_num; i++)
7777 sp->fifo_selector[i] = fifo_selector[i];
7780 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7781 for (i = 0; i < config->tx_fifo_num; i++) {
7782 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7784 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7785 if (tx_cfg->fifo_len < 65) {
7786 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7790 /* + 2 because one Txd for skb->data and one Txd for UFO */
7791 config->max_txds = MAX_SKB_FRAGS + 2;
7793 /* Rx side parameters. */
7794 config->rx_ring_num = rx_ring_num;
7795 for (i = 0; i < config->rx_ring_num; i++) {
7796 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7797 struct ring_info *ring = &mac_control->rings[i];
7799 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7800 rx_cfg->ring_priority = i;
7801 ring->rx_bufs_left = 0;
7802 ring->rxd_mode = sp->rxd_mode;
7803 ring->rxd_count = rxd_count[sp->rxd_mode];
7804 ring->pdev = sp->pdev;
7805 ring->dev = sp->dev;
7808 for (i = 0; i < rx_ring_num; i++) {
7809 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7811 rx_cfg->ring_org = RING_ORG_BUFF1;
7812 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7815 /* Setting Mac Control parameters */
7816 mac_control->rmac_pause_time = rmac_pause_time;
7817 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7818 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7821 /* initialize the shared memory used by the NIC and the host */
7822 if (init_shared_mem(sp)) {
7823 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
7825 goto mem_alloc_failed;
7828 sp->bar0 = pci_ioremap_bar(pdev, 0);
7830 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7833 goto bar0_remap_failed;
7836 sp->bar1 = pci_ioremap_bar(pdev, 2);
7838 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7841 goto bar1_remap_failed;
7844 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7845 for (j = 0; j < MAX_TX_FIFOS; j++) {
7846 mac_control->tx_FIFO_start[j] = sp->bar1 + (j * 0x00020000);
7849 /* Driver entry points */
7850 dev->netdev_ops = &s2io_netdev_ops;
7851 dev->ethtool_ops = &netdev_ethtool_ops;
7852 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
7853 NETIF_F_TSO | NETIF_F_TSO6 |
7854 NETIF_F_RXCSUM | NETIF_F_LRO;
7855 dev->features |= dev->hw_features |
7856 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7857 if (sp->high_dma_flag == true)
7858 dev->features |= NETIF_F_HIGHDMA;
7859 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7860 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7861 INIT_WORK(&sp->set_link_task, s2io_set_link);
7863 pci_save_state(sp->pdev);
7865 /* Setting swapper control on the NIC, for proper reset operation */
7866 if (s2io_set_swapper(sp)) {
7867 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
7870 goto set_swap_failed;
7873 /* Verify if the Herc works on the slot its placed into */
7874 if (sp->device_type & XFRAME_II_DEVICE) {
7875 mode = s2io_verify_pci_mode(sp);
7877 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
7880 goto set_swap_failed;
7884 if (sp->config.intr_type == MSI_X) {
7885 sp->num_entries = config->rx_ring_num + 1;
7886 ret = s2io_enable_msi_x(sp);
7889 ret = s2io_test_msi(sp);
7890 /* rollback MSI-X, will re-enable during add_isr() */
7891 remove_msix_isr(sp);
7896 "MSI-X requested but failed to enable\n");
7897 sp->config.intr_type = INTA;
7901 if (config->intr_type == MSI_X) {
7902 for (i = 0; i < config->rx_ring_num ; i++) {
7903 struct ring_info *ring = &mac_control->rings[i];
7905 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
7908 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
7911 /* Not needed for Herc */
7912 if (sp->device_type & XFRAME_I_DEVICE) {
7914 * Fix for all "FFs" MAC address problems observed on
7917 fix_mac_address(sp);
7922 * MAC address initialization.
7923 * For now only one mac address will be read and used.
7926 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7927 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
7928 writeq(val64, &bar0->rmac_addr_cmd_mem);
7929 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7930 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
7932 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7933 mac_down = (u32)tmp64;
7934 mac_up = (u32) (tmp64 >> 32);
7936 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7937 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7938 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7939 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7940 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7941 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7943 /* Set the factory defined MAC address initially */
7944 dev->addr_len = ETH_ALEN;
7945 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7947 /* initialize number of multicast & unicast MAC entries variables */
7948 if (sp->device_type == XFRAME_I_DEVICE) {
7949 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
7950 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
7951 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
7952 } else if (sp->device_type == XFRAME_II_DEVICE) {
7953 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
7954 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
7955 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
7958 /* MTU range: 46 - 9600 */
7959 dev->min_mtu = MIN_MTU;
7960 dev->max_mtu = S2IO_JUMBO_SIZE;
7962 /* store mac addresses from CAM to s2io_nic structure */
7963 do_s2io_store_unicast_mc(sp);
7965 /* Configure MSIX vector for number of rings configured plus one */
7966 if ((sp->device_type == XFRAME_II_DEVICE) &&
7967 (config->intr_type == MSI_X))
7968 sp->num_entries = config->rx_ring_num + 1;
7970 /* Store the values of the MSIX table in the s2io_nic structure */
7971 store_xmsi_data(sp);
7972 /* reset Nic and bring it to known state */
7976 * Initialize link state flags
7977 * and the card state parameter
7981 /* Initialize spinlocks */
7982 for (i = 0; i < sp->config.tx_fifo_num; i++) {
7983 struct fifo_info *fifo = &mac_control->fifos[i];
7985 spin_lock_init(&fifo->tx_lock);
7989 * SXE-002: Configure link and activity LED to init state
7992 subid = sp->pdev->subsystem_device;
7993 if ((subid & 0xFF) >= 0x07) {
7994 val64 = readq(&bar0->gpio_control);
7995 val64 |= 0x0000800000000000ULL;
7996 writeq(val64, &bar0->gpio_control);
7997 val64 = 0x0411040400000000ULL;
7998 writeq(val64, (void __iomem *)bar0 + 0x2700);
7999 val64 = readq(&bar0->gpio_control);
8002 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8004 if (register_netdev(dev)) {
8005 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8007 goto register_failed;
8010 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
8011 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8012 sp->product_name, pdev->revision);
8013 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8014 s2io_driver_version);
8015 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8016 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8017 if (sp->device_type & XFRAME_II_DEVICE) {
8018 mode = s2io_print_pci_mode(sp);
8021 unregister_netdev(dev);
8022 goto set_swap_failed;
8025 switch (sp->rxd_mode) {
8027 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8031 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8036 switch (sp->config.napi) {
8038 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8041 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8045 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8046 sp->config.tx_fifo_num);
8048 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8049 sp->config.rx_ring_num);
8051 switch (sp->config.intr_type) {
8053 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8056 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8059 if (sp->config.multiq) {
8060 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8061 struct fifo_info *fifo = &mac_control->fifos[i];
8063 fifo->multiq = config->multiq;
8065 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8068 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8071 switch (sp->config.tx_steering_type) {
8073 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8076 case TX_PRIORITY_STEERING:
8078 "%s: Priority steering enabled for transmit\n",
8081 case TX_DEFAULT_STEERING:
8083 "%s: Default steering enabled for transmit\n",
8087 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8089 /* Initialize device name */
8090 snprintf(sp->name, sizeof(sp->name), "%s Neterion %s", dev->name,
8094 sp->vlan_strip_flag = 1;
8096 sp->vlan_strip_flag = 0;
8099 * Make Link state as off at this point, when the Link change
8100 * interrupt comes the state will be automatically changed to
8103 netif_carrier_off(dev);
8114 free_shared_mem(sp);
8115 pci_disable_device(pdev);
8116 pci_release_regions(pdev);
8123 * s2io_rem_nic - Free the PCI device
8124 * @pdev: structure containing the PCI related information of the device.
8125 * Description: This function is called by the Pci subsystem to release a
8126 * PCI device and free up all resource held up by the device. This could
8127 * be in response to a Hot plug event or when the driver is to be removed
8131 static void s2io_rem_nic(struct pci_dev *pdev)
8133 struct net_device *dev = pci_get_drvdata(pdev);
8134 struct s2io_nic *sp;
8137 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8141 sp = netdev_priv(dev);
8143 cancel_work_sync(&sp->rst_timer_task);
8144 cancel_work_sync(&sp->set_link_task);
8146 unregister_netdev(dev);
8148 free_shared_mem(sp);
8151 pci_release_regions(pdev);
8153 pci_disable_device(pdev);
8156 module_pci_driver(s2io_driver);
8158 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8159 struct tcphdr **tcp, struct RxD_t *rxdp,
8160 struct s2io_nic *sp)
8163 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8165 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8167 "%s: Non-TCP frames not supported for LRO\n",
8172 /* Checking for DIX type or DIX type with VLAN */
8173 if ((l2_type == 0) || (l2_type == 4)) {
8174 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8176 * If vlan stripping is disabled and the frame is VLAN tagged,
8177 * shift the offset by the VLAN header size bytes.
8179 if ((!sp->vlan_strip_flag) &&
8180 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8181 ip_off += HEADER_VLAN_SIZE;
8183 /* LLC, SNAP etc are considered non-mergeable */
8187 *ip = (struct iphdr *)(buffer + ip_off);
8188 ip_len = (u8)((*ip)->ihl);
8190 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8195 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8198 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8199 if ((lro->iph->saddr != ip->saddr) ||
8200 (lro->iph->daddr != ip->daddr) ||
8201 (lro->tcph->source != tcp->source) ||
8202 (lro->tcph->dest != tcp->dest))
8207 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8209 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8212 static void initiate_new_session(struct lro *lro, u8 *l2h,
8213 struct iphdr *ip, struct tcphdr *tcp,
8214 u32 tcp_pyld_len, u16 vlan_tag)
8216 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8220 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8221 lro->tcp_ack = tcp->ack_seq;
8223 lro->total_len = ntohs(ip->tot_len);
8225 lro->vlan_tag = vlan_tag;
8227 * Check if we saw TCP timestamp.
8228 * Other consistency checks have already been done.
8230 if (tcp->doff == 8) {
8232 ptr = (__be32 *)(tcp+1);
8234 lro->cur_tsval = ntohl(*(ptr+1));
8235 lro->cur_tsecr = *(ptr+2);
8240 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8242 struct iphdr *ip = lro->iph;
8243 struct tcphdr *tcp = lro->tcph;
8244 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8246 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8248 /* Update L3 header */
8249 csum_replace2(&ip->check, ip->tot_len, htons(lro->total_len));
8250 ip->tot_len = htons(lro->total_len);
8252 /* Update L4 header */
8253 tcp->ack_seq = lro->tcp_ack;
8254 tcp->window = lro->window;
8256 /* Update tsecr field if this session has timestamps enabled */
8258 __be32 *ptr = (__be32 *)(tcp + 1);
8259 *(ptr+2) = lro->cur_tsecr;
8262 /* Update counters required for calculation of
8263 * average no. of packets aggregated.
8265 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8266 swstats->num_aggregations++;
8269 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8270 struct tcphdr *tcp, u32 l4_pyld)
8272 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8273 lro->total_len += l4_pyld;
8274 lro->frags_len += l4_pyld;
8275 lro->tcp_next_seq += l4_pyld;
8278 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8279 lro->tcp_ack = tcp->ack_seq;
8280 lro->window = tcp->window;
8284 /* Update tsecr and tsval from this packet */
8285 ptr = (__be32 *)(tcp+1);
8286 lro->cur_tsval = ntohl(*(ptr+1));
8287 lro->cur_tsecr = *(ptr + 2);
8291 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8292 struct tcphdr *tcp, u32 tcp_pyld_len)
8296 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8298 if (!tcp_pyld_len) {
8299 /* Runt frame or a pure ack */
8303 if (ip->ihl != 5) /* IP has options */
8306 /* If we see CE codepoint in IP header, packet is not mergeable */
8307 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8310 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8311 if (tcp->urg || tcp->psh || tcp->rst ||
8312 tcp->syn || tcp->fin ||
8313 tcp->ece || tcp->cwr || !tcp->ack) {
8315 * Currently recognize only the ack control word and
8316 * any other control field being set would result in
8317 * flushing the LRO session
8323 * Allow only one TCP timestamp option. Don't aggregate if
8324 * any other options are detected.
8326 if (tcp->doff != 5 && tcp->doff != 8)
8329 if (tcp->doff == 8) {
8330 ptr = (u8 *)(tcp + 1);
8331 while (*ptr == TCPOPT_NOP)
8333 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8336 /* Ensure timestamp value increases monotonically */
8338 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8341 /* timestamp echo reply should be non-zero */
8342 if (*((__be32 *)(ptr+6)) == 0)
8349 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8350 u8 **tcp, u32 *tcp_len, struct lro **lro,
8351 struct RxD_t *rxdp, struct s2io_nic *sp)
8354 struct tcphdr *tcph;
8357 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8359 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8364 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8366 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8367 tcph = (struct tcphdr *)*tcp;
8368 *tcp_len = get_l4_pyld_length(ip, tcph);
8369 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8370 struct lro *l_lro = &ring_data->lro0_n[i];
8371 if (l_lro->in_use) {
8372 if (check_for_socket_match(l_lro, ip, tcph))
8374 /* Sock pair matched */
8377 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8378 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8379 "expected 0x%x, actual 0x%x\n",
8381 (*lro)->tcp_next_seq,
8384 swstats->outof_sequence_pkts++;
8389 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8391 ret = 1; /* Aggregate */
8393 ret = 2; /* Flush both */
8399 /* Before searching for available LRO objects,
8400 * check if the pkt is L3/L4 aggregatable. If not
8401 * don't create new LRO session. Just send this
8404 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8407 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8408 struct lro *l_lro = &ring_data->lro0_n[i];
8409 if (!(l_lro->in_use)) {
8411 ret = 3; /* Begin anew */
8417 if (ret == 0) { /* sessions exceeded */
8418 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8426 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8430 update_L3L4_header(sp, *lro);
8433 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8434 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8435 update_L3L4_header(sp, *lro);
8436 ret = 4; /* Flush the LRO */
8440 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8447 static void clear_lro_session(struct lro *lro)
8449 static u16 lro_struct_size = sizeof(struct lro);
8451 memset(lro, 0, lro_struct_size);
8454 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8456 struct net_device *dev = skb->dev;
8457 struct s2io_nic *sp = netdev_priv(dev);
8459 skb->protocol = eth_type_trans(skb, dev);
8460 if (vlan_tag && sp->vlan_strip_flag)
8461 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
8462 if (sp->config.napi)
8463 netif_receive_skb(skb);
8468 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8469 struct sk_buff *skb, u32 tcp_len)
8471 struct sk_buff *first = lro->parent;
8472 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8474 first->len += tcp_len;
8475 first->data_len = lro->frags_len;
8476 skb_pull(skb, (skb->len - tcp_len));
8477 if (skb_shinfo(first)->frag_list)
8478 lro->last_frag->next = skb;
8480 skb_shinfo(first)->frag_list = skb;
8481 first->truesize += skb->truesize;
8482 lro->last_frag = skb;
8483 swstats->clubbed_frms_cnt++;
8487 * s2io_io_error_detected - called when PCI error is detected
8488 * @pdev: Pointer to PCI device
8489 * @state: The current pci connection state
8491 * This function is called after a PCI bus error affecting
8492 * this device has been detected.
8494 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8495 pci_channel_state_t state)
8497 struct net_device *netdev = pci_get_drvdata(pdev);
8498 struct s2io_nic *sp = netdev_priv(netdev);
8500 netif_device_detach(netdev);
8502 if (state == pci_channel_io_perm_failure)
8503 return PCI_ERS_RESULT_DISCONNECT;
8505 if (netif_running(netdev)) {
8506 /* Bring down the card, while avoiding PCI I/O */
8507 do_s2io_card_down(sp, 0);
8509 pci_disable_device(pdev);
8511 return PCI_ERS_RESULT_NEED_RESET;
8515 * s2io_io_slot_reset - called after the pci bus has been reset.
8516 * @pdev: Pointer to PCI device
8518 * Restart the card from scratch, as if from a cold-boot.
8519 * At this point, the card has exprienced a hard reset,
8520 * followed by fixups by BIOS, and has its config space
8521 * set up identically to what it was at cold boot.
8523 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8525 struct net_device *netdev = pci_get_drvdata(pdev);
8526 struct s2io_nic *sp = netdev_priv(netdev);
8528 if (pci_enable_device(pdev)) {
8529 pr_err("Cannot re-enable PCI device after reset.\n");
8530 return PCI_ERS_RESULT_DISCONNECT;
8533 pci_set_master(pdev);
8536 return PCI_ERS_RESULT_RECOVERED;
8540 * s2io_io_resume - called when traffic can start flowing again.
8541 * @pdev: Pointer to PCI device
8543 * This callback is called when the error recovery driver tells
8544 * us that its OK to resume normal operation.
8546 static void s2io_io_resume(struct pci_dev *pdev)
8548 struct net_device *netdev = pci_get_drvdata(pdev);
8549 struct s2io_nic *sp = netdev_priv(netdev);
8551 if (netif_running(netdev)) {
8552 if (s2io_card_up(sp)) {
8553 pr_err("Can't bring device back up after reset.\n");
8557 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8559 pr_err("Can't restore mac addr after reset.\n");
8564 netif_device_attach(netdev);
8565 netif_tx_wake_all_queues(netdev);
projects / linux-2.6-microblaze.git / blob