1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /* ns83820.c by Benjamin LaHaise with contributions.
5 * Questions/comments/discussion to linux-ns83820@kvack.org.
7 * $Revision: 1.34.2.23 $
9 * Copyright 2001 Benjamin LaHaise.
10 * Copyright 2001, 2002 Red Hat.
12 * Mmmm, chocolate vanilla mocha...
16 * 20010414 0.1 - created
17 * 20010622 0.2 - basic rx and tx.
18 * 20010711 0.3 - added duplex and link state detection support.
19 * 20010713 0.4 - zero copy, no hangs.
20 * 0.5 - 64 bit dma support (davem will hate me for this)
21 * - disable jumbo frames to avoid tx hangs
22 * - work around tx deadlocks on my 1.02 card via
24 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
25 * 20010816 0.7 - misc cleanups
26 * 20010826 0.8 - fix critical zero copy bugs
27 * 0.9 - internal experiment
28 * 20010827 0.10 - fix ia64 unaligned access.
29 * 20010906 0.11 - accept all packets with checksum errors as
30 * otherwise fragments get lost
32 * 0.12 - add statistics counters
33 * - add allmulti/promisc support
34 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
35 * 20011204 0.13a - optical transceiver support added
36 * by Michael Clark <michael@metaparadigm.com>
37 * 20011205 0.13b - call register_netdev earlier in initialization
38 * suppress duplicate link status messages
39 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
40 * 20011204 0.15 get ppc (big endian) working
41 * 20011218 0.16 various cleanups
42 * 20020310 0.17 speedups
43 * 20020610 0.18 - actually use the pci dma api for highmem
44 * - remove pci latency register fiddling
45 * 0.19 - better bist support
46 * - add ihr and reset_phy parameters
48 * - fix missed txok introduced during performance
50 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
51 * 20040828 0.21 - add hardware vlan accleration
52 * by Neil Horman <nhorman@redhat.com>
53 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
54 * - removal of dead code from Adrian Bunk
55 * - fix half duplex collision behaviour
59 * This driver was originally written for the National Semiconductor
60 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
61 * this code will turn out to be a) clean, b) correct, and c) fast.
62 * With that in mind, I'm aiming to split the code up as much as
63 * reasonably possible. At present there are X major sections that
64 * break down into a) packet receive, b) packet transmit, c) link
65 * management, d) initialization and configuration. Where possible,
66 * these code paths are designed to run in parallel.
68 * This driver has been tested and found to work with the following
69 * cards (in no particular order):
71 * Cameo SOHO-GA2000T SOHO-GA2500T
73 * PureData PDP8023Z-TG
74 * SMC SMC9452TX SMC9462TX
77 * Special thanks to SMC for providing hardware to test this driver on.
79 * Reports of success or failure would be greatly appreciated.
81 //#define dprintk printk
82 #define dprintk(x...) do { } while (0)
84 #include <linux/module.h>
85 #include <linux/moduleparam.h>
86 #include <linux/types.h>
87 #include <linux/pci.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/netdevice.h>
90 #include <linux/etherdevice.h>
91 #include <linux/delay.h>
92 #include <linux/workqueue.h>
93 #include <linux/init.h>
94 #include <linux/interrupt.h>
95 #include <linux/ip.h> /* for iph */
96 #include <linux/in.h> /* for IPPROTO_... */
97 #include <linux/compiler.h>
98 #include <linux/prefetch.h>
99 #include <linux/ethtool.h>
100 #include <linux/sched.h>
101 #include <linux/timer.h>
102 #include <linux/if_vlan.h>
103 #include <linux/rtnetlink.h>
104 #include <linux/jiffies.h>
105 #include <linux/slab.h>
108 #include <linux/uaccess.h>
110 #define DRV_NAME "ns83820"
112 /* Global parameters. See module_param near the bottom. */
114 static int reset_phy = 0;
115 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
117 /* Dprintk is used for more interesting debug events */
119 #define Dprintk dprintk
122 #define RX_BUF_SIZE 1500 /* 8192 */
123 #if IS_ENABLED(CONFIG_VLAN_8021Q)
124 #define NS83820_VLAN_ACCEL_SUPPORT
127 /* Must not exceed ~65000. */
128 #define NR_RX_DESC 64
129 #define NR_TX_DESC 128
132 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
134 #define MIN_TX_DESC_FREE 8
136 /* register defines */
139 #define CR_TXE 0x00000001
140 #define CR_TXD 0x00000002
141 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
142 * The Receive engine skips one descriptor and moves
143 * onto the next one!! */
144 #define CR_RXE 0x00000004
145 #define CR_RXD 0x00000008
146 #define CR_TXR 0x00000010
147 #define CR_RXR 0x00000020
148 #define CR_SWI 0x00000080
149 #define CR_RST 0x00000100
151 #define PTSCR_EEBIST_FAIL 0x00000001
152 #define PTSCR_EEBIST_EN 0x00000002
153 #define PTSCR_EELOAD_EN 0x00000004
154 #define PTSCR_RBIST_FAIL 0x000001b8
155 #define PTSCR_RBIST_DONE 0x00000200
156 #define PTSCR_RBIST_EN 0x00000400
157 #define PTSCR_RBIST_RST 0x00002000
159 #define MEAR_EEDI 0x00000001
160 #define MEAR_EEDO 0x00000002
161 #define MEAR_EECLK 0x00000004
162 #define MEAR_EESEL 0x00000008
163 #define MEAR_MDIO 0x00000010
164 #define MEAR_MDDIR 0x00000020
165 #define MEAR_MDC 0x00000040
167 #define ISR_TXDESC3 0x40000000
168 #define ISR_TXDESC2 0x20000000
169 #define ISR_TXDESC1 0x10000000
170 #define ISR_TXDESC0 0x08000000
171 #define ISR_RXDESC3 0x04000000
172 #define ISR_RXDESC2 0x02000000
173 #define ISR_RXDESC1 0x01000000
174 #define ISR_RXDESC0 0x00800000
175 #define ISR_TXRCMP 0x00400000
176 #define ISR_RXRCMP 0x00200000
177 #define ISR_DPERR 0x00100000
178 #define ISR_SSERR 0x00080000
179 #define ISR_RMABT 0x00040000
180 #define ISR_RTABT 0x00020000
181 #define ISR_RXSOVR 0x00010000
182 #define ISR_HIBINT 0x00008000
183 #define ISR_PHY 0x00004000
184 #define ISR_PME 0x00002000
185 #define ISR_SWI 0x00001000
186 #define ISR_MIB 0x00000800
187 #define ISR_TXURN 0x00000400
188 #define ISR_TXIDLE 0x00000200
189 #define ISR_TXERR 0x00000100
190 #define ISR_TXDESC 0x00000080
191 #define ISR_TXOK 0x00000040
192 #define ISR_RXORN 0x00000020
193 #define ISR_RXIDLE 0x00000010
194 #define ISR_RXEARLY 0x00000008
195 #define ISR_RXERR 0x00000004
196 #define ISR_RXDESC 0x00000002
197 #define ISR_RXOK 0x00000001
199 #define TXCFG_CSI 0x80000000
200 #define TXCFG_HBI 0x40000000
201 #define TXCFG_MLB 0x20000000
202 #define TXCFG_ATP 0x10000000
203 #define TXCFG_ECRETRY 0x00800000
204 #define TXCFG_BRST_DIS 0x00080000
205 #define TXCFG_MXDMA1024 0x00000000
206 #define TXCFG_MXDMA512 0x00700000
207 #define TXCFG_MXDMA256 0x00600000
208 #define TXCFG_MXDMA128 0x00500000
209 #define TXCFG_MXDMA64 0x00400000
210 #define TXCFG_MXDMA32 0x00300000
211 #define TXCFG_MXDMA16 0x00200000
212 #define TXCFG_MXDMA8 0x00100000
214 #define CFG_LNKSTS 0x80000000
215 #define CFG_SPDSTS 0x60000000
216 #define CFG_SPDSTS1 0x40000000
217 #define CFG_SPDSTS0 0x20000000
218 #define CFG_DUPSTS 0x10000000
219 #define CFG_TBI_EN 0x01000000
220 #define CFG_MODE_1000 0x00400000
221 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
222 * Read the Phy response and then configure the MAC accordingly */
223 #define CFG_AUTO_1000 0x00200000
224 #define CFG_PINT_CTL 0x001c0000
225 #define CFG_PINT_DUPSTS 0x00100000
226 #define CFG_PINT_LNKSTS 0x00080000
227 #define CFG_PINT_SPDSTS 0x00040000
228 #define CFG_TMRTEST 0x00020000
229 #define CFG_MRM_DIS 0x00010000
230 #define CFG_MWI_DIS 0x00008000
231 #define CFG_T64ADDR 0x00004000
232 #define CFG_PCI64_DET 0x00002000
233 #define CFG_DATA64_EN 0x00001000
234 #define CFG_M64ADDR 0x00000800
235 #define CFG_PHY_RST 0x00000400
236 #define CFG_PHY_DIS 0x00000200
237 #define CFG_EXTSTS_EN 0x00000100
238 #define CFG_REQALG 0x00000080
239 #define CFG_SB 0x00000040
240 #define CFG_POW 0x00000020
241 #define CFG_EXD 0x00000010
242 #define CFG_PESEL 0x00000008
243 #define CFG_BROM_DIS 0x00000004
244 #define CFG_EXT_125 0x00000002
245 #define CFG_BEM 0x00000001
247 #define EXTSTS_UDPPKT 0x00200000
248 #define EXTSTS_TCPPKT 0x00080000
249 #define EXTSTS_IPPKT 0x00020000
250 #define EXTSTS_VPKT 0x00010000
251 #define EXTSTS_VTG_MASK 0x0000ffff
253 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
255 #define MIBC_MIBS 0x00000008
256 #define MIBC_ACLR 0x00000004
257 #define MIBC_FRZ 0x00000002
258 #define MIBC_WRN 0x00000001
260 #define PCR_PSEN (1 << 31)
261 #define PCR_PS_MCAST (1 << 30)
262 #define PCR_PS_DA (1 << 29)
263 #define PCR_STHI_8 (3 << 23)
264 #define PCR_STLO_4 (1 << 23)
265 #define PCR_FFHI_8K (3 << 21)
266 #define PCR_FFLO_4K (1 << 21)
267 #define PCR_PAUSE_CNT 0xFFFE
269 #define RXCFG_AEP 0x80000000
270 #define RXCFG_ARP 0x40000000
271 #define RXCFG_STRIPCRC 0x20000000
272 #define RXCFG_RX_FD 0x10000000
273 #define RXCFG_ALP 0x08000000
274 #define RXCFG_AIRL 0x04000000
275 #define RXCFG_MXDMA512 0x00700000
276 #define RXCFG_DRTH 0x0000003e
277 #define RXCFG_DRTH0 0x00000002
279 #define RFCR_RFEN 0x80000000
280 #define RFCR_AAB 0x40000000
281 #define RFCR_AAM 0x20000000
282 #define RFCR_AAU 0x10000000
283 #define RFCR_APM 0x08000000
284 #define RFCR_APAT 0x07800000
285 #define RFCR_APAT3 0x04000000
286 #define RFCR_APAT2 0x02000000
287 #define RFCR_APAT1 0x01000000
288 #define RFCR_APAT0 0x00800000
289 #define RFCR_AARP 0x00400000
290 #define RFCR_MHEN 0x00200000
291 #define RFCR_UHEN 0x00100000
292 #define RFCR_ULM 0x00080000
294 #define VRCR_RUDPE 0x00000080
295 #define VRCR_RTCPE 0x00000040
296 #define VRCR_RIPE 0x00000020
297 #define VRCR_IPEN 0x00000010
298 #define VRCR_DUTF 0x00000008
299 #define VRCR_DVTF 0x00000004
300 #define VRCR_VTREN 0x00000002
301 #define VRCR_VTDEN 0x00000001
303 #define VTCR_PPCHK 0x00000008
304 #define VTCR_GCHK 0x00000004
305 #define VTCR_VPPTI 0x00000002
306 #define VTCR_VGTI 0x00000001
343 #define TBICR_MR_AN_ENABLE 0x00001000
344 #define TBICR_MR_RESTART_AN 0x00000200
346 #define TBISR_MR_LINK_STATUS 0x00000020
347 #define TBISR_MR_AN_COMPLETE 0x00000004
349 #define TANAR_PS2 0x00000100
350 #define TANAR_PS1 0x00000080
351 #define TANAR_HALF_DUP 0x00000040
352 #define TANAR_FULL_DUP 0x00000020
354 #define GPIOR_GP5_OE 0x00000200
355 #define GPIOR_GP4_OE 0x00000100
356 #define GPIOR_GP3_OE 0x00000080
357 #define GPIOR_GP2_OE 0x00000040
358 #define GPIOR_GP1_OE 0x00000020
359 #define GPIOR_GP3_OUT 0x00000004
360 #define GPIOR_GP1_OUT 0x00000001
362 #define LINK_AUTONEGOTIATE 0x01
363 #define LINK_DOWN 0x02
366 #define HW_ADDR_LEN sizeof(dma_addr_t)
367 #define desc_addr_set(desc, addr) \
369 ((desc)[0] = cpu_to_le32(addr)); \
370 if (HW_ADDR_LEN == 8) \
371 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
373 #define desc_addr_get(desc) \
374 (le32_to_cpu((desc)[0]) | \
375 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
378 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
379 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
380 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
382 #define CMDSTS_OWN 0x80000000
383 #define CMDSTS_MORE 0x40000000
384 #define CMDSTS_INTR 0x20000000
385 #define CMDSTS_ERR 0x10000000
386 #define CMDSTS_OK 0x08000000
387 #define CMDSTS_RUNT 0x00200000
388 #define CMDSTS_LEN_MASK 0x0000ffff
390 #define CMDSTS_DEST_MASK 0x01800000
391 #define CMDSTS_DEST_SELF 0x00800000
392 #define CMDSTS_DEST_MULTI 0x01000000
394 #define DESC_SIZE 8 /* Should be cache line sized */
401 struct sk_buff *skbs[NR_RX_DESC];
403 __le32 *next_rx_desc;
404 u16 next_rx, next_empty;
407 dma_addr_t phy_descs;
414 struct pci_dev *pci_dev;
415 struct net_device *ndev;
417 struct rx_info rx_info;
418 struct tasklet_struct rx_tasklet;
421 struct work_struct tq_refill;
423 /* protects everything below. irqsave when using. */
424 spinlock_t misc_lock;
437 volatile u16 tx_free_idx; /* idx of free desc chain */
441 struct sk_buff *tx_skbs[NR_TX_DESC];
443 char pad[16] __attribute__((aligned(16)));
445 dma_addr_t tx_phy_descs;
447 struct timer_list tx_watchdog;
450 static inline struct ns83820 *PRIV(struct net_device *dev)
452 return netdev_priv(dev);
455 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
457 static inline void kick_rx(struct net_device *ndev)
459 struct ns83820 *dev = PRIV(ndev);
460 dprintk("kick_rx: maybe kicking\n");
461 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
462 dprintk("actually kicking\n");
463 writel(dev->rx_info.phy_descs +
464 (4 * DESC_SIZE * dev->rx_info.next_rx),
466 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
467 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
473 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
474 #define start_tx_okay(dev) \
475 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
479 * The hardware supports linked lists of receive descriptors for
480 * which ownership is transferred back and forth by means of an
481 * ownership bit. While the hardware does support the use of a
482 * ring for receive descriptors, we only make use of a chain in
483 * an attempt to reduce bus traffic under heavy load scenarios.
484 * This will also make bugs a bit more obvious. The current code
485 * only makes use of a single rx chain; I hope to implement
486 * priority based rx for version 1.0. Goal: even under overload
487 * conditions, still route realtime traffic with as low jitter as
490 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
492 desc_addr_set(desc + DESC_LINK, link);
493 desc_addr_set(desc + DESC_BUFPTR, buf);
494 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
496 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
499 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
500 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
507 next_empty = dev->rx_info.next_empty;
509 /* don't overrun last rx marker */
510 if (unlikely(nr_rx_empty(dev) <= 2)) {
516 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
517 dev->rx_info.next_empty,
518 dev->rx_info.nr_used,
523 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
524 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
525 dev->rx_info.skbs[next_empty] = skb;
527 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
528 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
529 buf = dma_map_single(&dev->pci_dev->dev, skb->data, REAL_RX_BUF_SIZE,
531 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
532 /* update link of previous rx */
533 if (likely(next_empty != dev->rx_info.next_rx))
534 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
539 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
541 struct ns83820 *dev = PRIV(ndev);
543 unsigned long flags = 0;
545 if (unlikely(nr_rx_empty(dev) <= 2))
548 dprintk("rx_refill(%p)\n", ndev);
549 if (gfp == GFP_ATOMIC)
550 spin_lock_irqsave(&dev->rx_info.lock, flags);
551 for (i=0; i<NR_RX_DESC; i++) {
555 /* extra 16 bytes for alignment */
556 skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp);
560 skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16));
561 if (gfp != GFP_ATOMIC)
562 spin_lock_irqsave(&dev->rx_info.lock, flags);
563 res = ns83820_add_rx_skb(dev, skb);
564 if (gfp != GFP_ATOMIC)
565 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
571 if (gfp == GFP_ATOMIC)
572 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
574 return i ? 0 : -ENOMEM;
577 static void rx_refill_atomic(struct net_device *ndev)
579 rx_refill(ndev, GFP_ATOMIC);
583 static inline void queue_refill(struct work_struct *work)
585 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
586 struct net_device *ndev = dev->ndev;
588 rx_refill(ndev, GFP_KERNEL);
593 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
595 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
598 static void phy_intr(struct net_device *ndev)
600 struct ns83820 *dev = PRIV(ndev);
601 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
603 u32 tbisr, tanar, tanlpar;
604 int speed, fullduplex, newlinkstate;
606 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
608 if (dev->CFG_cache & CFG_TBI_EN) {
609 /* we have an optical transceiver */
610 tbisr = readl(dev->base + TBISR);
611 tanar = readl(dev->base + TANAR);
612 tanlpar = readl(dev->base + TANLPAR);
613 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
614 tbisr, tanar, tanlpar);
616 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP) &&
617 (tanar & TANAR_FULL_DUP)) ) {
619 /* both of us are full duplex */
620 writel(readl(dev->base + TXCFG)
621 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
623 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
625 /* Light up full duplex LED */
626 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
629 } else if (((tanlpar & TANAR_HALF_DUP) &&
630 (tanar & TANAR_HALF_DUP)) ||
631 ((tanlpar & TANAR_FULL_DUP) &&
632 (tanar & TANAR_HALF_DUP)) ||
633 ((tanlpar & TANAR_HALF_DUP) &&
634 (tanar & TANAR_FULL_DUP))) {
636 /* one or both of us are half duplex */
637 writel((readl(dev->base + TXCFG)
638 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
640 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
642 /* Turn off full duplex LED */
643 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
647 speed = 4; /* 1000F */
650 /* we have a copper transceiver */
651 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
653 if (cfg & CFG_SPDSTS1)
654 new_cfg |= CFG_MODE_1000;
656 new_cfg &= ~CFG_MODE_1000;
658 speed = ((cfg / CFG_SPDSTS0) & 3);
659 fullduplex = (cfg & CFG_DUPSTS);
663 writel(readl(dev->base + TXCFG)
664 | TXCFG_CSI | TXCFG_HBI,
666 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
669 writel(readl(dev->base + TXCFG)
670 & ~(TXCFG_CSI | TXCFG_HBI),
672 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
676 if ((cfg & CFG_LNKSTS) &&
677 ((new_cfg ^ dev->CFG_cache) != 0)) {
678 writel(new_cfg, dev->base + CFG);
679 dev->CFG_cache = new_cfg;
682 dev->CFG_cache &= ~CFG_SPDSTS;
683 dev->CFG_cache |= cfg & CFG_SPDSTS;
686 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
688 if (newlinkstate & LINK_UP &&
689 dev->linkstate != newlinkstate) {
690 netif_start_queue(ndev);
691 netif_wake_queue(ndev);
692 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
695 fullduplex ? "full" : "half");
696 } else if (newlinkstate & LINK_DOWN &&
697 dev->linkstate != newlinkstate) {
698 netif_stop_queue(ndev);
699 printk(KERN_INFO "%s: link now down.\n", ndev->name);
702 dev->linkstate = newlinkstate;
705 static int ns83820_setup_rx(struct net_device *ndev)
707 struct ns83820 *dev = PRIV(ndev);
711 dprintk("ns83820_setup_rx(%p)\n", ndev);
713 dev->rx_info.idle = 1;
714 dev->rx_info.next_rx = 0;
715 dev->rx_info.next_rx_desc = dev->rx_info.descs;
716 dev->rx_info.next_empty = 0;
718 for (i=0; i<NR_RX_DESC; i++)
719 clear_rx_desc(dev, i);
721 writel(0, dev->base + RXDP_HI);
722 writel(dev->rx_info.phy_descs, dev->base + RXDP);
724 ret = rx_refill(ndev, GFP_KERNEL);
726 dprintk("starting receiver\n");
727 /* prevent the interrupt handler from stomping on us */
728 spin_lock_irq(&dev->rx_info.lock);
730 writel(0x0001, dev->base + CCSR);
731 writel(0, dev->base + RFCR);
732 writel(0x7fc00000, dev->base + RFCR);
733 writel(0xffc00000, dev->base + RFCR);
739 /* Okay, let it rip */
740 spin_lock(&dev->misc_lock);
741 dev->IMR_cache |= ISR_PHY;
742 dev->IMR_cache |= ISR_RXRCMP;
743 //dev->IMR_cache |= ISR_RXERR;
744 //dev->IMR_cache |= ISR_RXOK;
745 dev->IMR_cache |= ISR_RXORN;
746 dev->IMR_cache |= ISR_RXSOVR;
747 dev->IMR_cache |= ISR_RXDESC;
748 dev->IMR_cache |= ISR_RXIDLE;
749 dev->IMR_cache |= ISR_TXDESC;
750 dev->IMR_cache |= ISR_TXIDLE;
752 writel(dev->IMR_cache, dev->base + IMR);
753 writel(1, dev->base + IER);
754 spin_unlock(&dev->misc_lock);
758 spin_unlock_irq(&dev->rx_info.lock);
763 static void ns83820_cleanup_rx(struct ns83820 *dev)
768 dprintk("ns83820_cleanup_rx(%p)\n", dev);
770 /* disable receive interrupts */
771 spin_lock_irqsave(&dev->misc_lock, flags);
772 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
773 writel(dev->IMR_cache, dev->base + IMR);
774 spin_unlock_irqrestore(&dev->misc_lock, flags);
776 /* synchronize with the interrupt handler and kill it */
778 synchronize_irq(dev->pci_dev->irq);
780 /* touch the pci bus... */
781 readl(dev->base + IMR);
783 /* assumes the transmitter is already disabled and reset */
784 writel(0, dev->base + RXDP_HI);
785 writel(0, dev->base + RXDP);
787 for (i=0; i<NR_RX_DESC; i++) {
788 struct sk_buff *skb = dev->rx_info.skbs[i];
789 dev->rx_info.skbs[i] = NULL;
790 clear_rx_desc(dev, i);
795 static void ns83820_rx_kick(struct net_device *ndev)
797 struct ns83820 *dev = PRIV(ndev);
798 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
799 if (dev->rx_info.up) {
800 rx_refill_atomic(ndev);
805 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
806 schedule_work(&dev->tq_refill);
809 if (dev->rx_info.idle)
810 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
816 static void rx_irq(struct net_device *ndev)
818 struct ns83820 *dev = PRIV(ndev);
819 struct rx_info *info = &dev->rx_info;
827 dprintk("rx_irq(%p)\n", ndev);
828 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
829 readl(dev->base + RXDP),
830 (long)(dev->rx_info.phy_descs),
831 (int)dev->rx_info.next_rx,
832 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
833 (int)dev->rx_info.next_empty,
834 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
837 spin_lock_irqsave(&info->lock, flags);
841 dprintk("walking descs\n");
842 next_rx = info->next_rx;
843 desc = info->next_rx_desc;
844 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
845 (cmdsts != CMDSTS_OWN)) {
847 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
848 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
850 dprintk("cmdsts: %08x\n", cmdsts);
851 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
852 dprintk("extsts: %08x\n", extsts);
854 skb = info->skbs[next_rx];
855 info->skbs[next_rx] = NULL;
856 info->next_rx = (next_rx + 1) % NR_RX_DESC;
859 clear_rx_desc(dev, next_rx);
861 dma_unmap_single(&dev->pci_dev->dev, bufptr, RX_BUF_SIZE,
863 len = cmdsts & CMDSTS_LEN_MASK;
864 #ifdef NS83820_VLAN_ACCEL_SUPPORT
865 /* NH: As was mentioned below, this chip is kinda
866 * brain dead about vlan tag stripping. Frames
867 * that are 64 bytes with a vlan header appended
868 * like arp frames, or pings, are flagged as Runts
869 * when the tag is stripped and hardware. This
870 * also means that the OK bit in the descriptor
871 * is cleared when the frame comes in so we have
872 * to do a specific length check here to make sure
873 * the frame would have been ok, had we not stripped
876 if (likely((CMDSTS_OK & cmdsts) ||
877 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
879 if (likely(CMDSTS_OK & cmdsts)) {
883 goto netdev_mangle_me_harder_failed;
884 if (cmdsts & CMDSTS_DEST_MULTI)
885 ndev->stats.multicast++;
886 ndev->stats.rx_packets++;
887 ndev->stats.rx_bytes += len;
888 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
889 skb->ip_summed = CHECKSUM_UNNECESSARY;
891 skb_checksum_none_assert(skb);
893 skb->protocol = eth_type_trans(skb, ndev);
894 #ifdef NS83820_VLAN_ACCEL_SUPPORT
895 if(extsts & EXTSTS_VPKT) {
898 tag = ntohs(extsts & EXTSTS_VTG_MASK);
899 __vlan_hwaccel_put_tag(skb, htons(ETH_P_IPV6), tag);
902 rx_rc = netif_rx(skb);
903 if (NET_RX_DROP == rx_rc) {
904 netdev_mangle_me_harder_failed:
905 ndev->stats.rx_dropped++;
908 dev_kfree_skb_irq(skb);
912 next_rx = info->next_rx;
913 desc = info->descs + (DESC_SIZE * next_rx);
915 info->next_rx = next_rx;
916 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
920 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
923 spin_unlock_irqrestore(&info->lock, flags);
926 static void rx_action(unsigned long _dev)
928 struct net_device *ndev = (void *)_dev;
929 struct ns83820 *dev = PRIV(ndev);
931 writel(ihr, dev->base + IHR);
933 spin_lock_irq(&dev->misc_lock);
934 dev->IMR_cache |= ISR_RXDESC;
935 writel(dev->IMR_cache, dev->base + IMR);
936 spin_unlock_irq(&dev->misc_lock);
939 ns83820_rx_kick(ndev);
942 /* Packet Transmit code
944 static inline void kick_tx(struct ns83820 *dev)
946 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
947 dev, dev->tx_idx, dev->tx_free_idx);
948 writel(CR_TXE, dev->base + CR);
951 /* No spinlock needed on the transmit irq path as the interrupt handler is
954 static void do_tx_done(struct net_device *ndev)
956 struct ns83820 *dev = PRIV(ndev);
957 u32 cmdsts, tx_done_idx;
960 dprintk("do_tx_done(%p)\n", ndev);
961 tx_done_idx = dev->tx_done_idx;
962 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
964 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
965 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
966 while ((tx_done_idx != dev->tx_free_idx) &&
967 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
972 if (cmdsts & CMDSTS_ERR)
973 ndev->stats.tx_errors++;
974 if (cmdsts & CMDSTS_OK)
975 ndev->stats.tx_packets++;
976 if (cmdsts & CMDSTS_OK)
977 ndev->stats.tx_bytes += cmdsts & 0xffff;
979 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
980 tx_done_idx, dev->tx_free_idx, cmdsts);
981 skb = dev->tx_skbs[tx_done_idx];
982 dev->tx_skbs[tx_done_idx] = NULL;
983 dprintk("done(%p)\n", skb);
985 len = cmdsts & CMDSTS_LEN_MASK;
986 addr = desc_addr_get(desc + DESC_BUFPTR);
988 dma_unmap_single(&dev->pci_dev->dev, addr, len,
990 dev_consume_skb_irq(skb);
991 atomic_dec(&dev->nr_tx_skbs);
993 dma_unmap_page(&dev->pci_dev->dev, addr, len,
996 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
997 dev->tx_done_idx = tx_done_idx;
998 desc[DESC_CMDSTS] = cpu_to_le32(0);
1000 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1003 /* Allow network stack to resume queueing packets after we've
1004 * finished transmitting at least 1/4 of the packets in the queue.
1006 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1007 dprintk("start_queue(%p)\n", ndev);
1008 netif_start_queue(ndev);
1009 netif_wake_queue(ndev);
1013 static void ns83820_cleanup_tx(struct ns83820 *dev)
1017 for (i=0; i<NR_TX_DESC; i++) {
1018 struct sk_buff *skb = dev->tx_skbs[i];
1019 dev->tx_skbs[i] = NULL;
1021 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1022 dma_unmap_single(&dev->pci_dev->dev,
1023 desc_addr_get(desc + DESC_BUFPTR),
1024 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1026 dev_kfree_skb_irq(skb);
1027 atomic_dec(&dev->nr_tx_skbs);
1031 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1034 /* transmit routine. This code relies on the network layer serializing
1035 * its calls in, but will run happily in parallel with the interrupt
1036 * handler. This code currently has provisions for fragmenting tx buffers
1037 * while trying to track down a bug in either the zero copy code or
1038 * the tx fifo (hence the MAX_FRAG_LEN).
1040 static netdev_tx_t ns83820_hard_start_xmit(struct sk_buff *skb,
1041 struct net_device *ndev)
1043 struct ns83820 *dev = PRIV(ndev);
1044 u32 free_idx, cmdsts, extsts;
1045 int nr_free, nr_frags;
1046 unsigned tx_done_idx, last_idx;
1052 volatile __le32 *first_desc;
1054 dprintk("ns83820_hard_start_xmit\n");
1056 nr_frags = skb_shinfo(skb)->nr_frags;
1058 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1059 netif_stop_queue(ndev);
1060 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1061 return NETDEV_TX_BUSY;
1062 netif_start_queue(ndev);
1065 last_idx = free_idx = dev->tx_free_idx;
1066 tx_done_idx = dev->tx_done_idx;
1067 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1069 if (nr_free <= nr_frags) {
1070 dprintk("stop_queue - not enough(%p)\n", ndev);
1071 netif_stop_queue(ndev);
1073 /* Check again: we may have raced with a tx done irq */
1074 if (dev->tx_done_idx != tx_done_idx) {
1075 dprintk("restart queue(%p)\n", ndev);
1076 netif_start_queue(ndev);
1079 return NETDEV_TX_BUSY;
1082 if (free_idx == dev->tx_intr_idx) {
1084 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1087 nr_free -= nr_frags;
1088 if (nr_free < MIN_TX_DESC_FREE) {
1089 dprintk("stop_queue - last entry(%p)\n", ndev);
1090 netif_stop_queue(ndev);
1094 frag = skb_shinfo(skb)->frags;
1098 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1099 extsts |= EXTSTS_IPPKT;
1100 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1101 extsts |= EXTSTS_TCPPKT;
1102 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1103 extsts |= EXTSTS_UDPPKT;
1106 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1107 if (skb_vlan_tag_present(skb)) {
1108 /* fetch the vlan tag info out of the
1109 * ancillary data if the vlan code
1110 * is using hw vlan acceleration
1112 short tag = skb_vlan_tag_get(skb);
1113 extsts |= (EXTSTS_VPKT | htons(tag));
1119 len -= skb->data_len;
1120 buf = dma_map_single(&dev->pci_dev->dev, skb->data, len,
1123 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1126 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1128 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1129 (unsigned long long)buf);
1130 last_idx = free_idx;
1131 free_idx = (free_idx + 1) % NR_TX_DESC;
1132 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1133 desc_addr_set(desc + DESC_BUFPTR, buf);
1134 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1136 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1137 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1139 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1144 buf = skb_frag_dma_map(&dev->pci_dev->dev, frag, 0,
1145 skb_frag_size(frag), DMA_TO_DEVICE);
1146 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1147 (long long)buf, (long) page_to_pfn(frag->page),
1149 len = skb_frag_size(frag);
1153 dprintk("done pkt\n");
1155 spin_lock_irq(&dev->tx_lock);
1156 dev->tx_skbs[last_idx] = skb;
1157 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1158 dev->tx_free_idx = free_idx;
1159 atomic_inc(&dev->nr_tx_skbs);
1160 spin_unlock_irq(&dev->tx_lock);
1164 /* Check again: we may have raced with a tx done irq */
1165 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1166 netif_start_queue(ndev);
1168 return NETDEV_TX_OK;
1171 static void ns83820_update_stats(struct ns83820 *dev)
1173 struct net_device *ndev = dev->ndev;
1174 u8 __iomem *base = dev->base;
1176 /* the DP83820 will freeze counters, so we need to read all of them */
1177 ndev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1178 ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1179 ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1180 ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1181 /*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1182 ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1183 ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1184 /*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1185 /*ndev->stats.rx_pause_count += */ readl(base + 0x80);
1186 /*ndev->stats.tx_pause_count += */ readl(base + 0x84);
1187 ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1190 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1192 struct ns83820 *dev = PRIV(ndev);
1194 /* somewhat overkill */
1195 spin_lock_irq(&dev->misc_lock);
1196 ns83820_update_stats(dev);
1197 spin_unlock_irq(&dev->misc_lock);
1199 return &ndev->stats;
1202 /* Let ethtool retrieve info */
1203 static int ns83820_get_link_ksettings(struct net_device *ndev,
1204 struct ethtool_link_ksettings *cmd)
1206 struct ns83820 *dev = PRIV(ndev);
1207 u32 cfg, tanar, tbicr;
1212 * Here's the list of available ethtool commands from other drivers:
1213 * cmd->advertising =
1214 * ethtool_cmd_speed_set(cmd, ...)
1217 * cmd->phy_address =
1218 * cmd->transceiver = 0;
1220 * cmd->maxtxpkt = 0;
1221 * cmd->maxrxpkt = 0;
1224 /* read current configuration */
1225 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1226 tanar = readl(dev->base + TANAR);
1227 tbicr = readl(dev->base + TBICR);
1229 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1231 supported = SUPPORTED_Autoneg;
1233 if (dev->CFG_cache & CFG_TBI_EN) {
1234 /* we have optical interface */
1235 supported |= SUPPORTED_1000baseT_Half |
1236 SUPPORTED_1000baseT_Full |
1238 cmd->base.port = PORT_FIBRE;
1240 /* we have copper */
1241 supported |= SUPPORTED_10baseT_Half |
1242 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
1243 SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half |
1244 SUPPORTED_1000baseT_Full |
1246 cmd->base.port = PORT_MII;
1249 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1252 cmd->base.duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1253 switch (cfg / CFG_SPDSTS0 & 3) {
1255 cmd->base.speed = SPEED_1000;
1258 cmd->base.speed = SPEED_100;
1261 cmd->base.speed = SPEED_10;
1264 cmd->base.autoneg = (tbicr & TBICR_MR_AN_ENABLE)
1265 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1269 /* Let ethool change settings*/
1270 static int ns83820_set_link_ksettings(struct net_device *ndev,
1271 const struct ethtool_link_ksettings *cmd)
1273 struct ns83820 *dev = PRIV(ndev);
1275 int have_optical = 0;
1278 /* read current configuration */
1279 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1280 tanar = readl(dev->base + TANAR);
1282 if (dev->CFG_cache & CFG_TBI_EN) {
1283 /* we have optical */
1285 fullduplex = (tanar & TANAR_FULL_DUP);
1288 /* we have copper */
1289 fullduplex = cfg & CFG_DUPSTS;
1292 spin_lock_irq(&dev->misc_lock);
1293 spin_lock(&dev->tx_lock);
1296 if (cmd->base.duplex != fullduplex) {
1299 if (cmd->base.duplex == DUPLEX_FULL) {
1300 /* force full duplex */
1301 writel(readl(dev->base + TXCFG)
1302 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
1304 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1306 /* Light up full duplex LED */
1307 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1310 /*TODO: set half duplex */
1315 /* TODO: Set duplex for copper cards */
1317 printk(KERN_INFO "%s: Duplex set via ethtool\n",
1321 /* Set autonegotiation */
1323 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1324 /* restart auto negotiation */
1325 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1327 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1328 dev->linkstate = LINK_AUTONEGOTIATE;
1330 printk(KERN_INFO "%s: autoneg enabled via ethtool\n",
1333 /* disable auto negotiation */
1334 writel(0x00000000, dev->base + TBICR);
1337 printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
1338 cmd->base.autoneg ? "ENABLED" : "DISABLED");
1342 spin_unlock(&dev->tx_lock);
1343 spin_unlock_irq(&dev->misc_lock);
1347 /* end ethtool get/set support -df */
1349 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1351 struct ns83820 *dev = PRIV(ndev);
1352 strlcpy(info->driver, "ns83820", sizeof(info->driver));
1353 strlcpy(info->version, VERSION, sizeof(info->version));
1354 strlcpy(info->bus_info, pci_name(dev->pci_dev), sizeof(info->bus_info));
1357 static u32 ns83820_get_link(struct net_device *ndev)
1359 struct ns83820 *dev = PRIV(ndev);
1360 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1361 return cfg & CFG_LNKSTS ? 1 : 0;
1364 static const struct ethtool_ops ops = {
1365 .get_drvinfo = ns83820_get_drvinfo,
1366 .get_link = ns83820_get_link,
1367 .get_link_ksettings = ns83820_get_link_ksettings,
1368 .set_link_ksettings = ns83820_set_link_ksettings,
1371 static inline void ns83820_disable_interrupts(struct ns83820 *dev)
1373 writel(0, dev->base + IMR);
1374 writel(0, dev->base + IER);
1375 readl(dev->base + IER);
1378 /* this function is called in irq context from the ISR */
1379 static void ns83820_mib_isr(struct ns83820 *dev)
1381 unsigned long flags;
1382 spin_lock_irqsave(&dev->misc_lock, flags);
1383 ns83820_update_stats(dev);
1384 spin_unlock_irqrestore(&dev->misc_lock, flags);
1387 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1388 static irqreturn_t ns83820_irq(int foo, void *data)
1390 struct net_device *ndev = data;
1391 struct ns83820 *dev = PRIV(ndev);
1393 dprintk("ns83820_irq(%p)\n", ndev);
1397 isr = readl(dev->base + ISR);
1398 dprintk("irq: %08x\n", isr);
1399 ns83820_do_isr(ndev, isr);
1403 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1405 struct ns83820 *dev = PRIV(ndev);
1406 unsigned long flags;
1409 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1410 Dprintk("odd isr? 0x%08x\n", isr);
1413 if (ISR_RXIDLE & isr) {
1414 dev->rx_info.idle = 1;
1415 Dprintk("oh dear, we are idle\n");
1416 ns83820_rx_kick(ndev);
1419 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1420 prefetch(dev->rx_info.next_rx_desc);
1422 spin_lock_irqsave(&dev->misc_lock, flags);
1423 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1424 writel(dev->IMR_cache, dev->base + IMR);
1425 spin_unlock_irqrestore(&dev->misc_lock, flags);
1427 tasklet_schedule(&dev->rx_tasklet);
1429 //writel(4, dev->base + IHR);
1432 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1433 ns83820_rx_kick(ndev);
1435 if (unlikely(ISR_RXSOVR & isr)) {
1436 //printk("overrun: rxsovr\n");
1437 ndev->stats.rx_fifo_errors++;
1440 if (unlikely(ISR_RXORN & isr)) {
1441 //printk("overrun: rxorn\n");
1442 ndev->stats.rx_fifo_errors++;
1445 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1446 writel(CR_RXE, dev->base + CR);
1448 if (ISR_TXIDLE & isr) {
1450 txdp = readl(dev->base + TXDP);
1451 dprintk("txdp: %08x\n", txdp);
1452 txdp -= dev->tx_phy_descs;
1453 dev->tx_idx = txdp / (DESC_SIZE * 4);
1454 if (dev->tx_idx >= NR_TX_DESC) {
1455 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1458 /* The may have been a race between a pci originated read
1459 * and the descriptor update from the cpu. Just in case,
1460 * kick the transmitter if the hardware thinks it is on a
1461 * different descriptor than we are.
1463 if (dev->tx_idx != dev->tx_free_idx)
1467 /* Defer tx ring processing until more than a minimum amount of
1468 * work has accumulated
1470 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1471 spin_lock_irqsave(&dev->tx_lock, flags);
1473 spin_unlock_irqrestore(&dev->tx_lock, flags);
1475 /* Disable TxOk if there are no outstanding tx packets.
1477 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1478 (dev->IMR_cache & ISR_TXOK)) {
1479 spin_lock_irqsave(&dev->misc_lock, flags);
1480 dev->IMR_cache &= ~ISR_TXOK;
1481 writel(dev->IMR_cache, dev->base + IMR);
1482 spin_unlock_irqrestore(&dev->misc_lock, flags);
1486 /* The TxIdle interrupt can come in before the transmit has
1487 * completed. Normally we reap packets off of the combination
1488 * of TxDesc and TxIdle and leave TxOk disabled (since it
1489 * occurs on every packet), but when no further irqs of this
1490 * nature are expected, we must enable TxOk.
1492 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1493 spin_lock_irqsave(&dev->misc_lock, flags);
1494 dev->IMR_cache |= ISR_TXOK;
1495 writel(dev->IMR_cache, dev->base + IMR);
1496 spin_unlock_irqrestore(&dev->misc_lock, flags);
1499 /* MIB interrupt: one of the statistics counters is about to overflow */
1500 if (unlikely(ISR_MIB & isr))
1501 ns83820_mib_isr(dev);
1503 /* PHY: Link up/down/negotiation state change */
1504 if (unlikely(ISR_PHY & isr))
1507 #if 0 /* Still working on the interrupt mitigation strategy */
1509 writel(dev->ihr, dev->base + IHR);
1513 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1515 Dprintk("resetting chip...\n");
1516 writel(which, dev->base + CR);
1519 } while (readl(dev->base + CR) & which);
1523 static int ns83820_stop(struct net_device *ndev)
1525 struct ns83820 *dev = PRIV(ndev);
1527 /* FIXME: protect against interrupt handler? */
1528 del_timer_sync(&dev->tx_watchdog);
1530 ns83820_disable_interrupts(dev);
1532 dev->rx_info.up = 0;
1533 synchronize_irq(dev->pci_dev->irq);
1535 ns83820_do_reset(dev, CR_RST);
1537 synchronize_irq(dev->pci_dev->irq);
1539 spin_lock_irq(&dev->misc_lock);
1540 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1541 spin_unlock_irq(&dev->misc_lock);
1543 ns83820_cleanup_rx(dev);
1544 ns83820_cleanup_tx(dev);
1549 static void ns83820_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1551 struct ns83820 *dev = PRIV(ndev);
1554 unsigned long flags;
1556 spin_lock_irqsave(&dev->tx_lock, flags);
1558 tx_done_idx = dev->tx_done_idx;
1559 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1561 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1563 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1568 isr = readl(dev->base + ISR);
1569 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1570 ns83820_do_isr(ndev, isr);
1576 tx_done_idx = dev->tx_done_idx;
1577 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1579 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1581 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1583 spin_unlock_irqrestore(&dev->tx_lock, flags);
1586 static void ns83820_tx_watch(struct timer_list *t)
1588 struct ns83820 *dev = from_timer(dev, t, tx_watchdog);
1589 struct net_device *ndev = dev->ndev;
1592 printk("ns83820_tx_watch: %u %u %d\n",
1593 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1597 if (time_after(jiffies, dev_trans_start(ndev) + 1*HZ) &&
1598 dev->tx_done_idx != dev->tx_free_idx) {
1599 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1601 dev->tx_done_idx, dev->tx_free_idx,
1602 atomic_read(&dev->nr_tx_skbs));
1603 ns83820_tx_timeout(ndev, UINT_MAX);
1606 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1609 static int ns83820_open(struct net_device *ndev)
1611 struct ns83820 *dev = PRIV(ndev);
1616 dprintk("ns83820_open\n");
1618 writel(0, dev->base + PQCR);
1620 ret = ns83820_setup_rx(ndev);
1624 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1625 for (i=0; i<NR_TX_DESC; i++) {
1626 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1629 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1633 dev->tx_done_idx = 0;
1634 desc = dev->tx_phy_descs;
1635 writel(0, dev->base + TXDP_HI);
1636 writel(desc, dev->base + TXDP);
1638 timer_setup(&dev->tx_watchdog, ns83820_tx_watch, 0);
1639 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1641 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1650 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1653 for (i=0; i<3; i++) {
1656 /* Read from the perfect match memory: this is loaded by
1657 * the chip from the EEPROM via the EELOAD self test.
1659 writel(i*2, dev->base + RFCR);
1660 data = readl(dev->base + RFDR);
1667 static void ns83820_set_multicast(struct net_device *ndev)
1669 struct ns83820 *dev = PRIV(ndev);
1670 u8 __iomem *rfcr = dev->base + RFCR;
1671 u32 and_mask = 0xffffffff;
1675 if (ndev->flags & IFF_PROMISC)
1676 or_mask |= RFCR_AAU | RFCR_AAM;
1678 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1680 if (ndev->flags & IFF_ALLMULTI || netdev_mc_count(ndev))
1681 or_mask |= RFCR_AAM;
1683 and_mask &= ~RFCR_AAM;
1685 spin_lock_irq(&dev->misc_lock);
1686 val = (readl(rfcr) & and_mask) | or_mask;
1687 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1688 writel(val & ~RFCR_RFEN, rfcr);
1690 spin_unlock_irq(&dev->misc_lock);
1693 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1695 struct ns83820 *dev = PRIV(ndev);
1697 unsigned long start;
1701 dprintk("%s: start %s\n", ndev->name, name);
1705 writel(enable, dev->base + PTSCR);
1708 status = readl(dev->base + PTSCR);
1709 if (!(status & enable))
1715 if (time_after_eq(jiffies, start + HZ)) {
1719 schedule_timeout_uninterruptible(1);
1723 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1724 ndev->name, name, status, fail);
1726 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1727 ndev->name, name, status);
1729 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1732 #ifdef PHY_CODE_IS_FINISHED
1733 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1736 dev->MEAR_cache &= ~MEAR_MDC;
1737 writel(dev->MEAR_cache, dev->base + MEAR);
1738 readl(dev->base + MEAR);
1740 /* enable output, set bit */
1741 dev->MEAR_cache |= MEAR_MDDIR;
1743 dev->MEAR_cache |= MEAR_MDIO;
1745 dev->MEAR_cache &= ~MEAR_MDIO;
1747 /* set the output bit */
1748 writel(dev->MEAR_cache, dev->base + MEAR);
1749 readl(dev->base + MEAR);
1751 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1754 /* drive MDC high causing the data bit to be latched */
1755 dev->MEAR_cache |= MEAR_MDC;
1756 writel(dev->MEAR_cache, dev->base + MEAR);
1757 readl(dev->base + MEAR);
1763 static int ns83820_mii_read_bit(struct ns83820 *dev)
1767 /* drive MDC low, disable output */
1768 dev->MEAR_cache &= ~MEAR_MDC;
1769 dev->MEAR_cache &= ~MEAR_MDDIR;
1770 writel(dev->MEAR_cache, dev->base + MEAR);
1771 readl(dev->base + MEAR);
1773 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1776 /* drive MDC high causing the data bit to be latched */
1777 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1778 dev->MEAR_cache |= MEAR_MDC;
1779 writel(dev->MEAR_cache, dev->base + MEAR);
1787 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1792 /* read some garbage so that we eventually sync up */
1793 for (i=0; i<64; i++)
1794 ns83820_mii_read_bit(dev);
1796 ns83820_mii_write_bit(dev, 0); /* start */
1797 ns83820_mii_write_bit(dev, 1);
1798 ns83820_mii_write_bit(dev, 1); /* opcode read */
1799 ns83820_mii_write_bit(dev, 0);
1801 /* write out the phy address: 5 bits, msb first */
1803 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1805 /* write out the register address, 5 bits, msb first */
1807 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1809 ns83820_mii_read_bit(dev); /* turn around cycles */
1810 ns83820_mii_read_bit(dev);
1812 /* read in the register data, 16 bits msb first */
1813 for (i=0; i<16; i++) {
1815 data |= ns83820_mii_read_bit(dev);
1821 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1825 /* read some garbage so that we eventually sync up */
1826 for (i=0; i<64; i++)
1827 ns83820_mii_read_bit(dev);
1829 ns83820_mii_write_bit(dev, 0); /* start */
1830 ns83820_mii_write_bit(dev, 1);
1831 ns83820_mii_write_bit(dev, 0); /* opcode read */
1832 ns83820_mii_write_bit(dev, 1);
1834 /* write out the phy address: 5 bits, msb first */
1836 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1838 /* write out the register address, 5 bits, msb first */
1840 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1842 ns83820_mii_read_bit(dev); /* turn around cycles */
1843 ns83820_mii_read_bit(dev);
1845 /* read in the register data, 16 bits msb first */
1846 for (i=0; i<16; i++)
1847 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1852 static void ns83820_probe_phy(struct net_device *ndev)
1854 struct ns83820 *dev = PRIV(ndev);
1858 for (j = 0; j < 0x16; j += 4) {
1859 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1861 ns83820_mii_read_reg(dev, 1, 0 + j),
1862 ns83820_mii_read_reg(dev, 1, 1 + j),
1863 ns83820_mii_read_reg(dev, 1, 2 + j),
1864 ns83820_mii_read_reg(dev, 1, 3 + j)
1868 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1869 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1870 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1871 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1873 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1874 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1875 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1876 dprintk("version: 0x%04x 0x%04x\n", a, b);
1880 static const struct net_device_ops netdev_ops = {
1881 .ndo_open = ns83820_open,
1882 .ndo_stop = ns83820_stop,
1883 .ndo_start_xmit = ns83820_hard_start_xmit,
1884 .ndo_get_stats = ns83820_get_stats,
1885 .ndo_set_rx_mode = ns83820_set_multicast,
1886 .ndo_validate_addr = eth_validate_addr,
1887 .ndo_set_mac_address = eth_mac_addr,
1888 .ndo_tx_timeout = ns83820_tx_timeout,
1891 static int ns83820_init_one(struct pci_dev *pci_dev,
1892 const struct pci_device_id *id)
1894 struct net_device *ndev;
1895 struct ns83820 *dev;
1900 /* See if we can set the dma mask early on; failure is fatal. */
1901 if (sizeof(dma_addr_t) == 8 &&
1902 !dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(64))) {
1904 } else if (!dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32))) {
1907 dev_warn(&pci_dev->dev, "dma_set_mask failed!\n");
1911 ndev = alloc_etherdev(sizeof(struct ns83820));
1919 spin_lock_init(&dev->rx_info.lock);
1920 spin_lock_init(&dev->tx_lock);
1921 spin_lock_init(&dev->misc_lock);
1922 dev->pci_dev = pci_dev;
1924 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1926 INIT_WORK(&dev->tq_refill, queue_refill);
1927 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1929 err = pci_enable_device(pci_dev);
1931 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1935 pci_set_master(pci_dev);
1936 addr = pci_resource_start(pci_dev, 1);
1937 dev->base = ioremap(addr, PAGE_SIZE);
1938 dev->tx_descs = dma_alloc_coherent(&pci_dev->dev,
1939 4 * DESC_SIZE * NR_TX_DESC,
1940 &dev->tx_phy_descs, GFP_KERNEL);
1941 dev->rx_info.descs = dma_alloc_coherent(&pci_dev->dev,
1942 4 * DESC_SIZE * NR_RX_DESC,
1943 &dev->rx_info.phy_descs, GFP_KERNEL);
1945 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1948 dprintk("%p: %08lx %p: %08lx\n",
1949 dev->tx_descs, (long)dev->tx_phy_descs,
1950 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1952 ns83820_disable_interrupts(dev);
1956 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
1959 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
1965 * FIXME: we are holding rtnl_lock() over obscenely long area only
1966 * because some of the setup code uses dev->name. It's Wrong(tm) -
1967 * we should be using driver-specific names for all that stuff.
1968 * For now that will do, but we really need to come back and kill
1969 * most of the dev_alloc_name() users later.
1972 err = dev_alloc_name(ndev, ndev->name);
1974 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1978 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1979 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1980 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1982 ndev->netdev_ops = &netdev_ops;
1983 ndev->ethtool_ops = &ops;
1984 ndev->watchdog_timeo = 5 * HZ;
1985 pci_set_drvdata(pci_dev, ndev);
1987 ns83820_do_reset(dev, CR_RST);
1989 /* Must reset the ram bist before running it */
1990 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1991 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1992 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1993 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1995 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1997 /* I love config registers */
1998 dev->CFG_cache = readl(dev->base + CFG);
2000 if ((dev->CFG_cache & CFG_PCI64_DET)) {
2001 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
2003 /*dev->CFG_cache |= CFG_DATA64_EN;*/
2004 if (!(dev->CFG_cache & CFG_DATA64_EN))
2005 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
2008 dev->CFG_cache &= ~(CFG_DATA64_EN);
2010 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
2011 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
2013 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2014 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
2015 dev->CFG_cache |= CFG_REQALG;
2016 dev->CFG_cache |= CFG_POW;
2017 dev->CFG_cache |= CFG_TMRTEST;
2019 /* When compiled with 64 bit addressing, we must always enable
2020 * the 64 bit descriptor format.
2022 if (sizeof(dma_addr_t) == 8)
2023 dev->CFG_cache |= CFG_M64ADDR;
2025 dev->CFG_cache |= CFG_T64ADDR;
2027 /* Big endian mode does not seem to do what the docs suggest */
2028 dev->CFG_cache &= ~CFG_BEM;
2030 /* setup optical transceiver if we have one */
2031 if (dev->CFG_cache & CFG_TBI_EN) {
2032 printk(KERN_INFO "%s: enabling optical transceiver\n",
2034 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2036 /* setup auto negotiation feature advertisement */
2037 writel(readl(dev->base + TANAR)
2038 | TANAR_HALF_DUP | TANAR_FULL_DUP,
2041 /* start auto negotiation */
2042 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
2044 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2045 dev->linkstate = LINK_AUTONEGOTIATE;
2047 dev->CFG_cache |= CFG_MODE_1000;
2050 writel(dev->CFG_cache, dev->base + CFG);
2051 dprintk("CFG: %08x\n", dev->CFG_cache);
2054 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2055 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2057 writel(dev->CFG_cache, dev->base + CFG);
2060 #if 0 /* Huh? This sets the PCI latency register. Should be done via
2061 * the PCI layer. FIXME.
2063 if (readl(dev->base + SRR))
2064 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2067 /* Note! The DMA burst size interacts with packet
2068 * transmission, such that the largest packet that
2069 * can be transmitted is 8192 - FLTH - burst size.
2070 * If only the transmit fifo was larger...
2072 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2073 * some DELL and COMPAQ SMP systems */
2074 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2075 | ((1600 / 32) * 0x100),
2078 /* Flush the interrupt holdoff timer */
2079 writel(0x000, dev->base + IHR);
2080 writel(0x100, dev->base + IHR);
2081 writel(0x000, dev->base + IHR);
2083 /* Set Rx to full duplex, don't accept runt, errored, long or length
2084 * range errored packets. Use 512 byte DMA.
2086 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2087 * some DELL and COMPAQ SMP systems
2088 * Turn on ALP, only we are accpeting Jumbo Packets */
2089 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2092 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2094 /* Disable priority queueing */
2095 writel(0, dev->base + PQCR);
2097 /* Enable IP checksum validation and detetion of VLAN headers.
2098 * Note: do not set the reject options as at least the 0x102
2099 * revision of the chip does not properly accept IP fragments
2102 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2103 * the MAC it calculates the packetsize AFTER stripping the VLAN
2104 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2105 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2106 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2107 * it discrards it!. These guys......
2108 * also turn on tag stripping if hardware acceleration is enabled
2110 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2111 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2113 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2115 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2117 /* Enable per-packet TCP/UDP/IP checksumming
2118 * and per packet vlan tag insertion if
2119 * vlan hardware acceleration is enabled
2121 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2122 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2124 #define VTCR_INIT_VALUE VTCR_PPCHK
2126 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2128 /* Ramit : Enable async and sync pause frames */
2129 /* writel(0, dev->base + PCR); */
2130 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2131 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2134 /* Disable Wake On Lan */
2135 writel(0, dev->base + WCSR);
2137 ns83820_getmac(dev, ndev->dev_addr);
2139 /* Yes, we support dumb IP checksum on transmit */
2140 ndev->features |= NETIF_F_SG;
2141 ndev->features |= NETIF_F_IP_CSUM;
2145 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2146 /* We also support hardware vlan acceleration */
2147 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
2151 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2153 ndev->features |= NETIF_F_HIGHDMA;
2156 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n",
2158 (unsigned)readl(dev->base + SRR) >> 8,
2159 (unsigned)readl(dev->base + SRR) & 0xff,
2160 ndev->dev_addr, addr, pci_dev->irq,
2161 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2164 #ifdef PHY_CODE_IS_FINISHED
2165 ns83820_probe_phy(ndev);
2168 err = register_netdevice(ndev);
2170 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2178 ns83820_disable_interrupts(dev); /* paranoia */
2181 free_irq(pci_dev->irq, ndev);
2185 dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
2186 dev->tx_descs, dev->tx_phy_descs);
2187 dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
2188 dev->rx_info.descs, dev->rx_info.phy_descs);
2189 pci_disable_device(pci_dev);
2196 static void ns83820_remove_one(struct pci_dev *pci_dev)
2198 struct net_device *ndev = pci_get_drvdata(pci_dev);
2199 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2201 if (!ndev) /* paranoia */
2204 ns83820_disable_interrupts(dev); /* paranoia */
2206 unregister_netdev(ndev);
2207 free_irq(dev->pci_dev->irq, ndev);
2209 dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
2210 dev->tx_descs, dev->tx_phy_descs);
2211 dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
2212 dev->rx_info.descs, dev->rx_info.phy_descs);
2213 pci_disable_device(dev->pci_dev);
2217 static const struct pci_device_id ns83820_pci_tbl[] = {
2218 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2222 static struct pci_driver driver = {
2224 .id_table = ns83820_pci_tbl,
2225 .probe = ns83820_init_one,
2226 .remove = ns83820_remove_one,
2227 #if 0 /* FIXME: implement */
2234 static int __init ns83820_init(void)
2236 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2237 return pci_register_driver(&driver);
2240 static void __exit ns83820_exit(void)
2242 pci_unregister_driver(&driver);
2245 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2246 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2247 MODULE_LICENSE("GPL");
2249 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2251 module_param(lnksts, int, 0);
2252 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2254 module_param(ihr, int, 0);
2255 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2257 module_param(reset_phy, int, 0);
2258 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2260 module_init(ns83820_init);
2261 module_exit(ns83820_exit);