1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/dsa/ocelot.h>
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
10 #include <linux/of_net.h>
11 #include <linux/netdevice.h>
12 #include <linux/of_mdio.h>
13 #include <linux/of_platform.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/skbuff.h>
16 #include <net/switchdev.h>
18 #include <soc/mscc/ocelot_vcap.h>
19 #include <soc/mscc/ocelot_hsio.h>
22 static const u32 ocelot_ana_regmap[] = {
23 REG(ANA_ADVLEARN, 0x009000),
24 REG(ANA_VLANMASK, 0x009004),
25 REG(ANA_PORT_B_DOMAIN, 0x009008),
26 REG(ANA_ANAGEFIL, 0x00900c),
27 REG(ANA_ANEVENTS, 0x009010),
28 REG(ANA_STORMLIMIT_BURST, 0x009014),
29 REG(ANA_STORMLIMIT_CFG, 0x009018),
30 REG(ANA_ISOLATED_PORTS, 0x009028),
31 REG(ANA_COMMUNITY_PORTS, 0x00902c),
32 REG(ANA_AUTOAGE, 0x009030),
33 REG(ANA_MACTOPTIONS, 0x009034),
34 REG(ANA_LEARNDISC, 0x009038),
35 REG(ANA_AGENCTRL, 0x00903c),
36 REG(ANA_MIRRORPORTS, 0x009040),
37 REG(ANA_EMIRRORPORTS, 0x009044),
38 REG(ANA_FLOODING, 0x009048),
39 REG(ANA_FLOODING_IPMC, 0x00904c),
40 REG(ANA_SFLOW_CFG, 0x009050),
41 REG(ANA_PORT_MODE, 0x009080),
42 REG(ANA_PGID_PGID, 0x008c00),
43 REG(ANA_TABLES_ANMOVED, 0x008b30),
44 REG(ANA_TABLES_MACHDATA, 0x008b34),
45 REG(ANA_TABLES_MACLDATA, 0x008b38),
46 REG(ANA_TABLES_MACACCESS, 0x008b3c),
47 REG(ANA_TABLES_MACTINDX, 0x008b40),
48 REG(ANA_TABLES_VLANACCESS, 0x008b44),
49 REG(ANA_TABLES_VLANTIDX, 0x008b48),
50 REG(ANA_TABLES_ISDXACCESS, 0x008b4c),
51 REG(ANA_TABLES_ISDXTIDX, 0x008b50),
52 REG(ANA_TABLES_ENTRYLIM, 0x008b00),
53 REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54),
54 REG(ANA_TABLES_PTP_ID_LOW, 0x008b58),
55 REG(ANA_MSTI_STATE, 0x008e00),
56 REG(ANA_PORT_VLAN_CFG, 0x007000),
57 REG(ANA_PORT_DROP_CFG, 0x007004),
58 REG(ANA_PORT_QOS_CFG, 0x007008),
59 REG(ANA_PORT_VCAP_CFG, 0x00700c),
60 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010),
61 REG(ANA_PORT_VCAP_S2_CFG, 0x00701c),
62 REG(ANA_PORT_PCP_DEI_MAP, 0x007020),
63 REG(ANA_PORT_CPU_FWD_CFG, 0x007060),
64 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064),
65 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068),
66 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c),
67 REG(ANA_PORT_PORT_CFG, 0x007070),
68 REG(ANA_PORT_POL_CFG, 0x007074),
69 REG(ANA_PORT_PTP_CFG, 0x007078),
70 REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c),
71 REG(ANA_OAM_UPM_LM_CNT, 0x007c00),
72 REG(ANA_PORT_PTP_DLY2_CFG, 0x007080),
73 REG(ANA_PFC_PFC_CFG, 0x008800),
74 REG(ANA_PFC_PFC_TIMER, 0x008804),
75 REG(ANA_IPT_OAM_MEP_CFG, 0x008000),
76 REG(ANA_IPT_IPT, 0x008004),
77 REG(ANA_PPT_PPT, 0x008ac0),
78 REG(ANA_FID_MAP_FID_MAP, 0x000000),
79 REG(ANA_AGGR_CFG, 0x0090b4),
80 REG(ANA_CPUQ_CFG, 0x0090b8),
81 REG(ANA_CPUQ_CFG2, 0x0090bc),
82 REG(ANA_CPUQ_8021_CFG, 0x0090c0),
83 REG(ANA_DSCP_CFG, 0x009100),
84 REG(ANA_DSCP_REWR_CFG, 0x009200),
85 REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240),
86 REG(ANA_VCAP_RNG_VAL_CFG, 0x009260),
87 REG(ANA_VRAP_CFG, 0x009280),
88 REG(ANA_VRAP_HDR_DATA, 0x009284),
89 REG(ANA_VRAP_HDR_MASK, 0x009288),
90 REG(ANA_DISCARD_CFG, 0x00928c),
91 REG(ANA_FID_CFG, 0x009290),
92 REG(ANA_POL_PIR_CFG, 0x004000),
93 REG(ANA_POL_CIR_CFG, 0x004004),
94 REG(ANA_POL_MODE_CFG, 0x004008),
95 REG(ANA_POL_PIR_STATE, 0x00400c),
96 REG(ANA_POL_CIR_STATE, 0x004010),
97 REG(ANA_POL_STATE, 0x004014),
98 REG(ANA_POL_FLOWC, 0x008b80),
99 REG(ANA_POL_HYST, 0x008bec),
100 REG(ANA_POL_MISC_CFG, 0x008bf0),
103 static const u32 ocelot_qs_regmap[] = {
104 REG(QS_XTR_GRP_CFG, 0x000000),
105 REG(QS_XTR_RD, 0x000008),
106 REG(QS_XTR_FRM_PRUNING, 0x000010),
107 REG(QS_XTR_FLUSH, 0x000018),
108 REG(QS_XTR_DATA_PRESENT, 0x00001c),
109 REG(QS_XTR_CFG, 0x000020),
110 REG(QS_INJ_GRP_CFG, 0x000024),
111 REG(QS_INJ_WR, 0x00002c),
112 REG(QS_INJ_CTRL, 0x000034),
113 REG(QS_INJ_STATUS, 0x00003c),
114 REG(QS_INJ_ERR, 0x000040),
115 REG(QS_INH_DBG, 0x000048),
118 static const u32 ocelot_qsys_regmap[] = {
119 REG(QSYS_PORT_MODE, 0x011200),
120 REG(QSYS_SWITCH_PORT_MODE, 0x011234),
121 REG(QSYS_STAT_CNT_CFG, 0x011264),
122 REG(QSYS_EEE_CFG, 0x011268),
123 REG(QSYS_EEE_THRES, 0x011294),
124 REG(QSYS_IGR_NO_SHARING, 0x011298),
125 REG(QSYS_EGR_NO_SHARING, 0x01129c),
126 REG(QSYS_SW_STATUS, 0x0112a0),
127 REG(QSYS_EXT_CPU_CFG, 0x0112d0),
128 REG(QSYS_PAD_CFG, 0x0112d4),
129 REG(QSYS_CPU_GROUP_MAP, 0x0112d8),
130 REG(QSYS_QMAP, 0x0112dc),
131 REG(QSYS_ISDX_SGRP, 0x011400),
132 REG(QSYS_TIMED_FRAME_ENTRY, 0x014000),
133 REG(QSYS_TFRM_MISC, 0x011310),
134 REG(QSYS_TFRM_PORT_DLY, 0x011314),
135 REG(QSYS_TFRM_TIMER_CFG_1, 0x011318),
136 REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c),
137 REG(QSYS_TFRM_TIMER_CFG_3, 0x011320),
138 REG(QSYS_TFRM_TIMER_CFG_4, 0x011324),
139 REG(QSYS_TFRM_TIMER_CFG_5, 0x011328),
140 REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c),
141 REG(QSYS_TFRM_TIMER_CFG_7, 0x011330),
142 REG(QSYS_TFRM_TIMER_CFG_8, 0x011334),
143 REG(QSYS_RED_PROFILE, 0x011338),
144 REG(QSYS_RES_QOS_MODE, 0x011378),
145 REG(QSYS_RES_CFG, 0x012000),
146 REG(QSYS_RES_STAT, 0x012004),
147 REG(QSYS_EGR_DROP_MODE, 0x01137c),
148 REG(QSYS_EQ_CTRL, 0x011380),
149 REG(QSYS_EVENTS_CORE, 0x011384),
150 REG(QSYS_CIR_CFG, 0x000000),
151 REG(QSYS_EIR_CFG, 0x000004),
152 REG(QSYS_SE_CFG, 0x000008),
153 REG(QSYS_SE_DWRR_CFG, 0x00000c),
154 REG(QSYS_SE_CONNECT, 0x00003c),
155 REG(QSYS_SE_DLB_SENSE, 0x000040),
156 REG(QSYS_CIR_STATE, 0x000044),
157 REG(QSYS_EIR_STATE, 0x000048),
158 REG(QSYS_SE_STATE, 0x00004c),
159 REG(QSYS_HSCH_MISC_CFG, 0x011388),
162 static const u32 ocelot_rew_regmap[] = {
163 REG(REW_PORT_VLAN_CFG, 0x000000),
164 REG(REW_TAG_CFG, 0x000004),
165 REG(REW_PORT_CFG, 0x000008),
166 REG(REW_DSCP_CFG, 0x00000c),
167 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
168 REG(REW_PTP_CFG, 0x000050),
169 REG(REW_PTP_DLY1_CFG, 0x000054),
170 REG(REW_DSCP_REMAP_DP1_CFG, 0x000690),
171 REG(REW_DSCP_REMAP_CFG, 0x000790),
172 REG(REW_STAT_CFG, 0x000890),
173 REG(REW_PPT, 0x000680),
176 static const u32 ocelot_sys_regmap[] = {
177 REG(SYS_COUNT_RX_OCTETS, 0x000000),
178 REG(SYS_COUNT_RX_UNICAST, 0x000004),
179 REG(SYS_COUNT_RX_MULTICAST, 0x000008),
180 REG(SYS_COUNT_RX_BROADCAST, 0x00000c),
181 REG(SYS_COUNT_RX_SHORTS, 0x000010),
182 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
183 REG(SYS_COUNT_RX_JABBERS, 0x000018),
184 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c),
185 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020),
186 REG(SYS_COUNT_RX_64, 0x000024),
187 REG(SYS_COUNT_RX_65_127, 0x000028),
188 REG(SYS_COUNT_RX_128_255, 0x00002c),
189 REG(SYS_COUNT_RX_256_1023, 0x000030),
190 REG(SYS_COUNT_RX_1024_1526, 0x000034),
191 REG(SYS_COUNT_RX_1527_MAX, 0x000038),
192 REG(SYS_COUNT_RX_PAUSE, 0x00003c),
193 REG(SYS_COUNT_RX_CONTROL, 0x000040),
194 REG(SYS_COUNT_RX_LONGS, 0x000044),
195 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048),
196 REG(SYS_COUNT_TX_OCTETS, 0x000100),
197 REG(SYS_COUNT_TX_UNICAST, 0x000104),
198 REG(SYS_COUNT_TX_MULTICAST, 0x000108),
199 REG(SYS_COUNT_TX_BROADCAST, 0x00010c),
200 REG(SYS_COUNT_TX_COLLISION, 0x000110),
201 REG(SYS_COUNT_TX_DROPS, 0x000114),
202 REG(SYS_COUNT_TX_PAUSE, 0x000118),
203 REG(SYS_COUNT_TX_64, 0x00011c),
204 REG(SYS_COUNT_TX_65_127, 0x000120),
205 REG(SYS_COUNT_TX_128_511, 0x000124),
206 REG(SYS_COUNT_TX_512_1023, 0x000128),
207 REG(SYS_COUNT_TX_1024_1526, 0x00012c),
208 REG(SYS_COUNT_TX_1527_MAX, 0x000130),
209 REG(SYS_COUNT_TX_AGING, 0x000170),
210 REG(SYS_RESET_CFG, 0x000508),
211 REG(SYS_CMID, 0x00050c),
212 REG(SYS_VLAN_ETYPE_CFG, 0x000510),
213 REG(SYS_PORT_MODE, 0x000514),
214 REG(SYS_FRONT_PORT_MODE, 0x000548),
215 REG(SYS_FRM_AGING, 0x000574),
216 REG(SYS_STAT_CFG, 0x000578),
217 REG(SYS_SW_STATUS, 0x00057c),
218 REG(SYS_MISC_CFG, 0x0005ac),
219 REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0),
220 REG(SYS_REW_MAC_LOW_CFG, 0x0005dc),
221 REG(SYS_CM_ADDR, 0x000500),
222 REG(SYS_CM_DATA, 0x000504),
223 REG(SYS_PAUSE_CFG, 0x000608),
224 REG(SYS_PAUSE_TOT_CFG, 0x000638),
225 REG(SYS_ATOP, 0x00063c),
226 REG(SYS_ATOP_TOT_CFG, 0x00066c),
227 REG(SYS_MAC_FC_CFG, 0x000670),
228 REG(SYS_MMGT, 0x00069c),
229 REG(SYS_MMGT_FAST, 0x0006a0),
230 REG(SYS_EVENTS_DIF, 0x0006a4),
231 REG(SYS_EVENTS_CORE, 0x0006b4),
232 REG(SYS_CNT, 0x000000),
233 REG(SYS_PTP_STATUS, 0x0006b8),
234 REG(SYS_PTP_TXSTAMP, 0x0006bc),
235 REG(SYS_PTP_NXT, 0x0006c0),
236 REG(SYS_PTP_CFG, 0x0006c4),
239 static const u32 ocelot_vcap_regmap[] = {
241 REG(VCAP_CORE_UPDATE_CTRL, 0x000000),
242 REG(VCAP_CORE_MV_CFG, 0x000004),
243 /* VCAP_CORE_CACHE */
244 REG(VCAP_CACHE_ENTRY_DAT, 0x000008),
245 REG(VCAP_CACHE_MASK_DAT, 0x000108),
246 REG(VCAP_CACHE_ACTION_DAT, 0x000208),
247 REG(VCAP_CACHE_CNT_DAT, 0x000308),
248 REG(VCAP_CACHE_TG_DAT, 0x000388),
250 REG(VCAP_CONST_VCAP_VER, 0x000398),
251 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c),
252 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0),
253 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4),
254 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8),
255 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac),
256 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0),
257 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4),
258 REG(VCAP_CONST_CORE_CNT, 0x0003b8),
259 REG(VCAP_CONST_IF_CNT, 0x0003bc),
262 static const u32 ocelot_ptp_regmap[] = {
263 REG(PTP_PIN_CFG, 0x000000),
264 REG(PTP_PIN_TOD_SEC_MSB, 0x000004),
265 REG(PTP_PIN_TOD_SEC_LSB, 0x000008),
266 REG(PTP_PIN_TOD_NSEC, 0x00000c),
267 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014),
268 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018),
269 REG(PTP_CFG_MISC, 0x0000a0),
270 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4),
271 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8),
274 static const u32 ocelot_dev_gmii_regmap[] = {
275 REG(DEV_CLOCK_CFG, 0x0),
276 REG(DEV_PORT_MISC, 0x4),
277 REG(DEV_EVENTS, 0x8),
278 REG(DEV_EEE_CFG, 0xc),
279 REG(DEV_RX_PATH_DELAY, 0x10),
280 REG(DEV_TX_PATH_DELAY, 0x14),
281 REG(DEV_PTP_PREDICT_CFG, 0x18),
282 REG(DEV_MAC_ENA_CFG, 0x1c),
283 REG(DEV_MAC_MODE_CFG, 0x20),
284 REG(DEV_MAC_MAXLEN_CFG, 0x24),
285 REG(DEV_MAC_TAGS_CFG, 0x28),
286 REG(DEV_MAC_ADV_CHK_CFG, 0x2c),
287 REG(DEV_MAC_IFG_CFG, 0x30),
288 REG(DEV_MAC_HDX_CFG, 0x34),
289 REG(DEV_MAC_DBG_CFG, 0x38),
290 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c),
291 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40),
292 REG(DEV_MAC_STICKY, 0x44),
293 REG(PCS1G_CFG, 0x48),
294 REG(PCS1G_MODE_CFG, 0x4c),
295 REG(PCS1G_SD_CFG, 0x50),
296 REG(PCS1G_ANEG_CFG, 0x54),
297 REG(PCS1G_ANEG_NP_CFG, 0x58),
298 REG(PCS1G_LB_CFG, 0x5c),
299 REG(PCS1G_DBG_CFG, 0x60),
300 REG(PCS1G_CDET_CFG, 0x64),
301 REG(PCS1G_ANEG_STATUS, 0x68),
302 REG(PCS1G_ANEG_NP_STATUS, 0x6c),
303 REG(PCS1G_LINK_STATUS, 0x70),
304 REG(PCS1G_LINK_DOWN_CNT, 0x74),
305 REG(PCS1G_STICKY, 0x78),
306 REG(PCS1G_DEBUG_STATUS, 0x7c),
307 REG(PCS1G_LPI_CFG, 0x80),
308 REG(PCS1G_LPI_WAKE_ERROR_CNT, 0x84),
309 REG(PCS1G_LPI_STATUS, 0x88),
310 REG(PCS1G_TSTPAT_MODE_CFG, 0x8c),
311 REG(PCS1G_TSTPAT_STATUS, 0x90),
312 REG(DEV_PCS_FX100_CFG, 0x94),
313 REG(DEV_PCS_FX100_STATUS, 0x98),
316 static const u32 *ocelot_regmap[TARGET_MAX] = {
317 [ANA] = ocelot_ana_regmap,
318 [QS] = ocelot_qs_regmap,
319 [QSYS] = ocelot_qsys_regmap,
320 [REW] = ocelot_rew_regmap,
321 [SYS] = ocelot_sys_regmap,
322 [S0] = ocelot_vcap_regmap,
323 [S1] = ocelot_vcap_regmap,
324 [S2] = ocelot_vcap_regmap,
325 [PTP] = ocelot_ptp_regmap,
326 [DEV_GMII] = ocelot_dev_gmii_regmap,
329 static const struct reg_field ocelot_regfields[REGFIELD_MAX] = {
330 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11),
331 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10),
332 [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27),
333 [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26),
334 [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25),
335 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24),
336 [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23),
337 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22),
338 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21),
339 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20),
340 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19),
341 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
342 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17),
343 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16),
344 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15),
345 [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14),
346 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13),
347 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12),
348 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
349 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
350 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9),
351 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8),
352 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7),
353 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
354 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
355 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4),
356 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3),
357 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2),
358 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1),
359 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0),
360 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18),
361 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11),
362 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9),
363 [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20),
364 [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19),
365 [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7),
366 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3),
367 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0),
368 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2),
369 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1),
370 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0),
371 /* Replicated per number of ports (12), register size 4 per port */
372 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4),
373 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4),
374 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4),
375 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4),
376 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4),
377 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4),
378 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4),
379 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4),
380 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4),
381 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4),
382 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4),
383 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4),
384 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4),
387 static const struct ocelot_stat_layout ocelot_stats_layout[] = {
388 { .name = "rx_octets", .offset = 0x00, },
389 { .name = "rx_unicast", .offset = 0x01, },
390 { .name = "rx_multicast", .offset = 0x02, },
391 { .name = "rx_broadcast", .offset = 0x03, },
392 { .name = "rx_shorts", .offset = 0x04, },
393 { .name = "rx_fragments", .offset = 0x05, },
394 { .name = "rx_jabbers", .offset = 0x06, },
395 { .name = "rx_crc_align_errs", .offset = 0x07, },
396 { .name = "rx_sym_errs", .offset = 0x08, },
397 { .name = "rx_frames_below_65_octets", .offset = 0x09, },
398 { .name = "rx_frames_65_to_127_octets", .offset = 0x0A, },
399 { .name = "rx_frames_128_to_255_octets", .offset = 0x0B, },
400 { .name = "rx_frames_256_to_511_octets", .offset = 0x0C, },
401 { .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, },
402 { .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, },
403 { .name = "rx_frames_over_1526_octets", .offset = 0x0F, },
404 { .name = "rx_pause", .offset = 0x10, },
405 { .name = "rx_control", .offset = 0x11, },
406 { .name = "rx_longs", .offset = 0x12, },
407 { .name = "rx_classified_drops", .offset = 0x13, },
408 { .name = "rx_red_prio_0", .offset = 0x14, },
409 { .name = "rx_red_prio_1", .offset = 0x15, },
410 { .name = "rx_red_prio_2", .offset = 0x16, },
411 { .name = "rx_red_prio_3", .offset = 0x17, },
412 { .name = "rx_red_prio_4", .offset = 0x18, },
413 { .name = "rx_red_prio_5", .offset = 0x19, },
414 { .name = "rx_red_prio_6", .offset = 0x1A, },
415 { .name = "rx_red_prio_7", .offset = 0x1B, },
416 { .name = "rx_yellow_prio_0", .offset = 0x1C, },
417 { .name = "rx_yellow_prio_1", .offset = 0x1D, },
418 { .name = "rx_yellow_prio_2", .offset = 0x1E, },
419 { .name = "rx_yellow_prio_3", .offset = 0x1F, },
420 { .name = "rx_yellow_prio_4", .offset = 0x20, },
421 { .name = "rx_yellow_prio_5", .offset = 0x21, },
422 { .name = "rx_yellow_prio_6", .offset = 0x22, },
423 { .name = "rx_yellow_prio_7", .offset = 0x23, },
424 { .name = "rx_green_prio_0", .offset = 0x24, },
425 { .name = "rx_green_prio_1", .offset = 0x25, },
426 { .name = "rx_green_prio_2", .offset = 0x26, },
427 { .name = "rx_green_prio_3", .offset = 0x27, },
428 { .name = "rx_green_prio_4", .offset = 0x28, },
429 { .name = "rx_green_prio_5", .offset = 0x29, },
430 { .name = "rx_green_prio_6", .offset = 0x2A, },
431 { .name = "rx_green_prio_7", .offset = 0x2B, },
432 { .name = "tx_octets", .offset = 0x40, },
433 { .name = "tx_unicast", .offset = 0x41, },
434 { .name = "tx_multicast", .offset = 0x42, },
435 { .name = "tx_broadcast", .offset = 0x43, },
436 { .name = "tx_collision", .offset = 0x44, },
437 { .name = "tx_drops", .offset = 0x45, },
438 { .name = "tx_pause", .offset = 0x46, },
439 { .name = "tx_frames_below_65_octets", .offset = 0x47, },
440 { .name = "tx_frames_65_to_127_octets", .offset = 0x48, },
441 { .name = "tx_frames_128_255_octets", .offset = 0x49, },
442 { .name = "tx_frames_256_511_octets", .offset = 0x4A, },
443 { .name = "tx_frames_512_1023_octets", .offset = 0x4B, },
444 { .name = "tx_frames_1024_1526_octets", .offset = 0x4C, },
445 { .name = "tx_frames_over_1526_octets", .offset = 0x4D, },
446 { .name = "tx_yellow_prio_0", .offset = 0x4E, },
447 { .name = "tx_yellow_prio_1", .offset = 0x4F, },
448 { .name = "tx_yellow_prio_2", .offset = 0x50, },
449 { .name = "tx_yellow_prio_3", .offset = 0x51, },
450 { .name = "tx_yellow_prio_4", .offset = 0x52, },
451 { .name = "tx_yellow_prio_5", .offset = 0x53, },
452 { .name = "tx_yellow_prio_6", .offset = 0x54, },
453 { .name = "tx_yellow_prio_7", .offset = 0x55, },
454 { .name = "tx_green_prio_0", .offset = 0x56, },
455 { .name = "tx_green_prio_1", .offset = 0x57, },
456 { .name = "tx_green_prio_2", .offset = 0x58, },
457 { .name = "tx_green_prio_3", .offset = 0x59, },
458 { .name = "tx_green_prio_4", .offset = 0x5A, },
459 { .name = "tx_green_prio_5", .offset = 0x5B, },
460 { .name = "tx_green_prio_6", .offset = 0x5C, },
461 { .name = "tx_green_prio_7", .offset = 0x5D, },
462 { .name = "tx_aged", .offset = 0x5E, },
463 { .name = "drop_local", .offset = 0x80, },
464 { .name = "drop_tail", .offset = 0x81, },
465 { .name = "drop_yellow_prio_0", .offset = 0x82, },
466 { .name = "drop_yellow_prio_1", .offset = 0x83, },
467 { .name = "drop_yellow_prio_2", .offset = 0x84, },
468 { .name = "drop_yellow_prio_3", .offset = 0x85, },
469 { .name = "drop_yellow_prio_4", .offset = 0x86, },
470 { .name = "drop_yellow_prio_5", .offset = 0x87, },
471 { .name = "drop_yellow_prio_6", .offset = 0x88, },
472 { .name = "drop_yellow_prio_7", .offset = 0x89, },
473 { .name = "drop_green_prio_0", .offset = 0x8A, },
474 { .name = "drop_green_prio_1", .offset = 0x8B, },
475 { .name = "drop_green_prio_2", .offset = 0x8C, },
476 { .name = "drop_green_prio_3", .offset = 0x8D, },
477 { .name = "drop_green_prio_4", .offset = 0x8E, },
478 { .name = "drop_green_prio_5", .offset = 0x8F, },
479 { .name = "drop_green_prio_6", .offset = 0x90, },
480 { .name = "drop_green_prio_7", .offset = 0x91, },
483 static void ocelot_pll5_init(struct ocelot *ocelot)
485 /* Configure PLL5. This will need a proper CCF driver
486 * The values are coming from the VTSS API for Ocelot
488 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
489 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
490 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
491 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
492 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
493 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
494 HSIO_PLL5G_CFG0_ENA_BIAS |
495 HSIO_PLL5G_CFG0_ENA_VCO_BUF |
496 HSIO_PLL5G_CFG0_ENA_CP1 |
497 HSIO_PLL5G_CFG0_SELCPI(2) |
498 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
499 HSIO_PLL5G_CFG0_SELBGV820(4) |
500 HSIO_PLL5G_CFG0_DIV4 |
501 HSIO_PLL5G_CFG0_ENA_CLKTREE |
502 HSIO_PLL5G_CFG0_ENA_LANE);
503 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
504 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
505 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
506 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
507 HSIO_PLL5G_CFG2_ENA_AMPCTRL |
508 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
509 HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
512 static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops)
516 ocelot->map = ocelot_regmap;
517 ocelot->stats_layout = ocelot_stats_layout;
518 ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout);
519 ocelot->num_mact_rows = 1024;
522 ret = ocelot_regfields_init(ocelot, ocelot_regfields);
526 ocelot_pll5_init(ocelot);
528 eth_random_addr(ocelot->base_mac);
529 ocelot->base_mac[5] &= 0xf0;
534 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
540 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
541 if (val == XTR_NOT_READY) {
546 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
547 } while (val == XTR_NOT_READY);
558 bytes_valid = XTR_VALID_BYTES(val);
559 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
560 if (val == XTR_ESCAPE)
561 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
567 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
577 static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg)
579 struct ocelot *ocelot = arg;
583 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) {
584 struct skb_shared_hwtstamps *shhwtstamps;
585 struct ocelot_port_private *priv;
586 struct ocelot_port *ocelot_port;
587 u64 tod_in_ns, full_ts_in_ns;
588 u64 src_port, len, timestamp;
589 struct net_device *dev;
590 u32 xfh[4], val, *buf;
591 struct timespec64 ts;
595 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
596 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
601 /* At this point the XFH was read correctly, so it is safe to
602 * presume that there is no error. The err needs to be reset
603 * otherwise a frame could come in CPU queue between the while
604 * condition and the check for error later on. And in that case
605 * the new frame is just removed and not processed.
609 ocelot_xfh_get_src_port(xfh, &src_port);
610 ocelot_xfh_get_len(xfh, &len);
611 ocelot_xfh_get_rew_val(xfh, ×tamp);
613 ocelot_port = ocelot->ports[src_port];
614 priv = container_of(ocelot_port, struct ocelot_port_private,
618 skb = netdev_alloc_skb(dev, len);
620 if (unlikely(!skb)) {
621 netdev_err(dev, "Unable to allocate sk_buff\n");
625 buf_len = len - ETH_FCS_LEN;
626 buf = (u32 *)skb_put(skb, buf_len);
630 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
637 } while (len < buf_len);
640 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
646 /* Update the statistics if part of the FCS was read before */
647 len -= ETH_FCS_LEN - sz;
649 if (unlikely(dev->features & NETIF_F_RXFCS)) {
650 buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
655 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
657 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
658 if ((tod_in_ns & 0xffffffff) < timestamp)
659 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
662 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
665 shhwtstamps = skb_hwtstamps(skb);
666 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
667 shhwtstamps->hwtstamp = full_ts_in_ns;
670 /* Everything we see on an interface that is in the HW bridge
671 * has already been forwarded.
673 if (ocelot->bridge_mask & BIT(src_port))
674 skb->offload_fwd_mark = 1;
676 skb->protocol = eth_type_trans(skb, dev);
677 if (!skb_defer_rx_timestamp(skb))
679 dev->stats.rx_bytes += len;
680 dev->stats.rx_packets++;
685 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
686 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
691 static irqreturn_t ocelot_ptp_rdy_irq_handler(int irq, void *arg)
693 struct ocelot *ocelot = arg;
695 ocelot_get_txtstamp(ocelot);
700 static const struct of_device_id mscc_ocelot_match[] = {
701 { .compatible = "mscc,vsc7514-switch" },
704 MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
706 static int ocelot_reset(struct ocelot *ocelot)
711 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
712 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
716 regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
718 } while (val && --retries);
723 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
724 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
730 * Bit 8: Unit; 0:1, 1:16
731 * Bit 7-0: Value to be multiplied with unit
733 static u16 ocelot_wm_enc(u16 value)
735 WARN_ON(value >= 16 * BIT(8));
738 return BIT(8) | (value / 16);
743 static u16 ocelot_wm_dec(u16 wm)
746 return (wm & GENMASK(7, 0)) * 16;
751 static void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
753 *inuse = (val & GENMASK(23, 12)) >> 12;
754 *maxuse = val & GENMASK(11, 0);
757 static const struct ocelot_ops ocelot_ops = {
758 .reset = ocelot_reset,
759 .wm_enc = ocelot_wm_enc,
760 .wm_dec = ocelot_wm_dec,
761 .wm_stat = ocelot_wm_stat,
762 .port_to_netdev = ocelot_port_to_netdev,
763 .netdev_to_port = ocelot_netdev_to_port,
766 static const struct vcap_field vsc7514_vcap_es0_keys[] = {
767 [VCAP_ES0_EGR_PORT] = { 0, 4},
768 [VCAP_ES0_IGR_PORT] = { 4, 4},
769 [VCAP_ES0_RSV] = { 8, 2},
770 [VCAP_ES0_L2_MC] = { 10, 1},
771 [VCAP_ES0_L2_BC] = { 11, 1},
772 [VCAP_ES0_VID] = { 12, 12},
773 [VCAP_ES0_DP] = { 24, 1},
774 [VCAP_ES0_PCP] = { 25, 3},
777 static const struct vcap_field vsc7514_vcap_es0_actions[] = {
778 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2},
779 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1},
780 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2},
781 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1},
782 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2},
783 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2},
784 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2},
785 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1},
786 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2},
787 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2},
788 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12},
789 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3},
790 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1},
791 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12},
792 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3},
793 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1},
794 [VCAP_ES0_ACT_RSV] = { 49, 24},
795 [VCAP_ES0_ACT_HIT_STICKY] = { 73, 1},
798 static const struct vcap_field vsc7514_vcap_is1_keys[] = {
799 [VCAP_IS1_HK_TYPE] = { 0, 1},
800 [VCAP_IS1_HK_LOOKUP] = { 1, 2},
801 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 12},
802 [VCAP_IS1_HK_RSV] = { 15, 9},
803 [VCAP_IS1_HK_OAM_Y1731] = { 24, 1},
804 [VCAP_IS1_HK_L2_MC] = { 25, 1},
805 [VCAP_IS1_HK_L2_BC] = { 26, 1},
806 [VCAP_IS1_HK_IP_MC] = { 27, 1},
807 [VCAP_IS1_HK_VLAN_TAGGED] = { 28, 1},
808 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 29, 1},
809 [VCAP_IS1_HK_TPID] = { 30, 1},
810 [VCAP_IS1_HK_VID] = { 31, 12},
811 [VCAP_IS1_HK_DEI] = { 43, 1},
812 [VCAP_IS1_HK_PCP] = { 44, 3},
813 /* Specific Fields for IS1 Half Key S1_NORMAL */
814 [VCAP_IS1_HK_L2_SMAC] = { 47, 48},
815 [VCAP_IS1_HK_ETYPE_LEN] = { 95, 1},
816 [VCAP_IS1_HK_ETYPE] = { 96, 16},
817 [VCAP_IS1_HK_IP_SNAP] = {112, 1},
818 [VCAP_IS1_HK_IP4] = {113, 1},
819 /* Layer-3 Information */
820 [VCAP_IS1_HK_L3_FRAGMENT] = {114, 1},
821 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {115, 1},
822 [VCAP_IS1_HK_L3_OPTIONS] = {116, 1},
823 [VCAP_IS1_HK_L3_DSCP] = {117, 6},
824 [VCAP_IS1_HK_L3_IP4_SIP] = {123, 32},
825 /* Layer-4 Information */
826 [VCAP_IS1_HK_TCP_UDP] = {155, 1},
827 [VCAP_IS1_HK_TCP] = {156, 1},
828 [VCAP_IS1_HK_L4_SPORT] = {157, 16},
829 [VCAP_IS1_HK_L4_RNG] = {173, 8},
830 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
831 [VCAP_IS1_HK_IP4_INNER_TPID] = { 47, 1},
832 [VCAP_IS1_HK_IP4_INNER_VID] = { 48, 12},
833 [VCAP_IS1_HK_IP4_INNER_DEI] = { 60, 1},
834 [VCAP_IS1_HK_IP4_INNER_PCP] = { 61, 3},
835 [VCAP_IS1_HK_IP4_IP4] = { 64, 1},
836 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 65, 1},
837 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 66, 1},
838 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 67, 1},
839 [VCAP_IS1_HK_IP4_L3_DSCP] = { 68, 6},
840 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 74, 32},
841 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {106, 32},
842 [VCAP_IS1_HK_IP4_L3_PROTO] = {138, 8},
843 [VCAP_IS1_HK_IP4_TCP_UDP] = {146, 1},
844 [VCAP_IS1_HK_IP4_TCP] = {147, 1},
845 [VCAP_IS1_HK_IP4_L4_RNG] = {148, 8},
846 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {156, 32},
849 static const struct vcap_field vsc7514_vcap_is1_actions[] = {
850 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1},
851 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6},
852 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1},
853 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3},
854 [VCAP_IS1_ACT_DP_ENA] = { 11, 1},
855 [VCAP_IS1_ACT_DP_VAL] = { 12, 1},
856 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8},
857 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8},
858 [VCAP_IS1_ACT_RSV] = { 29, 9},
859 /* The fields below are incorrectly shifted by 2 in the manual */
860 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1},
861 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12},
862 [VCAP_IS1_ACT_FID_SEL] = { 51, 2},
863 [VCAP_IS1_ACT_FID_VAL] = { 53, 13},
864 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1},
865 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3},
866 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1},
867 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1},
868 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2},
869 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4},
870 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1},
873 static const struct vcap_field vsc7514_vcap_is2_keys[] = {
874 /* Common: 46 bits */
875 [VCAP_IS2_TYPE] = { 0, 4},
876 [VCAP_IS2_HK_FIRST] = { 4, 1},
877 [VCAP_IS2_HK_PAG] = { 5, 8},
878 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 12},
879 [VCAP_IS2_HK_RSV2] = { 25, 1},
880 [VCAP_IS2_HK_HOST_MATCH] = { 26, 1},
881 [VCAP_IS2_HK_L2_MC] = { 27, 1},
882 [VCAP_IS2_HK_L2_BC] = { 28, 1},
883 [VCAP_IS2_HK_VLAN_TAGGED] = { 29, 1},
884 [VCAP_IS2_HK_VID] = { 30, 12},
885 [VCAP_IS2_HK_DEI] = { 42, 1},
886 [VCAP_IS2_HK_PCP] = { 43, 3},
887 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
888 [VCAP_IS2_HK_L2_DMAC] = { 46, 48},
889 [VCAP_IS2_HK_L2_SMAC] = { 94, 48},
890 /* MAC_ETYPE (TYPE=000) */
891 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {142, 16},
892 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {158, 16},
893 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {174, 8},
894 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {182, 3},
895 /* MAC_LLC (TYPE=001) */
896 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {142, 40},
897 /* MAC_SNAP (TYPE=010) */
898 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {142, 40},
899 /* MAC_ARP (TYPE=011) */
900 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 46, 48},
901 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 94, 1},
902 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 95, 1},
903 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 96, 1},
904 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 97, 1},
905 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 98, 1},
906 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 99, 1},
907 [VCAP_IS2_HK_MAC_ARP_OPCODE] = {100, 2},
908 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {102, 32},
909 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {134, 32},
910 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {166, 1},
911 /* IP4_TCP_UDP / IP4_OTHER common */
912 [VCAP_IS2_HK_IP4] = { 46, 1},
913 [VCAP_IS2_HK_L3_FRAGMENT] = { 47, 1},
914 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 48, 1},
915 [VCAP_IS2_HK_L3_OPTIONS] = { 49, 1},
916 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 50, 1},
917 [VCAP_IS2_HK_L3_TOS] = { 51, 8},
918 [VCAP_IS2_HK_L3_IP4_DIP] = { 59, 32},
919 [VCAP_IS2_HK_L3_IP4_SIP] = { 91, 32},
920 [VCAP_IS2_HK_DIP_EQ_SIP] = {123, 1},
921 /* IP4_TCP_UDP (TYPE=100) */
922 [VCAP_IS2_HK_TCP] = {124, 1},
923 [VCAP_IS2_HK_L4_DPORT] = {125, 16},
924 [VCAP_IS2_HK_L4_SPORT] = {141, 16},
925 [VCAP_IS2_HK_L4_RNG] = {157, 8},
926 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {165, 1},
927 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {166, 1},
928 [VCAP_IS2_HK_L4_FIN] = {167, 1},
929 [VCAP_IS2_HK_L4_SYN] = {168, 1},
930 [VCAP_IS2_HK_L4_RST] = {169, 1},
931 [VCAP_IS2_HK_L4_PSH] = {170, 1},
932 [VCAP_IS2_HK_L4_ACK] = {171, 1},
933 [VCAP_IS2_HK_L4_URG] = {172, 1},
934 [VCAP_IS2_HK_L4_1588_DOM] = {173, 8},
935 [VCAP_IS2_HK_L4_1588_VER] = {181, 4},
936 /* IP4_OTHER (TYPE=101) */
937 [VCAP_IS2_HK_IP4_L3_PROTO] = {124, 8},
938 [VCAP_IS2_HK_L3_PAYLOAD] = {132, 56},
939 /* IP6_STD (TYPE=110) */
940 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 46, 1},
941 [VCAP_IS2_HK_L3_IP6_SIP] = { 47, 128},
942 [VCAP_IS2_HK_IP6_L3_PROTO] = {175, 8},
944 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {142, 7},
945 [VCAP_IS2_HK_OAM_VER] = {149, 5},
946 [VCAP_IS2_HK_OAM_OPCODE] = {154, 8},
947 [VCAP_IS2_HK_OAM_FLAGS] = {162, 8},
948 [VCAP_IS2_HK_OAM_MEPID] = {170, 16},
949 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {186, 1},
950 [VCAP_IS2_HK_OAM_IS_Y1731] = {187, 1},
953 static const struct vcap_field vsc7514_vcap_is2_actions[] = {
954 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1},
955 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1},
956 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3},
957 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2},
958 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1},
959 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1},
960 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1},
961 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9},
962 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1},
963 [VCAP_IS2_ACT_PORT_MASK] = { 20, 11},
964 [VCAP_IS2_ACT_REW_OP] = { 31, 9},
965 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1},
966 [VCAP_IS2_ACT_RSV] = { 41, 2},
967 [VCAP_IS2_ACT_ACL_ID] = { 43, 6},
968 [VCAP_IS2_ACT_HIT_CNT] = { 49, 32},
971 static struct vcap_props vsc7514_vcap_props[] = {
973 .action_type_width = 0,
975 [ES0_ACTION_TYPE_NORMAL] = {
976 .width = 73, /* HIT_STICKY not included */
981 .keys = vsc7514_vcap_es0_keys,
982 .actions = vsc7514_vcap_es0_actions,
985 .action_type_width = 0,
987 [IS1_ACTION_TYPE_NORMAL] = {
988 .width = 78, /* HIT_STICKY not included */
993 .keys = vsc7514_vcap_is1_keys,
994 .actions = vsc7514_vcap_is1_actions,
997 .action_type_width = 1,
999 [IS2_ACTION_TYPE_NORMAL] = {
1003 [IS2_ACTION_TYPE_SMAC_SIP] = {
1009 .keys = vsc7514_vcap_is2_keys,
1010 .actions = vsc7514_vcap_is2_actions,
1014 static struct ptp_clock_info ocelot_ptp_clock_info = {
1015 .owner = THIS_MODULE,
1016 .name = "ocelot ptp",
1017 .max_adj = 0x7fffffff,
1020 .n_per_out = OCELOT_PTP_PINS_NUM,
1021 .n_pins = OCELOT_PTP_PINS_NUM,
1023 .gettime64 = ocelot_ptp_gettime64,
1024 .settime64 = ocelot_ptp_settime64,
1025 .adjtime = ocelot_ptp_adjtime,
1026 .adjfine = ocelot_ptp_adjfine,
1027 .verify = ocelot_ptp_verify,
1028 .enable = ocelot_ptp_enable,
1031 static void mscc_ocelot_teardown_devlink_ports(struct ocelot *ocelot)
1035 for (port = 0; port < ocelot->num_phys_ports; port++)
1036 ocelot_port_devlink_teardown(ocelot, port);
1039 static void mscc_ocelot_release_ports(struct ocelot *ocelot)
1043 for (port = 0; port < ocelot->num_phys_ports; port++) {
1044 struct ocelot_port *ocelot_port;
1046 ocelot_port = ocelot->ports[port];
1050 ocelot_deinit_port(ocelot, port);
1051 ocelot_release_port(ocelot_port);
1055 static int mscc_ocelot_init_ports(struct platform_device *pdev,
1056 struct device_node *ports)
1058 struct ocelot *ocelot = platform_get_drvdata(pdev);
1059 u32 devlink_ports_registered = 0;
1060 struct device_node *portnp;
1064 ocelot->ports = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
1065 sizeof(struct ocelot_port *), GFP_KERNEL);
1069 ocelot->devlink_ports = devm_kcalloc(ocelot->dev,
1070 ocelot->num_phys_ports,
1071 sizeof(*ocelot->devlink_ports),
1073 if (!ocelot->devlink_ports)
1076 for_each_available_child_of_node(ports, portnp) {
1077 struct ocelot_port_private *priv;
1078 struct ocelot_port *ocelot_port;
1079 struct device_node *phy_node;
1080 struct devlink_port *dlp;
1081 phy_interface_t phy_mode;
1082 struct phy_device *phy;
1083 struct regmap *target;
1084 struct resource *res;
1088 if (of_property_read_u32(portnp, "reg", ®))
1092 if (port < 0 || port >= ocelot->num_phys_ports) {
1093 dev_err(ocelot->dev,
1094 "invalid port number: %d >= %d\n", port,
1095 ocelot->num_phys_ports);
1099 snprintf(res_name, sizeof(res_name), "port%d", port);
1101 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1103 target = ocelot_regmap_init(ocelot, res);
1104 if (IS_ERR(target)) {
1105 err = PTR_ERR(target);
1109 phy_node = of_parse_phandle(portnp, "phy-handle", 0);
1113 phy = of_phy_find_device(phy_node);
1114 of_node_put(phy_node);
1118 err = ocelot_port_devlink_init(ocelot, port,
1119 DEVLINK_PORT_FLAVOUR_PHYSICAL);
1121 of_node_put(portnp);
1124 devlink_ports_registered |= BIT(port);
1126 err = ocelot_probe_port(ocelot, port, target, phy);
1128 of_node_put(portnp);
1132 ocelot_port = ocelot->ports[port];
1133 priv = container_of(ocelot_port, struct ocelot_port_private,
1135 dlp = &ocelot->devlink_ports[port];
1136 devlink_port_type_eth_set(dlp, priv->dev);
1138 of_get_phy_mode(portnp, &phy_mode);
1140 ocelot_port->phy_mode = phy_mode;
1142 switch (ocelot_port->phy_mode) {
1143 case PHY_INTERFACE_MODE_NA:
1145 case PHY_INTERFACE_MODE_SGMII:
1147 case PHY_INTERFACE_MODE_QSGMII:
1148 /* Ensure clock signals and speed is set on all
1151 ocelot_port_writel(ocelot_port,
1152 DEV_CLOCK_CFG_LINK_SPEED
1153 (OCELOT_SPEED_1000),
1157 dev_err(ocelot->dev,
1158 "invalid phy mode for port%d, (Q)SGMII only\n",
1160 of_node_put(portnp);
1165 serdes = devm_of_phy_get(ocelot->dev, portnp, NULL);
1166 if (IS_ERR(serdes)) {
1167 err = PTR_ERR(serdes);
1168 if (err == -EPROBE_DEFER)
1169 dev_dbg(ocelot->dev, "deferring probe\n");
1171 dev_err(ocelot->dev,
1172 "missing SerDes phys for port%d\n",
1175 of_node_put(portnp);
1179 priv->serdes = serdes;
1182 /* Initialize unused devlink ports at the end */
1183 for (port = 0; port < ocelot->num_phys_ports; port++) {
1184 if (devlink_ports_registered & BIT(port))
1187 err = ocelot_port_devlink_init(ocelot, port,
1188 DEVLINK_PORT_FLAVOUR_UNUSED);
1192 devlink_ports_registered |= BIT(port);
1198 /* Unregister the network interfaces */
1199 mscc_ocelot_release_ports(ocelot);
1200 /* Tear down devlink ports for the registered network interfaces */
1201 for (port = 0; port < ocelot->num_phys_ports; port++) {
1202 if (devlink_ports_registered & BIT(port))
1203 ocelot_port_devlink_teardown(ocelot, port);
1208 static int mscc_ocelot_probe(struct platform_device *pdev)
1210 struct device_node *np = pdev->dev.of_node;
1211 int err, irq_xtr, irq_ptp_rdy;
1212 struct device_node *ports;
1213 struct devlink *devlink;
1214 struct ocelot *ocelot;
1215 struct regmap *hsio;
1219 enum ocelot_target id;
1234 if (!np && !pdev->dev.platform_data)
1237 devlink = devlink_alloc(&ocelot_devlink_ops, sizeof(*ocelot));
1241 ocelot = devlink_priv(devlink);
1242 ocelot->devlink = priv_to_devlink(ocelot);
1243 platform_set_drvdata(pdev, ocelot);
1244 ocelot->dev = &pdev->dev;
1246 for (i = 0; i < ARRAY_SIZE(io_target); i++) {
1247 struct regmap *target;
1248 struct resource *res;
1250 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1253 target = ocelot_regmap_init(ocelot, res);
1254 if (IS_ERR(target)) {
1255 if (io_target[i].optional) {
1256 ocelot->targets[io_target[i].id] = NULL;
1259 err = PTR_ERR(target);
1260 goto out_free_devlink;
1263 ocelot->targets[io_target[i].id] = target;
1266 hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio");
1268 dev_err(&pdev->dev, "missing hsio syscon\n");
1269 err = PTR_ERR(hsio);
1270 goto out_free_devlink;
1273 ocelot->targets[HSIO] = hsio;
1275 err = ocelot_chip_init(ocelot, &ocelot_ops);
1277 goto out_free_devlink;
1279 irq_xtr = platform_get_irq_byname(pdev, "xtr");
1282 goto out_free_devlink;
1285 err = devm_request_threaded_irq(&pdev->dev, irq_xtr, NULL,
1286 ocelot_xtr_irq_handler, IRQF_ONESHOT,
1287 "frame extraction", ocelot);
1289 goto out_free_devlink;
1291 irq_ptp_rdy = platform_get_irq_byname(pdev, "ptp_rdy");
1292 if (irq_ptp_rdy > 0 && ocelot->targets[PTP]) {
1293 err = devm_request_threaded_irq(&pdev->dev, irq_ptp_rdy, NULL,
1294 ocelot_ptp_rdy_irq_handler,
1295 IRQF_ONESHOT, "ptp ready",
1298 goto out_free_devlink;
1300 /* Both the PTP interrupt and the PTP bank are available */
1304 ports = of_get_child_by_name(np, "ethernet-ports");
1306 dev_err(ocelot->dev, "no ethernet-ports child node found\n");
1308 goto out_free_devlink;
1311 ocelot->num_phys_ports = of_get_child_count(ports);
1312 ocelot->num_flooding_pgids = 1;
1314 ocelot->vcap = vsc7514_vcap_props;
1317 err = ocelot_init(ocelot);
1321 err = devlink_register(devlink, ocelot->dev);
1323 goto out_ocelot_deinit;
1325 err = mscc_ocelot_init_ports(pdev, ports);
1327 goto out_ocelot_devlink_unregister;
1329 err = ocelot_devlink_sb_register(ocelot);
1331 goto out_ocelot_release_ports;
1334 err = ocelot_init_timestamp(ocelot, &ocelot_ptp_clock_info);
1336 dev_err(ocelot->dev,
1337 "Timestamp initialization failed\n");
1342 register_netdevice_notifier(&ocelot_netdevice_nb);
1343 register_switchdev_notifier(&ocelot_switchdev_nb);
1344 register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb);
1348 dev_info(&pdev->dev, "Ocelot switch probed\n");
1352 out_ocelot_release_ports:
1353 mscc_ocelot_release_ports(ocelot);
1354 mscc_ocelot_teardown_devlink_ports(ocelot);
1355 out_ocelot_devlink_unregister:
1356 devlink_unregister(devlink);
1358 ocelot_deinit(ocelot);
1362 devlink_free(devlink);
1366 static int mscc_ocelot_remove(struct platform_device *pdev)
1368 struct ocelot *ocelot = platform_get_drvdata(pdev);
1370 ocelot_deinit_timestamp(ocelot);
1371 ocelot_devlink_sb_unregister(ocelot);
1372 mscc_ocelot_release_ports(ocelot);
1373 mscc_ocelot_teardown_devlink_ports(ocelot);
1374 devlink_unregister(ocelot->devlink);
1375 ocelot_deinit(ocelot);
1376 unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb);
1377 unregister_switchdev_notifier(&ocelot_switchdev_nb);
1378 unregister_netdevice_notifier(&ocelot_netdevice_nb);
1379 devlink_free(ocelot->devlink);
1384 static struct platform_driver mscc_ocelot_driver = {
1385 .probe = mscc_ocelot_probe,
1386 .remove = mscc_ocelot_remove,
1388 .name = "ocelot-switch",
1389 .of_match_table = mscc_ocelot_match,
1393 module_platform_driver(mscc_ocelot_driver);
1395 MODULE_DESCRIPTION("Microsemi Ocelot switch driver");
1396 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
1397 MODULE_LICENSE("Dual MIT/GPL");