drivers/net/ethernet/mscc/ocelot_vcap.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Microsemi Ocelot Switch driver
   3  * Copyright (c) 2019 Microsemi Corporation
   4  */
   5
   6 #include <linux/iopoll.h>
   7 #include <linux/proc_fs.h>
   8
   9 #include <soc/mscc/ocelot_vcap.h>
  10 #include "ocelot_police.h"
  11 #include "ocelot_vcap.h"
  12
  13 #define ENTRY_WIDTH 32
  14
  15 enum vcap_sel {
  16         VCAP_SEL_ENTRY = 0x1,
  17         VCAP_SEL_ACTION = 0x2,
  18         VCAP_SEL_COUNTER = 0x4,
  19         VCAP_SEL_ALL = 0x7,
  20 };
  21
  22 enum vcap_cmd {
  23         VCAP_CMD_WRITE = 0, /* Copy from Cache to TCAM */
  24         VCAP_CMD_READ = 1, /* Copy from TCAM to Cache */
  25         VCAP_CMD_MOVE_UP = 2, /* Move <count> up */
  26         VCAP_CMD_MOVE_DOWN = 3, /* Move <count> down */
  27         VCAP_CMD_INITIALIZE = 4, /* Write all (from cache) */
  28 };
  29
  30 #define VCAP_ENTRY_WIDTH 12 /* Max entry width (32bit words) */
  31 #define VCAP_COUNTER_WIDTH 4 /* Max counter width (32bit words) */
  32
  33 struct vcap_data {
  34         u32 entry[VCAP_ENTRY_WIDTH]; /* ENTRY_DAT */
  35         u32 mask[VCAP_ENTRY_WIDTH]; /* MASK_DAT */
  36         u32 action[VCAP_ENTRY_WIDTH]; /* ACTION_DAT */
  37         u32 counter[VCAP_COUNTER_WIDTH]; /* CNT_DAT */
  38         u32 tg; /* TG_DAT */
  39         u32 type; /* Action type */
  40         u32 tg_sw; /* Current type-group */
  41         u32 cnt; /* Current counter */
  42         u32 key_offset; /* Current entry offset */
  43         u32 action_offset; /* Current action offset */
  44         u32 counter_offset; /* Current counter offset */
  45         u32 tg_value; /* Current type-group value */
  46         u32 tg_mask; /* Current type-group mask */
  47 };
  48
  49 static u32 vcap_read_update_ctrl(struct ocelot *ocelot,
  50                                  const struct vcap_props *vcap)
  51 {
  52         return ocelot_target_read(ocelot, vcap->target, VCAP_CORE_UPDATE_CTRL);
  53 }
  54
  55 static void vcap_cmd(struct ocelot *ocelot, const struct vcap_props *vcap,
  56                      u16 ix, int cmd, int sel)
  57 {
  58         u32 value = (VCAP_CORE_UPDATE_CTRL_UPDATE_CMD(cmd) |
  59                      VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(ix) |
  60                      VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT);
  61
  62         if ((sel & VCAP_SEL_ENTRY) && ix >= vcap->entry_count)
  63                 return;
  64
  65         if (!(sel & VCAP_SEL_ENTRY))
  66                 value |= VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS;
  67
  68         if (!(sel & VCAP_SEL_ACTION))
  69                 value |= VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS;
  70
  71         if (!(sel & VCAP_SEL_COUNTER))
  72                 value |= VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS;
  73
  74         ocelot_target_write(ocelot, vcap->target, value, VCAP_CORE_UPDATE_CTRL);
  75
  76         read_poll_timeout(vcap_read_update_ctrl, value,
  77                           (value & VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT) == 0,
  78                           10, 100000, false, ocelot, vcap);
  79 }
  80
  81 /* Convert from 0-based row to VCAP entry row and run command */
  82 static void vcap_row_cmd(struct ocelot *ocelot, const struct vcap_props *vcap,
  83                          u32 row, int cmd, int sel)
  84 {
  85         vcap_cmd(ocelot, vcap, vcap->entry_count - row - 1, cmd, sel);
  86 }
  87
  88 static void vcap_entry2cache(struct ocelot *ocelot,
  89                              const struct vcap_props *vcap,
  90                              struct vcap_data *data)
  91 {
  92         u32 entry_words, i;
  93
  94         entry_words = DIV_ROUND_UP(vcap->entry_width, ENTRY_WIDTH);
  95
  96         for (i = 0; i < entry_words; i++) {
  97                 ocelot_target_write_rix(ocelot, vcap->target, data->entry[i],
  98                                         VCAP_CACHE_ENTRY_DAT, i);
  99                 ocelot_target_write_rix(ocelot, vcap->target, ~data->mask[i],
 100                                         VCAP_CACHE_MASK_DAT, i);
 101         }
 102         ocelot_target_write(ocelot, vcap->target, data->tg, VCAP_CACHE_TG_DAT);
 103 }
 104
 105 static void vcap_cache2entry(struct ocelot *ocelot,
 106                              const struct vcap_props *vcap,
 107                              struct vcap_data *data)
 108 {
 109         u32 entry_words, i;
 110
 111         entry_words = DIV_ROUND_UP(vcap->entry_width, ENTRY_WIDTH);
 112
 113         for (i = 0; i < entry_words; i++) {
 114                 data->entry[i] = ocelot_target_read_rix(ocelot, vcap->target,
 115                                                         VCAP_CACHE_ENTRY_DAT, i);
 116                 // Invert mask
 117                 data->mask[i] = ~ocelot_target_read_rix(ocelot, vcap->target,
 118                                                         VCAP_CACHE_MASK_DAT, i);
 119         }
 120         data->tg = ocelot_target_read(ocelot, vcap->target, VCAP_CACHE_TG_DAT);
 121 }
 122
 123 static void vcap_action2cache(struct ocelot *ocelot,
 124                               const struct vcap_props *vcap,
 125                               struct vcap_data *data)
 126 {
 127         u32 action_words, mask;
 128         int i, width;
 129
 130         /* Encode action type */
 131         width = vcap->action_type_width;
 132         if (width) {
 133                 mask = GENMASK(width, 0);
 134                 data->action[0] = ((data->action[0] & ~mask) | data->type);
 135         }
 136
 137         action_words = DIV_ROUND_UP(vcap->action_width, ENTRY_WIDTH);
 138
 139         for (i = 0; i < action_words; i++)
 140                 ocelot_target_write_rix(ocelot, vcap->target, data->action[i],
 141                                         VCAP_CACHE_ACTION_DAT, i);
 142
 143         for (i = 0; i < vcap->counter_words; i++)
 144                 ocelot_target_write_rix(ocelot, vcap->target, data->counter[i],
 145                                         VCAP_CACHE_CNT_DAT, i);
 146 }
 147
 148 static void vcap_cache2action(struct ocelot *ocelot,
 149                               const struct vcap_props *vcap,
 150                               struct vcap_data *data)
 151 {
 152         u32 action_words;
 153         int i, width;
 154
 155         action_words = DIV_ROUND_UP(vcap->action_width, ENTRY_WIDTH);
 156
 157         for (i = 0; i < action_words; i++)
 158                 data->action[i] = ocelot_target_read_rix(ocelot, vcap->target,
 159                                                          VCAP_CACHE_ACTION_DAT,
 160                                                          i);
 161
 162         for (i = 0; i < vcap->counter_words; i++)
 163                 data->counter[i] = ocelot_target_read_rix(ocelot, vcap->target,
 164                                                           VCAP_CACHE_CNT_DAT,
 165                                                           i);
 166
 167         /* Extract action type */
 168         width = vcap->action_type_width;
 169         data->type = (width ? (data->action[0] & GENMASK(width, 0)) : 0);
 170 }
 171
 172 /* Calculate offsets for entry */
 173 static void vcap_data_offset_get(const struct vcap_props *vcap,
 174                                  struct vcap_data *data, int ix)
 175 {
 176         int num_subwords_per_entry, num_subwords_per_action;
 177         int i, col, offset, num_entries_per_row, base;
 178         u32 width = vcap->tg_width;
 179
 180         switch (data->tg_sw) {
 181         case VCAP_TG_FULL:
 182                 num_entries_per_row = 1;
 183                 break;
 184         case VCAP_TG_HALF:
 185                 num_entries_per_row = 2;
 186                 break;
 187         case VCAP_TG_QUARTER:
 188                 num_entries_per_row = 4;
 189                 break;
 190         default:
 191                 return;
 192         }
 193
 194         col = (ix % num_entries_per_row);
 195         num_subwords_per_entry = (vcap->sw_count / num_entries_per_row);
 196         base = (vcap->sw_count - col * num_subwords_per_entry -
 197                 num_subwords_per_entry);
 198         data->tg_value = 0;
 199         data->tg_mask = 0;
 200         for (i = 0; i < num_subwords_per_entry; i++) {
 201                 offset = ((base + i) * width);
 202                 data->tg_value |= (data->tg_sw << offset);
 203                 data->tg_mask |= GENMASK(offset + width - 1, offset);
 204         }
 205
 206         /* Calculate key/action/counter offsets */
 207         col = (num_entries_per_row - col - 1);
 208         data->key_offset = (base * vcap->entry_width) / vcap->sw_count;
 209         data->counter_offset = (num_subwords_per_entry * col *
 210                                 vcap->counter_width);
 211         i = data->type;
 212         width = vcap->action_table[i].width;
 213         num_subwords_per_action = vcap->action_table[i].count;
 214         data->action_offset = ((num_subwords_per_action * col * width) /
 215                                 num_entries_per_row);
 216         data->action_offset += vcap->action_type_width;
 217 }
 218
 219 static void vcap_data_set(u32 *data, u32 offset, u32 len, u32 value)
 220 {
 221         u32 i, v, m;
 222
 223         for (i = 0; i < len; i++, offset++) {
 224                 v = data[offset / ENTRY_WIDTH];
 225                 m = (1 << (offset % ENTRY_WIDTH));
 226                 if (value & (1 << i))
 227                         v |= m;
 228                 else
 229                         v &= ~m;
 230                 data[offset / ENTRY_WIDTH] = v;
 231         }
 232 }
 233
 234 static u32 vcap_data_get(u32 *data, u32 offset, u32 len)
 235 {
 236         u32 i, v, m, value = 0;
 237
 238         for (i = 0; i < len; i++, offset++) {
 239                 v = data[offset / ENTRY_WIDTH];
 240                 m = (1 << (offset % ENTRY_WIDTH));
 241                 if (v & m)
 242                         value |= (1 << i);
 243         }
 244         return value;
 245 }
 246
 247 static void vcap_key_field_set(struct vcap_data *data, u32 offset, u32 width,
 248                                u32 value, u32 mask)
 249 {
 250         vcap_data_set(data->entry, offset + data->key_offset, width, value);
 251         vcap_data_set(data->mask, offset + data->key_offset, width, mask);
 252 }
 253
 254 static void vcap_key_set(const struct vcap_props *vcap, struct vcap_data *data,
 255                          int field, u32 value, u32 mask)
 256 {
 257         u32 offset = vcap->keys[field].offset;
 258         u32 length = vcap->keys[field].length;
 259
 260         vcap_key_field_set(data, offset, length, value, mask);
 261 }
 262
 263 static void vcap_key_bytes_set(const struct vcap_props *vcap,
 264                                struct vcap_data *data, int field,
 265                                u8 *val, u8 *msk)
 266 {
 267         u32 offset = vcap->keys[field].offset;
 268         u32 count  = vcap->keys[field].length;
 269         u32 i, j, n = 0, value = 0, mask = 0;
 270
 271         WARN_ON(count % 8);
 272
 273         /* Data wider than 32 bits are split up in chunks of maximum 32 bits.
 274          * The 32 LSB of the data are written to the 32 MSB of the TCAM.
 275          */
 276         offset += count;
 277         count /= 8;
 278
 279         for (i = 0; i < count; i++) {
 280                 j = (count - i - 1);
 281                 value += (val[j] << n);
 282                 mask += (msk[j] << n);
 283                 n += 8;
 284                 if (n == ENTRY_WIDTH || (i + 1) == count) {
 285                         offset -= n;
 286                         vcap_key_field_set(data, offset, n, value, mask);
 287                         n = 0;
 288                         value = 0;
 289                         mask = 0;
 290                 }
 291         }
 292 }
 293
 294 static void vcap_key_l4_port_set(const struct vcap_props *vcap,
 295                                  struct vcap_data *data, int field,
 296                                  struct ocelot_vcap_udp_tcp *port)
 297 {
 298         u32 offset = vcap->keys[field].offset;
 299         u32 length = vcap->keys[field].length;
 300
 301         WARN_ON(length != 16);
 302
 303         vcap_key_field_set(data, offset, length, port->value, port->mask);
 304 }
 305
 306 static void vcap_key_bit_set(const struct vcap_props *vcap,
 307                              struct vcap_data *data, int field,
 308                              enum ocelot_vcap_bit val)
 309 {
 310         u32 value = (val == OCELOT_VCAP_BIT_1 ? 1 : 0);
 311         u32 msk = (val == OCELOT_VCAP_BIT_ANY ? 0 : 1);
 312         u32 offset = vcap->keys[field].offset;
 313         u32 length = vcap->keys[field].length;
 314
 315         WARN_ON(length != 1);
 316
 317         vcap_key_field_set(data, offset, length, value, msk);
 318 }
 319
 320 static void vcap_action_set(const struct vcap_props *vcap,
 321                             struct vcap_data *data, int field, u32 value)
 322 {
 323         int offset = vcap->actions[field].offset;
 324         int length = vcap->actions[field].length;
 325
 326         vcap_data_set(data->action, offset + data->action_offset, length,
 327                       value);
 328 }
 329
 330 static void is2_action_set(struct ocelot *ocelot, struct vcap_data *data,
 331                            struct ocelot_vcap_filter *filter)
 332 {
 333         const struct vcap_props *vcap = &ocelot->vcap[VCAP_IS2];
 334         struct ocelot_vcap_action *a = &filter->action;
 335
 336         vcap_action_set(vcap, data, VCAP_IS2_ACT_MASK_MODE, a->mask_mode);
 337         vcap_action_set(vcap, data, VCAP_IS2_ACT_PORT_MASK, a->port_mask);
 338         vcap_action_set(vcap, data, VCAP_IS2_ACT_POLICE_ENA, a->police_ena);
 339         vcap_action_set(vcap, data, VCAP_IS2_ACT_POLICE_IDX, a->pol_ix);
 340         vcap_action_set(vcap, data, VCAP_IS2_ACT_CPU_QU_NUM, a->cpu_qu_num);
 341         vcap_action_set(vcap, data, VCAP_IS2_ACT_CPU_COPY_ENA, a->cpu_copy_ena);
 342 }
 343
 344 static void is2_entry_set(struct ocelot *ocelot, int ix,
 345                           struct ocelot_vcap_filter *filter)
 346 {
 347         const struct vcap_props *vcap = &ocelot->vcap[VCAP_IS2];
 348         struct ocelot_vcap_key_vlan *tag = &filter->vlan;
 349         u32 val, msk, type, type_mask = 0xf, i, count;
 350         struct ocelot_vcap_u64 payload;
 351         struct vcap_data data;
 352         int row = (ix / 2);
 353
 354         memset(&payload, 0, sizeof(payload));
 355         memset(&data, 0, sizeof(data));
 356
 357         /* Read row */
 358         vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_READ, VCAP_SEL_ALL);
 359         vcap_cache2entry(ocelot, vcap, &data);
 360         vcap_cache2action(ocelot, vcap, &data);
 361
 362         data.tg_sw = VCAP_TG_HALF;
 363         vcap_data_offset_get(vcap, &data, ix);
 364         data.tg = (data.tg & ~data.tg_mask);
 365         if (filter->prio != 0)
 366                 data.tg |= data.tg_value;
 367
 368         data.type = IS2_ACTION_TYPE_NORMAL;
 369
 370         vcap_key_set(vcap, &data, VCAP_IS2_HK_PAG, 0, 0);
 371         vcap_key_set(vcap, &data, VCAP_IS2_HK_IGR_PORT_MASK, 0,
 372                      ~filter->ingress_port_mask);
 373         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_FIRST, OCELOT_VCAP_BIT_ANY);
 374         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_HOST_MATCH,
 375                          OCELOT_VCAP_BIT_ANY);
 376         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L2_MC, filter->dmac_mc);
 377         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L2_BC, filter->dmac_bc);
 378         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_VLAN_TAGGED, tag->tagged);
 379         vcap_key_set(vcap, &data, VCAP_IS2_HK_VID,
 380                      tag->vid.value, tag->vid.mask);
 381         vcap_key_set(vcap, &data, VCAP_IS2_HK_PCP,
 382                      tag->pcp.value[0], tag->pcp.mask[0]);
 383         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_DEI, tag->dei);
 384
 385         switch (filter->key_type) {
 386         case OCELOT_VCAP_KEY_ETYPE: {
 387                 struct ocelot_vcap_key_etype *etype = &filter->key.etype;
 388
 389                 type = IS2_TYPE_ETYPE;
 390                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_DMAC,
 391                                    etype->dmac.value, etype->dmac.mask);
 392                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_SMAC,
 393                                    etype->smac.value, etype->smac.mask);
 394                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_MAC_ETYPE_ETYPE,
 395                                    etype->etype.value, etype->etype.mask);
 396                 /* Clear unused bits */
 397                 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0,
 398                              0, 0);
 399                 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1,
 400                              0, 0);
 401                 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2,
 402                              0, 0);
 403                 vcap_key_bytes_set(vcap, &data,
 404                                    VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0,
 405                                    etype->data.value, etype->data.mask);
 406                 break;
 407         }
 408         case OCELOT_VCAP_KEY_LLC: {
 409                 struct ocelot_vcap_key_llc *llc = &filter->key.llc;
 410
 411                 type = IS2_TYPE_LLC;
 412                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_DMAC,
 413                                    llc->dmac.value, llc->dmac.mask);
 414                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_SMAC,
 415                                    llc->smac.value, llc->smac.mask);
 416                 for (i = 0; i < 4; i++) {
 417                         payload.value[i] = llc->llc.value[i];
 418                         payload.mask[i] = llc->llc.mask[i];
 419                 }
 420                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_MAC_LLC_L2_LLC,
 421                                    payload.value, payload.mask);
 422                 break;
 423         }
 424         case OCELOT_VCAP_KEY_SNAP: {
 425                 struct ocelot_vcap_key_snap *snap = &filter->key.snap;
 426
 427                 type = IS2_TYPE_SNAP;
 428                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_DMAC,
 429                                    snap->dmac.value, snap->dmac.mask);
 430                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_SMAC,
 431                                    snap->smac.value, snap->smac.mask);
 432                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_MAC_SNAP_L2_SNAP,
 433                                    filter->key.snap.snap.value,
 434                                    filter->key.snap.snap.mask);
 435                 break;
 436         }
 437         case OCELOT_VCAP_KEY_ARP: {
 438                 struct ocelot_vcap_key_arp *arp = &filter->key.arp;
 439
 440                 type = IS2_TYPE_ARP;
 441                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_MAC_ARP_SMAC,
 442                                    arp->smac.value, arp->smac.mask);
 443                 vcap_key_bit_set(vcap, &data,
 444                                  VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK,
 445                                  arp->ethernet);
 446                 vcap_key_bit_set(vcap, &data,
 447                                  VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK,
 448                                  arp->ip);
 449                 vcap_key_bit_set(vcap, &data,
 450                                  VCAP_IS2_HK_MAC_ARP_LEN_OK,
 451                                  arp->length);
 452                 vcap_key_bit_set(vcap, &data,
 453                                  VCAP_IS2_HK_MAC_ARP_TARGET_MATCH,
 454                                  arp->dmac_match);
 455                 vcap_key_bit_set(vcap, &data,
 456                                  VCAP_IS2_HK_MAC_ARP_SENDER_MATCH,
 457                                  arp->smac_match);
 458                 vcap_key_bit_set(vcap, &data,
 459                                  VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN,
 460                                  arp->unknown);
 461
 462                 /* OPCODE is inverse, bit 0 is reply flag, bit 1 is RARP flag */
 463                 val = ((arp->req == OCELOT_VCAP_BIT_0 ? 1 : 0) |
 464                        (arp->arp == OCELOT_VCAP_BIT_0 ? 2 : 0));
 465                 msk = ((arp->req == OCELOT_VCAP_BIT_ANY ? 0 : 1) |
 466                        (arp->arp == OCELOT_VCAP_BIT_ANY ? 0 : 2));
 467                 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ARP_OPCODE,
 468                              val, msk);
 469                 vcap_key_bytes_set(vcap, &data,
 470                                    VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP,
 471                                    arp->dip.value.addr, arp->dip.mask.addr);
 472                 vcap_key_bytes_set(vcap, &data,
 473                                    VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP,
 474                                    arp->sip.value.addr, arp->sip.mask.addr);
 475                 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP,
 476                              0, 0);
 477                 break;
 478         }
 479         case OCELOT_VCAP_KEY_IPV4:
 480         case OCELOT_VCAP_KEY_IPV6: {
 481                 enum ocelot_vcap_bit sip_eq_dip, sport_eq_dport, seq_zero, tcp;
 482                 enum ocelot_vcap_bit ttl, fragment, options, tcp_ack, tcp_urg;
 483                 enum ocelot_vcap_bit tcp_fin, tcp_syn, tcp_rst, tcp_psh;
 484                 struct ocelot_vcap_key_ipv4 *ipv4 = NULL;
 485                 struct ocelot_vcap_key_ipv6 *ipv6 = NULL;
 486                 struct ocelot_vcap_udp_tcp *sport, *dport;
 487                 struct ocelot_vcap_ipv4 sip, dip;
 488                 struct ocelot_vcap_u8 proto, ds;
 489                 struct ocelot_vcap_u48 *ip_data;
 490
 491                 if (filter->key_type == OCELOT_VCAP_KEY_IPV4) {
 492                         ipv4 = &filter->key.ipv4;
 493                         ttl = ipv4->ttl;
 494                         fragment = ipv4->fragment;
 495                         options = ipv4->options;
 496                         proto = ipv4->proto;
 497                         ds = ipv4->ds;
 498                         ip_data = &ipv4->data;
 499                         sip = ipv4->sip;
 500                         dip = ipv4->dip;
 501                         sport = &ipv4->sport;
 502                         dport = &ipv4->dport;
 503                         tcp_fin = ipv4->tcp_fin;
 504                         tcp_syn = ipv4->tcp_syn;
 505                         tcp_rst = ipv4->tcp_rst;
 506                         tcp_psh = ipv4->tcp_psh;
 507                         tcp_ack = ipv4->tcp_ack;
 508                         tcp_urg = ipv4->tcp_urg;
 509                         sip_eq_dip = ipv4->sip_eq_dip;
 510                         sport_eq_dport = ipv4->sport_eq_dport;
 511                         seq_zero = ipv4->seq_zero;
 512                 } else {
 513                         ipv6 = &filter->key.ipv6;
 514                         ttl = ipv6->ttl;
 515                         fragment = OCELOT_VCAP_BIT_ANY;
 516                         options = OCELOT_VCAP_BIT_ANY;
 517                         proto = ipv6->proto;
 518                         ds = ipv6->ds;
 519                         ip_data = &ipv6->data;
 520                         for (i = 0; i < 8; i++) {
 521                                 val = ipv6->sip.value[i + 8];
 522                                 msk = ipv6->sip.mask[i + 8];
 523                                 if (i < 4) {
 524                                         dip.value.addr[i] = val;
 525                                         dip.mask.addr[i] = msk;
 526                                 } else {
 527                                         sip.value.addr[i - 4] = val;
 528                                         sip.mask.addr[i - 4] = msk;
 529                                 }
 530                         }
 531                         sport = &ipv6->sport;
 532                         dport = &ipv6->dport;
 533                         tcp_fin = ipv6->tcp_fin;
 534                         tcp_syn = ipv6->tcp_syn;
 535                         tcp_rst = ipv6->tcp_rst;
 536                         tcp_psh = ipv6->tcp_psh;
 537                         tcp_ack = ipv6->tcp_ack;
 538                         tcp_urg = ipv6->tcp_urg;
 539                         sip_eq_dip = ipv6->sip_eq_dip;
 540                         sport_eq_dport = ipv6->sport_eq_dport;
 541                         seq_zero = ipv6->seq_zero;
 542                 }
 543
 544                 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_IP4,
 545                                  ipv4 ? OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0);
 546                 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L3_FRAGMENT,
 547                                  fragment);
 548                 vcap_key_set(vcap, &data, VCAP_IS2_HK_L3_FRAG_OFS_GT0, 0, 0);
 549                 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L3_OPTIONS,
 550                                  options);
 551                 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_IP4_L3_TTL_GT0,
 552                                  ttl);
 553                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L3_TOS,
 554                                    ds.value, ds.mask);
 555                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L3_IP4_DIP,
 556                                    dip.value.addr, dip.mask.addr);
 557                 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L3_IP4_SIP,
 558                                    sip.value.addr, sip.mask.addr);
 559                 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_DIP_EQ_SIP,
 560                                  sip_eq_dip);
 561                 val = proto.value[0];
 562                 msk = proto.mask[0];
 563                 type = IS2_TYPE_IP_UDP_TCP;
 564                 if (msk == 0xff && (val == 6 || val == 17)) {
 565                         /* UDP/TCP protocol match */
 566                         tcp = (val == 6 ?
 567                                OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0);
 568                         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_TCP, tcp);
 569                         vcap_key_l4_port_set(vcap, &data,
 570                                              VCAP_IS2_HK_L4_DPORT, dport);
 571                         vcap_key_l4_port_set(vcap, &data,
 572                                              VCAP_IS2_HK_L4_SPORT, sport);
 573                         vcap_key_set(vcap, &data, VCAP_IS2_HK_L4_RNG, 0, 0);
 574                         vcap_key_bit_set(vcap, &data,
 575                                          VCAP_IS2_HK_L4_SPORT_EQ_DPORT,
 576                                          sport_eq_dport);
 577                         vcap_key_bit_set(vcap, &data,
 578                                          VCAP_IS2_HK_L4_SEQUENCE_EQ0,
 579                                          seq_zero);
 580                         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_FIN,
 581                                          tcp_fin);
 582                         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_SYN,
 583                                          tcp_syn);
 584                         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_RST,
 585                                          tcp_rst);
 586                         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_PSH,
 587                                          tcp_psh);
 588                         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_ACK,
 589                                          tcp_ack);
 590                         vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_URG,
 591                                          tcp_urg);
 592                         vcap_key_set(vcap, &data, VCAP_IS2_HK_L4_1588_DOM,
 593                                      0, 0);
 594                         vcap_key_set(vcap, &data, VCAP_IS2_HK_L4_1588_VER,
 595                                      0, 0);
 596                 } else {
 597                         if (msk == 0) {
 598                                 /* Any IP protocol match */
 599                                 type_mask = IS2_TYPE_MASK_IP_ANY;
 600                         } else {
 601                                 /* Non-UDP/TCP protocol match */
 602                                 type = IS2_TYPE_IP_OTHER;
 603                                 for (i = 0; i < 6; i++) {
 604                                         payload.value[i] = ip_data->value[i];
 605                                         payload.mask[i] = ip_data->mask[i];
 606                                 }
 607                         }
 608                         vcap_key_bytes_set(vcap, &data,
 609                                            VCAP_IS2_HK_IP4_L3_PROTO,
 610                                            proto.value, proto.mask);
 611                         vcap_key_bytes_set(vcap, &data,
 612                                            VCAP_IS2_HK_L3_PAYLOAD,
 613                                            payload.value, payload.mask);
 614                 }
 615                 break;
 616         }
 617         case OCELOT_VCAP_KEY_ANY:
 618         default:
 619                 type = 0;
 620                 type_mask = 0;
 621                 count = vcap->entry_width / 2;
 622                 /* Iterate over the non-common part of the key and
 623                  * clear entry data
 624                  */
 625                 for (i = vcap->keys[VCAP_IS2_HK_L2_DMAC].offset;
 626                      i < count; i += ENTRY_WIDTH) {
 627                         vcap_key_field_set(&data, i, min(32u, count - i), 0, 0);
 628                 }
 629                 break;
 630         }
 631
 632         vcap_key_set(vcap, &data, VCAP_IS2_TYPE, type, type_mask);
 633         is2_action_set(ocelot, &data, filter);
 634         vcap_data_set(data.counter, data.counter_offset,
 635                       vcap->counter_width, filter->stats.pkts);
 636
 637         /* Write row */
 638         vcap_entry2cache(ocelot, vcap, &data);
 639         vcap_action2cache(ocelot, vcap, &data);
 640         vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_WRITE, VCAP_SEL_ALL);
 641 }
 642
 643 static void
 644 vcap_entry_get(struct ocelot *ocelot, struct ocelot_vcap_filter *filter, int ix)
 645 {
 646         const struct vcap_props *vcap = &ocelot->vcap[VCAP_IS2];
 647         struct vcap_data data;
 648         int row, count;
 649         u32 cnt;
 650
 651         data.tg_sw = VCAP_TG_HALF;
 652         count = (1 << (data.tg_sw - 1));
 653         row = (ix / count);
 654         vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_READ, VCAP_SEL_COUNTER);
 655         vcap_cache2action(ocelot, vcap, &data);
 656         vcap_data_offset_get(vcap, &data, ix);
 657         cnt = vcap_data_get(data.counter, data.counter_offset,
 658                             vcap->counter_width);
 659
 660         filter->stats.pkts = cnt;
 661 }
 662
 663 static int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix,
 664                                    struct ocelot_policer *pol)
 665 {
 666         struct qos_policer_conf pp = { 0 };
 667
 668         if (!pol)
 669                 return -EINVAL;
 670
 671         pp.mode = MSCC_QOS_RATE_MODE_DATA;
 672         pp.pir = pol->rate;
 673         pp.pbs = pol->burst;
 674
 675         return qos_policer_conf_set(ocelot, 0, pol_ix, &pp);
 676 }
 677
 678 static void ocelot_vcap_policer_del(struct ocelot *ocelot,
 679                                     struct ocelot_vcap_block *block,
 680                                     u32 pol_ix)
 681 {
 682         struct ocelot_vcap_filter *filter;
 683         struct qos_policer_conf pp = {0};
 684         int index = -1;
 685
 686         if (pol_ix < block->pol_lpr)
 687                 return;
 688
 689         list_for_each_entry(filter, &block->rules, list) {
 690                 index++;
 691                 if (filter->action.police_ena &&
 692                     filter->action.pol_ix < pol_ix) {
 693                         filter->action.pol_ix += 1;
 694                         ocelot_vcap_policer_add(ocelot, filter->action.pol_ix,
 695                                                 &filter->action.pol);
 696                         is2_entry_set(ocelot, index, filter);
 697                 }
 698         }
 699
 700         pp.mode = MSCC_QOS_RATE_MODE_DISABLED;
 701         qos_policer_conf_set(ocelot, 0, pol_ix, &pp);
 702
 703         block->pol_lpr++;
 704 }
 705
 706 static void ocelot_vcap_filter_add_to_block(struct ocelot *ocelot,
 707                                             struct ocelot_vcap_block *block,
 708                                             struct ocelot_vcap_filter *filter)
 709 {
 710         struct ocelot_vcap_filter *tmp;
 711         struct list_head *pos, *n;
 712
 713         if (filter->action.police_ena) {
 714                 block->pol_lpr--;
 715                 filter->action.pol_ix = block->pol_lpr;
 716                 ocelot_vcap_policer_add(ocelot, filter->action.pol_ix,
 717                                         &filter->action.pol);
 718         }
 719
 720         block->count++;
 721
 722         if (list_empty(&block->rules)) {
 723                 list_add(&filter->list, &block->rules);
 724                 return;
 725         }
 726
 727         list_for_each_safe(pos, n, &block->rules) {
 728                 tmp = list_entry(pos, struct ocelot_vcap_filter, list);
 729                 if (filter->prio < tmp->prio)
 730                         break;
 731         }
 732         list_add(&filter->list, pos->prev);
 733 }
 734
 735 static int ocelot_vcap_block_get_filter_index(struct ocelot_vcap_block *block,
 736                                               struct ocelot_vcap_filter *filter)
 737 {
 738         struct ocelot_vcap_filter *tmp;
 739         int index = 0;
 740
 741         list_for_each_entry(tmp, &block->rules, list) {
 742                 if (filter->id == tmp->id)
 743                         return index;
 744                 index++;
 745         }
 746
 747         return -ENOENT;
 748 }
 749
 750 static struct ocelot_vcap_filter*
 751 ocelot_vcap_block_find_filter_by_index(struct ocelot_vcap_block *block,
 752                                        int index)
 753 {
 754         struct ocelot_vcap_filter *tmp;
 755         int i = 0;
 756
 757         list_for_each_entry(tmp, &block->rules, list) {
 758                 if (i == index)
 759                         return tmp;
 760                 ++i;
 761         }
 762
 763         return NULL;
 764 }
 765
 766 struct ocelot_vcap_filter *
 767 ocelot_vcap_block_find_filter_by_id(struct ocelot_vcap_block *block, int id)
 768 {
 769         struct ocelot_vcap_filter *filter;
 770
 771         list_for_each_entry(filter, &block->rules, list)
 772                 if (filter->id == id)
 773                         return filter;
 774
 775         return NULL;
 776 }
 777
 778 /* If @on=false, then SNAP, ARP, IP and OAM frames will not match on keys based
 779  * on destination and source MAC addresses, but only on higher-level protocol
 780  * information. The only frame types to match on keys containing MAC addresses
 781  * in this case are non-SNAP, non-ARP, non-IP and non-OAM frames.
 782  *
 783  * If @on=true, then the above frame types (SNAP, ARP, IP and OAM) will match
 784  * on MAC_ETYPE keys such as destination and source MAC on this ingress port.
 785  * However the setting has the side effect of making these frames not matching
 786  * on any _other_ keys than MAC_ETYPE ones.
 787  */
 788 static void ocelot_match_all_as_mac_etype(struct ocelot *ocelot, int port,
 789                                           bool on)
 790 {
 791         u32 val = 0;
 792
 793         if (on)
 794                 val = ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(3) |
 795                       ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(3) |
 796                       ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(3) |
 797                       ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(3) |
 798                       ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(3);
 799
 800         ocelot_rmw_gix(ocelot, val,
 801                        ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M |
 802                        ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M |
 803                        ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M |
 804                        ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M |
 805                        ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M,
 806                        ANA_PORT_VCAP_S2_CFG, port);
 807 }
 808
 809 static bool
 810 ocelot_vcap_is_problematic_mac_etype(struct ocelot_vcap_filter *filter)
 811 {
 812         u16 proto, mask;
 813
 814         if (filter->key_type != OCELOT_VCAP_KEY_ETYPE)
 815                 return false;
 816
 817         proto = ntohs(*(__be16 *)filter->key.etype.etype.value);
 818         mask = ntohs(*(__be16 *)filter->key.etype.etype.mask);
 819
 820         /* ETH_P_ALL match, so all protocols below are included */
 821         if (mask == 0)
 822                 return true;
 823         if (proto == ETH_P_ARP)
 824                 return true;
 825         if (proto == ETH_P_IP)
 826                 return true;
 827         if (proto == ETH_P_IPV6)
 828                 return true;
 829
 830         return false;
 831 }
 832
 833 static bool
 834 ocelot_vcap_is_problematic_non_mac_etype(struct ocelot_vcap_filter *filter)
 835 {
 836         if (filter->key_type == OCELOT_VCAP_KEY_SNAP)
 837                 return true;
 838         if (filter->key_type == OCELOT_VCAP_KEY_ARP)
 839                 return true;
 840         if (filter->key_type == OCELOT_VCAP_KEY_IPV4)
 841                 return true;
 842         if (filter->key_type == OCELOT_VCAP_KEY_IPV6)
 843                 return true;
 844         return false;
 845 }
 846
 847 static bool
 848 ocelot_exclusive_mac_etype_filter_rules(struct ocelot *ocelot,
 849                                         struct ocelot_vcap_filter *filter)
 850 {
 851         struct ocelot_vcap_block *block = &ocelot->block;
 852         struct ocelot_vcap_filter *tmp;
 853         unsigned long port;
 854         int i;
 855
 856         if (ocelot_vcap_is_problematic_mac_etype(filter)) {
 857                 /* Search for any non-MAC_ETYPE rules on the port */
 858                 for (i = 0; i < block->count; i++) {
 859                         tmp = ocelot_vcap_block_find_filter_by_index(block, i);
 860                         if (tmp->ingress_port_mask & filter->ingress_port_mask &&
 861                             ocelot_vcap_is_problematic_non_mac_etype(tmp))
 862                                 return false;
 863                 }
 864
 865                 for_each_set_bit(port, &filter->ingress_port_mask,
 866                                  ocelot->num_phys_ports)
 867                         ocelot_match_all_as_mac_etype(ocelot, port, true);
 868         } else if (ocelot_vcap_is_problematic_non_mac_etype(filter)) {
 869                 /* Search for any MAC_ETYPE rules on the port */
 870                 for (i = 0; i < block->count; i++) {
 871                         tmp = ocelot_vcap_block_find_filter_by_index(block, i);
 872                         if (tmp->ingress_port_mask & filter->ingress_port_mask &&
 873                             ocelot_vcap_is_problematic_mac_etype(tmp))
 874                                 return false;
 875                 }
 876
 877                 for_each_set_bit(port, &filter->ingress_port_mask,
 878                                  ocelot->num_phys_ports)
 879                         ocelot_match_all_as_mac_etype(ocelot, port, false);
 880         }
 881
 882         return true;
 883 }
 884
 885 int ocelot_vcap_filter_add(struct ocelot *ocelot,
 886                            struct ocelot_vcap_filter *filter,
 887                            struct netlink_ext_ack *extack)
 888 {
 889         struct ocelot_vcap_block *block = &ocelot->block;
 890         int i, index;
 891
 892         if (!ocelot_exclusive_mac_etype_filter_rules(ocelot, filter)) {
 893                 NL_SET_ERR_MSG_MOD(extack,
 894                                    "Cannot mix MAC_ETYPE with non-MAC_ETYPE rules");
 895                 return -EBUSY;
 896         }
 897
 898         /* Add filter to the linked list */
 899         ocelot_vcap_filter_add_to_block(ocelot, block, filter);
 900
 901         /* Get the index of the inserted filter */
 902         index = ocelot_vcap_block_get_filter_index(block, filter);
 903         if (index < 0)
 904                 return index;
 905
 906         /* Move down the rules to make place for the new filter */
 907         for (i = block->count - 1; i > index; i--) {
 908                 struct ocelot_vcap_filter *tmp;
 909
 910                 tmp = ocelot_vcap_block_find_filter_by_index(block, i);
 911                 is2_entry_set(ocelot, i, tmp);
 912         }
 913
 914         /* Now insert the new filter */
 915         is2_entry_set(ocelot, index, filter);
 916         return 0;
 917 }
 918
 919 static void ocelot_vcap_block_remove_filter(struct ocelot *ocelot,
 920                                             struct ocelot_vcap_block *block,
 921                                             struct ocelot_vcap_filter *filter)
 922 {
 923         struct ocelot_vcap_filter *tmp;
 924         struct list_head *pos, *q;
 925
 926         list_for_each_safe(pos, q, &block->rules) {
 927                 tmp = list_entry(pos, struct ocelot_vcap_filter, list);
 928                 if (tmp->id == filter->id) {
 929                         if (tmp->action.police_ena)
 930                                 ocelot_vcap_policer_del(ocelot, block,
 931                                                         tmp->action.pol_ix);
 932
 933                         list_del(pos);
 934                         kfree(tmp);
 935                 }
 936         }
 937
 938         block->count--;
 939 }
 940
 941 int ocelot_vcap_filter_del(struct ocelot *ocelot,
 942                            struct ocelot_vcap_filter *filter)
 943 {
 944         struct ocelot_vcap_block *block = &ocelot->block;
 945         struct ocelot_vcap_filter del_filter;
 946         int i, index;
 947
 948         memset(&del_filter, 0, sizeof(del_filter));
 949
 950         /* Gets index of the filter */
 951         index = ocelot_vcap_block_get_filter_index(block, filter);
 952         if (index < 0)
 953                 return index;
 954
 955         /* Delete filter */
 956         ocelot_vcap_block_remove_filter(ocelot, block, filter);
 957
 958         /* Move up all the blocks over the deleted filter */
 959         for (i = index; i < block->count; i++) {
 960                 struct ocelot_vcap_filter *tmp;
 961
 962                 tmp = ocelot_vcap_block_find_filter_by_index(block, i);
 963                 is2_entry_set(ocelot, i, tmp);
 964         }
 965
 966         /* Now delete the last filter, because it is duplicated */
 967         is2_entry_set(ocelot, block->count, &del_filter);
 968
 969         return 0;
 970 }
 971
 972 int ocelot_vcap_filter_stats_update(struct ocelot *ocelot,
 973                                     struct ocelot_vcap_filter *filter)
 974 {
 975         struct ocelot_vcap_block *block = &ocelot->block;
 976         struct ocelot_vcap_filter tmp;
 977         int index;
 978
 979         index = ocelot_vcap_block_get_filter_index(block, filter);
 980         if (index < 0)
 981                 return index;
 982
 983         vcap_entry_get(ocelot, filter, index);
 984
 985         /* After we get the result we need to clear the counters */
 986         tmp = *filter;
 987         tmp.stats.pkts = 0;
 988         is2_entry_set(ocelot, index, &tmp);
 989
 990         return 0;
 991 }
 992
 993 static void ocelot_vcap_init_one(struct ocelot *ocelot,
 994                                  const struct vcap_props *vcap)
 995 {
 996         struct vcap_data data;
 997
 998         memset(&data, 0, sizeof(data));
 999
1000         vcap_entry2cache(ocelot, vcap, &data);
1001         ocelot_target_write(ocelot, vcap->target, vcap->entry_count,
1002                             VCAP_CORE_MV_CFG);
1003         vcap_cmd(ocelot, vcap, 0, VCAP_CMD_INITIALIZE, VCAP_SEL_ENTRY);
1004
1005         vcap_action2cache(ocelot, vcap, &data);
1006         ocelot_target_write(ocelot, vcap->target, vcap->action_count,
1007                             VCAP_CORE_MV_CFG);
1008         vcap_cmd(ocelot, vcap, 0, VCAP_CMD_INITIALIZE,
1009                  VCAP_SEL_ACTION | VCAP_SEL_COUNTER);
1010 }
1011
1012 static void ocelot_vcap_detect_constants(struct ocelot *ocelot,
1013                                          struct vcap_props *vcap)
1014 {
1015         int counter_memory_width;
1016         int num_default_actions;
1017         int version;
1018
1019         version = ocelot_target_read(ocelot, vcap->target,
1020                                      VCAP_CONST_VCAP_VER);
1021         /* Only version 0 VCAP supported for now */
1022         if (WARN_ON(version != 0))
1023                 return;
1024
1025         /* Width in bits of type-group field */
1026         vcap->tg_width = ocelot_target_read(ocelot, vcap->target,
1027                                             VCAP_CONST_ENTRY_TG_WIDTH);
1028         /* Number of subwords per TCAM row */
1029         vcap->sw_count = ocelot_target_read(ocelot, vcap->target,
1030                                             VCAP_CONST_ENTRY_SWCNT);
1031         /* Number of rows in TCAM. There can be this many full keys, or double
1032          * this number half keys, or 4 times this number quarter keys.
1033          */
1034         vcap->entry_count = ocelot_target_read(ocelot, vcap->target,
1035                                                VCAP_CONST_ENTRY_CNT);
1036         /* Assuming there are 4 subwords per TCAM row, their layout in the
1037          * actual TCAM (not in the cache) would be:
1038          *
1039          * |  SW 3  | TG 3 |  SW 2  | TG 2 |  SW 1  | TG 1 |  SW 0  | TG 0 |
1040          *
1041          * (where SW=subword and TG=Type-Group).
1042          *
1043          * What VCAP_CONST_ENTRY_CNT is giving us is the width of one full TCAM
1044          * row. But when software accesses the TCAM through the cache
1045          * registers, the Type-Group values are written through another set of
1046          * registers VCAP_TG_DAT, and therefore, it appears as though the 4
1047          * subwords are contiguous in the cache memory.
1048          * Important mention: regardless of the number of key entries per row
1049          * (and therefore of key size: 1 full key or 2 half keys or 4 quarter
1050          * keys), software always has to configure 4 Type-Group values. For
1051          * example, in the case of 1 full key, the driver needs to set all 4
1052          * Type-Group to be full key.
1053          *
1054          * For this reason, we need to fix up the value that the hardware is
1055          * giving us. We don't actually care about the width of the entry in
1056          * the TCAM. What we care about is the width of the entry in the cache
1057          * registers, which is how we get to interact with it. And since the
1058          * VCAP_ENTRY_DAT cache registers access only the subwords and not the
1059          * Type-Groups, this means we need to subtract the width of the
1060          * Type-Groups when packing and unpacking key entry data in a TCAM row.
1061          */
1062         vcap->entry_width = ocelot_target_read(ocelot, vcap->target,
1063                                                VCAP_CONST_ENTRY_WIDTH);
1064         vcap->entry_width -= vcap->tg_width * vcap->sw_count;
1065         num_default_actions = ocelot_target_read(ocelot, vcap->target,
1066                                                  VCAP_CONST_ACTION_DEF_CNT);
1067         vcap->action_count = vcap->entry_count + num_default_actions;
1068         vcap->action_width = ocelot_target_read(ocelot, vcap->target,
1069                                                 VCAP_CONST_ACTION_WIDTH);
1070         /* The width of the counter memory, this is the complete width of all
1071          * counter-fields associated with one full-word entry. There is one
1072          * counter per entry sub-word (see CAP_CORE::ENTRY_SWCNT for number of
1073          * subwords.)
1074          */
1075         vcap->counter_words = vcap->sw_count;
1076         counter_memory_width = ocelot_target_read(ocelot, vcap->target,
1077                                                   VCAP_CONST_CNT_WIDTH);
1078         vcap->counter_width = counter_memory_width / vcap->counter_words;
1079 }
1080
1081 int ocelot_vcap_init(struct ocelot *ocelot)
1082 {
1083         struct ocelot_vcap_block *block = &ocelot->block;
1084         int i;
1085
1086         /* Create a policer that will drop the frames for the cpu.
1087          * This policer will be used as action in the acl rules to drop
1088          * frames.
1089          */
1090         ocelot_write_gix(ocelot, 0x299, ANA_POL_MODE_CFG,
1091                          OCELOT_POLICER_DISCARD);
1092         ocelot_write_gix(ocelot, 0x1, ANA_POL_PIR_CFG,
1093                          OCELOT_POLICER_DISCARD);
1094         ocelot_write_gix(ocelot, 0x3fffff, ANA_POL_PIR_STATE,
1095                          OCELOT_POLICER_DISCARD);
1096         ocelot_write_gix(ocelot, 0x0, ANA_POL_CIR_CFG,
1097                          OCELOT_POLICER_DISCARD);
1098         ocelot_write_gix(ocelot, 0x3fffff, ANA_POL_CIR_STATE,
1099                          OCELOT_POLICER_DISCARD);
1100
1101         for (i = 0; i < OCELOT_NUM_VCAP_BLOCKS; i++) {
1102                 struct vcap_props *vcap = &ocelot->vcap[i];
1103
1104                 ocelot_vcap_detect_constants(ocelot, vcap);
1105                 ocelot_vcap_init_one(ocelot, vcap);
1106         }
1107
1108         block->pol_lpr = OCELOT_POLICER_DISCARD - 1;
1109
1110         INIT_LIST_HEAD(&block->rules);
1111
1112         return 0;
1113 }