drivers/net/ethernet/mscc/ocelot_board.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Microsemi Ocelot Switch driver
   4  *
   5  * Copyright (c) 2017 Microsemi Corporation
   6  */
   7 #include <linux/interrupt.h>
   8 #include <linux/module.h>
   9 #include <linux/of_net.h>
  10 #include <linux/netdevice.h>
  11 #include <linux/of_mdio.h>
  12 #include <linux/of_platform.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/skbuff.h>
  15 #include <net/switchdev.h>
  16
  17 #include "ocelot.h"
  18
  19 #define IFH_EXTRACT_BITFIELD64(x, o, w) (((x) >> (o)) & GENMASK_ULL((w) - 1, 0))
  20
  21 static int ocelot_parse_ifh(u32 *_ifh, struct frame_info *info)
  22 {
  23         u8 llen, wlen;
  24         u64 ifh[2];
  25
  26         ifh[0] = be64_to_cpu(((__force __be64 *)_ifh)[0]);
  27         ifh[1] = be64_to_cpu(((__force __be64 *)_ifh)[1]);
  28
  29         wlen = IFH_EXTRACT_BITFIELD64(ifh[0], 7,  8);
  30         llen = IFH_EXTRACT_BITFIELD64(ifh[0], 15,  6);
  31
  32         info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80;
  33
  34         info->timestamp = IFH_EXTRACT_BITFIELD64(ifh[0], 21, 32);
  35
  36         info->port = IFH_EXTRACT_BITFIELD64(ifh[1], 43, 4);
  37
  38         info->tag_type = IFH_EXTRACT_BITFIELD64(ifh[1], 16,  1);
  39         info->vid = IFH_EXTRACT_BITFIELD64(ifh[1], 0,  12);
  40
  41         return 0;
  42 }
  43
  44 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
  45                                 u32 *rval)
  46 {
  47         u32 val;
  48         u32 bytes_valid;
  49
  50         val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  51         if (val == XTR_NOT_READY) {
  52                 if (ifh)
  53                         return -EIO;
  54
  55                 do {
  56                         val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  57                 } while (val == XTR_NOT_READY);
  58         }
  59
  60         switch (val) {
  61         case XTR_ABORT:
  62                 return -EIO;
  63         case XTR_EOF_0:
  64         case XTR_EOF_1:
  65         case XTR_EOF_2:
  66         case XTR_EOF_3:
  67         case XTR_PRUNED:
  68                 bytes_valid = XTR_VALID_BYTES(val);
  69                 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  70                 if (val == XTR_ESCAPE)
  71                         *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  72                 else
  73                         *rval = val;
  74
  75                 return bytes_valid;
  76         case XTR_ESCAPE:
  77                 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  78
  79                 return 4;
  80         default:
  81                 *rval = val;
  82
  83                 return 4;
  84         }
  85 }
  86
  87 static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg)
  88 {
  89         struct ocelot *ocelot = arg;
  90         int i = 0, grp = 0;
  91         int err = 0;
  92
  93         if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)))
  94                 return IRQ_NONE;
  95
  96         do {
  97                 struct skb_shared_hwtstamps *shhwtstamps;
  98                 struct ocelot_port_private *priv;
  99                 struct ocelot_port *ocelot_port;
 100                 u64 tod_in_ns, full_ts_in_ns;
 101                 struct frame_info info = {};
 102                 struct net_device *dev;
 103                 u32 ifh[4], val, *buf;
 104                 struct timespec64 ts;
 105                 int sz, len, buf_len;
 106                 struct sk_buff *skb;
 107
 108                 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
 109                         err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]);
 110                         if (err != 4)
 111                                 break;
 112                 }
 113
 114                 if (err != 4)
 115                         break;
 116
 117                 ocelot_parse_ifh(ifh, &info);
 118
 119                 ocelot_port = ocelot->ports[info.port];
 120                 priv = container_of(ocelot_port, struct ocelot_port_private,
 121                                     port);
 122                 dev = priv->dev;
 123
 124                 skb = netdev_alloc_skb(dev, info.len);
 125
 126                 if (unlikely(!skb)) {
 127                         netdev_err(dev, "Unable to allocate sk_buff\n");
 128                         err = -ENOMEM;
 129                         break;
 130                 }
 131                 buf_len = info.len - ETH_FCS_LEN;
 132                 buf = (u32 *)skb_put(skb, buf_len);
 133
 134                 len = 0;
 135                 do {
 136                         sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
 137                         *buf++ = val;
 138                         len += sz;
 139                 } while (len < buf_len);
 140
 141                 /* Read the FCS */
 142                 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
 143                 /* Update the statistics if part of the FCS was read before */
 144                 len -= ETH_FCS_LEN - sz;
 145
 146                 if (unlikely(dev->features & NETIF_F_RXFCS)) {
 147                         buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
 148                         *buf = val;
 149                 }
 150
 151                 if (sz < 0) {
 152                         err = sz;
 153                         break;
 154                 }
 155
 156                 if (ocelot->ptp) {
 157                         ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
 158
 159                         tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
 160                         if ((tod_in_ns & 0xffffffff) < info.timestamp)
 161                                 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
 162                                                 info.timestamp;
 163                         else
 164                                 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
 165                                                 info.timestamp;
 166
 167                         shhwtstamps = skb_hwtstamps(skb);
 168                         memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
 169                         shhwtstamps->hwtstamp = full_ts_in_ns;
 170                 }
 171
 172                 /* Everything we see on an interface that is in the HW bridge
 173                  * has already been forwarded.
 174                  */
 175                 if (ocelot->bridge_mask & BIT(info.port))
 176                         skb->offload_fwd_mark = 1;
 177
 178                 skb->protocol = eth_type_trans(skb, dev);
 179                 netif_rx(skb);
 180                 dev->stats.rx_bytes += len;
 181                 dev->stats.rx_packets++;
 182         } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp));
 183
 184         if (err)
 185                 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
 186                         ocelot_read_rix(ocelot, QS_XTR_RD, grp);
 187
 188         return IRQ_HANDLED;
 189 }
 190
 191 static irqreturn_t ocelot_ptp_rdy_irq_handler(int irq, void *arg)
 192 {
 193         struct ocelot *ocelot = arg;
 194
 195         ocelot_get_txtstamp(ocelot);
 196
 197         return IRQ_HANDLED;
 198 }
 199
 200 static const struct of_device_id mscc_ocelot_match[] = {
 201         { .compatible = "mscc,vsc7514-switch" },
 202         { }
 203 };
 204 MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
 205
 206 static void ocelot_port_pcs_init(struct ocelot *ocelot, int port)
 207 {
 208         struct ocelot_port *ocelot_port = ocelot->ports[port];
 209
 210         /* Disable HDX fast control */
 211         ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
 212                            DEV_PORT_MISC);
 213
 214         /* SGMII only for now */
 215         ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
 216                            PCS1G_MODE_CFG);
 217         ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
 218
 219         /* Enable PCS */
 220         ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
 221
 222         /* No aneg on SGMII */
 223         ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
 224
 225         /* No loopback */
 226         ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
 227 }
 228
 229 static int ocelot_reset(struct ocelot *ocelot)
 230 {
 231         int retries = 100;
 232         u32 val;
 233
 234         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
 235         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
 236
 237         do {
 238                 msleep(1);
 239                 regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
 240                                   &val);
 241         } while (val && --retries);
 242
 243         if (!retries)
 244                 return -ETIMEDOUT;
 245
 246         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
 247         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
 248
 249         return 0;
 250 }
 251
 252 static const struct ocelot_ops ocelot_ops = {
 253         .pcs_init               = ocelot_port_pcs_init,
 254         .reset                  = ocelot_reset,
 255 };
 256
 257 static int mscc_ocelot_probe(struct platform_device *pdev)
 258 {
 259         struct device_node *np = pdev->dev.of_node;
 260         struct device_node *ports, *portnp;
 261         int err, irq_xtr, irq_ptp_rdy;
 262         struct ocelot *ocelot;
 263         struct regmap *hsio;
 264         unsigned int i;
 265
 266         struct {
 267                 enum ocelot_target id;
 268                 char *name;
 269                 u8 optional:1;
 270         } io_target[] = {
 271                 { SYS, "sys" },
 272                 { REW, "rew" },
 273                 { QSYS, "qsys" },
 274                 { ANA, "ana" },
 275                 { QS, "qs" },
 276                 { S2, "s2" },
 277                 { PTP, "ptp", 1 },
 278         };
 279
 280         if (!np && !pdev->dev.platform_data)
 281                 return -ENODEV;
 282
 283         ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL);
 284         if (!ocelot)
 285                 return -ENOMEM;
 286
 287         platform_set_drvdata(pdev, ocelot);
 288         ocelot->dev = &pdev->dev;
 289
 290         for (i = 0; i < ARRAY_SIZE(io_target); i++) {
 291                 struct regmap *target;
 292                 struct resource *res;
 293
 294                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 295                                                    io_target[i].name);
 296
 297                 target = ocelot_regmap_init(ocelot, res);
 298                 if (IS_ERR(target)) {
 299                         if (io_target[i].optional) {
 300                                 ocelot->targets[io_target[i].id] = NULL;
 301                                 continue;
 302                         }
 303                         return PTR_ERR(target);
 304                 }
 305
 306                 ocelot->targets[io_target[i].id] = target;
 307         }
 308
 309         hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio");
 310         if (IS_ERR(hsio)) {
 311                 dev_err(&pdev->dev, "missing hsio syscon\n");
 312                 return PTR_ERR(hsio);
 313         }
 314
 315         ocelot->targets[HSIO] = hsio;
 316
 317         err = ocelot_chip_init(ocelot, &ocelot_ops);
 318         if (err)
 319                 return err;
 320
 321         irq_xtr = platform_get_irq_byname(pdev, "xtr");
 322         if (irq_xtr < 0)
 323                 return -ENODEV;
 324
 325         err = devm_request_threaded_irq(&pdev->dev, irq_xtr, NULL,
 326                                         ocelot_xtr_irq_handler, IRQF_ONESHOT,
 327                                         "frame extraction", ocelot);
 328         if (err)
 329                 return err;
 330
 331         irq_ptp_rdy = platform_get_irq_byname(pdev, "ptp_rdy");
 332         if (irq_ptp_rdy > 0 && ocelot->targets[PTP]) {
 333                 err = devm_request_threaded_irq(&pdev->dev, irq_ptp_rdy, NULL,
 334                                                 ocelot_ptp_rdy_irq_handler,
 335                                                 IRQF_ONESHOT, "ptp ready",
 336                                                 ocelot);
 337                 if (err)
 338                         return err;
 339
 340                 /* Both the PTP interrupt and the PTP bank are available */
 341                 ocelot->ptp = 1;
 342         }
 343
 344         ocelot->num_cpu_ports = 1; /* 1 port on the switch, two groups */
 345
 346         ports = of_get_child_by_name(np, "ethernet-ports");
 347         if (!ports) {
 348                 dev_err(&pdev->dev, "no ethernet-ports child node found\n");
 349                 return -ENODEV;
 350         }
 351
 352         ocelot->num_phys_ports = of_get_child_count(ports);
 353
 354         ocelot->ports = devm_kcalloc(&pdev->dev, ocelot->num_phys_ports,
 355                                      sizeof(struct ocelot_port *), GFP_KERNEL);
 356
 357         ocelot_init(ocelot);
 358         ocelot_set_cpu_port(ocelot, ocelot->num_phys_ports,
 359                             OCELOT_TAG_PREFIX_NONE, OCELOT_TAG_PREFIX_NONE);
 360
 361         for_each_available_child_of_node(ports, portnp) {
 362                 struct ocelot_port_private *priv;
 363                 struct ocelot_port *ocelot_port;
 364                 struct device_node *phy_node;
 365                 phy_interface_t phy_mode;
 366                 struct phy_device *phy;
 367                 struct resource *res;
 368                 struct phy *serdes;
 369                 void __iomem *regs;
 370                 char res_name[8];
 371                 u32 port;
 372
 373                 if (of_property_read_u32(portnp, "reg", &port))
 374                         continue;
 375
 376                 snprintf(res_name, sizeof(res_name), "port%d", port);
 377
 378                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 379                                                    res_name);
 380                 regs = devm_ioremap_resource(&pdev->dev, res);
 381                 if (IS_ERR(regs))
 382                         continue;
 383
 384                 phy_node = of_parse_phandle(portnp, "phy-handle", 0);
 385                 if (!phy_node)
 386                         continue;
 387
 388                 phy = of_phy_find_device(phy_node);
 389                 of_node_put(phy_node);
 390                 if (!phy)
 391                         continue;
 392
 393                 err = ocelot_probe_port(ocelot, port, regs, phy);
 394                 if (err) {
 395                         of_node_put(portnp);
 396                         goto out_put_ports;
 397                 }
 398
 399                 ocelot_port = ocelot->ports[port];
 400                 priv = container_of(ocelot_port, struct ocelot_port_private,
 401                                     port);
 402
 403                 of_get_phy_mode(portnp, &phy_mode);
 404
 405                 ocelot_port->phy_mode = phy_mode;
 406
 407                 switch (ocelot_port->phy_mode) {
 408                 case PHY_INTERFACE_MODE_NA:
 409                         continue;
 410                 case PHY_INTERFACE_MODE_SGMII:
 411                         break;
 412                 case PHY_INTERFACE_MODE_QSGMII:
 413                         /* Ensure clock signals and speed is set on all
 414                          * QSGMII links
 415                          */
 416                         ocelot_port_writel(ocelot_port,
 417                                            DEV_CLOCK_CFG_LINK_SPEED
 418                                            (OCELOT_SPEED_1000),
 419                                            DEV_CLOCK_CFG);
 420                         break;
 421                 default:
 422                         dev_err(ocelot->dev,
 423                                 "invalid phy mode for port%d, (Q)SGMII only\n",
 424                                 port);
 425                         of_node_put(portnp);
 426                         err = -EINVAL;
 427                         goto out_put_ports;
 428                 }
 429
 430                 serdes = devm_of_phy_get(ocelot->dev, portnp, NULL);
 431                 if (IS_ERR(serdes)) {
 432                         err = PTR_ERR(serdes);
 433                         if (err == -EPROBE_DEFER)
 434                                 dev_dbg(ocelot->dev, "deferring probe\n");
 435                         else
 436                                 dev_err(ocelot->dev,
 437                                         "missing SerDes phys for port%d\n",
 438                                         port);
 439
 440                         of_node_put(portnp);
 441                         goto out_put_ports;
 442                 }
 443
 444                 priv->serdes = serdes;
 445         }
 446
 447         register_netdevice_notifier(&ocelot_netdevice_nb);
 448         register_switchdev_notifier(&ocelot_switchdev_nb);
 449         register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb);
 450
 451         dev_info(&pdev->dev, "Ocelot switch probed\n");
 452
 453 out_put_ports:
 454         of_node_put(ports);
 455         return err;
 456 }
 457
 458 static int mscc_ocelot_remove(struct platform_device *pdev)
 459 {
 460         struct ocelot *ocelot = platform_get_drvdata(pdev);
 461
 462         ocelot_deinit(ocelot);
 463         unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb);
 464         unregister_switchdev_notifier(&ocelot_switchdev_nb);
 465         unregister_netdevice_notifier(&ocelot_netdevice_nb);
 466
 467         return 0;
 468 }
 469
 470 static struct platform_driver mscc_ocelot_driver = {
 471         .probe = mscc_ocelot_probe,
 472         .remove = mscc_ocelot_remove,
 473         .driver = {
 474                 .name = "ocelot-switch",
 475                 .of_match_table = mscc_ocelot_match,
 476         },
 477 };
 478
 479 module_platform_driver(mscc_ocelot_driver);
 480
 481 MODULE_DESCRIPTION("Microsemi Ocelot switch driver");
 482 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
 483 MODULE_LICENSE("Dual MIT/GPL");