1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Microsemi Ocelot Switch driver
3 * Copyright (c) 2019 Microsemi Corporation
6 #include <linux/iopoll.h>
7 #include <linux/proc_fs.h>
9 #include <soc/mscc/ocelot_vcap.h>
10 #include "ocelot_police.h"
11 #include "ocelot_ace.h"
12 #include "ocelot_s2.h"
14 #define OCELOT_POLICER_DISCARD 0x17f
15 #define ENTRY_WIDTH 32
19 VCAP_SEL_ACTION = 0x2,
20 VCAP_SEL_COUNTER = 0x4,
25 VCAP_CMD_WRITE = 0, /* Copy from Cache to TCAM */
26 VCAP_CMD_READ = 1, /* Copy from TCAM to Cache */
27 VCAP_CMD_MOVE_UP = 2, /* Move <count> up */
28 VCAP_CMD_MOVE_DOWN = 3, /* Move <count> down */
29 VCAP_CMD_INITIALIZE = 4, /* Write all (from cache) */
32 #define VCAP_ENTRY_WIDTH 12 /* Max entry width (32bit words) */
33 #define VCAP_COUNTER_WIDTH 4 /* Max counter width (32bit words) */
36 u32 entry[VCAP_ENTRY_WIDTH]; /* ENTRY_DAT */
37 u32 mask[VCAP_ENTRY_WIDTH]; /* MASK_DAT */
38 u32 action[VCAP_ENTRY_WIDTH]; /* ACTION_DAT */
39 u32 counter[VCAP_COUNTER_WIDTH]; /* CNT_DAT */
41 u32 type; /* Action type */
42 u32 tg_sw; /* Current type-group */
43 u32 cnt; /* Current counter */
44 u32 key_offset; /* Current entry offset */
45 u32 action_offset; /* Current action offset */
46 u32 counter_offset; /* Current counter offset */
47 u32 tg_value; /* Current type-group value */
48 u32 tg_mask; /* Current type-group mask */
51 static u32 vcap_s2_read_update_ctrl(struct ocelot *ocelot)
53 return ocelot_read(ocelot, S2_CORE_UPDATE_CTRL);
56 static void vcap_cmd(struct ocelot *ocelot, u16 ix, int cmd, int sel)
58 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2];
60 u32 value = (S2_CORE_UPDATE_CTRL_UPDATE_CMD(cmd) |
61 S2_CORE_UPDATE_CTRL_UPDATE_ADDR(ix) |
62 S2_CORE_UPDATE_CTRL_UPDATE_SHOT);
64 if ((sel & VCAP_SEL_ENTRY) && ix >= vcap_is2->entry_count)
67 if (!(sel & VCAP_SEL_ENTRY))
68 value |= S2_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS;
70 if (!(sel & VCAP_SEL_ACTION))
71 value |= S2_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS;
73 if (!(sel & VCAP_SEL_COUNTER))
74 value |= S2_CORE_UPDATE_CTRL_UPDATE_CNT_DIS;
76 ocelot_write(ocelot, value, S2_CORE_UPDATE_CTRL);
77 readx_poll_timeout(vcap_s2_read_update_ctrl, ocelot, value,
78 (value & S2_CORE_UPDATE_CTRL_UPDATE_SHOT) == 0,
82 /* Convert from 0-based row to VCAP entry row and run command */
83 static void vcap_row_cmd(struct ocelot *ocelot, u32 row, int cmd, int sel)
85 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2];
87 vcap_cmd(ocelot, vcap_is2->entry_count - row - 1, cmd, sel);
90 static void vcap_entry2cache(struct ocelot *ocelot, struct vcap_data *data)
92 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2];
95 entry_words = DIV_ROUND_UP(vcap_is2->entry_width, ENTRY_WIDTH);
97 for (i = 0; i < entry_words; i++) {
98 ocelot_write_rix(ocelot, data->entry[i], S2_CACHE_ENTRY_DAT, i);
99 ocelot_write_rix(ocelot, ~data->mask[i], S2_CACHE_MASK_DAT, i);
101 ocelot_write(ocelot, data->tg, S2_CACHE_TG_DAT);
104 static void vcap_cache2entry(struct ocelot *ocelot, struct vcap_data *data)
106 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2];
109 entry_words = DIV_ROUND_UP(vcap_is2->entry_width, ENTRY_WIDTH);
111 for (i = 0; i < entry_words; i++) {
112 data->entry[i] = ocelot_read_rix(ocelot, S2_CACHE_ENTRY_DAT, i);
114 data->mask[i] = ~ocelot_read_rix(ocelot, S2_CACHE_MASK_DAT, i);
116 data->tg = ocelot_read(ocelot, S2_CACHE_TG_DAT);
119 static void vcap_action2cache(struct ocelot *ocelot, struct vcap_data *data)
121 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2];
122 u32 action_words, i, width, mask;
124 /* Encode action type */
125 width = vcap_is2->action_type_width;
127 mask = GENMASK(width, 0);
128 data->action[0] = ((data->action[0] & ~mask) | data->type);
131 action_words = DIV_ROUND_UP(vcap_is2->action_width, ENTRY_WIDTH);
133 for (i = 0; i < action_words; i++)
134 ocelot_write_rix(ocelot, data->action[i], S2_CACHE_ACTION_DAT,
137 for (i = 0; i < vcap_is2->counter_words; i++)
138 ocelot_write_rix(ocelot, data->counter[i], S2_CACHE_CNT_DAT, i);
141 static void vcap_cache2action(struct ocelot *ocelot, struct vcap_data *data)
143 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2];
144 u32 action_words, i, width;
146 action_words = DIV_ROUND_UP(vcap_is2->action_width, ENTRY_WIDTH);
148 for (i = 0; i < action_words; i++)
149 data->action[i] = ocelot_read_rix(ocelot, S2_CACHE_ACTION_DAT,
152 for (i = 0; i < vcap_is2->counter_words; i++)
153 data->counter[i] = ocelot_read_rix(ocelot, S2_CACHE_CNT_DAT, i);
155 /* Extract action type */
156 width = vcap_is2->action_type_width;
157 data->type = (width ? (data->action[0] & GENMASK(width, 0)) : 0);
160 /* Calculate offsets for entry */
161 static void is2_data_get(struct ocelot *ocelot, struct vcap_data *data, int ix)
163 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2];
164 u32 i, col, offset, count, cnt, base;
165 u32 width = vcap_is2->tg_width;
167 count = (data->tg_sw == VCAP_TG_HALF ? 2 : 4);
169 cnt = (vcap_is2->sw_count / count);
170 base = (vcap_is2->sw_count - col * cnt - cnt);
173 for (i = 0; i < cnt; i++) {
174 offset = ((base + i) * width);
175 data->tg_value |= (data->tg_sw << offset);
176 data->tg_mask |= GENMASK(offset + width - 1, offset);
179 /* Calculate key/action/counter offsets */
180 col = (count - col - 1);
181 data->key_offset = (base * vcap_is2->entry_width) / vcap_is2->sw_count;
182 data->counter_offset = (cnt * col * vcap_is2->counter_width);
184 width = vcap_is2->action_table[i].width;
185 cnt = vcap_is2->action_table[i].count;
186 data->action_offset =
187 (((cnt * col * width) / count) + vcap_is2->action_type_width);
190 static void vcap_data_set(u32 *data, u32 offset, u32 len, u32 value)
194 for (i = 0; i < len; i++, offset++) {
195 v = data[offset / ENTRY_WIDTH];
196 m = (1 << (offset % ENTRY_WIDTH));
197 if (value & (1 << i))
201 data[offset / ENTRY_WIDTH] = v;
205 static u32 vcap_data_get(u32 *data, u32 offset, u32 len)
207 u32 i, v, m, value = 0;
209 for (i = 0; i < len; i++, offset++) {
210 v = data[offset / ENTRY_WIDTH];
211 m = (1 << (offset % ENTRY_WIDTH));
218 static void vcap_key_field_set(struct vcap_data *data, u32 offset, u32 width,
221 vcap_data_set(data->entry, offset + data->key_offset, width, value);
222 vcap_data_set(data->mask, offset + data->key_offset, width, mask);
225 static void vcap_key_set(struct ocelot *ocelot, struct vcap_data *data,
226 enum vcap_is2_half_key_field field,
229 u32 offset = ocelot->vcap_is2_keys[field].offset;
230 u32 length = ocelot->vcap_is2_keys[field].length;
232 vcap_key_field_set(data, offset, length, value, mask);
235 static void vcap_key_bytes_set(struct ocelot *ocelot, struct vcap_data *data,
236 enum vcap_is2_half_key_field field,
239 u32 offset = ocelot->vcap_is2_keys[field].offset;
240 u32 count = ocelot->vcap_is2_keys[field].length;
241 u32 i, j, n = 0, value = 0, mask = 0;
245 /* Data wider than 32 bits are split up in chunks of maximum 32 bits.
246 * The 32 LSB of the data are written to the 32 MSB of the TCAM.
251 for (i = 0; i < count; i++) {
253 value += (val[j] << n);
254 mask += (msk[j] << n);
256 if (n == ENTRY_WIDTH || (i + 1) == count) {
258 vcap_key_field_set(data, offset, n, value, mask);
266 static void vcap_key_l4_port_set(struct ocelot *ocelot, struct vcap_data *data,
267 enum vcap_is2_half_key_field field,
268 struct ocelot_vcap_udp_tcp *port)
270 u32 offset = ocelot->vcap_is2_keys[field].offset;
271 u32 length = ocelot->vcap_is2_keys[field].length;
273 WARN_ON(length != 16);
275 vcap_key_field_set(data, offset, length, port->value, port->mask);
278 static void vcap_key_bit_set(struct ocelot *ocelot, struct vcap_data *data,
279 enum vcap_is2_half_key_field field,
280 enum ocelot_vcap_bit val)
282 u32 offset = ocelot->vcap_is2_keys[field].offset;
283 u32 length = ocelot->vcap_is2_keys[field].length;
284 u32 value = (val == OCELOT_VCAP_BIT_1 ? 1 : 0);
285 u32 msk = (val == OCELOT_VCAP_BIT_ANY ? 0 : 1);
287 WARN_ON(length != 1);
289 vcap_key_field_set(data, offset, length, value, msk);
292 static void vcap_action_set(struct ocelot *ocelot, struct vcap_data *data,
293 enum vcap_is2_action_field field, u32 value)
295 int offset = ocelot->vcap_is2_actions[field].offset;
296 int length = ocelot->vcap_is2_actions[field].length;
298 vcap_data_set(data->action, offset + data->action_offset, length,
302 static void is2_action_set(struct ocelot *ocelot, struct vcap_data *data,
303 struct ocelot_ace_rule *ace)
305 switch (ace->action) {
306 case OCELOT_ACL_ACTION_DROP:
307 vcap_action_set(ocelot, data, VCAP_IS2_ACT_PORT_MASK, 0);
308 vcap_action_set(ocelot, data, VCAP_IS2_ACT_MASK_MODE, 1);
309 vcap_action_set(ocelot, data, VCAP_IS2_ACT_POLICE_ENA, 1);
310 vcap_action_set(ocelot, data, VCAP_IS2_ACT_POLICE_IDX,
311 OCELOT_POLICER_DISCARD);
312 vcap_action_set(ocelot, data, VCAP_IS2_ACT_CPU_QU_NUM, 0);
313 vcap_action_set(ocelot, data, VCAP_IS2_ACT_CPU_COPY_ENA, 0);
315 case OCELOT_ACL_ACTION_TRAP:
316 vcap_action_set(ocelot, data, VCAP_IS2_ACT_PORT_MASK, 0);
317 vcap_action_set(ocelot, data, VCAP_IS2_ACT_MASK_MODE, 1);
318 vcap_action_set(ocelot, data, VCAP_IS2_ACT_POLICE_ENA, 0);
319 vcap_action_set(ocelot, data, VCAP_IS2_ACT_POLICE_IDX, 0);
320 vcap_action_set(ocelot, data, VCAP_IS2_ACT_CPU_QU_NUM, 0);
321 vcap_action_set(ocelot, data, VCAP_IS2_ACT_CPU_COPY_ENA, 1);
323 case OCELOT_ACL_ACTION_POLICE:
324 vcap_action_set(ocelot, data, VCAP_IS2_ACT_PORT_MASK, 0);
325 vcap_action_set(ocelot, data, VCAP_IS2_ACT_MASK_MODE, 0);
326 vcap_action_set(ocelot, data, VCAP_IS2_ACT_POLICE_ENA, 1);
327 vcap_action_set(ocelot, data, VCAP_IS2_ACT_POLICE_IDX,
329 vcap_action_set(ocelot, data, VCAP_IS2_ACT_CPU_QU_NUM, 0);
330 vcap_action_set(ocelot, data, VCAP_IS2_ACT_CPU_COPY_ENA, 0);
335 static void is2_entry_set(struct ocelot *ocelot, int ix,
336 struct ocelot_ace_rule *ace)
338 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2];
339 u32 val, msk, type, type_mask = 0xf, i, count;
340 struct ocelot_ace_vlan *tag = &ace->vlan;
341 struct ocelot_vcap_u64 payload;
342 struct vcap_data data;
345 memset(&payload, 0, sizeof(payload));
346 memset(&data, 0, sizeof(data));
349 vcap_row_cmd(ocelot, row, VCAP_CMD_READ, VCAP_SEL_ALL);
350 vcap_cache2entry(ocelot, &data);
351 vcap_cache2action(ocelot, &data);
353 data.tg_sw = VCAP_TG_HALF;
354 is2_data_get(ocelot, &data, ix);
355 data.tg = (data.tg & ~data.tg_mask);
357 data.tg |= data.tg_value;
359 data.type = IS2_ACTION_TYPE_NORMAL;
361 vcap_key_set(ocelot, &data, VCAP_IS2_HK_PAG, 0, 0);
362 vcap_key_set(ocelot, &data, VCAP_IS2_HK_IGR_PORT_MASK, 0,
363 ~ace->ingress_port_mask);
364 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_FIRST, OCELOT_VCAP_BIT_1);
365 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_HOST_MATCH,
366 OCELOT_VCAP_BIT_ANY);
367 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L2_MC, ace->dmac_mc);
368 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L2_BC, ace->dmac_bc);
369 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_VLAN_TAGGED, tag->tagged);
370 vcap_key_set(ocelot, &data, VCAP_IS2_HK_VID,
371 tag->vid.value, tag->vid.mask);
372 vcap_key_set(ocelot, &data, VCAP_IS2_HK_PCP,
373 tag->pcp.value[0], tag->pcp.mask[0]);
374 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_DEI, tag->dei);
377 case OCELOT_ACE_TYPE_ETYPE: {
378 struct ocelot_ace_frame_etype *etype = &ace->frame.etype;
380 type = IS2_TYPE_ETYPE;
381 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L2_DMAC,
382 etype->dmac.value, etype->dmac.mask);
383 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L2_SMAC,
384 etype->smac.value, etype->smac.mask);
385 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_MAC_ETYPE_ETYPE,
386 etype->etype.value, etype->etype.mask);
387 /* Clear unused bits */
388 vcap_key_set(ocelot, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0,
390 vcap_key_set(ocelot, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1,
392 vcap_key_set(ocelot, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2,
394 vcap_key_bytes_set(ocelot, &data,
395 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0,
396 etype->data.value, etype->data.mask);
399 case OCELOT_ACE_TYPE_LLC: {
400 struct ocelot_ace_frame_llc *llc = &ace->frame.llc;
403 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L2_DMAC,
404 llc->dmac.value, llc->dmac.mask);
405 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L2_SMAC,
406 llc->smac.value, llc->smac.mask);
407 for (i = 0; i < 4; i++) {
408 payload.value[i] = llc->llc.value[i];
409 payload.mask[i] = llc->llc.mask[i];
411 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_MAC_LLC_L2_LLC,
412 payload.value, payload.mask);
415 case OCELOT_ACE_TYPE_SNAP: {
416 struct ocelot_ace_frame_snap *snap = &ace->frame.snap;
418 type = IS2_TYPE_SNAP;
419 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L2_DMAC,
420 snap->dmac.value, snap->dmac.mask);
421 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L2_SMAC,
422 snap->smac.value, snap->smac.mask);
423 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_MAC_SNAP_L2_SNAP,
424 ace->frame.snap.snap.value,
425 ace->frame.snap.snap.mask);
428 case OCELOT_ACE_TYPE_ARP: {
429 struct ocelot_ace_frame_arp *arp = &ace->frame.arp;
432 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_MAC_ARP_SMAC,
433 arp->smac.value, arp->smac.mask);
434 vcap_key_bit_set(ocelot, &data,
435 VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK,
437 vcap_key_bit_set(ocelot, &data,
438 VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK,
440 vcap_key_bit_set(ocelot, &data,
441 VCAP_IS2_HK_MAC_ARP_LEN_OK,
443 vcap_key_bit_set(ocelot, &data,
444 VCAP_IS2_HK_MAC_ARP_TARGET_MATCH,
446 vcap_key_bit_set(ocelot, &data,
447 VCAP_IS2_HK_MAC_ARP_SENDER_MATCH,
449 vcap_key_bit_set(ocelot, &data,
450 VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN,
453 /* OPCODE is inverse, bit 0 is reply flag, bit 1 is RARP flag */
454 val = ((arp->req == OCELOT_VCAP_BIT_0 ? 1 : 0) |
455 (arp->arp == OCELOT_VCAP_BIT_0 ? 2 : 0));
456 msk = ((arp->req == OCELOT_VCAP_BIT_ANY ? 0 : 1) |
457 (arp->arp == OCELOT_VCAP_BIT_ANY ? 0 : 2));
458 vcap_key_set(ocelot, &data, VCAP_IS2_HK_MAC_ARP_OPCODE,
460 vcap_key_bytes_set(ocelot, &data,
461 VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP,
462 arp->dip.value.addr, arp->dip.mask.addr);
463 vcap_key_bytes_set(ocelot, &data,
464 VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP,
465 arp->sip.value.addr, arp->sip.mask.addr);
466 vcap_key_set(ocelot, &data, VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP,
470 case OCELOT_ACE_TYPE_IPV4:
471 case OCELOT_ACE_TYPE_IPV6: {
472 enum ocelot_vcap_bit sip_eq_dip, sport_eq_dport, seq_zero, tcp;
473 enum ocelot_vcap_bit ttl, fragment, options, tcp_ack, tcp_urg;
474 enum ocelot_vcap_bit tcp_fin, tcp_syn, tcp_rst, tcp_psh;
475 struct ocelot_ace_frame_ipv4 *ipv4 = NULL;
476 struct ocelot_ace_frame_ipv6 *ipv6 = NULL;
477 struct ocelot_vcap_udp_tcp *sport, *dport;
478 struct ocelot_vcap_ipv4 sip, dip;
479 struct ocelot_vcap_u8 proto, ds;
480 struct ocelot_vcap_u48 *ip_data;
482 if (ace->type == OCELOT_ACE_TYPE_IPV4) {
483 ipv4 = &ace->frame.ipv4;
485 fragment = ipv4->fragment;
486 options = ipv4->options;
489 ip_data = &ipv4->data;
492 sport = &ipv4->sport;
493 dport = &ipv4->dport;
494 tcp_fin = ipv4->tcp_fin;
495 tcp_syn = ipv4->tcp_syn;
496 tcp_rst = ipv4->tcp_rst;
497 tcp_psh = ipv4->tcp_psh;
498 tcp_ack = ipv4->tcp_ack;
499 tcp_urg = ipv4->tcp_urg;
500 sip_eq_dip = ipv4->sip_eq_dip;
501 sport_eq_dport = ipv4->sport_eq_dport;
502 seq_zero = ipv4->seq_zero;
504 ipv6 = &ace->frame.ipv6;
506 fragment = OCELOT_VCAP_BIT_ANY;
507 options = OCELOT_VCAP_BIT_ANY;
510 ip_data = &ipv6->data;
511 for (i = 0; i < 8; i++) {
512 val = ipv6->sip.value[i + 8];
513 msk = ipv6->sip.mask[i + 8];
515 dip.value.addr[i] = val;
516 dip.mask.addr[i] = msk;
518 sip.value.addr[i - 4] = val;
519 sip.mask.addr[i - 4] = msk;
522 sport = &ipv6->sport;
523 dport = &ipv6->dport;
524 tcp_fin = ipv6->tcp_fin;
525 tcp_syn = ipv6->tcp_syn;
526 tcp_rst = ipv6->tcp_rst;
527 tcp_psh = ipv6->tcp_psh;
528 tcp_ack = ipv6->tcp_ack;
529 tcp_urg = ipv6->tcp_urg;
530 sip_eq_dip = ipv6->sip_eq_dip;
531 sport_eq_dport = ipv6->sport_eq_dport;
532 seq_zero = ipv6->seq_zero;
535 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_IP4,
536 ipv4 ? OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0);
537 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L3_FRAGMENT,
539 vcap_key_set(ocelot, &data, VCAP_IS2_HK_L3_FRAG_OFS_GT0, 0, 0);
540 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L3_OPTIONS,
542 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_IP4_L3_TTL_GT0,
544 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L3_TOS,
546 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L3_IP4_DIP,
547 dip.value.addr, dip.mask.addr);
548 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L3_IP4_SIP,
549 sip.value.addr, sip.mask.addr);
550 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_DIP_EQ_SIP,
552 val = proto.value[0];
554 type = IS2_TYPE_IP_UDP_TCP;
555 if (msk == 0xff && (val == 6 || val == 17)) {
556 /* UDP/TCP protocol match */
558 OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0);
559 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_TCP, tcp);
560 vcap_key_l4_port_set(ocelot, &data,
561 VCAP_IS2_HK_L4_DPORT, dport);
562 vcap_key_l4_port_set(ocelot, &data,
563 VCAP_IS2_HK_L4_SPORT, sport);
564 vcap_key_set(ocelot, &data, VCAP_IS2_HK_L4_RNG, 0, 0);
565 vcap_key_bit_set(ocelot, &data,
566 VCAP_IS2_HK_L4_SPORT_EQ_DPORT,
568 vcap_key_bit_set(ocelot, &data,
569 VCAP_IS2_HK_L4_SEQUENCE_EQ0,
571 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L4_FIN,
573 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L4_SYN,
575 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L4_RST,
577 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L4_PSH,
579 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L4_ACK,
581 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L4_URG,
583 vcap_key_set(ocelot, &data, VCAP_IS2_HK_L4_1588_DOM,
585 vcap_key_set(ocelot, &data, VCAP_IS2_HK_L4_1588_VER,
589 /* Any IP protocol match */
590 type_mask = IS2_TYPE_MASK_IP_ANY;
592 /* Non-UDP/TCP protocol match */
593 type = IS2_TYPE_IP_OTHER;
594 for (i = 0; i < 6; i++) {
595 payload.value[i] = ip_data->value[i];
596 payload.mask[i] = ip_data->mask[i];
599 vcap_key_bytes_set(ocelot, &data,
600 VCAP_IS2_HK_IP4_L3_PROTO,
601 proto.value, proto.mask);
602 vcap_key_bytes_set(ocelot, &data,
603 VCAP_IS2_HK_L3_PAYLOAD,
604 payload.value, payload.mask);
608 case OCELOT_ACE_TYPE_ANY:
612 count = vcap_is2->entry_width / 2;
613 /* Iterate over the non-common part of the key and
616 for (i = ocelot->vcap_is2_keys[VCAP_IS2_HK_L2_DMAC].offset;
617 i < count; i += ENTRY_WIDTH) {
618 vcap_key_field_set(&data, i, min(32u, count - i), 0, 0);
623 vcap_key_set(ocelot, &data, VCAP_IS2_TYPE, type, type_mask);
624 is2_action_set(ocelot, &data, ace);
625 vcap_data_set(data.counter, data.counter_offset,
626 vcap_is2->counter_width, ace->stats.pkts);
629 vcap_entry2cache(ocelot, &data);
630 vcap_action2cache(ocelot, &data);
631 vcap_row_cmd(ocelot, row, VCAP_CMD_WRITE, VCAP_SEL_ALL);
634 static void is2_entry_get(struct ocelot *ocelot, struct ocelot_ace_rule *rule,
637 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2];
638 struct vcap_data data;
642 vcap_row_cmd(ocelot, row, VCAP_CMD_READ, VCAP_SEL_COUNTER);
643 vcap_cache2action(ocelot, &data);
644 data.tg_sw = VCAP_TG_HALF;
645 is2_data_get(ocelot, &data, ix);
646 cnt = vcap_data_get(data.counter, data.counter_offset,
647 vcap_is2->counter_width);
649 rule->stats.pkts = cnt;
652 static void ocelot_ace_rule_add(struct ocelot *ocelot,
653 struct ocelot_acl_block *block,
654 struct ocelot_ace_rule *rule)
656 struct ocelot_ace_rule *tmp;
657 struct list_head *pos, *n;
659 if (rule->action == OCELOT_ACL_ACTION_POLICE) {
661 rule->pol_ix = block->pol_lpr;
662 ocelot_ace_policer_add(ocelot, rule->pol_ix, &rule->pol);
667 if (list_empty(&block->rules)) {
668 list_add(&rule->list, &block->rules);
672 list_for_each_safe(pos, n, &block->rules) {
673 tmp = list_entry(pos, struct ocelot_ace_rule, list);
674 if (rule->prio < tmp->prio)
677 list_add(&rule->list, pos->prev);
680 static int ocelot_ace_rule_get_index_id(struct ocelot_acl_block *block,
681 struct ocelot_ace_rule *rule)
683 struct ocelot_ace_rule *tmp;
686 list_for_each_entry(tmp, &block->rules, list) {
688 if (rule->id == tmp->id)
694 static struct ocelot_ace_rule*
695 ocelot_ace_rule_get_rule_index(struct ocelot_acl_block *block, int index)
697 struct ocelot_ace_rule *tmp;
700 list_for_each_entry(tmp, &block->rules, list) {
709 int ocelot_ace_rule_offload_add(struct ocelot *ocelot,
710 struct ocelot_ace_rule *rule)
712 struct ocelot_acl_block *block = &ocelot->acl_block;
713 struct ocelot_ace_rule *ace;
716 /* Add rule to the linked list */
717 ocelot_ace_rule_add(ocelot, block, rule);
719 /* Get the index of the inserted rule */
720 index = ocelot_ace_rule_get_index_id(block, rule);
722 /* Move down the rules to make place for the new rule */
723 for (i = block->count - 1; i > index; i--) {
724 ace = ocelot_ace_rule_get_rule_index(block, i);
725 is2_entry_set(ocelot, i, ace);
728 /* Now insert the new rule */
729 is2_entry_set(ocelot, index, rule);
733 static void ocelot_ace_police_del(struct ocelot *ocelot,
734 struct ocelot_acl_block *block,
737 struct ocelot_ace_rule *ace;
740 if (ix < block->pol_lpr)
743 list_for_each_entry(ace, &block->rules, list) {
745 if (ace->action == OCELOT_ACL_ACTION_POLICE &&
748 ocelot_ace_policer_add(ocelot, ace->pol_ix,
750 is2_entry_set(ocelot, index, ace);
754 ocelot_ace_policer_del(ocelot, block->pol_lpr);
758 static void ocelot_ace_rule_del(struct ocelot *ocelot,
759 struct ocelot_acl_block *block,
760 struct ocelot_ace_rule *rule)
762 struct ocelot_ace_rule *tmp;
763 struct list_head *pos, *q;
765 list_for_each_safe(pos, q, &block->rules) {
766 tmp = list_entry(pos, struct ocelot_ace_rule, list);
767 if (tmp->id == rule->id) {
768 if (tmp->action == OCELOT_ACL_ACTION_POLICE)
769 ocelot_ace_police_del(ocelot, block,
780 int ocelot_ace_rule_offload_del(struct ocelot *ocelot,
781 struct ocelot_ace_rule *rule)
783 struct ocelot_acl_block *block = &ocelot->acl_block;
784 struct ocelot_ace_rule del_ace;
785 struct ocelot_ace_rule *ace;
788 memset(&del_ace, 0, sizeof(del_ace));
790 /* Gets index of the rule */
791 index = ocelot_ace_rule_get_index_id(block, rule);
794 ocelot_ace_rule_del(ocelot, block, rule);
796 /* Move up all the blocks over the deleted rule */
797 for (i = index; i < block->count; i++) {
798 ace = ocelot_ace_rule_get_rule_index(block, i);
799 is2_entry_set(ocelot, i, ace);
802 /* Now delete the last rule, because it is duplicated */
803 is2_entry_set(ocelot, block->count, &del_ace);
808 int ocelot_ace_rule_stats_update(struct ocelot *ocelot,
809 struct ocelot_ace_rule *rule)
811 struct ocelot_acl_block *block = &ocelot->acl_block;
812 struct ocelot_ace_rule *tmp;
815 index = ocelot_ace_rule_get_index_id(block, rule);
816 is2_entry_get(ocelot, rule, index);
818 /* After we get the result we need to clear the counters */
819 tmp = ocelot_ace_rule_get_rule_index(block, index);
821 is2_entry_set(ocelot, index, tmp);
826 int ocelot_ace_init(struct ocelot *ocelot)
828 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2];
829 struct ocelot_acl_block *block = &ocelot->acl_block;
830 struct vcap_data data;
832 memset(&data, 0, sizeof(data));
834 vcap_entry2cache(ocelot, &data);
835 ocelot_write(ocelot, vcap_is2->entry_count, S2_CORE_MV_CFG);
836 vcap_cmd(ocelot, 0, VCAP_CMD_INITIALIZE, VCAP_SEL_ENTRY);
838 vcap_action2cache(ocelot, &data);
839 ocelot_write(ocelot, vcap_is2->action_count, S2_CORE_MV_CFG);
840 vcap_cmd(ocelot, 0, VCAP_CMD_INITIALIZE,
841 VCAP_SEL_ACTION | VCAP_SEL_COUNTER);
843 /* Create a policer that will drop the frames for the cpu.
844 * This policer will be used as action in the acl rules to drop
847 ocelot_write_gix(ocelot, 0x299, ANA_POL_MODE_CFG,
848 OCELOT_POLICER_DISCARD);
849 ocelot_write_gix(ocelot, 0x1, ANA_POL_PIR_CFG,
850 OCELOT_POLICER_DISCARD);
851 ocelot_write_gix(ocelot, 0x3fffff, ANA_POL_PIR_STATE,
852 OCELOT_POLICER_DISCARD);
853 ocelot_write_gix(ocelot, 0x0, ANA_POL_CIR_CFG,
854 OCELOT_POLICER_DISCARD);
855 ocelot_write_gix(ocelot, 0x3fffff, ANA_POL_CIR_STATE,
856 OCELOT_POLICER_DISCARD);
858 block->pol_lpr = OCELOT_POLICER_DISCARD - 1;
860 INIT_LIST_HEAD(&ocelot->acl_block.rules);