1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/etherdevice.h>
8 #include <linux/ethtool.h>
9 #include <linux/if_bridge.h>
10 #include <linux/if_ether.h>
11 #include <linux/if_vlan.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
17 #include <linux/skbuff.h>
18 #include <linux/iopoll.h>
20 #include <net/netevent.h>
21 #include <net/rtnetlink.h>
22 #include <net/switchdev.h>
26 #define TABLE_UPDATE_SLEEP_US 10
27 #define TABLE_UPDATE_TIMEOUT_US 100000
29 /* MAC table entry types.
30 * ENTRYTYPE_NORMAL is subject to aging.
31 * ENTRYTYPE_LOCKED is not subject to aging.
32 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
33 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
35 enum macaccess_entry_type {
42 struct ocelot_mact_entry {
45 enum macaccess_entry_type type;
48 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
50 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
53 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
57 return readx_poll_timeout(ocelot_mact_read_macaccess,
59 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
61 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
64 static void ocelot_mact_select(struct ocelot *ocelot,
65 const unsigned char mac[ETH_ALEN],
68 u32 macl = 0, mach = 0;
70 /* Set the MAC address to handle and the vlan associated in a format
71 * understood by the hardware.
81 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
82 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
86 static int ocelot_mact_learn(struct ocelot *ocelot, int port,
87 const unsigned char mac[ETH_ALEN],
89 enum macaccess_entry_type type)
91 ocelot_mact_select(ocelot, mac, vid);
93 /* Issue a write command */
94 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
95 ANA_TABLES_MACACCESS_DEST_IDX(port) |
96 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
97 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
98 ANA_TABLES_MACACCESS);
100 return ocelot_mact_wait_for_completion(ocelot);
103 static int ocelot_mact_forget(struct ocelot *ocelot,
104 const unsigned char mac[ETH_ALEN],
107 ocelot_mact_select(ocelot, mac, vid);
109 /* Issue a forget command */
111 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
112 ANA_TABLES_MACACCESS);
114 return ocelot_mact_wait_for_completion(ocelot);
117 static void ocelot_mact_init(struct ocelot *ocelot)
119 /* Configure the learning mode entries attributes:
120 * - Do not copy the frame to the CPU extraction queues.
121 * - Use the vlan and mac_cpoy for dmac lookup.
123 ocelot_rmw(ocelot, 0,
124 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
125 | ANA_AGENCTRL_LEARN_FWD_KILL
126 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
129 /* Clear the MAC table */
130 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
133 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
135 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
138 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
142 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
145 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
146 ANA_TABLES_VLANACCESS_CMD_IDLE,
147 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
150 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
152 /* Select the VID to configure */
153 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
154 ANA_TABLES_VLANTIDX);
155 /* Set the vlan port members mask and issue a write command */
156 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
157 ANA_TABLES_VLANACCESS_CMD_WRITE,
158 ANA_TABLES_VLANACCESS);
160 return ocelot_vlant_wait_for_completion(ocelot);
163 static void ocelot_vlan_mode(struct ocelot_port *port,
164 netdev_features_t features)
166 struct ocelot *ocelot = port->ocelot;
167 u8 p = port->chip_port;
171 val = ocelot_read(ocelot, ANA_VLANMASK);
172 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
176 ocelot_write(ocelot, val, ANA_VLANMASK);
179 static void ocelot_vlan_port_apply(struct ocelot *ocelot,
180 struct ocelot_port *port)
184 /* Ingress clasification (ANA_PORT_VLAN_CFG) */
185 /* Default vlan to clasify for untagged frames (may be zero) */
186 val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid);
187 if (port->vlan_aware)
188 val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
189 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
191 ocelot_rmw_gix(ocelot, val,
192 ANA_PORT_VLAN_CFG_VLAN_VID_M |
193 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
194 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
195 ANA_PORT_VLAN_CFG, port->chip_port);
197 /* Drop frames with multicast source address */
198 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA;
199 if (port->vlan_aware && !port->vid)
200 /* If port is vlan-aware and tagged, drop untagged and priority
203 val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
204 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
205 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
206 ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port);
208 /* Egress configuration (REW_TAG_CFG): VLAN tag type to 8021Q. */
209 val = REW_TAG_CFG_TAG_TPID_CFG(0);
211 if (port->vlan_aware) {
213 /* Tag all frames except when VID == DEFAULT_VLAN */
214 val |= REW_TAG_CFG_TAG_CFG(1);
217 val |= REW_TAG_CFG_TAG_CFG(3);
219 ocelot_rmw_gix(ocelot, val,
220 REW_TAG_CFG_TAG_TPID_CFG_M |
221 REW_TAG_CFG_TAG_CFG_M,
222 REW_TAG_CFG, port->chip_port);
224 /* Set default VLAN and tag type to 8021Q. */
225 val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) |
226 REW_PORT_VLAN_CFG_PORT_VID(port->vid);
227 ocelot_rmw_gix(ocelot, val,
228 REW_PORT_VLAN_CFG_PORT_TPID_M |
229 REW_PORT_VLAN_CFG_PORT_VID_M,
230 REW_PORT_VLAN_CFG, port->chip_port);
233 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid,
236 struct ocelot_port *port = netdev_priv(dev);
237 struct ocelot *ocelot = port->ocelot;
240 /* Add the port MAC address to with the right VLAN information */
241 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid,
244 /* Make the port a member of the VLAN */
245 ocelot->vlan_mask[vid] |= BIT(port->chip_port);
246 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
250 /* Default ingress vlan classification */
254 /* Untagged egress vlan clasification */
258 ocelot_vlan_port_apply(ocelot, port);
263 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid)
265 struct ocelot_port *port = netdev_priv(dev);
266 struct ocelot *ocelot = port->ocelot;
269 /* 8021q removes VID 0 on module unload for all interfaces
270 * with VLAN filtering feature. We need to keep it to receive
276 /* Del the port MAC address to with the right VLAN information */
277 ocelot_mact_forget(ocelot, dev->dev_addr, vid);
279 /* Stop the port from being a member of the vlan */
280 ocelot->vlan_mask[vid] &= ~BIT(port->chip_port);
281 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
286 if (port->pvid == vid)
290 if (port->vid == vid)
293 ocelot_vlan_port_apply(ocelot, port);
298 static void ocelot_vlan_init(struct ocelot *ocelot)
302 /* Clear VLAN table, by default all ports are members of all VLANs */
303 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
304 ANA_TABLES_VLANACCESS);
305 ocelot_vlant_wait_for_completion(ocelot);
307 /* Configure the port VLAN memberships */
308 for (vid = 1; vid < VLAN_N_VID; vid++) {
309 ocelot->vlan_mask[vid] = 0;
310 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
313 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
314 * traffic. It is added automatically if 8021q module is loaded, but
315 * we can't rely on it since module may be not loaded.
317 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
318 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
320 /* Configure the CPU port to be VLAN aware */
321 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
322 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
323 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
324 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports);
326 /* Set vlan ingress filter mask to all ports but the CPU port by
329 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK);
331 for (port = 0; port < ocelot->num_phys_ports; port++) {
332 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
333 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
338 * Bit 8: Unit; 0:1, 1:16
339 * Bit 7-0: Value to be multiplied with unit
341 static u16 ocelot_wm_enc(u16 value)
344 return BIT(8) | (value / 16);
349 static void ocelot_port_adjust_link(struct net_device *dev)
351 struct ocelot_port *port = netdev_priv(dev);
352 struct ocelot *ocelot = port->ocelot;
353 u8 p = port->chip_port;
354 int speed, atop_wm, mode = 0;
356 switch (dev->phydev->speed) {
358 speed = OCELOT_SPEED_10;
361 speed = OCELOT_SPEED_100;
364 speed = OCELOT_SPEED_1000;
365 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
368 speed = OCELOT_SPEED_2500;
369 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
372 netdev_err(dev, "Unsupported PHY speed: %d\n",
377 phy_print_status(dev->phydev);
379 if (!dev->phydev->link)
382 /* Only full duplex supported for now */
383 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA |
384 mode, DEV_MAC_MODE_CFG);
387 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
388 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
390 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG);
392 /* Load seed (0) and set MAC HDX late collision */
393 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
394 DEV_MAC_HDX_CFG_SEED_LOAD,
397 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
400 /* Disable HDX fast control */
401 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC);
403 /* SGMII only for now */
404 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG);
405 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
408 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
410 /* No aneg on SGMII */
411 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG);
414 ocelot_port_writel(port, 0, PCS1G_LB_CFG);
416 /* Set Max Length and maximum tags allowed */
417 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG);
418 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
419 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
420 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
423 /* Enable MAC module */
424 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA |
425 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
427 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
429 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed),
432 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
433 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
434 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG);
437 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
440 /* Set Pause WM hysteresis
441 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
442 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
444 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
445 SYS_PAUSE_CFG_PAUSE_STOP(101) |
446 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p);
448 /* Core: Enable port for frame transfer */
449 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
450 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
451 QSYS_SWITCH_PORT_MODE_PORT_ENA,
452 QSYS_SWITCH_PORT_MODE, p);
455 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
456 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
457 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
458 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
459 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
461 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p);
463 /* Tail dropping watermark */
464 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
465 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
467 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
470 static int ocelot_port_open(struct net_device *dev)
472 struct ocelot_port *port = netdev_priv(dev);
473 struct ocelot *ocelot = port->ocelot;
476 /* Enable receiving frames on the port, and activate auto-learning of
479 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
480 ANA_PORT_PORT_CFG_RECV_ENA |
481 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port),
482 ANA_PORT_PORT_CFG, port->chip_port);
485 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET,
488 netdev_err(dev, "Could not set mode of SerDes\n");
493 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link,
496 netdev_err(dev, "Could not attach to PHY\n");
500 dev->phydev = port->phy;
502 phy_attached_info(port->phy);
503 phy_start(port->phy);
507 static int ocelot_port_stop(struct net_device *dev)
509 struct ocelot_port *port = netdev_priv(dev);
511 phy_disconnect(port->phy);
515 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG);
516 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,
517 QSYS_SWITCH_PORT_MODE, port->chip_port);
521 /* Generate the IFH for frame injection
523 * The IFH is a 128bit-value
524 * bit 127: bypass the analyzer processing
525 * bit 56-67: destination mask
526 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
527 * bit 20-27: cpu extraction queue mask
528 * bit 16: tag type 0: C-tag, 1: S-tag
531 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info)
533 ifh[0] = IFH_INJ_BYPASS;
534 ifh[1] = (0xf00 & info->port) >> 8;
535 ifh[2] = (0xff & info->port) << 24;
536 ifh[3] = (info->tag_type << 16) | info->vid;
541 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev)
543 struct ocelot_port *port = netdev_priv(dev);
544 struct ocelot *ocelot = port->ocelot;
545 u32 val, ifh[IFH_LEN];
546 struct frame_info info = {};
547 u8 grp = 0; /* Send everything on CPU group 0 */
548 unsigned int i, count, last;
550 val = ocelot_read(ocelot, QS_INJ_STATUS);
551 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) ||
552 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))))
553 return NETDEV_TX_BUSY;
555 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
556 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
558 info.port = BIT(port->chip_port);
559 info.tag_type = IFH_TAG_TYPE_C;
560 info.vid = skb_vlan_tag_get(skb);
561 ocelot_gen_ifh(ifh, &info);
563 for (i = 0; i < IFH_LEN; i++)
564 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]),
567 count = (skb->len + 3) / 4;
569 for (i = 0; i < count; i++) {
570 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
574 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
575 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
579 /* Indicate EOF and valid bytes in last word */
580 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
581 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
586 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
587 skb_tx_timestamp(skb);
589 dev->stats.tx_packets++;
590 dev->stats.tx_bytes += skb->len;
591 dev_kfree_skb_any(skb);
596 static void ocelot_mact_mc_reset(struct ocelot_port *port)
598 struct ocelot *ocelot = port->ocelot;
599 struct netdev_hw_addr *ha, *n;
601 /* Free and forget all the MAC addresses stored in the port private mc
602 * list. These are mc addresses that were previously added by calling
603 * ocelot_mact_mc_add().
605 list_for_each_entry_safe(ha, n, &port->mc, list) {
606 ocelot_mact_forget(ocelot, ha->addr, port->pvid);
612 static int ocelot_mact_mc_add(struct ocelot_port *port,
613 struct netdev_hw_addr *hw_addr)
615 struct ocelot *ocelot = port->ocelot;
616 struct netdev_hw_addr *ha = kzalloc(sizeof(*ha), GFP_ATOMIC);
621 memcpy(ha, hw_addr, sizeof(*ha));
622 list_add_tail(&ha->list, &port->mc);
624 ocelot_mact_learn(ocelot, PGID_CPU, ha->addr, port->pvid,
630 static void ocelot_set_rx_mode(struct net_device *dev)
632 struct ocelot_port *port = netdev_priv(dev);
633 struct ocelot *ocelot = port->ocelot;
634 struct netdev_hw_addr *ha;
638 /* This doesn't handle promiscuous mode because the bridge core is
639 * setting IFF_PROMISC on all slave interfaces and all frames would be
640 * forwarded to the CPU port.
642 val = GENMASK(ocelot->num_phys_ports - 1, 0);
643 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++)
644 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
646 /* Handle the device multicast addresses. First remove all the
647 * previously installed addresses and then add the latest ones to the
650 ocelot_mact_mc_reset(port);
651 netdev_for_each_mc_addr(ha, dev)
652 ocelot_mact_mc_add(port, ha);
655 static int ocelot_port_get_phys_port_name(struct net_device *dev,
656 char *buf, size_t len)
658 struct ocelot_port *port = netdev_priv(dev);
661 ret = snprintf(buf, len, "p%d", port->chip_port);
668 static int ocelot_port_set_mac_address(struct net_device *dev, void *p)
670 struct ocelot_port *port = netdev_priv(dev);
671 struct ocelot *ocelot = port->ocelot;
672 const struct sockaddr *addr = p;
674 /* Learn the new net device MAC address in the mac table. */
675 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid,
677 /* Then forget the previous one. */
678 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid);
680 ether_addr_copy(dev->dev_addr, addr->sa_data);
684 static void ocelot_get_stats64(struct net_device *dev,
685 struct rtnl_link_stats64 *stats)
687 struct ocelot_port *port = netdev_priv(dev);
688 struct ocelot *ocelot = port->ocelot;
690 /* Configure the port to read the stats from */
691 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port),
695 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS);
696 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) +
697 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) +
698 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) +
699 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) +
700 ocelot_read(ocelot, SYS_COUNT_RX_64) +
701 ocelot_read(ocelot, SYS_COUNT_RX_65_127) +
702 ocelot_read(ocelot, SYS_COUNT_RX_128_255) +
703 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) +
704 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) +
705 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX);
706 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST);
707 stats->rx_dropped = dev->stats.rx_dropped;
710 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS);
711 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) +
712 ocelot_read(ocelot, SYS_COUNT_TX_65_127) +
713 ocelot_read(ocelot, SYS_COUNT_TX_128_511) +
714 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) +
715 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) +
716 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX);
717 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) +
718 ocelot_read(ocelot, SYS_COUNT_TX_AGING);
719 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION);
722 static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
723 struct net_device *dev, const unsigned char *addr,
725 struct netlink_ext_ack *extack)
727 struct ocelot_port *port = netdev_priv(dev);
728 struct ocelot *ocelot = port->ocelot;
731 if (!port->vlan_aware)
732 /* If the bridge is not VLAN aware and no VID was
733 * provided, set it to pvid to ensure the MAC entry
734 * matches incoming untagged packets
738 /* If the bridge is VLAN aware a VID must be provided as
739 * otherwise the learnt entry wouldn't match any frame.
744 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid,
748 static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
749 struct net_device *dev,
750 const unsigned char *addr, u16 vid)
752 struct ocelot_port *port = netdev_priv(dev);
753 struct ocelot *ocelot = port->ocelot;
755 return ocelot_mact_forget(ocelot, addr, vid);
758 struct ocelot_dump_ctx {
759 struct net_device *dev;
761 struct netlink_callback *cb;
765 static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry,
766 struct ocelot_dump_ctx *dump)
768 u32 portid = NETLINK_CB(dump->cb->skb).portid;
769 u32 seq = dump->cb->nlh->nlmsg_seq;
770 struct nlmsghdr *nlh;
773 if (dump->idx < dump->cb->args[2])
776 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
777 sizeof(*ndm), NLM_F_MULTI);
781 ndm = nlmsg_data(nlh);
782 ndm->ndm_family = AF_BRIDGE;
785 ndm->ndm_flags = NTF_SELF;
787 ndm->ndm_ifindex = dump->dev->ifindex;
788 ndm->ndm_state = NUD_REACHABLE;
790 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac))
791 goto nla_put_failure;
793 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid))
794 goto nla_put_failure;
796 nlmsg_end(dump->skb, nlh);
803 nlmsg_cancel(dump->skb, nlh);
807 static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col,
808 struct ocelot_mact_entry *entry)
810 struct ocelot *ocelot = port->ocelot;
812 u32 val, dst, macl, mach;
814 /* Set row and column to read from */
815 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
816 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
818 /* Issue a read command */
820 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
821 ANA_TABLES_MACACCESS);
823 if (ocelot_mact_wait_for_completion(ocelot))
826 /* Read the entry flags */
827 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
828 if (!(val & ANA_TABLES_MACACCESS_VALID))
831 /* If the entry read has another port configured as its destination,
834 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
835 if (dst != port->chip_port)
838 /* Get the entry's MAC address and VLAN id */
839 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
840 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
842 mac[0] = (mach >> 8) & 0xff;
843 mac[1] = (mach >> 0) & 0xff;
844 mac[2] = (macl >> 24) & 0xff;
845 mac[3] = (macl >> 16) & 0xff;
846 mac[4] = (macl >> 8) & 0xff;
847 mac[5] = (macl >> 0) & 0xff;
849 entry->vid = (mach >> 16) & 0xfff;
850 ether_addr_copy(entry->mac, mac);
855 static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb,
856 struct net_device *dev,
857 struct net_device *filter_dev, int *idx)
859 struct ocelot_port *port = netdev_priv(dev);
861 struct ocelot_dump_ctx dump = {
868 struct ocelot_mact_entry entry;
870 /* Loop through all the mac tables entries. There are 1024 rows of 4
873 for (i = 0; i < 1024; i++) {
874 for (j = 0; j < 4; j++) {
875 ret = ocelot_mact_read(port, i, j, &entry);
876 /* If the entry is invalid (wrong port, invalid...),
884 ret = ocelot_fdb_do_dump(&entry, &dump);
895 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto,
898 return ocelot_vlan_vid_add(dev, vid, false, true);
901 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto,
904 return ocelot_vlan_vid_del(dev, vid);
907 static int ocelot_set_features(struct net_device *dev,
908 netdev_features_t features)
910 struct ocelot_port *port = netdev_priv(dev);
911 netdev_features_t changed = dev->features ^ features;
913 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER)
914 ocelot_vlan_mode(port, features);
919 static int ocelot_get_port_parent_id(struct net_device *dev,
920 struct netdev_phys_item_id *ppid)
922 struct ocelot_port *ocelot_port = netdev_priv(dev);
923 struct ocelot *ocelot = ocelot_port->ocelot;
925 ppid->id_len = sizeof(ocelot->base_mac);
926 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len);
931 static const struct net_device_ops ocelot_port_netdev_ops = {
932 .ndo_open = ocelot_port_open,
933 .ndo_stop = ocelot_port_stop,
934 .ndo_start_xmit = ocelot_port_xmit,
935 .ndo_set_rx_mode = ocelot_set_rx_mode,
936 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name,
937 .ndo_set_mac_address = ocelot_port_set_mac_address,
938 .ndo_get_stats64 = ocelot_get_stats64,
939 .ndo_fdb_add = ocelot_fdb_add,
940 .ndo_fdb_del = ocelot_fdb_del,
941 .ndo_fdb_dump = ocelot_fdb_dump,
942 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid,
943 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid,
944 .ndo_set_features = ocelot_set_features,
945 .ndo_get_port_parent_id = ocelot_get_port_parent_id,
948 static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data)
950 struct ocelot_port *port = netdev_priv(netdev);
951 struct ocelot *ocelot = port->ocelot;
954 if (sset != ETH_SS_STATS)
957 for (i = 0; i < ocelot->num_stats; i++)
958 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
962 static void ocelot_update_stats(struct ocelot *ocelot)
966 mutex_lock(&ocelot->stats_lock);
968 for (i = 0; i < ocelot->num_phys_ports; i++) {
969 /* Configure the port to read the stats from */
970 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
972 for (j = 0; j < ocelot->num_stats; j++) {
974 unsigned int idx = i * ocelot->num_stats + j;
976 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
977 ocelot->stats_layout[j].offset);
979 if (val < (ocelot->stats[idx] & U32_MAX))
980 ocelot->stats[idx] += (u64)1 << 32;
982 ocelot->stats[idx] = (ocelot->stats[idx] &
983 ~(u64)U32_MAX) + val;
987 mutex_unlock(&ocelot->stats_lock);
990 static void ocelot_check_stats_work(struct work_struct *work)
992 struct delayed_work *del_work = to_delayed_work(work);
993 struct ocelot *ocelot = container_of(del_work, struct ocelot,
996 ocelot_update_stats(ocelot);
998 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
999 OCELOT_STATS_CHECK_DELAY);
1002 static void ocelot_get_ethtool_stats(struct net_device *dev,
1003 struct ethtool_stats *stats, u64 *data)
1005 struct ocelot_port *port = netdev_priv(dev);
1006 struct ocelot *ocelot = port->ocelot;
1009 /* check and update now */
1010 ocelot_update_stats(ocelot);
1012 /* Copy all counters */
1013 for (i = 0; i < ocelot->num_stats; i++)
1014 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i];
1017 static int ocelot_get_sset_count(struct net_device *dev, int sset)
1019 struct ocelot_port *port = netdev_priv(dev);
1020 struct ocelot *ocelot = port->ocelot;
1022 if (sset != ETH_SS_STATS)
1024 return ocelot->num_stats;
1027 static const struct ethtool_ops ocelot_ethtool_ops = {
1028 .get_strings = ocelot_get_strings,
1029 .get_ethtool_stats = ocelot_get_ethtool_stats,
1030 .get_sset_count = ocelot_get_sset_count,
1031 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1032 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1035 static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port,
1036 struct switchdev_trans *trans,
1039 struct ocelot *ocelot = ocelot_port->ocelot;
1043 if (switchdev_trans_ph_prepare(trans))
1046 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask))
1049 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG,
1050 ocelot_port->chip_port);
1053 case BR_STATE_FORWARDING:
1054 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port);
1056 case BR_STATE_LEARNING:
1057 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1061 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1062 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port);
1066 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG,
1067 ocelot_port->chip_port);
1069 /* Apply FWD mask. The loop is needed to add/remove the current port as
1070 * a source for the other ports.
1072 for (port = 0; port < ocelot->num_phys_ports; port++) {
1073 if (ocelot->bridge_fwd_mask & BIT(port)) {
1074 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port);
1076 for (i = 0; i < ocelot->num_phys_ports; i++) {
1077 unsigned long bond_mask = ocelot->lags[i];
1082 if (bond_mask & BIT(port)) {
1088 ocelot_write_rix(ocelot,
1089 BIT(ocelot->num_phys_ports) | mask,
1090 ANA_PGID_PGID, PGID_SRC + port);
1092 /* Only the CPU port, this is compatible with link
1095 ocelot_write_rix(ocelot,
1096 BIT(ocelot->num_phys_ports),
1097 ANA_PGID_PGID, PGID_SRC + port);
1104 static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port,
1105 unsigned long ageing_clock_t)
1107 struct ocelot *ocelot = ocelot_port->ocelot;
1108 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t);
1109 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000;
1111 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2),
1115 static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc)
1117 struct ocelot *ocelot = port->ocelot;
1118 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG,
1122 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1123 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1124 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
1126 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1127 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1128 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA);
1130 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port);
1133 static int ocelot_port_attr_set(struct net_device *dev,
1134 const struct switchdev_attr *attr,
1135 struct switchdev_trans *trans)
1137 struct ocelot_port *ocelot_port = netdev_priv(dev);
1141 case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
1142 ocelot_port_attr_stp_state_set(ocelot_port, trans,
1145 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
1146 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time);
1148 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
1149 ocelot_port->vlan_aware = attr->u.vlan_filtering;
1150 ocelot_vlan_port_apply(ocelot_port->ocelot, ocelot_port);
1152 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED:
1153 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled);
1163 static int ocelot_port_obj_add_vlan(struct net_device *dev,
1164 const struct switchdev_obj_port_vlan *vlan,
1165 struct switchdev_trans *trans)
1170 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1171 ret = ocelot_vlan_vid_add(dev, vid,
1172 vlan->flags & BRIDGE_VLAN_INFO_PVID,
1173 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED);
1181 static int ocelot_port_vlan_del_vlan(struct net_device *dev,
1182 const struct switchdev_obj_port_vlan *vlan)
1187 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1188 ret = ocelot_vlan_vid_del(dev, vid);
1197 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1198 const unsigned char *addr,
1201 struct ocelot_multicast *mc;
1203 list_for_each_entry(mc, &ocelot->multicast, list) {
1204 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1211 static int ocelot_port_obj_add_mdb(struct net_device *dev,
1212 const struct switchdev_obj_port_mdb *mdb,
1213 struct switchdev_trans *trans)
1215 struct ocelot_port *port = netdev_priv(dev);
1216 struct ocelot *ocelot = port->ocelot;
1217 struct ocelot_multicast *mc;
1218 unsigned char addr[ETH_ALEN];
1225 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1227 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1231 memcpy(mc->addr, mdb->addr, ETH_ALEN);
1234 list_add_tail(&mc->list, &ocelot->multicast);
1238 memcpy(addr, mc->addr, ETH_ALEN);
1242 addr[2] = mc->ports << 0;
1243 addr[1] = mc->ports << 8;
1244 ocelot_mact_forget(ocelot, addr, vid);
1247 mc->ports |= BIT(port->chip_port);
1248 addr[2] = mc->ports << 0;
1249 addr[1] = mc->ports << 8;
1251 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1254 static int ocelot_port_obj_del_mdb(struct net_device *dev,
1255 const struct switchdev_obj_port_mdb *mdb)
1257 struct ocelot_port *port = netdev_priv(dev);
1258 struct ocelot *ocelot = port->ocelot;
1259 struct ocelot_multicast *mc;
1260 unsigned char addr[ETH_ALEN];
1266 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1270 memcpy(addr, mc->addr, ETH_ALEN);
1271 addr[2] = mc->ports << 0;
1272 addr[1] = mc->ports << 8;
1274 ocelot_mact_forget(ocelot, addr, vid);
1276 mc->ports &= ~BIT(port->chip_port);
1278 list_del(&mc->list);
1279 devm_kfree(ocelot->dev, mc);
1283 addr[2] = mc->ports << 0;
1284 addr[1] = mc->ports << 8;
1286 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1289 static int ocelot_port_obj_add(struct net_device *dev,
1290 const struct switchdev_obj *obj,
1291 struct switchdev_trans *trans,
1292 struct netlink_ext_ack *extack)
1297 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1298 ret = ocelot_port_obj_add_vlan(dev,
1299 SWITCHDEV_OBJ_PORT_VLAN(obj),
1302 case SWITCHDEV_OBJ_ID_PORT_MDB:
1303 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj),
1313 static int ocelot_port_obj_del(struct net_device *dev,
1314 const struct switchdev_obj *obj)
1319 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1320 ret = ocelot_port_vlan_del_vlan(dev,
1321 SWITCHDEV_OBJ_PORT_VLAN(obj));
1323 case SWITCHDEV_OBJ_ID_PORT_MDB:
1324 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj));
1333 static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port,
1334 struct net_device *bridge)
1336 struct ocelot *ocelot = ocelot_port->ocelot;
1338 if (!ocelot->bridge_mask) {
1339 ocelot->hw_bridge_dev = bridge;
1341 if (ocelot->hw_bridge_dev != bridge)
1342 /* This is adding the port to a second bridge, this is
1347 ocelot->bridge_mask |= BIT(ocelot_port->chip_port);
1352 static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port,
1353 struct net_device *bridge)
1355 struct ocelot *ocelot = ocelot_port->ocelot;
1357 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port);
1359 if (!ocelot->bridge_mask)
1360 ocelot->hw_bridge_dev = NULL;
1362 /* Clear bridge vlan settings before calling ocelot_vlan_port_apply */
1363 ocelot_port->vlan_aware = 0;
1364 ocelot_port->pvid = 0;
1365 ocelot_port->vid = 0;
1368 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1372 /* Reset destination and aggregation PGIDS */
1373 for (port = 0; port < ocelot->num_phys_ports; port++)
1374 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1376 for (i = PGID_AGGR; i < PGID_SRC; i++)
1377 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1380 /* Now, set PGIDs for each LAG */
1381 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1382 unsigned long bond_mask;
1386 bond_mask = ocelot->lags[lag];
1390 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1392 ocelot_write_rix(ocelot, bond_mask,
1393 ANA_PGID_PGID, port);
1394 aggr_idx[aggr_count] = port;
1398 for (i = PGID_AGGR; i < PGID_SRC; i++) {
1401 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1403 ac |= BIT(aggr_idx[i % aggr_count]);
1404 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1409 static void ocelot_setup_lag(struct ocelot *ocelot, int lag)
1411 unsigned long bond_mask = ocelot->lags[lag];
1414 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) {
1415 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1417 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1419 /* Use lag port as logical port for port i */
1420 ocelot_write_gix(ocelot, port_cfg |
1421 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1422 ANA_PORT_PORT_CFG, p);
1426 static int ocelot_port_lag_join(struct ocelot_port *ocelot_port,
1427 struct net_device *bond)
1429 struct ocelot *ocelot = ocelot_port->ocelot;
1430 int p = ocelot_port->chip_port;
1432 struct net_device *ndev;
1436 for_each_netdev_in_bond_rcu(bond, ndev) {
1437 struct ocelot_port *port = netdev_priv(ndev);
1439 bond_mask |= BIT(port->chip_port);
1443 lp = __ffs(bond_mask);
1445 /* If the new port is the lowest one, use it as the logical port from
1450 ocelot->lags[p] = bond_mask;
1451 bond_mask &= ~BIT(p);
1453 lp = __ffs(bond_mask);
1454 ocelot->lags[lp] = 0;
1458 ocelot->lags[lp] |= BIT(p);
1461 ocelot_setup_lag(ocelot, lag);
1462 ocelot_set_aggr_pgids(ocelot);
1467 static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port,
1468 struct net_device *bond)
1470 struct ocelot *ocelot = ocelot_port->ocelot;
1471 int p = ocelot_port->chip_port;
1475 /* Remove port from any lag */
1476 for (i = 0; i < ocelot->num_phys_ports; i++)
1477 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port);
1479 /* if it was the logical port of the lag, move the lag config to the
1482 if (ocelot->lags[p]) {
1483 int n = __ffs(ocelot->lags[p]);
1485 ocelot->lags[n] = ocelot->lags[p];
1486 ocelot->lags[p] = 0;
1488 ocelot_setup_lag(ocelot, n);
1491 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1492 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1493 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p),
1494 ANA_PORT_PORT_CFG, p);
1496 ocelot_set_aggr_pgids(ocelot);
1499 /* Checks if the net_device instance given to us originate from our driver. */
1500 static bool ocelot_netdevice_dev_check(const struct net_device *dev)
1502 return dev->netdev_ops == &ocelot_port_netdev_ops;
1505 static int ocelot_netdevice_port_event(struct net_device *dev,
1506 unsigned long event,
1507 struct netdev_notifier_changeupper_info *info)
1509 struct ocelot_port *ocelot_port = netdev_priv(dev);
1512 if (!ocelot_netdevice_dev_check(dev))
1516 case NETDEV_CHANGEUPPER:
1517 if (netif_is_bridge_master(info->upper_dev)) {
1519 err = ocelot_port_bridge_join(ocelot_port,
1522 ocelot_port_bridge_leave(ocelot_port,
1525 ocelot_vlan_port_apply(ocelot_port->ocelot,
1528 if (netif_is_lag_master(info->upper_dev)) {
1530 err = ocelot_port_lag_join(ocelot_port,
1533 ocelot_port_lag_leave(ocelot_port,
1544 static int ocelot_netdevice_event(struct notifier_block *unused,
1545 unsigned long event, void *ptr)
1547 struct netdev_notifier_changeupper_info *info = ptr;
1548 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
1551 if (event == NETDEV_PRECHANGEUPPER &&
1552 netif_is_lag_master(info->upper_dev)) {
1553 struct netdev_lag_upper_info *lag_upper_info = info->upper_info;
1554 struct netlink_ext_ack *extack;
1556 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1557 extack = netdev_notifier_info_to_extack(&info->info);
1558 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
1565 if (netif_is_lag_master(dev)) {
1566 struct net_device *slave;
1567 struct list_head *iter;
1569 netdev_for_each_lower_dev(dev, slave, iter) {
1570 ret = ocelot_netdevice_port_event(slave, event, info);
1575 ret = ocelot_netdevice_port_event(dev, event, info);
1579 return notifier_from_errno(ret);
1582 struct notifier_block ocelot_netdevice_nb __read_mostly = {
1583 .notifier_call = ocelot_netdevice_event,
1585 EXPORT_SYMBOL(ocelot_netdevice_nb);
1587 static int ocelot_switchdev_event(struct notifier_block *unused,
1588 unsigned long event, void *ptr)
1590 struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
1594 case SWITCHDEV_PORT_ATTR_SET:
1595 err = switchdev_handle_port_attr_set(dev, ptr,
1596 ocelot_netdevice_dev_check,
1597 ocelot_port_attr_set);
1598 return notifier_from_errno(err);
1604 struct notifier_block ocelot_switchdev_nb __read_mostly = {
1605 .notifier_call = ocelot_switchdev_event,
1607 EXPORT_SYMBOL(ocelot_switchdev_nb);
1609 static int ocelot_switchdev_blocking_event(struct notifier_block *unused,
1610 unsigned long event, void *ptr)
1612 struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
1616 /* Blocking events. */
1617 case SWITCHDEV_PORT_OBJ_ADD:
1618 err = switchdev_handle_port_obj_add(dev, ptr,
1619 ocelot_netdevice_dev_check,
1620 ocelot_port_obj_add);
1621 return notifier_from_errno(err);
1622 case SWITCHDEV_PORT_OBJ_DEL:
1623 err = switchdev_handle_port_obj_del(dev, ptr,
1624 ocelot_netdevice_dev_check,
1625 ocelot_port_obj_del);
1626 return notifier_from_errno(err);
1627 case SWITCHDEV_PORT_ATTR_SET:
1628 err = switchdev_handle_port_attr_set(dev, ptr,
1629 ocelot_netdevice_dev_check,
1630 ocelot_port_attr_set);
1631 return notifier_from_errno(err);
1637 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = {
1638 .notifier_call = ocelot_switchdev_blocking_event,
1640 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb);
1642 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
1644 struct phy_device *phy)
1646 struct ocelot_port *ocelot_port;
1647 struct net_device *dev;
1650 dev = alloc_etherdev(sizeof(struct ocelot_port));
1653 SET_NETDEV_DEV(dev, ocelot->dev);
1654 ocelot_port = netdev_priv(dev);
1655 ocelot_port->dev = dev;
1656 ocelot_port->ocelot = ocelot;
1657 ocelot_port->regs = regs;
1658 ocelot_port->chip_port = port;
1659 ocelot_port->phy = phy;
1660 INIT_LIST_HEAD(&ocelot_port->mc);
1661 ocelot->ports[port] = ocelot_port;
1663 dev->netdev_ops = &ocelot_port_netdev_ops;
1664 dev->ethtool_ops = &ocelot_ethtool_ops;
1666 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS;
1667 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1669 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN);
1670 dev->dev_addr[ETH_ALEN - 1] += port;
1671 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid,
1674 err = register_netdev(dev);
1676 dev_err(ocelot->dev, "register_netdev failed\n");
1677 goto err_register_netdev;
1680 /* Basic L2 initialization */
1681 ocelot_vlan_port_apply(ocelot, ocelot_port);
1685 err_register_netdev:
1689 EXPORT_SYMBOL(ocelot_probe_port);
1691 int ocelot_init(struct ocelot *ocelot)
1694 int i, cpu = ocelot->num_phys_ports;
1695 char queue_name[32];
1697 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
1698 sizeof(u32), GFP_KERNEL);
1702 ocelot->stats = devm_kcalloc(ocelot->dev,
1703 ocelot->num_phys_ports * ocelot->num_stats,
1704 sizeof(u64), GFP_KERNEL);
1708 mutex_init(&ocelot->stats_lock);
1709 snprintf(queue_name, sizeof(queue_name), "%s-stats",
1710 dev_name(ocelot->dev));
1711 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
1712 if (!ocelot->stats_queue)
1715 ocelot_mact_init(ocelot);
1716 ocelot_vlan_init(ocelot);
1718 for (port = 0; port < ocelot->num_phys_ports; port++) {
1719 /* Clear all counters (5 groups) */
1720 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
1721 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
1725 /* Only use S-Tag */
1726 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
1728 /* Aggregation mode */
1729 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
1730 ANA_AGGR_CFG_AC_DMAC_ENA |
1731 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
1732 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG);
1734 /* Set MAC age time to default value. The entry is aged after
1737 ocelot_write(ocelot,
1738 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
1741 /* Disable learning for frames discarded by VLAN ingress filtering */
1742 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
1744 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
1745 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
1746 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
1748 /* Setup flooding PGIDs */
1749 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
1750 ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
1751 ANA_FLOODING_FLD_UNICAST(PGID_UC),
1753 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
1754 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
1755 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
1756 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
1759 for (port = 0; port < ocelot->num_phys_ports; port++) {
1760 /* Transmit the frame to the local port. */
1761 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1762 /* Do not forward BPDU frames to the front ports. */
1763 ocelot_write_gix(ocelot,
1764 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
1765 ANA_PORT_CPU_FWD_BPDU_CFG,
1767 /* Ensure bridging is disabled */
1768 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
1771 /* Configure and enable the CPU port. */
1772 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
1773 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
1774 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
1775 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
1776 ANA_PORT_PORT_CFG, cpu);
1778 /* Allow broadcast MAC frames. */
1779 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) {
1780 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
1782 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
1784 ocelot_write_rix(ocelot,
1785 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
1786 ANA_PGID_PGID, PGID_MC);
1787 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
1788 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
1790 /* CPU port Injection/Extraction configuration */
1791 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
1792 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
1793 QSYS_SWITCH_PORT_MODE_PORT_ENA,
1794 QSYS_SWITCH_PORT_MODE, cpu);
1795 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) |
1796 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu);
1797 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
1798 * registers endianness.
1800 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
1801 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
1802 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
1803 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
1804 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
1805 ANA_CPUQ_CFG_CPUQ_LRN(2) |
1806 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
1807 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
1808 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
1809 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
1810 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
1811 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
1812 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
1813 for (i = 0; i < 16; i++)
1814 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
1815 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
1816 ANA_CPUQ_8021_CFG, i);
1818 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
1819 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1820 OCELOT_STATS_CHECK_DELAY);
1823 EXPORT_SYMBOL(ocelot_init);
1825 void ocelot_deinit(struct ocelot *ocelot)
1827 destroy_workqueue(ocelot->stats_queue);
1828 mutex_destroy(&ocelot->stats_lock);
1830 EXPORT_SYMBOL(ocelot_deinit);
1832 MODULE_LICENSE("Dual MIT/GPL");