1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/dsa/ocelot.h>
8 #include <linux/if_bridge.h>
9 #include <linux/ptp_classify.h>
10 #include <soc/mscc/ocelot_vcap.h>
12 #include "ocelot_vcap.h"
14 #define TABLE_UPDATE_SLEEP_US 10
15 #define TABLE_UPDATE_TIMEOUT_US 100000
17 struct ocelot_mact_entry {
20 enum macaccess_entry_type type;
23 /* Caller must hold &ocelot->mact_lock */
24 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
26 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
29 /* Caller must hold &ocelot->mact_lock */
30 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
34 return readx_poll_timeout(ocelot_mact_read_macaccess,
36 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
38 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
41 /* Caller must hold &ocelot->mact_lock */
42 static void ocelot_mact_select(struct ocelot *ocelot,
43 const unsigned char mac[ETH_ALEN],
46 u32 macl = 0, mach = 0;
48 /* Set the MAC address to handle and the vlan associated in a format
49 * understood by the hardware.
59 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
60 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
64 int ocelot_mact_learn(struct ocelot *ocelot, int port,
65 const unsigned char mac[ETH_ALEN],
66 unsigned int vid, enum macaccess_entry_type type)
68 u32 cmd = ANA_TABLES_MACACCESS_VALID |
69 ANA_TABLES_MACACCESS_DEST_IDX(port) |
70 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
71 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
72 unsigned int mc_ports;
75 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
76 if (type == ENTRYTYPE_MACv4)
77 mc_ports = (mac[1] << 8) | mac[2];
78 else if (type == ENTRYTYPE_MACv6)
79 mc_ports = (mac[0] << 8) | mac[1];
83 if (mc_ports & BIT(ocelot->num_phys_ports))
84 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
86 mutex_lock(&ocelot->mact_lock);
88 ocelot_mact_select(ocelot, mac, vid);
90 /* Issue a write command */
91 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
93 err = ocelot_mact_wait_for_completion(ocelot);
95 mutex_unlock(&ocelot->mact_lock);
99 EXPORT_SYMBOL(ocelot_mact_learn);
101 int ocelot_mact_forget(struct ocelot *ocelot,
102 const unsigned char mac[ETH_ALEN], unsigned int vid)
106 mutex_lock(&ocelot->mact_lock);
108 ocelot_mact_select(ocelot, mac, vid);
110 /* Issue a forget command */
112 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
113 ANA_TABLES_MACACCESS);
115 err = ocelot_mact_wait_for_completion(ocelot);
117 mutex_unlock(&ocelot->mact_lock);
121 EXPORT_SYMBOL(ocelot_mact_forget);
123 static void ocelot_mact_init(struct ocelot *ocelot)
125 /* Configure the learning mode entries attributes:
126 * - Do not copy the frame to the CPU extraction queues.
127 * - Use the vlan and mac_cpoy for dmac lookup.
129 ocelot_rmw(ocelot, 0,
130 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
131 | ANA_AGENCTRL_LEARN_FWD_KILL
132 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
135 /* Clear the MAC table. We are not concurrent with anyone, so
136 * holding &ocelot->mact_lock is pointless.
138 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
141 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
143 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
144 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
145 ANA_PORT_VCAP_S2_CFG, port);
147 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
148 ANA_PORT_VCAP_CFG, port);
150 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
155 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
157 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
160 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
164 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
167 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
168 ANA_TABLES_VLANACCESS_CMD_IDLE,
169 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
172 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
174 /* Select the VID to configure */
175 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
176 ANA_TABLES_VLANTIDX);
177 /* Set the vlan port members mask and issue a write command */
178 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
179 ANA_TABLES_VLANACCESS_CMD_WRITE,
180 ANA_TABLES_VLANACCESS);
182 return ocelot_vlant_wait_for_completion(ocelot);
185 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port)
187 struct ocelot_bridge_vlan *vlan;
188 int num_untagged = 0;
190 list_for_each_entry(vlan, &ocelot->vlans, list) {
191 if (!(vlan->portmask & BIT(port)))
194 if (vlan->untagged & BIT(port))
201 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port)
203 struct ocelot_bridge_vlan *vlan;
206 list_for_each_entry(vlan, &ocelot->vlans, list) {
207 if (!(vlan->portmask & BIT(port)))
210 if (!(vlan->untagged & BIT(port)))
217 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly
218 * _one_ egress-untagged VLAN (_the_ native VLAN)
220 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port)
222 return ocelot_port_num_tagged_vlans(ocelot, port) &&
223 ocelot_port_num_untagged_vlans(ocelot, port) == 1;
226 static struct ocelot_bridge_vlan *
227 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port)
229 struct ocelot_bridge_vlan *vlan;
231 list_for_each_entry(vlan, &ocelot->vlans, list)
232 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port))
238 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable,
239 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness
242 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port)
244 struct ocelot_port *ocelot_port = ocelot->ports[port];
245 enum ocelot_port_tag_config tag_cfg;
246 bool uses_native_vlan = false;
248 if (ocelot_port->vlan_aware) {
249 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port);
251 if (uses_native_vlan)
252 tag_cfg = OCELOT_PORT_TAG_NATIVE;
253 else if (ocelot_port_num_untagged_vlans(ocelot, port))
254 tag_cfg = OCELOT_PORT_TAG_DISABLED;
256 tag_cfg = OCELOT_PORT_TAG_TRUNK;
258 tag_cfg = OCELOT_PORT_TAG_DISABLED;
261 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg),
262 REW_TAG_CFG_TAG_CFG_M,
265 if (uses_native_vlan) {
266 struct ocelot_bridge_vlan *native_vlan;
268 /* Not having a native VLAN is impossible, because
269 * ocelot_port_num_untagged_vlans has returned 1.
270 * So there is no use in checking for NULL here.
272 native_vlan = ocelot_port_find_native_vlan(ocelot, port);
274 ocelot_rmw_gix(ocelot,
275 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid),
276 REW_PORT_VLAN_CFG_PORT_VID_M,
277 REW_PORT_VLAN_CFG, port);
281 /* Default vlan to clasify for untagged frames (may be zero) */
282 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port,
283 const struct ocelot_bridge_vlan *pvid_vlan)
285 struct ocelot_port *ocelot_port = ocelot->ports[port];
286 u16 pvid = OCELOT_VLAN_UNAWARE_PVID;
289 ocelot_port->pvid_vlan = pvid_vlan;
291 if (ocelot_port->vlan_aware && pvid_vlan)
292 pvid = pvid_vlan->vid;
294 ocelot_rmw_gix(ocelot,
295 ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
296 ANA_PORT_VLAN_CFG_VLAN_VID_M,
297 ANA_PORT_VLAN_CFG, port);
299 /* If there's no pvid, we should drop not only untagged traffic (which
300 * happens automatically), but also 802.1p traffic which gets
301 * classified to VLAN 0, but that is always in our RX filter, so it
302 * would get accepted were it not for this setting.
304 if (!pvid_vlan && ocelot_port->vlan_aware)
305 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
306 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
308 ocelot_rmw_gix(ocelot, val,
309 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
310 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
311 ANA_PORT_DROP_CFG, port);
314 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot,
317 struct ocelot_bridge_vlan *vlan;
319 list_for_each_entry(vlan, &ocelot->vlans, list)
320 if (vlan->vid == vid)
326 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid,
329 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
330 unsigned long portmask;
334 portmask = vlan->portmask | BIT(port);
336 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
340 vlan->portmask = portmask;
341 /* Bridge VLANs can be overwritten with a different
342 * egress-tagging setting, so make sure to override an untagged
343 * with a tagged VID if that's going on.
346 vlan->untagged |= BIT(port);
348 vlan->untagged &= ~BIT(port);
353 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
357 portmask = BIT(port);
359 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
366 vlan->portmask = portmask;
368 vlan->untagged = BIT(port);
369 INIT_LIST_HEAD(&vlan->list);
370 list_add_tail(&vlan->list, &ocelot->vlans);
375 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid)
377 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
378 unsigned long portmask;
384 portmask = vlan->portmask & ~BIT(port);
386 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
390 vlan->portmask = portmask;
394 list_del(&vlan->list);
400 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
401 bool vlan_aware, struct netlink_ext_ack *extack)
403 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
404 struct ocelot_port *ocelot_port = ocelot->ports[port];
405 struct ocelot_vcap_filter *filter;
408 list_for_each_entry(filter, &block->rules, list) {
409 if (filter->ingress_port_mask & BIT(port) &&
410 filter->action.vid_replace_ena) {
411 NL_SET_ERR_MSG_MOD(extack,
412 "Cannot change VLAN state with vlan modify rules active");
417 ocelot_port->vlan_aware = vlan_aware;
420 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
421 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
424 ocelot_rmw_gix(ocelot, val,
425 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
426 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
427 ANA_PORT_VLAN_CFG, port);
429 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
430 ocelot_port_manage_port_tag(ocelot, port);
434 EXPORT_SYMBOL(ocelot_port_vlan_filtering);
436 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
437 bool untagged, struct netlink_ext_ack *extack)
440 /* We are adding an egress-tagged VLAN */
441 if (ocelot_port_uses_native_vlan(ocelot, port)) {
442 NL_SET_ERR_MSG_MOD(extack,
443 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN");
447 /* We are adding an egress-tagged VLAN */
448 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) {
449 NL_SET_ERR_MSG_MOD(extack,
450 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs");
457 EXPORT_SYMBOL(ocelot_vlan_prepare);
459 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
464 err = ocelot_vlan_member_add(ocelot, port, vid, untagged);
468 /* Default ingress vlan classification */
470 ocelot_port_set_pvid(ocelot, port,
471 ocelot_bridge_vlan_find(ocelot, vid));
473 /* Untagged egress vlan clasification */
474 ocelot_port_manage_port_tag(ocelot, port);
478 EXPORT_SYMBOL(ocelot_vlan_add);
480 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
482 struct ocelot_port *ocelot_port = ocelot->ports[port];
485 err = ocelot_vlan_member_del(ocelot, port, vid);
490 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid)
491 ocelot_port_set_pvid(ocelot, port, NULL);
494 ocelot_port_manage_port_tag(ocelot, port);
498 EXPORT_SYMBOL(ocelot_vlan_del);
500 static void ocelot_vlan_init(struct ocelot *ocelot)
502 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0);
505 /* Clear VLAN table, by default all ports are members of all VLANs */
506 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
507 ANA_TABLES_VLANACCESS);
508 ocelot_vlant_wait_for_completion(ocelot);
510 /* Configure the port VLAN memberships */
511 for (vid = 1; vid < VLAN_N_VID; vid++)
512 ocelot_vlant_set_mask(ocelot, vid, 0);
514 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
515 * traffic. It is added automatically if 8021q module is loaded, but
516 * we can't rely on it since module may be not loaded.
518 ocelot_vlant_set_mask(ocelot, OCELOT_VLAN_UNAWARE_PVID, all_ports);
520 /* Set vlan ingress filter mask to all ports but the CPU port by
523 ocelot_write(ocelot, all_ports, ANA_VLANMASK);
525 for (port = 0; port < ocelot->num_phys_ports; port++) {
526 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
527 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
531 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
533 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
536 static int ocelot_port_flush(struct ocelot *ocelot, int port)
538 unsigned int pause_ena;
541 /* Disable dequeuing from the egress queues */
542 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
543 QSYS_PORT_MODE_DEQUEUE_DIS,
544 QSYS_PORT_MODE, port);
546 /* Disable flow control */
547 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
548 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
550 /* Disable priority flow control */
551 ocelot_fields_write(ocelot, port,
552 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0);
554 /* Wait at least the time it takes to receive a frame of maximum length
556 * Worst-case delays for 10 kilobyte jumbo frames are:
558 * 800 μs on a 100M port
559 * 80 μs on a 1G port
560 * 32 μs on a 2.5G port
562 usleep_range(8000, 10000);
564 /* Disable half duplex backpressure. */
565 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
566 SYS_FRONT_PORT_MODE, port);
568 /* Flush the queues associated with the port. */
569 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
572 /* Enable dequeuing from the egress queues. */
573 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
576 /* Wait until flushing is complete. */
577 err = read_poll_timeout(ocelot_read_eq_avail, val, !val,
578 100, 2000000, false, ocelot, port);
580 /* Clear flushing again. */
581 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
583 /* Re-enable flow control */
584 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
589 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
590 unsigned int link_an_mode,
591 phy_interface_t interface,
592 unsigned long quirks)
594 struct ocelot_port *ocelot_port = ocelot->ports[port];
597 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
600 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
602 err = ocelot_port_flush(ocelot, port);
604 dev_err(ocelot->dev, "failed to flush port %d: %d\n",
607 /* Put the port in reset. */
608 if (interface != PHY_INTERFACE_MODE_QSGMII ||
609 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP))
610 ocelot_port_rmwl(ocelot_port,
611 DEV_CLOCK_CFG_MAC_TX_RST |
612 DEV_CLOCK_CFG_MAC_RX_RST,
613 DEV_CLOCK_CFG_MAC_TX_RST |
614 DEV_CLOCK_CFG_MAC_RX_RST,
617 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down);
619 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
620 struct phy_device *phydev,
621 unsigned int link_an_mode,
622 phy_interface_t interface,
623 int speed, int duplex,
624 bool tx_pause, bool rx_pause,
625 unsigned long quirks)
627 struct ocelot_port *ocelot_port = ocelot->ports[port];
628 int mac_speed, mode = 0;
631 /* The MAC might be integrated in systems where the MAC speed is fixed
632 * and it's the PCS who is performing the rate adaptation, so we have
633 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG
634 * (which is also its default value).
636 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) ||
637 speed == SPEED_1000) {
638 mac_speed = OCELOT_SPEED_1000;
639 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
640 } else if (speed == SPEED_2500) {
641 mac_speed = OCELOT_SPEED_2500;
642 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
643 } else if (speed == SPEED_100) {
644 mac_speed = OCELOT_SPEED_100;
646 mac_speed = OCELOT_SPEED_10;
649 if (duplex == DUPLEX_FULL)
650 mode |= DEV_MAC_MODE_CFG_FDX_ENA;
652 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG);
654 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
655 * PORT_RST bits in DEV_CLOCK_CFG.
657 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),
662 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10);
665 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100);
669 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000);
672 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
677 /* Handle RX pause in all cases, with 2500base-X this is used for rate
680 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
683 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
684 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
685 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
686 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
688 /* Flow control. Link speed is only used here to evaluate the time
689 * specification in incoming pause frames.
691 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
693 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
695 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause);
697 /* Undo the effects of ocelot_phylink_mac_link_down:
700 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
701 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
703 /* Core: Enable port for frame transfer */
704 ocelot_fields_write(ocelot, port,
705 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
707 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up);
709 static int ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port,
710 struct sk_buff *clone)
712 struct ocelot_port *ocelot_port = ocelot->ports[port];
715 spin_lock_irqsave(&ocelot->ts_id_lock, flags);
717 if (ocelot_port->ptp_skbs_in_flight == OCELOT_MAX_PTP_ID ||
718 ocelot->ptp_skbs_in_flight == OCELOT_PTP_FIFO_SIZE) {
719 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags);
723 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS;
724 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */
725 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id;
727 ocelot_port->ts_id++;
728 if (ocelot_port->ts_id == OCELOT_MAX_PTP_ID)
729 ocelot_port->ts_id = 0;
731 ocelot_port->ptp_skbs_in_flight++;
732 ocelot->ptp_skbs_in_flight++;
734 skb_queue_tail(&ocelot_port->tx_skbs, clone);
736 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags);
741 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb,
742 unsigned int ptp_class)
744 struct ptp_header *hdr;
747 hdr = ptp_parse_header(skb, ptp_class);
751 msgtype = ptp_get_msgtype(hdr, ptp_class);
752 twostep = hdr->flag_field[0] & 0x2;
754 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0)
760 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port,
762 struct sk_buff **clone)
764 struct ocelot_port *ocelot_port = ocelot->ports[port];
765 u8 ptp_cmd = ocelot_port->ptp_cmd;
766 unsigned int ptp_class;
769 /* Don't do anything if PTP timestamping not enabled */
773 ptp_class = ptp_classify_raw(skb);
774 if (ptp_class == PTP_CLASS_NONE)
777 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */
778 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) {
779 if (ocelot_ptp_is_onestep_sync(skb, ptp_class)) {
780 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd;
784 /* Fall back to two-step timestamping */
785 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
788 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) {
789 *clone = skb_clone_sk(skb);
793 err = ocelot_port_add_txtstamp_skb(ocelot, port, *clone);
797 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd;
798 OCELOT_SKB_CB(*clone)->ptp_class = ptp_class;
803 EXPORT_SYMBOL(ocelot_port_txtstamp_request);
805 static void ocelot_get_hwtimestamp(struct ocelot *ocelot,
806 struct timespec64 *ts)
811 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
813 /* Read current PTP time to get seconds */
814 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
816 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
817 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
818 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
819 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
821 /* Read packet HW timestamp from FIFO */
822 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP);
823 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val);
825 /* Sec has incremented since the ts was registered */
826 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC))
829 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
832 static bool ocelot_validate_ptp_skb(struct sk_buff *clone, u16 seqid)
834 struct ptp_header *hdr;
836 hdr = ptp_parse_header(clone, OCELOT_SKB_CB(clone)->ptp_class);
840 return seqid == ntohs(hdr->sequence_id);
843 void ocelot_get_txtstamp(struct ocelot *ocelot)
845 int budget = OCELOT_PTP_QUEUE_SZ;
848 struct sk_buff *skb, *skb_tmp, *skb_match = NULL;
849 struct skb_shared_hwtstamps shhwtstamps;
850 u32 val, id, seqid, txport;
851 struct ocelot_port *port;
852 struct timespec64 ts;
855 val = ocelot_read(ocelot, SYS_PTP_STATUS);
857 /* Check if a timestamp can be retrieved */
858 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD))
861 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL);
863 /* Retrieve the ts ID and Tx port */
864 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val);
865 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val);
866 seqid = SYS_PTP_STATUS_PTP_MESS_SEQ_ID(val);
868 port = ocelot->ports[txport];
870 spin_lock(&ocelot->ts_id_lock);
871 port->ptp_skbs_in_flight--;
872 ocelot->ptp_skbs_in_flight--;
873 spin_unlock(&ocelot->ts_id_lock);
875 /* Retrieve its associated skb */
877 spin_lock_irqsave(&port->tx_skbs.lock, flags);
879 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) {
880 if (OCELOT_SKB_CB(skb)->ts_id != id)
882 __skb_unlink(skb, &port->tx_skbs);
887 spin_unlock_irqrestore(&port->tx_skbs.lock, flags);
889 if (WARN_ON(!skb_match))
892 if (!ocelot_validate_ptp_skb(skb_match, seqid)) {
893 dev_err_ratelimited(ocelot->dev,
894 "port %d received stale TX timestamp for seqid %d, discarding\n",
896 dev_kfree_skb_any(skb);
900 /* Get the h/w timestamp */
901 ocelot_get_hwtimestamp(ocelot, &ts);
903 /* Set the timestamp into the skb */
904 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
905 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
906 skb_complete_tx_timestamp(skb_match, &shhwtstamps);
909 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT);
912 EXPORT_SYMBOL(ocelot_get_txtstamp);
914 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
917 u32 bytes_valid, val;
919 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
920 if (val == XTR_NOT_READY) {
925 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
926 } while (val == XTR_NOT_READY);
937 bytes_valid = XTR_VALID_BYTES(val);
938 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
939 if (val == XTR_ESCAPE)
940 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
946 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
956 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
960 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
961 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
963 return (err < 0) ? err : -EIO;
969 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
971 struct skb_shared_hwtstamps *shhwtstamps;
972 u64 tod_in_ns, full_ts_in_ns;
973 u64 timestamp, src_port, len;
974 u32 xfh[OCELOT_TAG_LEN / 4];
975 struct net_device *dev;
976 struct timespec64 ts;
982 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
986 ocelot_xfh_get_src_port(xfh, &src_port);
987 ocelot_xfh_get_len(xfh, &len);
988 ocelot_xfh_get_rew_val(xfh, ×tamp);
990 if (WARN_ON(src_port >= ocelot->num_phys_ports))
993 dev = ocelot->ops->port_to_netdev(ocelot, src_port);
997 skb = netdev_alloc_skb(dev, len);
998 if (unlikely(!skb)) {
999 netdev_err(dev, "Unable to allocate sk_buff\n");
1003 buf_len = len - ETH_FCS_LEN;
1004 buf = (u32 *)skb_put(skb, buf_len);
1008 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1015 } while (len < buf_len);
1018 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1024 /* Update the statistics if part of the FCS was read before */
1025 len -= ETH_FCS_LEN - sz;
1027 if (unlikely(dev->features & NETIF_F_RXFCS)) {
1028 buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
1033 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1035 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
1036 if ((tod_in_ns & 0xffffffff) < timestamp)
1037 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
1040 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
1043 shhwtstamps = skb_hwtstamps(skb);
1044 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
1045 shhwtstamps->hwtstamp = full_ts_in_ns;
1048 /* Everything we see on an interface that is in the HW bridge
1049 * has already been forwarded.
1051 if (ocelot->ports[src_port]->bridge)
1052 skb->offload_fwd_mark = 1;
1054 skb->protocol = eth_type_trans(skb, dev);
1064 EXPORT_SYMBOL(ocelot_xtr_poll_frame);
1066 bool ocelot_can_inject(struct ocelot *ocelot, int grp)
1068 u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
1070 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))))
1072 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))
1077 EXPORT_SYMBOL(ocelot_can_inject);
1079 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
1080 u32 rew_op, struct sk_buff *skb)
1082 u32 ifh[OCELOT_TAG_LEN / 4] = {0};
1083 unsigned int i, count, last;
1085 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1086 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
1088 ocelot_ifh_set_bypass(ifh, 1);
1089 ocelot_ifh_set_dest(ifh, BIT_ULL(port));
1090 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C);
1091 ocelot_ifh_set_vlan_tci(ifh, skb_vlan_tag_get(skb));
1092 ocelot_ifh_set_rew_op(ifh, rew_op);
1094 for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
1095 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
1097 count = DIV_ROUND_UP(skb->len, 4);
1098 last = skb->len % 4;
1099 for (i = 0; i < count; i++)
1100 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
1103 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
1104 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1108 /* Indicate EOF and valid bytes in last word */
1109 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1110 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
1115 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1116 skb_tx_timestamp(skb);
1118 skb->dev->stats.tx_packets++;
1119 skb->dev->stats.tx_bytes += skb->len;
1121 EXPORT_SYMBOL(ocelot_port_inject_frame);
1123 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
1125 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
1126 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1128 EXPORT_SYMBOL(ocelot_drain_cpu_queue);
1130 int ocelot_fdb_add(struct ocelot *ocelot, int port,
1131 const unsigned char *addr, u16 vid)
1135 if (port == ocelot->npi)
1138 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED);
1140 EXPORT_SYMBOL(ocelot_fdb_add);
1142 int ocelot_fdb_del(struct ocelot *ocelot, int port,
1143 const unsigned char *addr, u16 vid)
1145 return ocelot_mact_forget(ocelot, addr, vid);
1147 EXPORT_SYMBOL(ocelot_fdb_del);
1149 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid,
1150 bool is_static, void *data)
1152 struct ocelot_dump_ctx *dump = data;
1153 u32 portid = NETLINK_CB(dump->cb->skb).portid;
1154 u32 seq = dump->cb->nlh->nlmsg_seq;
1155 struct nlmsghdr *nlh;
1158 if (dump->idx < dump->cb->args[2])
1161 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
1162 sizeof(*ndm), NLM_F_MULTI);
1166 ndm = nlmsg_data(nlh);
1167 ndm->ndm_family = AF_BRIDGE;
1170 ndm->ndm_flags = NTF_SELF;
1172 ndm->ndm_ifindex = dump->dev->ifindex;
1173 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
1175 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
1176 goto nla_put_failure;
1178 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
1179 goto nla_put_failure;
1181 nlmsg_end(dump->skb, nlh);
1188 nlmsg_cancel(dump->skb, nlh);
1191 EXPORT_SYMBOL(ocelot_port_fdb_do_dump);
1193 /* Caller must hold &ocelot->mact_lock */
1194 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
1195 struct ocelot_mact_entry *entry)
1197 u32 val, dst, macl, mach;
1200 /* Set row and column to read from */
1201 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
1202 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
1204 /* Issue a read command */
1205 ocelot_write(ocelot,
1206 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
1207 ANA_TABLES_MACACCESS);
1209 if (ocelot_mact_wait_for_completion(ocelot))
1212 /* Read the entry flags */
1213 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1214 if (!(val & ANA_TABLES_MACACCESS_VALID))
1217 /* If the entry read has another port configured as its destination,
1220 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
1224 /* Get the entry's MAC address and VLAN id */
1225 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1226 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1228 mac[0] = (mach >> 8) & 0xff;
1229 mac[1] = (mach >> 0) & 0xff;
1230 mac[2] = (macl >> 24) & 0xff;
1231 mac[3] = (macl >> 16) & 0xff;
1232 mac[4] = (macl >> 8) & 0xff;
1233 mac[5] = (macl >> 0) & 0xff;
1235 entry->vid = (mach >> 16) & 0xfff;
1236 ether_addr_copy(entry->mac, mac);
1241 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1242 dsa_fdb_dump_cb_t *cb, void *data)
1247 /* We could take the lock just around ocelot_mact_read, but doing so
1248 * thousands of times in a row seems rather pointless and inefficient.
1250 mutex_lock(&ocelot->mact_lock);
1252 /* Loop through all the mac tables entries. */
1253 for (i = 0; i < ocelot->num_mact_rows; i++) {
1254 for (j = 0; j < 4; j++) {
1255 struct ocelot_mact_entry entry;
1258 err = ocelot_mact_read(ocelot, port, i, j, &entry);
1259 /* If the entry is invalid (wrong port, invalid...),
1267 is_static = (entry.type == ENTRYTYPE_LOCKED);
1269 err = cb(entry.mac, entry.vid, is_static, data);
1275 mutex_unlock(&ocelot->mact_lock);
1279 EXPORT_SYMBOL(ocelot_fdb_dump);
1281 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr)
1283 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
1284 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
1286 EXPORT_SYMBOL(ocelot_hwstamp_get);
1288 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr)
1290 struct ocelot_port *ocelot_port = ocelot->ports[port];
1291 struct hwtstamp_config cfg;
1293 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1296 /* reserved for future extensions */
1300 /* Tx type sanity check */
1301 switch (cfg.tx_type) {
1302 case HWTSTAMP_TX_ON:
1303 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
1305 case HWTSTAMP_TX_ONESTEP_SYNC:
1306 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
1307 * need to update the origin time.
1309 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
1311 case HWTSTAMP_TX_OFF:
1312 ocelot_port->ptp_cmd = 0;
1318 mutex_lock(&ocelot->ptp_lock);
1320 switch (cfg.rx_filter) {
1321 case HWTSTAMP_FILTER_NONE:
1323 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1324 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1325 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1326 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1327 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1328 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1329 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1330 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1331 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1332 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1335 mutex_unlock(&ocelot->ptp_lock);
1339 /* Commit back the result & save it */
1340 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
1341 mutex_unlock(&ocelot->ptp_lock);
1343 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1345 EXPORT_SYMBOL(ocelot_hwstamp_set);
1347 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data)
1351 if (sset != ETH_SS_STATS)
1354 for (i = 0; i < ocelot->num_stats; i++)
1355 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
1358 EXPORT_SYMBOL(ocelot_get_strings);
1360 static void ocelot_update_stats(struct ocelot *ocelot)
1364 mutex_lock(&ocelot->stats_lock);
1366 for (i = 0; i < ocelot->num_phys_ports; i++) {
1367 /* Configure the port to read the stats from */
1368 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
1370 for (j = 0; j < ocelot->num_stats; j++) {
1372 unsigned int idx = i * ocelot->num_stats + j;
1374 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
1375 ocelot->stats_layout[j].offset);
1377 if (val < (ocelot->stats[idx] & U32_MAX))
1378 ocelot->stats[idx] += (u64)1 << 32;
1380 ocelot->stats[idx] = (ocelot->stats[idx] &
1381 ~(u64)U32_MAX) + val;
1385 mutex_unlock(&ocelot->stats_lock);
1388 static void ocelot_check_stats_work(struct work_struct *work)
1390 struct delayed_work *del_work = to_delayed_work(work);
1391 struct ocelot *ocelot = container_of(del_work, struct ocelot,
1394 ocelot_update_stats(ocelot);
1396 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1397 OCELOT_STATS_CHECK_DELAY);
1400 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
1404 /* check and update now */
1405 ocelot_update_stats(ocelot);
1407 /* Copy all counters */
1408 for (i = 0; i < ocelot->num_stats; i++)
1409 *data++ = ocelot->stats[port * ocelot->num_stats + i];
1411 EXPORT_SYMBOL(ocelot_get_ethtool_stats);
1413 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
1415 if (sset != ETH_SS_STATS)
1418 return ocelot->num_stats;
1420 EXPORT_SYMBOL(ocelot_get_sset_count);
1422 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
1423 struct ethtool_ts_info *info)
1425 info->phc_index = ocelot->ptp_clock ?
1426 ptp_clock_index(ocelot->ptp_clock) : -1;
1427 if (info->phc_index == -1) {
1428 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1429 SOF_TIMESTAMPING_RX_SOFTWARE |
1430 SOF_TIMESTAMPING_SOFTWARE;
1433 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1434 SOF_TIMESTAMPING_RX_SOFTWARE |
1435 SOF_TIMESTAMPING_SOFTWARE |
1436 SOF_TIMESTAMPING_TX_HARDWARE |
1437 SOF_TIMESTAMPING_RX_HARDWARE |
1438 SOF_TIMESTAMPING_RAW_HARDWARE;
1439 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
1440 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
1441 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1445 EXPORT_SYMBOL(ocelot_get_ts_info);
1447 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond,
1448 bool only_active_ports)
1453 for (port = 0; port < ocelot->num_phys_ports; port++) {
1454 struct ocelot_port *ocelot_port = ocelot->ports[port];
1459 if (ocelot_port->bond == bond) {
1460 if (only_active_ports && !ocelot_port->lag_tx_active)
1470 static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port,
1471 struct net_device *bridge)
1473 struct ocelot_port *ocelot_port = ocelot->ports[src_port];
1477 if (!ocelot_port || ocelot_port->bridge != bridge ||
1478 ocelot_port->stp_state != BR_STATE_FORWARDING)
1481 for (port = 0; port < ocelot->num_phys_ports; port++) {
1482 ocelot_port = ocelot->ports[port];
1487 if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
1488 ocelot_port->bridge == bridge)
1495 static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot)
1500 for (port = 0; port < ocelot->num_phys_ports; port++) {
1501 struct ocelot_port *ocelot_port = ocelot->ports[port];
1506 if (ocelot_port->is_dsa_8021q_cpu)
1513 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot)
1515 unsigned long cpu_fwd_mask;
1518 /* If a DSA tag_8021q CPU exists, it needs to be included in the
1519 * regular forwarding path of the front ports regardless of whether
1520 * those are bridged or standalone.
1521 * If DSA tag_8021q is not used, this returns 0, which is fine because
1522 * the hardware-based CPU port module can be a destination for packets
1523 * even if it isn't part of PGID_SRC.
1525 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot);
1527 /* Apply FWD mask. The loop is needed to add/remove the current port as
1528 * a source for the other ports.
1530 for (port = 0; port < ocelot->num_phys_ports; port++) {
1531 struct ocelot_port *ocelot_port = ocelot->ports[port];
1535 /* Unused ports can't send anywhere */
1537 } else if (ocelot_port->is_dsa_8021q_cpu) {
1538 /* The DSA tag_8021q CPU ports need to be able to
1539 * forward packets to all other ports except for
1542 mask = GENMASK(ocelot->num_phys_ports - 1, 0);
1543 mask &= ~cpu_fwd_mask;
1544 } else if (ocelot_port->bridge) {
1545 struct net_device *bridge = ocelot_port->bridge;
1546 struct net_device *bond = ocelot_port->bond;
1548 mask = ocelot_get_bridge_fwd_mask(ocelot, port, bridge);
1549 mask |= cpu_fwd_mask;
1552 mask &= ~ocelot_get_bond_mask(ocelot, bond,
1556 /* Standalone ports forward only to DSA tag_8021q CPU
1557 * ports (if those exist), or to the hardware CPU port
1560 mask = cpu_fwd_mask;
1563 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1566 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask);
1568 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1570 struct ocelot_port *ocelot_port = ocelot->ports[port];
1573 ocelot_port->stp_state = state;
1575 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) &&
1576 ocelot_port->learn_ena)
1577 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA;
1579 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA,
1580 ANA_PORT_PORT_CFG, port);
1582 ocelot_apply_bridge_fwd_mask(ocelot);
1584 EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
1586 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1588 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
1590 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
1591 * which is clearly not what our intention is. So avoid that.
1596 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
1598 EXPORT_SYMBOL(ocelot_set_ageing_time);
1600 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1601 const unsigned char *addr,
1604 struct ocelot_multicast *mc;
1606 list_for_each_entry(mc, &ocelot->multicast, list) {
1607 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1614 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
1616 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
1617 return ENTRYTYPE_MACv4;
1618 if (addr[0] == 0x33 && addr[1] == 0x33)
1619 return ENTRYTYPE_MACv6;
1620 return ENTRYTYPE_LOCKED;
1623 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
1624 unsigned long ports)
1626 struct ocelot_pgid *pgid;
1628 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL);
1630 return ERR_PTR(-ENOMEM);
1632 pgid->ports = ports;
1633 pgid->index = index;
1634 refcount_set(&pgid->refcount, 1);
1635 list_add_tail(&pgid->list, &ocelot->pgids);
1640 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
1642 if (!refcount_dec_and_test(&pgid->refcount))
1645 list_del(&pgid->list);
1649 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
1650 const struct ocelot_multicast *mc)
1652 struct ocelot_pgid *pgid;
1655 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
1656 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
1657 * destination mask table (PGID), the destination set is programmed as
1658 * part of the entry MAC address.", and the DEST_IDX is set to 0.
1660 if (mc->entry_type == ENTRYTYPE_MACv4 ||
1661 mc->entry_type == ENTRYTYPE_MACv6)
1662 return ocelot_pgid_alloc(ocelot, 0, mc->ports);
1664 list_for_each_entry(pgid, &ocelot->pgids, list) {
1665 /* When searching for a nonreserved multicast PGID, ignore the
1666 * dummy PGID of zero that we have for MACv4/MACv6 entries
1668 if (pgid->index && pgid->ports == mc->ports) {
1669 refcount_inc(&pgid->refcount);
1674 /* Search for a free index in the nonreserved multicast PGID area */
1675 for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
1678 list_for_each_entry(pgid, &ocelot->pgids, list) {
1679 if (pgid->index == index) {
1686 return ocelot_pgid_alloc(ocelot, index, mc->ports);
1689 return ERR_PTR(-ENOSPC);
1692 static void ocelot_encode_ports_to_mdb(unsigned char *addr,
1693 struct ocelot_multicast *mc)
1695 ether_addr_copy(addr, mc->addr);
1697 if (mc->entry_type == ENTRYTYPE_MACv4) {
1699 addr[1] = mc->ports >> 8;
1700 addr[2] = mc->ports & 0xff;
1701 } else if (mc->entry_type == ENTRYTYPE_MACv6) {
1702 addr[0] = mc->ports >> 8;
1703 addr[1] = mc->ports & 0xff;
1707 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1708 const struct switchdev_obj_port_mdb *mdb)
1710 unsigned char addr[ETH_ALEN];
1711 struct ocelot_multicast *mc;
1712 struct ocelot_pgid *pgid;
1715 if (port == ocelot->npi)
1716 port = ocelot->num_phys_ports;
1718 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1721 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1725 mc->entry_type = ocelot_classify_mdb(mdb->addr);
1726 ether_addr_copy(mc->addr, mdb->addr);
1729 list_add_tail(&mc->list, &ocelot->multicast);
1731 /* Existing entry. Clean up the current port mask from
1732 * hardware now, because we'll be modifying it.
1734 ocelot_pgid_free(ocelot, mc->pgid);
1735 ocelot_encode_ports_to_mdb(addr, mc);
1736 ocelot_mact_forget(ocelot, addr, vid);
1739 mc->ports |= BIT(port);
1741 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1743 dev_err(ocelot->dev,
1744 "Cannot allocate PGID for mdb %pM vid %d\n",
1746 devm_kfree(ocelot->dev, mc);
1747 return PTR_ERR(pgid);
1751 ocelot_encode_ports_to_mdb(addr, mc);
1753 if (mc->entry_type != ENTRYTYPE_MACv4 &&
1754 mc->entry_type != ENTRYTYPE_MACv6)
1755 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1758 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1761 EXPORT_SYMBOL(ocelot_port_mdb_add);
1763 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1764 const struct switchdev_obj_port_mdb *mdb)
1766 unsigned char addr[ETH_ALEN];
1767 struct ocelot_multicast *mc;
1768 struct ocelot_pgid *pgid;
1771 if (port == ocelot->npi)
1772 port = ocelot->num_phys_ports;
1774 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1778 ocelot_encode_ports_to_mdb(addr, mc);
1779 ocelot_mact_forget(ocelot, addr, vid);
1781 ocelot_pgid_free(ocelot, mc->pgid);
1782 mc->ports &= ~BIT(port);
1784 list_del(&mc->list);
1785 devm_kfree(ocelot->dev, mc);
1789 /* We have a PGID with fewer ports now */
1790 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1792 return PTR_ERR(pgid);
1795 ocelot_encode_ports_to_mdb(addr, mc);
1797 if (mc->entry_type != ENTRYTYPE_MACv4 &&
1798 mc->entry_type != ENTRYTYPE_MACv6)
1799 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1802 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1805 EXPORT_SYMBOL(ocelot_port_mdb_del);
1807 void ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1808 struct net_device *bridge)
1810 struct ocelot_port *ocelot_port = ocelot->ports[port];
1812 ocelot_port->bridge = bridge;
1814 ocelot_apply_bridge_fwd_mask(ocelot);
1816 EXPORT_SYMBOL(ocelot_port_bridge_join);
1818 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1819 struct net_device *bridge)
1821 struct ocelot_port *ocelot_port = ocelot->ports[port];
1823 ocelot_port->bridge = NULL;
1825 ocelot_port_set_pvid(ocelot, port, NULL);
1826 ocelot_port_manage_port_tag(ocelot, port);
1827 ocelot_apply_bridge_fwd_mask(ocelot);
1829 EXPORT_SYMBOL(ocelot_port_bridge_leave);
1831 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1833 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
1836 /* Reset destination and aggregation PGIDS */
1837 for_each_unicast_dest_pgid(ocelot, port)
1838 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1840 for_each_aggr_pgid(ocelot, i)
1841 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1844 /* The visited ports bitmask holds the list of ports offloading any
1845 * bonding interface. Initially we mark all these ports as unvisited,
1846 * then every time we visit a port in this bitmask, we know that it is
1847 * the lowest numbered port, i.e. the one whose logical ID == physical
1848 * port ID == LAG ID. So we mark as visited all further ports in the
1849 * bitmask that are offloading the same bonding interface. This way,
1850 * we set up the aggregation PGIDs only once per bonding interface.
1852 for (port = 0; port < ocelot->num_phys_ports; port++) {
1853 struct ocelot_port *ocelot_port = ocelot->ports[port];
1855 if (!ocelot_port || !ocelot_port->bond)
1858 visited &= ~BIT(port);
1861 /* Now, set PGIDs for each active LAG */
1862 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1863 struct net_device *bond = ocelot->ports[lag]->bond;
1864 int num_active_ports = 0;
1865 unsigned long bond_mask;
1868 if (!bond || (visited & BIT(lag)))
1871 bond_mask = ocelot_get_bond_mask(ocelot, bond, true);
1873 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1875 ocelot_write_rix(ocelot, bond_mask,
1876 ANA_PGID_PGID, port);
1877 aggr_idx[num_active_ports++] = port;
1880 for_each_aggr_pgid(ocelot, i) {
1883 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1885 /* Don't do division by zero if there was no active
1886 * port. Just make all aggregation codes zero.
1888 if (num_active_ports)
1889 ac |= BIT(aggr_idx[i % num_active_ports]);
1890 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1893 /* Mark all ports in the same LAG as visited to avoid applying
1894 * the same config again.
1896 for (port = lag; port < ocelot->num_phys_ports; port++) {
1897 struct ocelot_port *ocelot_port = ocelot->ports[port];
1902 if (ocelot_port->bond == bond)
1903 visited |= BIT(port);
1908 /* When offloading a bonding interface, the switch ports configured under the
1909 * same bond must have the same logical port ID, equal to the physical port ID
1910 * of the lowest numbered physical port in that bond. Otherwise, in standalone/
1911 * bridged mode, each port has a logical port ID equal to its physical port ID.
1913 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
1917 for (port = 0; port < ocelot->num_phys_ports; port++) {
1918 struct ocelot_port *ocelot_port = ocelot->ports[port];
1919 struct net_device *bond;
1924 bond = ocelot_port->bond;
1926 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond,
1929 ocelot_rmw_gix(ocelot,
1930 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1931 ANA_PORT_PORT_CFG_PORTID_VAL_M,
1932 ANA_PORT_PORT_CFG, port);
1934 ocelot_rmw_gix(ocelot,
1935 ANA_PORT_PORT_CFG_PORTID_VAL(port),
1936 ANA_PORT_PORT_CFG_PORTID_VAL_M,
1937 ANA_PORT_PORT_CFG, port);
1942 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1943 struct net_device *bond,
1944 struct netdev_lag_upper_info *info)
1946 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
1949 ocelot->ports[port]->bond = bond;
1951 ocelot_setup_logical_port_ids(ocelot);
1952 ocelot_apply_bridge_fwd_mask(ocelot);
1953 ocelot_set_aggr_pgids(ocelot);
1957 EXPORT_SYMBOL(ocelot_port_lag_join);
1959 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1960 struct net_device *bond)
1962 ocelot->ports[port]->bond = NULL;
1964 ocelot_setup_logical_port_ids(ocelot);
1965 ocelot_apply_bridge_fwd_mask(ocelot);
1966 ocelot_set_aggr_pgids(ocelot);
1968 EXPORT_SYMBOL(ocelot_port_lag_leave);
1970 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
1972 struct ocelot_port *ocelot_port = ocelot->ports[port];
1974 ocelot_port->lag_tx_active = lag_tx_active;
1976 /* Rebalance the LAGs */
1977 ocelot_set_aggr_pgids(ocelot);
1979 EXPORT_SYMBOL(ocelot_port_lag_change);
1981 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
1982 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
1983 * In the special case that it's the NPI port that we're configuring, the
1984 * length of the tag and optional prefix needs to be accounted for privately,
1985 * in order to be able to sustain communication at the requested @sdu.
1987 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
1989 struct ocelot_port *ocelot_port = ocelot->ports[port];
1990 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
1991 int pause_start, pause_stop;
1994 if (port == ocelot->npi) {
1995 maxlen += OCELOT_TAG_LEN;
1997 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1998 maxlen += OCELOT_SHORT_PREFIX_LEN;
1999 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2000 maxlen += OCELOT_LONG_PREFIX_LEN;
2003 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
2005 /* Set Pause watermark hysteresis */
2006 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
2007 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
2008 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
2010 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
2013 /* Tail dropping watermarks */
2014 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
2015 OCELOT_BUFFER_CELL_SZ;
2016 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
2017 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
2018 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
2020 EXPORT_SYMBOL(ocelot_port_set_maxlen);
2022 int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
2024 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
2026 if (port == ocelot->npi) {
2027 max_mtu -= OCELOT_TAG_LEN;
2029 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2030 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
2031 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2032 max_mtu -= OCELOT_LONG_PREFIX_LEN;
2037 EXPORT_SYMBOL(ocelot_get_max_mtu);
2039 static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
2042 struct ocelot_port *ocelot_port = ocelot->ports[port];
2046 val = ANA_PORT_PORT_CFG_LEARN_ENA;
2048 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
2049 ANA_PORT_PORT_CFG, port);
2051 ocelot_port->learn_ena = enabled;
2054 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
2062 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
2065 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
2073 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
2076 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
2084 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
2087 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
2088 struct switchdev_brport_flags flags)
2090 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2096 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
2098 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
2099 struct switchdev_brport_flags flags)
2101 if (flags.mask & BR_LEARNING)
2102 ocelot_port_set_learning(ocelot, port,
2103 !!(flags.val & BR_LEARNING));
2105 if (flags.mask & BR_FLOOD)
2106 ocelot_port_set_ucast_flood(ocelot, port,
2107 !!(flags.val & BR_FLOOD));
2109 if (flags.mask & BR_MCAST_FLOOD)
2110 ocelot_port_set_mcast_flood(ocelot, port,
2111 !!(flags.val & BR_MCAST_FLOOD));
2113 if (flags.mask & BR_BCAST_FLOOD)
2114 ocelot_port_set_bcast_flood(ocelot, port,
2115 !!(flags.val & BR_BCAST_FLOOD));
2117 EXPORT_SYMBOL(ocelot_port_bridge_flags);
2119 void ocelot_init_port(struct ocelot *ocelot, int port)
2121 struct ocelot_port *ocelot_port = ocelot->ports[port];
2123 skb_queue_head_init(&ocelot_port->tx_skbs);
2125 /* Basic L2 initialization */
2128 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
2129 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
2131 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
2134 /* Load seed (0) and set MAC HDX late collision */
2135 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
2136 DEV_MAC_HDX_CFG_SEED_LOAD,
2139 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
2142 /* Set Max Length and maximum tags allowed */
2143 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
2144 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
2145 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
2146 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
2147 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
2150 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
2151 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
2152 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
2154 /* Enable transmission of pause frames */
2155 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
2157 /* Drop frames with multicast source address */
2158 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2159 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2160 ANA_PORT_DROP_CFG, port);
2162 /* Set default VLAN and tag type to 8021Q. */
2163 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
2164 REW_PORT_VLAN_CFG_PORT_TPID_M,
2165 REW_PORT_VLAN_CFG, port);
2167 /* Disable source address learning for standalone mode */
2168 ocelot_port_set_learning(ocelot, port, false);
2170 /* Set the port's initial logical port ID value, enable receiving
2171 * frames on it, and configure the MAC address learning type to
2174 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
2175 ANA_PORT_PORT_CFG_RECV_ENA |
2176 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2177 ANA_PORT_PORT_CFG, port);
2179 /* Enable vcap lookups */
2180 ocelot_vcap_enable(ocelot, port);
2182 EXPORT_SYMBOL(ocelot_init_port);
2184 /* Configure and enable the CPU port module, which is a set of queues
2185 * accessible through register MMIO, frame DMA or Ethernet (in case
2186 * NPI mode is used).
2188 static void ocelot_cpu_port_init(struct ocelot *ocelot)
2190 int cpu = ocelot->num_phys_ports;
2192 /* The unicast destination PGID for the CPU port module is unused */
2193 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2194 /* Instead set up a multicast destination PGID for traffic copied to
2195 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
2196 * addresses will be copied to the CPU via this PGID.
2198 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2199 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2200 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2201 ANA_PORT_PORT_CFG, cpu);
2203 /* Enable CPU port module */
2204 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
2205 /* CPU port Injection/Extraction configuration */
2206 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
2207 OCELOT_TAG_PREFIX_NONE);
2208 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
2209 OCELOT_TAG_PREFIX_NONE);
2211 /* Configure the CPU port to be VLAN aware */
2212 ocelot_write_gix(ocelot,
2213 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_VLAN_UNAWARE_PVID) |
2214 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
2215 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
2216 ANA_PORT_VLAN_CFG, cpu);
2219 static void ocelot_detect_features(struct ocelot *ocelot)
2223 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
2224 * the number of 240-byte free memory words (aka 4-cell chunks) and not
2225 * 192 bytes as the documentation incorrectly says.
2227 mmgt = ocelot_read(ocelot, SYS_MMGT);
2228 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
2230 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
2231 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
2234 int ocelot_init(struct ocelot *ocelot)
2236 char queue_name[32];
2240 if (ocelot->ops->reset) {
2241 ret = ocelot->ops->reset(ocelot);
2243 dev_err(ocelot->dev, "Switch reset failed\n");
2248 ocelot->stats = devm_kcalloc(ocelot->dev,
2249 ocelot->num_phys_ports * ocelot->num_stats,
2250 sizeof(u64), GFP_KERNEL);
2254 mutex_init(&ocelot->stats_lock);
2255 mutex_init(&ocelot->ptp_lock);
2256 mutex_init(&ocelot->mact_lock);
2257 spin_lock_init(&ocelot->ptp_clock_lock);
2258 spin_lock_init(&ocelot->ts_id_lock);
2259 snprintf(queue_name, sizeof(queue_name), "%s-stats",
2260 dev_name(ocelot->dev));
2261 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
2262 if (!ocelot->stats_queue)
2265 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
2267 destroy_workqueue(ocelot->stats_queue);
2271 INIT_LIST_HEAD(&ocelot->multicast);
2272 INIT_LIST_HEAD(&ocelot->pgids);
2273 INIT_LIST_HEAD(&ocelot->vlans);
2274 ocelot_detect_features(ocelot);
2275 ocelot_mact_init(ocelot);
2276 ocelot_vlan_init(ocelot);
2277 ocelot_vcap_init(ocelot);
2278 ocelot_cpu_port_init(ocelot);
2280 for (port = 0; port < ocelot->num_phys_ports; port++) {
2281 /* Clear all counters (5 groups) */
2282 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2283 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
2287 /* Only use S-Tag */
2288 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
2290 /* Aggregation mode */
2291 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
2292 ANA_AGGR_CFG_AC_DMAC_ENA |
2293 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
2294 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
2295 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
2296 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
2299 /* Set MAC age time to default value. The entry is aged after
2302 ocelot_write(ocelot,
2303 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
2306 /* Disable learning for frames discarded by VLAN ingress filtering */
2307 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
2309 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2310 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
2311 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
2313 /* Setup flooding PGIDs */
2314 for (i = 0; i < ocelot->num_flooding_pgids; i++)
2315 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
2316 ANA_FLOODING_FLD_BROADCAST(PGID_BC) |
2317 ANA_FLOODING_FLD_UNICAST(PGID_UC),
2319 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
2320 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
2321 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
2322 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
2325 for (port = 0; port < ocelot->num_phys_ports; port++) {
2326 /* Transmit the frame to the local port. */
2327 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2328 /* Do not forward BPDU frames to the front ports. */
2329 ocelot_write_gix(ocelot,
2330 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2331 ANA_PORT_CPU_FWD_BPDU_CFG,
2333 /* Ensure bridging is disabled */
2334 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2337 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
2338 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2340 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2343 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE);
2345 /* Allow broadcast and unknown L2 multicast to the CPU. */
2346 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2347 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2348 ANA_PGID_PGID, PGID_MC);
2349 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2350 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2351 ANA_PGID_PGID, PGID_BC);
2352 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2353 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2355 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2356 * registers endianness.
2358 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2359 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
2360 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
2361 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
2362 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
2363 ANA_CPUQ_CFG_CPUQ_LRN(2) |
2364 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
2365 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
2366 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
2367 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
2368 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
2369 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
2370 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
2371 for (i = 0; i < 16; i++)
2372 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
2373 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
2374 ANA_CPUQ_8021_CFG, i);
2376 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
2377 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
2378 OCELOT_STATS_CHECK_DELAY);
2382 EXPORT_SYMBOL(ocelot_init);
2384 void ocelot_deinit(struct ocelot *ocelot)
2386 cancel_delayed_work(&ocelot->stats_work);
2387 destroy_workqueue(ocelot->stats_queue);
2388 destroy_workqueue(ocelot->owq);
2389 mutex_destroy(&ocelot->stats_lock);
2391 EXPORT_SYMBOL(ocelot_deinit);
2393 void ocelot_deinit_port(struct ocelot *ocelot, int port)
2395 struct ocelot_port *ocelot_port = ocelot->ports[port];
2397 skb_queue_purge(&ocelot_port->tx_skbs);
2399 EXPORT_SYMBOL(ocelot_deinit_port);
2401 MODULE_LICENSE("Dual MIT/GPL");