1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/if_bridge.h>
8 #include <soc/mscc/ocelot_vcap.h>
10 #include "ocelot_vcap.h"
12 #define TABLE_UPDATE_SLEEP_US 10
13 #define TABLE_UPDATE_TIMEOUT_US 100000
15 struct ocelot_mact_entry {
18 enum macaccess_entry_type type;
21 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
23 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
26 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
30 return readx_poll_timeout(ocelot_mact_read_macaccess,
32 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
34 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
37 static void ocelot_mact_select(struct ocelot *ocelot,
38 const unsigned char mac[ETH_ALEN],
41 u32 macl = 0, mach = 0;
43 /* Set the MAC address to handle and the vlan associated in a format
44 * understood by the hardware.
54 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
55 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
59 int ocelot_mact_learn(struct ocelot *ocelot, int port,
60 const unsigned char mac[ETH_ALEN],
61 unsigned int vid, enum macaccess_entry_type type)
63 u32 cmd = ANA_TABLES_MACACCESS_VALID |
64 ANA_TABLES_MACACCESS_DEST_IDX(port) |
65 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
66 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
67 unsigned int mc_ports;
69 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
70 if (type == ENTRYTYPE_MACv4)
71 mc_ports = (mac[1] << 8) | mac[2];
72 else if (type == ENTRYTYPE_MACv6)
73 mc_ports = (mac[0] << 8) | mac[1];
77 if (mc_ports & BIT(ocelot->num_phys_ports))
78 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
80 ocelot_mact_select(ocelot, mac, vid);
82 /* Issue a write command */
83 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
85 return ocelot_mact_wait_for_completion(ocelot);
87 EXPORT_SYMBOL(ocelot_mact_learn);
89 int ocelot_mact_forget(struct ocelot *ocelot,
90 const unsigned char mac[ETH_ALEN], unsigned int vid)
92 ocelot_mact_select(ocelot, mac, vid);
94 /* Issue a forget command */
96 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
97 ANA_TABLES_MACACCESS);
99 return ocelot_mact_wait_for_completion(ocelot);
101 EXPORT_SYMBOL(ocelot_mact_forget);
103 static void ocelot_mact_init(struct ocelot *ocelot)
105 /* Configure the learning mode entries attributes:
106 * - Do not copy the frame to the CPU extraction queues.
107 * - Use the vlan and mac_cpoy for dmac lookup.
109 ocelot_rmw(ocelot, 0,
110 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
111 | ANA_AGENCTRL_LEARN_FWD_KILL
112 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
115 /* Clear the MAC table */
116 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
119 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
121 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
122 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
123 ANA_PORT_VCAP_S2_CFG, port);
125 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
126 ANA_PORT_VCAP_CFG, port);
128 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
133 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
135 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
138 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
142 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
145 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
146 ANA_TABLES_VLANACCESS_CMD_IDLE,
147 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
150 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
152 /* Select the VID to configure */
153 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
154 ANA_TABLES_VLANTIDX);
155 /* Set the vlan port members mask and issue a write command */
156 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
157 ANA_TABLES_VLANACCESS_CMD_WRITE,
158 ANA_TABLES_VLANACCESS);
160 return ocelot_vlant_wait_for_completion(ocelot);
163 static void ocelot_port_set_native_vlan(struct ocelot *ocelot, int port,
164 struct ocelot_vlan native_vlan)
166 struct ocelot_port *ocelot_port = ocelot->ports[port];
169 ocelot_port->native_vlan = native_vlan;
171 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(native_vlan.vid),
172 REW_PORT_VLAN_CFG_PORT_VID_M,
173 REW_PORT_VLAN_CFG, port);
175 if (ocelot_port->vlan_aware) {
176 if (native_vlan.valid)
177 /* Tag all frames except when VID == DEFAULT_VLAN */
178 val = REW_TAG_CFG_TAG_CFG(1);
181 val = REW_TAG_CFG_TAG_CFG(3);
183 /* Port tagging disabled. */
184 val = REW_TAG_CFG_TAG_CFG(0);
186 ocelot_rmw_gix(ocelot, val,
187 REW_TAG_CFG_TAG_CFG_M,
191 /* Default vlan to clasify for untagged frames (may be zero) */
192 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port,
193 struct ocelot_vlan pvid_vlan)
195 struct ocelot_port *ocelot_port = ocelot->ports[port];
198 ocelot_port->pvid_vlan = pvid_vlan;
200 if (!ocelot_port->vlan_aware)
203 ocelot_rmw_gix(ocelot,
204 ANA_PORT_VLAN_CFG_VLAN_VID(pvid_vlan.vid),
205 ANA_PORT_VLAN_CFG_VLAN_VID_M,
206 ANA_PORT_VLAN_CFG, port);
208 /* If there's no pvid, we should drop not only untagged traffic (which
209 * happens automatically), but also 802.1p traffic which gets
210 * classified to VLAN 0, but that is always in our RX filter, so it
211 * would get accepted were it not for this setting.
213 if (!pvid_vlan.valid && ocelot_port->vlan_aware)
214 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
215 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
217 ocelot_rmw_gix(ocelot, val,
218 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
219 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
220 ANA_PORT_DROP_CFG, port);
223 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
226 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
227 struct ocelot_port *ocelot_port = ocelot->ports[port];
228 struct ocelot_vcap_filter *filter;
231 list_for_each_entry(filter, &block->rules, list) {
232 if (filter->ingress_port_mask & BIT(port) &&
233 filter->action.vid_replace_ena) {
235 "Cannot change VLAN state with vlan modify rules active\n");
240 ocelot_port->vlan_aware = vlan_aware;
243 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
244 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
247 ocelot_rmw_gix(ocelot, val,
248 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
249 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
250 ANA_PORT_VLAN_CFG, port);
252 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
253 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->native_vlan);
257 EXPORT_SYMBOL(ocelot_port_vlan_filtering);
259 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
262 struct ocelot_port *ocelot_port = ocelot->ports[port];
264 /* Deny changing the native VLAN, but always permit deleting it */
265 if (untagged && ocelot_port->native_vlan.vid != vid &&
266 ocelot_port->native_vlan.valid) {
268 "Port already has a native VLAN: %d\n",
269 ocelot_port->native_vlan.vid);
275 EXPORT_SYMBOL(ocelot_vlan_prepare);
277 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
282 /* Make the port a member of the VLAN */
283 ocelot->vlan_mask[vid] |= BIT(port);
284 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
288 /* Default ingress vlan classification */
290 struct ocelot_vlan pvid_vlan;
293 pvid_vlan.valid = true;
294 ocelot_port_set_pvid(ocelot, port, pvid_vlan);
297 /* Untagged egress vlan clasification */
299 struct ocelot_vlan native_vlan;
301 native_vlan.vid = vid;
302 native_vlan.valid = true;
303 ocelot_port_set_native_vlan(ocelot, port, native_vlan);
308 EXPORT_SYMBOL(ocelot_vlan_add);
310 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
312 struct ocelot_port *ocelot_port = ocelot->ports[port];
315 /* Stop the port from being a member of the vlan */
316 ocelot->vlan_mask[vid] &= ~BIT(port);
317 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
322 if (ocelot_port->pvid_vlan.vid == vid) {
323 struct ocelot_vlan pvid_vlan = {0};
325 ocelot_port_set_pvid(ocelot, port, pvid_vlan);
329 if (ocelot_port->native_vlan.vid == vid) {
330 struct ocelot_vlan native_vlan = {0};
332 ocelot_port_set_native_vlan(ocelot, port, native_vlan);
337 EXPORT_SYMBOL(ocelot_vlan_del);
339 static void ocelot_vlan_init(struct ocelot *ocelot)
343 /* Clear VLAN table, by default all ports are members of all VLANs */
344 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
345 ANA_TABLES_VLANACCESS);
346 ocelot_vlant_wait_for_completion(ocelot);
348 /* Configure the port VLAN memberships */
349 for (vid = 1; vid < VLAN_N_VID; vid++) {
350 ocelot->vlan_mask[vid] = 0;
351 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
354 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
355 * traffic. It is added automatically if 8021q module is loaded, but
356 * we can't rely on it since module may be not loaded.
358 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
359 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
361 /* Set vlan ingress filter mask to all ports but the CPU port by
364 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
367 for (port = 0; port < ocelot->num_phys_ports; port++) {
368 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
369 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
373 void ocelot_adjust_link(struct ocelot *ocelot, int port,
374 struct phy_device *phydev)
376 struct ocelot_port *ocelot_port = ocelot->ports[port];
379 switch (phydev->speed) {
381 speed = OCELOT_SPEED_10;
384 speed = OCELOT_SPEED_100;
387 speed = OCELOT_SPEED_1000;
388 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
391 speed = OCELOT_SPEED_2500;
392 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
395 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n",
396 port, phydev->speed);
400 phy_print_status(phydev);
405 /* Only full duplex supported for now */
406 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
407 mode, DEV_MAC_MODE_CFG);
409 /* Disable HDX fast control */
410 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
413 /* SGMII only for now */
414 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
416 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
419 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
421 /* No aneg on SGMII */
422 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
425 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
427 /* Enable MAC module */
428 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
429 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
431 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
433 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
437 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
438 ANA_PFC_PFC_CFG, port);
440 /* Core: Enable port for frame transfer */
441 ocelot_fields_write(ocelot, port,
442 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
445 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
446 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
447 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
448 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
449 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
450 SYS_MAC_FC_CFG, port);
451 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
453 EXPORT_SYMBOL(ocelot_adjust_link);
455 void ocelot_port_enable(struct ocelot *ocelot, int port,
456 struct phy_device *phy)
458 /* Enable receiving frames on the port, and activate auto-learning of
461 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
462 ANA_PORT_PORT_CFG_RECV_ENA |
463 ANA_PORT_PORT_CFG_PORTID_VAL(port),
464 ANA_PORT_PORT_CFG, port);
466 EXPORT_SYMBOL(ocelot_port_enable);
468 void ocelot_port_disable(struct ocelot *ocelot, int port)
470 struct ocelot_port *ocelot_port = ocelot->ports[port];
472 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG);
473 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
475 EXPORT_SYMBOL(ocelot_port_disable);
477 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port,
478 struct sk_buff *clone)
480 struct ocelot_port *ocelot_port = ocelot->ports[port];
482 spin_lock(&ocelot_port->ts_id_lock);
484 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS;
485 /* Store timestamp ID in cb[0] of sk_buff */
486 clone->cb[0] = ocelot_port->ts_id;
487 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4;
488 skb_queue_tail(&ocelot_port->tx_skbs, clone);
490 spin_unlock(&ocelot_port->ts_id_lock);
492 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb);
494 static void ocelot_get_hwtimestamp(struct ocelot *ocelot,
495 struct timespec64 *ts)
500 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
502 /* Read current PTP time to get seconds */
503 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
505 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
506 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
507 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
508 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
510 /* Read packet HW timestamp from FIFO */
511 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP);
512 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val);
514 /* Sec has incremented since the ts was registered */
515 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC))
518 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
521 void ocelot_get_txtstamp(struct ocelot *ocelot)
523 int budget = OCELOT_PTP_QUEUE_SZ;
526 struct sk_buff *skb, *skb_tmp, *skb_match = NULL;
527 struct skb_shared_hwtstamps shhwtstamps;
528 struct ocelot_port *port;
529 struct timespec64 ts;
533 val = ocelot_read(ocelot, SYS_PTP_STATUS);
535 /* Check if a timestamp can be retrieved */
536 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD))
539 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL);
541 /* Retrieve the ts ID and Tx port */
542 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val);
543 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val);
545 /* Retrieve its associated skb */
546 port = ocelot->ports[txport];
548 spin_lock_irqsave(&port->tx_skbs.lock, flags);
550 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) {
551 if (skb->cb[0] != id)
553 __skb_unlink(skb, &port->tx_skbs);
558 spin_unlock_irqrestore(&port->tx_skbs.lock, flags);
560 /* Get the h/w timestamp */
561 ocelot_get_hwtimestamp(ocelot, &ts);
563 if (unlikely(!skb_match))
566 /* Set the timestamp into the skb */
567 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
568 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
569 skb_complete_tx_timestamp(skb_match, &shhwtstamps);
572 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT);
575 EXPORT_SYMBOL(ocelot_get_txtstamp);
577 int ocelot_fdb_add(struct ocelot *ocelot, int port,
578 const unsigned char *addr, u16 vid)
582 if (port == ocelot->npi)
585 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED);
587 EXPORT_SYMBOL(ocelot_fdb_add);
589 int ocelot_fdb_del(struct ocelot *ocelot, int port,
590 const unsigned char *addr, u16 vid)
592 return ocelot_mact_forget(ocelot, addr, vid);
594 EXPORT_SYMBOL(ocelot_fdb_del);
596 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid,
597 bool is_static, void *data)
599 struct ocelot_dump_ctx *dump = data;
600 u32 portid = NETLINK_CB(dump->cb->skb).portid;
601 u32 seq = dump->cb->nlh->nlmsg_seq;
602 struct nlmsghdr *nlh;
605 if (dump->idx < dump->cb->args[2])
608 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
609 sizeof(*ndm), NLM_F_MULTI);
613 ndm = nlmsg_data(nlh);
614 ndm->ndm_family = AF_BRIDGE;
617 ndm->ndm_flags = NTF_SELF;
619 ndm->ndm_ifindex = dump->dev->ifindex;
620 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
622 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
623 goto nla_put_failure;
625 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
626 goto nla_put_failure;
628 nlmsg_end(dump->skb, nlh);
635 nlmsg_cancel(dump->skb, nlh);
638 EXPORT_SYMBOL(ocelot_port_fdb_do_dump);
640 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
641 struct ocelot_mact_entry *entry)
643 u32 val, dst, macl, mach;
646 /* Set row and column to read from */
647 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
648 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
650 /* Issue a read command */
652 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
653 ANA_TABLES_MACACCESS);
655 if (ocelot_mact_wait_for_completion(ocelot))
658 /* Read the entry flags */
659 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
660 if (!(val & ANA_TABLES_MACACCESS_VALID))
663 /* If the entry read has another port configured as its destination,
666 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
670 /* Get the entry's MAC address and VLAN id */
671 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
672 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
674 mac[0] = (mach >> 8) & 0xff;
675 mac[1] = (mach >> 0) & 0xff;
676 mac[2] = (macl >> 24) & 0xff;
677 mac[3] = (macl >> 16) & 0xff;
678 mac[4] = (macl >> 8) & 0xff;
679 mac[5] = (macl >> 0) & 0xff;
681 entry->vid = (mach >> 16) & 0xfff;
682 ether_addr_copy(entry->mac, mac);
687 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
688 dsa_fdb_dump_cb_t *cb, void *data)
692 /* Loop through all the mac tables entries. */
693 for (i = 0; i < ocelot->num_mact_rows; i++) {
694 for (j = 0; j < 4; j++) {
695 struct ocelot_mact_entry entry;
699 ret = ocelot_mact_read(ocelot, port, i, j, &entry);
700 /* If the entry is invalid (wrong port, invalid...),
708 is_static = (entry.type == ENTRYTYPE_LOCKED);
710 ret = cb(entry.mac, entry.vid, is_static, data);
718 EXPORT_SYMBOL(ocelot_fdb_dump);
720 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr)
722 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
723 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
725 EXPORT_SYMBOL(ocelot_hwstamp_get);
727 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr)
729 struct ocelot_port *ocelot_port = ocelot->ports[port];
730 struct hwtstamp_config cfg;
732 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
735 /* reserved for future extensions */
739 /* Tx type sanity check */
740 switch (cfg.tx_type) {
742 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
744 case HWTSTAMP_TX_ONESTEP_SYNC:
745 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
746 * need to update the origin time.
748 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
750 case HWTSTAMP_TX_OFF:
751 ocelot_port->ptp_cmd = 0;
757 mutex_lock(&ocelot->ptp_lock);
759 switch (cfg.rx_filter) {
760 case HWTSTAMP_FILTER_NONE:
762 case HWTSTAMP_FILTER_ALL:
763 case HWTSTAMP_FILTER_SOME:
764 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
765 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
766 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
767 case HWTSTAMP_FILTER_NTP_ALL:
768 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
769 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
770 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
771 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
772 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
773 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
774 case HWTSTAMP_FILTER_PTP_V2_EVENT:
775 case HWTSTAMP_FILTER_PTP_V2_SYNC:
776 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
777 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
780 mutex_unlock(&ocelot->ptp_lock);
784 /* Commit back the result & save it */
785 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
786 mutex_unlock(&ocelot->ptp_lock);
788 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
790 EXPORT_SYMBOL(ocelot_hwstamp_set);
792 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data)
796 if (sset != ETH_SS_STATS)
799 for (i = 0; i < ocelot->num_stats; i++)
800 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
803 EXPORT_SYMBOL(ocelot_get_strings);
805 static void ocelot_update_stats(struct ocelot *ocelot)
809 mutex_lock(&ocelot->stats_lock);
811 for (i = 0; i < ocelot->num_phys_ports; i++) {
812 /* Configure the port to read the stats from */
813 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
815 for (j = 0; j < ocelot->num_stats; j++) {
817 unsigned int idx = i * ocelot->num_stats + j;
819 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
820 ocelot->stats_layout[j].offset);
822 if (val < (ocelot->stats[idx] & U32_MAX))
823 ocelot->stats[idx] += (u64)1 << 32;
825 ocelot->stats[idx] = (ocelot->stats[idx] &
826 ~(u64)U32_MAX) + val;
830 mutex_unlock(&ocelot->stats_lock);
833 static void ocelot_check_stats_work(struct work_struct *work)
835 struct delayed_work *del_work = to_delayed_work(work);
836 struct ocelot *ocelot = container_of(del_work, struct ocelot,
839 ocelot_update_stats(ocelot);
841 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
842 OCELOT_STATS_CHECK_DELAY);
845 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
849 /* check and update now */
850 ocelot_update_stats(ocelot);
852 /* Copy all counters */
853 for (i = 0; i < ocelot->num_stats; i++)
854 *data++ = ocelot->stats[port * ocelot->num_stats + i];
856 EXPORT_SYMBOL(ocelot_get_ethtool_stats);
858 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
860 if (sset != ETH_SS_STATS)
863 return ocelot->num_stats;
865 EXPORT_SYMBOL(ocelot_get_sset_count);
867 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
868 struct ethtool_ts_info *info)
870 info->phc_index = ocelot->ptp_clock ?
871 ptp_clock_index(ocelot->ptp_clock) : -1;
872 if (info->phc_index == -1) {
873 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
874 SOF_TIMESTAMPING_RX_SOFTWARE |
875 SOF_TIMESTAMPING_SOFTWARE;
878 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
879 SOF_TIMESTAMPING_RX_SOFTWARE |
880 SOF_TIMESTAMPING_SOFTWARE |
881 SOF_TIMESTAMPING_TX_HARDWARE |
882 SOF_TIMESTAMPING_RX_HARDWARE |
883 SOF_TIMESTAMPING_RAW_HARDWARE;
884 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
885 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
886 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
890 EXPORT_SYMBOL(ocelot_get_ts_info);
892 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond)
897 for (port = 0; port < ocelot->num_phys_ports; port++) {
898 struct ocelot_port *ocelot_port = ocelot->ports[port];
903 if (ocelot_port->bond == bond)
910 static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot)
915 for (port = 0; port < ocelot->num_phys_ports; port++) {
916 struct ocelot_port *ocelot_port = ocelot->ports[port];
921 if (ocelot_port->is_dsa_8021q_cpu)
928 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot)
930 unsigned long cpu_fwd_mask;
933 /* If a DSA tag_8021q CPU exists, it needs to be included in the
934 * regular forwarding path of the front ports regardless of whether
935 * those are bridged or standalone.
936 * If DSA tag_8021q is not used, this returns 0, which is fine because
937 * the hardware-based CPU port module can be a destination for packets
938 * even if it isn't part of PGID_SRC.
940 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot);
942 /* Apply FWD mask. The loop is needed to add/remove the current port as
943 * a source for the other ports.
945 for (port = 0; port < ocelot->num_phys_ports; port++) {
946 struct ocelot_port *ocelot_port = ocelot->ports[port];
950 /* Unused ports can't send anywhere */
952 } else if (ocelot_port->is_dsa_8021q_cpu) {
953 /* The DSA tag_8021q CPU ports need to be able to
954 * forward packets to all other ports except for
957 mask = GENMASK(ocelot->num_phys_ports - 1, 0);
958 mask &= ~cpu_fwd_mask;
959 } else if (ocelot->bridge_fwd_mask & BIT(port)) {
962 mask = ocelot->bridge_fwd_mask & ~BIT(port);
964 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
965 unsigned long bond_mask = ocelot->lags[lag];
970 if (bond_mask & BIT(port)) {
976 /* Standalone ports forward only to DSA tag_8021q CPU
977 * ports (if those exist), or to the hardware CPU port
983 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
986 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask);
988 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
992 if (!(BIT(port) & ocelot->bridge_mask))
995 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
998 case BR_STATE_FORWARDING:
999 ocelot->bridge_fwd_mask |= BIT(port);
1001 case BR_STATE_LEARNING:
1002 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1006 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1007 ocelot->bridge_fwd_mask &= ~BIT(port);
1011 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port);
1013 ocelot_apply_bridge_fwd_mask(ocelot);
1015 EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
1017 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1019 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
1021 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
1022 * which is clearly not what our intention is. So avoid that.
1027 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
1029 EXPORT_SYMBOL(ocelot_set_ageing_time);
1031 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1032 const unsigned char *addr,
1035 struct ocelot_multicast *mc;
1037 list_for_each_entry(mc, &ocelot->multicast, list) {
1038 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1045 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
1047 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
1048 return ENTRYTYPE_MACv4;
1049 if (addr[0] == 0x33 && addr[1] == 0x33)
1050 return ENTRYTYPE_MACv6;
1051 return ENTRYTYPE_LOCKED;
1054 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
1055 unsigned long ports)
1057 struct ocelot_pgid *pgid;
1059 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL);
1061 return ERR_PTR(-ENOMEM);
1063 pgid->ports = ports;
1064 pgid->index = index;
1065 refcount_set(&pgid->refcount, 1);
1066 list_add_tail(&pgid->list, &ocelot->pgids);
1071 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
1073 if (!refcount_dec_and_test(&pgid->refcount))
1076 list_del(&pgid->list);
1080 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
1081 const struct ocelot_multicast *mc)
1083 struct ocelot_pgid *pgid;
1086 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
1087 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
1088 * destination mask table (PGID), the destination set is programmed as
1089 * part of the entry MAC address.", and the DEST_IDX is set to 0.
1091 if (mc->entry_type == ENTRYTYPE_MACv4 ||
1092 mc->entry_type == ENTRYTYPE_MACv6)
1093 return ocelot_pgid_alloc(ocelot, 0, mc->ports);
1095 list_for_each_entry(pgid, &ocelot->pgids, list) {
1096 /* When searching for a nonreserved multicast PGID, ignore the
1097 * dummy PGID of zero that we have for MACv4/MACv6 entries
1099 if (pgid->index && pgid->ports == mc->ports) {
1100 refcount_inc(&pgid->refcount);
1105 /* Search for a free index in the nonreserved multicast PGID area */
1106 for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
1109 list_for_each_entry(pgid, &ocelot->pgids, list) {
1110 if (pgid->index == index) {
1117 return ocelot_pgid_alloc(ocelot, index, mc->ports);
1120 return ERR_PTR(-ENOSPC);
1123 static void ocelot_encode_ports_to_mdb(unsigned char *addr,
1124 struct ocelot_multicast *mc)
1126 ether_addr_copy(addr, mc->addr);
1128 if (mc->entry_type == ENTRYTYPE_MACv4) {
1130 addr[1] = mc->ports >> 8;
1131 addr[2] = mc->ports & 0xff;
1132 } else if (mc->entry_type == ENTRYTYPE_MACv6) {
1133 addr[0] = mc->ports >> 8;
1134 addr[1] = mc->ports & 0xff;
1138 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1139 const struct switchdev_obj_port_mdb *mdb)
1141 unsigned char addr[ETH_ALEN];
1142 struct ocelot_multicast *mc;
1143 struct ocelot_pgid *pgid;
1146 if (port == ocelot->npi)
1147 port = ocelot->num_phys_ports;
1149 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1152 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1156 mc->entry_type = ocelot_classify_mdb(mdb->addr);
1157 ether_addr_copy(mc->addr, mdb->addr);
1160 list_add_tail(&mc->list, &ocelot->multicast);
1162 /* Existing entry. Clean up the current port mask from
1163 * hardware now, because we'll be modifying it.
1165 ocelot_pgid_free(ocelot, mc->pgid);
1166 ocelot_encode_ports_to_mdb(addr, mc);
1167 ocelot_mact_forget(ocelot, addr, vid);
1170 mc->ports |= BIT(port);
1172 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1174 dev_err(ocelot->dev,
1175 "Cannot allocate PGID for mdb %pM vid %d\n",
1177 devm_kfree(ocelot->dev, mc);
1178 return PTR_ERR(pgid);
1182 ocelot_encode_ports_to_mdb(addr, mc);
1184 if (mc->entry_type != ENTRYTYPE_MACv4 &&
1185 mc->entry_type != ENTRYTYPE_MACv6)
1186 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1189 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1192 EXPORT_SYMBOL(ocelot_port_mdb_add);
1194 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1195 const struct switchdev_obj_port_mdb *mdb)
1197 unsigned char addr[ETH_ALEN];
1198 struct ocelot_multicast *mc;
1199 struct ocelot_pgid *pgid;
1202 if (port == ocelot->npi)
1203 port = ocelot->num_phys_ports;
1205 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1209 ocelot_encode_ports_to_mdb(addr, mc);
1210 ocelot_mact_forget(ocelot, addr, vid);
1212 ocelot_pgid_free(ocelot, mc->pgid);
1213 mc->ports &= ~BIT(port);
1215 list_del(&mc->list);
1216 devm_kfree(ocelot->dev, mc);
1220 /* We have a PGID with fewer ports now */
1221 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1223 return PTR_ERR(pgid);
1226 ocelot_encode_ports_to_mdb(addr, mc);
1228 if (mc->entry_type != ENTRYTYPE_MACv4 &&
1229 mc->entry_type != ENTRYTYPE_MACv6)
1230 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1233 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1236 EXPORT_SYMBOL(ocelot_port_mdb_del);
1238 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1239 struct net_device *bridge)
1241 if (!ocelot->bridge_mask) {
1242 ocelot->hw_bridge_dev = bridge;
1244 if (ocelot->hw_bridge_dev != bridge)
1245 /* This is adding the port to a second bridge, this is
1250 ocelot->bridge_mask |= BIT(port);
1254 EXPORT_SYMBOL(ocelot_port_bridge_join);
1256 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1257 struct net_device *bridge)
1259 struct ocelot_vlan pvid = {0}, native_vlan = {0};
1262 ocelot->bridge_mask &= ~BIT(port);
1264 if (!ocelot->bridge_mask)
1265 ocelot->hw_bridge_dev = NULL;
1267 ret = ocelot_port_vlan_filtering(ocelot, port, false);
1271 ocelot_port_set_pvid(ocelot, port, pvid);
1272 ocelot_port_set_native_vlan(ocelot, port, native_vlan);
1276 EXPORT_SYMBOL(ocelot_port_bridge_leave);
1278 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1282 /* Reset destination and aggregation PGIDS */
1283 for_each_unicast_dest_pgid(ocelot, port)
1284 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1286 for_each_aggr_pgid(ocelot, i)
1287 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1290 /* Now, set PGIDs for each LAG */
1291 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1292 unsigned long bond_mask;
1296 bond_mask = ocelot->lags[lag];
1300 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1302 ocelot_write_rix(ocelot, bond_mask,
1303 ANA_PGID_PGID, port);
1304 aggr_idx[aggr_count] = port;
1308 for_each_aggr_pgid(ocelot, i) {
1311 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1313 ac |= BIT(aggr_idx[i % aggr_count]);
1314 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1319 static void ocelot_setup_lag(struct ocelot *ocelot, int lag)
1321 unsigned long bond_mask = ocelot->lags[lag];
1324 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) {
1325 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1327 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1329 /* Use lag port as logical port for port i */
1330 ocelot_write_gix(ocelot, port_cfg |
1331 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1332 ANA_PORT_PORT_CFG, p);
1336 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1337 struct net_device *bond,
1338 struct netdev_lag_upper_info *info)
1343 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
1346 ocelot->ports[port]->bond = bond;
1348 bond_mask = ocelot_get_bond_mask(ocelot, bond);
1350 lp = __ffs(bond_mask);
1352 /* If the new port is the lowest one, use it as the logical port from
1357 ocelot->lags[port] = bond_mask;
1358 bond_mask &= ~BIT(port);
1360 lp = __ffs(bond_mask);
1361 ocelot->lags[lp] = 0;
1365 ocelot->lags[lp] |= BIT(port);
1368 ocelot_setup_lag(ocelot, lag);
1369 ocelot_apply_bridge_fwd_mask(ocelot);
1370 ocelot_set_aggr_pgids(ocelot);
1374 EXPORT_SYMBOL(ocelot_port_lag_join);
1376 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1377 struct net_device *bond)
1382 ocelot->ports[port]->bond = NULL;
1384 /* Remove port from any lag */
1385 for (i = 0; i < ocelot->num_phys_ports; i++)
1386 ocelot->lags[i] &= ~BIT(port);
1388 /* if it was the logical port of the lag, move the lag config to the
1391 if (ocelot->lags[port]) {
1392 int n = __ffs(ocelot->lags[port]);
1394 ocelot->lags[n] = ocelot->lags[port];
1395 ocelot->lags[port] = 0;
1397 ocelot_setup_lag(ocelot, n);
1400 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
1401 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1402 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port),
1403 ANA_PORT_PORT_CFG, port);
1405 ocelot_apply_bridge_fwd_mask(ocelot);
1406 ocelot_set_aggr_pgids(ocelot);
1408 EXPORT_SYMBOL(ocelot_port_lag_leave);
1410 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
1411 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
1412 * In the special case that it's the NPI port that we're configuring, the
1413 * length of the tag and optional prefix needs to be accounted for privately,
1414 * in order to be able to sustain communication at the requested @sdu.
1416 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
1418 struct ocelot_port *ocelot_port = ocelot->ports[port];
1419 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
1420 int pause_start, pause_stop;
1423 if (port == ocelot->npi) {
1424 maxlen += OCELOT_TAG_LEN;
1426 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1427 maxlen += OCELOT_SHORT_PREFIX_LEN;
1428 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
1429 maxlen += OCELOT_LONG_PREFIX_LEN;
1432 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
1434 /* Set Pause watermark hysteresis */
1435 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
1436 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
1437 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
1439 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
1442 /* Tail dropping watermarks */
1443 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
1444 OCELOT_BUFFER_CELL_SZ;
1445 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
1446 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
1447 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
1449 EXPORT_SYMBOL(ocelot_port_set_maxlen);
1451 int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
1453 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
1455 if (port == ocelot->npi) {
1456 max_mtu -= OCELOT_TAG_LEN;
1458 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1459 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
1460 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
1461 max_mtu -= OCELOT_LONG_PREFIX_LEN;
1466 EXPORT_SYMBOL(ocelot_get_max_mtu);
1468 void ocelot_init_port(struct ocelot *ocelot, int port)
1470 struct ocelot_port *ocelot_port = ocelot->ports[port];
1472 skb_queue_head_init(&ocelot_port->tx_skbs);
1473 spin_lock_init(&ocelot_port->ts_id_lock);
1475 /* Basic L2 initialization */
1478 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
1479 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
1481 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
1484 /* Load seed (0) and set MAC HDX late collision */
1485 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
1486 DEV_MAC_HDX_CFG_SEED_LOAD,
1489 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
1492 /* Set Max Length and maximum tags allowed */
1493 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
1494 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
1495 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
1496 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
1497 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
1500 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
1501 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
1502 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
1504 /* Enable transmission of pause frames */
1505 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
1507 /* Drop frames with multicast source address */
1508 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
1509 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
1510 ANA_PORT_DROP_CFG, port);
1512 /* Set default VLAN and tag type to 8021Q. */
1513 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
1514 REW_PORT_VLAN_CFG_PORT_TPID_M,
1515 REW_PORT_VLAN_CFG, port);
1517 /* Enable vcap lookups */
1518 ocelot_vcap_enable(ocelot, port);
1520 EXPORT_SYMBOL(ocelot_init_port);
1522 /* Configure and enable the CPU port module, which is a set of queues
1523 * accessible through register MMIO, frame DMA or Ethernet (in case
1524 * NPI mode is used).
1526 static void ocelot_cpu_port_init(struct ocelot *ocelot)
1528 int cpu = ocelot->num_phys_ports;
1530 /* The unicast destination PGID for the CPU port module is unused */
1531 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
1532 /* Instead set up a multicast destination PGID for traffic copied to
1533 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
1534 * addresses will be copied to the CPU via this PGID.
1536 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
1537 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
1538 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
1539 ANA_PORT_PORT_CFG, cpu);
1541 /* Enable CPU port module */
1542 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
1543 /* CPU port Injection/Extraction configuration */
1544 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
1545 OCELOT_TAG_PREFIX_NONE);
1546 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
1547 OCELOT_TAG_PREFIX_NONE);
1549 /* Configure the CPU port to be VLAN aware */
1550 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
1551 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
1552 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
1553 ANA_PORT_VLAN_CFG, cpu);
1556 static void ocelot_detect_features(struct ocelot *ocelot)
1560 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
1561 * the number of 240-byte free memory words (aka 4-cell chunks) and not
1562 * 192 bytes as the documentation incorrectly says.
1564 mmgt = ocelot_read(ocelot, SYS_MMGT);
1565 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
1567 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
1568 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
1571 int ocelot_init(struct ocelot *ocelot)
1573 char queue_name[32];
1577 if (ocelot->ops->reset) {
1578 ret = ocelot->ops->reset(ocelot);
1580 dev_err(ocelot->dev, "Switch reset failed\n");
1585 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
1586 sizeof(u32), GFP_KERNEL);
1590 ocelot->stats = devm_kcalloc(ocelot->dev,
1591 ocelot->num_phys_ports * ocelot->num_stats,
1592 sizeof(u64), GFP_KERNEL);
1596 mutex_init(&ocelot->stats_lock);
1597 mutex_init(&ocelot->ptp_lock);
1598 spin_lock_init(&ocelot->ptp_clock_lock);
1599 snprintf(queue_name, sizeof(queue_name), "%s-stats",
1600 dev_name(ocelot->dev));
1601 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
1602 if (!ocelot->stats_queue)
1605 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
1607 destroy_workqueue(ocelot->stats_queue);
1611 INIT_LIST_HEAD(&ocelot->multicast);
1612 INIT_LIST_HEAD(&ocelot->pgids);
1613 ocelot_detect_features(ocelot);
1614 ocelot_mact_init(ocelot);
1615 ocelot_vlan_init(ocelot);
1616 ocelot_vcap_init(ocelot);
1617 ocelot_cpu_port_init(ocelot);
1619 for (port = 0; port < ocelot->num_phys_ports; port++) {
1620 /* Clear all counters (5 groups) */
1621 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
1622 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
1626 /* Only use S-Tag */
1627 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
1629 /* Aggregation mode */
1630 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
1631 ANA_AGGR_CFG_AC_DMAC_ENA |
1632 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
1633 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
1634 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
1635 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
1638 /* Set MAC age time to default value. The entry is aged after
1641 ocelot_write(ocelot,
1642 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
1645 /* Disable learning for frames discarded by VLAN ingress filtering */
1646 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
1648 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
1649 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
1650 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
1652 /* Setup flooding PGIDs */
1653 for (i = 0; i < ocelot->num_flooding_pgids; i++)
1654 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
1655 ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
1656 ANA_FLOODING_FLD_UNICAST(PGID_UC),
1658 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
1659 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
1660 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
1661 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
1664 for (port = 0; port < ocelot->num_phys_ports; port++) {
1665 /* Transmit the frame to the local port. */
1666 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1667 /* Do not forward BPDU frames to the front ports. */
1668 ocelot_write_gix(ocelot,
1669 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
1670 ANA_PORT_CPU_FWD_BPDU_CFG,
1672 /* Ensure bridging is disabled */
1673 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
1676 /* Allow broadcast MAC frames. */
1677 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
1678 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
1680 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
1682 ocelot_write_rix(ocelot,
1683 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
1684 ANA_PGID_PGID, PGID_MC);
1685 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
1686 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
1688 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
1689 * registers endianness.
1691 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
1692 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
1693 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
1694 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
1695 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
1696 ANA_CPUQ_CFG_CPUQ_LRN(2) |
1697 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
1698 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
1699 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
1700 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
1701 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
1702 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
1703 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
1704 for (i = 0; i < 16; i++)
1705 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
1706 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
1707 ANA_CPUQ_8021_CFG, i);
1709 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
1710 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1711 OCELOT_STATS_CHECK_DELAY);
1715 EXPORT_SYMBOL(ocelot_init);
1717 void ocelot_deinit(struct ocelot *ocelot)
1719 cancel_delayed_work(&ocelot->stats_work);
1720 destroy_workqueue(ocelot->stats_queue);
1721 destroy_workqueue(ocelot->owq);
1722 mutex_destroy(&ocelot->stats_lock);
1724 EXPORT_SYMBOL(ocelot_deinit);
1726 void ocelot_deinit_port(struct ocelot *ocelot, int port)
1728 struct ocelot_port *ocelot_port = ocelot->ports[port];
1730 skb_queue_purge(&ocelot_port->tx_skbs);
1732 EXPORT_SYMBOL(ocelot_deinit_port);
1734 MODULE_LICENSE("Dual MIT/GPL");