1 /* SPDX-License-Identifier: GPL-2.0+
2 * Microchip Sparx5 Switch driver
4 * Copyright (c) 2021 Microchip Technology Inc.
7 /* This file is autogenerated by cml-utils 2021-05-06 13:06:37 +0200.
8 * Commit ID: 9ae4ec441e25e4b9003f4e514df5cb12a36b84d3
11 #ifndef _SPARX5_MAIN_REGS_H_
12 #define _SPARX5_MAIN_REGS_H_
14 #include <linux/bitfield.h>
15 #include <linux/types.h>
16 #include <linux/bug.h>
21 TARGET_ANA_AC_POL = 4,
39 TARGET_PCS10G_BR = 132,
40 TARGET_PCS25G_BR = 144,
41 TARGET_PCS5G_BR = 160,
42 TARGET_PORT_CONF = 173,
48 TARGET_VCAP_SUPER = 326,
54 #define __REG(...) __VA_ARGS__
56 /* ANA_AC:RAM_CTRL:RAM_INIT */
57 #define ANA_AC_RAM_INIT __REG(TARGET_ANA_AC, 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4)
59 #define ANA_AC_RAM_INIT_RAM_INIT BIT(1)
60 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\
61 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
62 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\
63 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)
65 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK BIT(0)
66 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\
67 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
68 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\
69 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
71 /* ANA_AC:PS_COMMON:OWN_UPSID */
72 #define ANA_AC_OWN_UPSID(r) __REG(TARGET_ANA_AC, 0, 1, 894472, 0, 1, 352, 52, r, 3, 4)
74 #define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0)
75 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\
76 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
77 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\
78 FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x)
80 /* ANA_AC:SRC:SRC_CFG */
81 #define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 0, 0, 1, 4)
83 /* ANA_AC:SRC:SRC_CFG1 */
84 #define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 4, 0, 1, 4)
86 /* ANA_AC:SRC:SRC_CFG2 */
87 #define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 8, 0, 1, 4)
89 #define ANA_AC_SRC_CFG2_PORT_MASK2 BIT(0)
90 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\
91 FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x)
92 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\
93 FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x)
95 /* ANA_AC:PGID:PGID_CFG */
96 #define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4)
98 /* ANA_AC:PGID:PGID_CFG1 */
99 #define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4)
101 /* ANA_AC:PGID:PGID_CFG2 */
102 #define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4)
104 #define ANA_AC_PGID_CFG2_PORT_MASK2 BIT(0)
105 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\
106 FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x)
107 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\
108 FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x)
110 /* ANA_AC:PGID:PGID_MISC_CFG */
111 #define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4)
113 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU GENMASK(6, 4)
114 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\
115 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
116 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\
117 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
119 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA BIT(1)
120 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\
121 FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
122 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\
123 FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
125 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA BIT(0)
126 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\
127 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
128 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\
129 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
131 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */
132 #define ANA_AC_PORT_SGE_CFG(r) __REG(TARGET_ANA_AC, 0, 1, 851552, 0, 1, 20, 0, r, 4, 4)
134 #define ANA_AC_PORT_SGE_CFG_MASK GENMASK(15, 0)
135 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\
136 FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x)
137 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\
138 FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x)
140 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */
141 #define ANA_AC_STAT_RESET __REG(TARGET_ANA_AC, 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4)
143 #define ANA_AC_STAT_RESET_RESET BIT(0)
144 #define ANA_AC_STAT_RESET_RESET_SET(x)\
145 FIELD_PREP(ANA_AC_STAT_RESET_RESET, x)
146 #define ANA_AC_STAT_RESET_RESET_GET(x)\
147 FIELD_GET(ANA_AC_STAT_RESET_RESET, x)
149 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */
150 #define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 4, r, 4, 4)
152 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK GENMASK(11, 4)
153 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\
154 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
155 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\
156 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
158 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE GENMASK(3, 1)
159 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\
160 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
161 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\
162 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
164 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE BIT(0)
165 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\
166 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
167 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\
168 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
170 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */
171 #define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 20, r, 4, 4)
173 /* ANA_ACL:COMMON:OWN_UPSID */
174 #define ANA_ACL_OWN_UPSID(r) __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 580, r, 3, 4)
176 #define ANA_ACL_OWN_UPSID_OWN_UPSID GENMASK(4, 0)
177 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\
178 FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
179 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\
180 FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
182 /* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */
183 #define ANA_AC_POL_POL_UPD_INT_CFG __REG(TARGET_ANA_AC_POL, 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4)
185 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT GENMASK(9, 0)
186 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\
187 FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
188 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\
189 FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
191 /* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */
192 #define ANA_AC_POL_BDLB_DLB_CTRL __REG(TARGET_ANA_AC_POL, 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4)
194 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19)
195 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\
196 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
197 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\
198 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
200 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4)
201 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\
202 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
203 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\
204 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
206 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA BIT(1)
207 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\
208 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
209 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\
210 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
212 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA BIT(0)
213 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\
214 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
215 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\
216 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
218 /* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */
219 #define ANA_AC_POL_SLB_DLB_CTRL __REG(TARGET_ANA_AC_POL, 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4)
221 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19)
222 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\
223 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
224 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\
225 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
227 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4)
228 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\
229 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
230 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\
231 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
233 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA BIT(1)
234 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\
235 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
236 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\
237 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
239 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA BIT(0)
240 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\
241 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
242 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\
243 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
245 /* ANA_CL:PORT:FILTER_CTRL */
246 #define ANA_CL_FILTER_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 4, 0, 1, 4)
248 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS BIT(2)
249 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\
250 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
251 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\
252 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
254 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS BIT(1)
255 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\
256 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
257 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\
258 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
260 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA BIT(0)
261 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\
262 FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
263 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\
264 FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
266 /* ANA_CL:PORT:VLAN_FILTER_CTRL */
267 #define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 8, r, 3, 4)
269 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10)
270 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\
271 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
272 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\
273 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
275 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS BIT(9)
276 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\
277 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
278 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\
279 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
281 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS BIT(8)
282 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\
283 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
284 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\
285 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
287 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS BIT(7)
288 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\
289 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
290 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\
291 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
293 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS BIT(6)
294 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\
295 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
296 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\
297 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
299 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS BIT(5)
300 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\
301 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
302 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\
303 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
305 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS BIT(4)
306 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\
307 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
308 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\
309 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
311 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS BIT(3)
312 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\
313 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
314 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\
315 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
317 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS BIT(2)
318 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\
319 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
320 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\
321 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
323 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS BIT(1)
324 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\
325 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
326 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\
327 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
329 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS BIT(0)
330 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\
331 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
332 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\
333 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
335 /* ANA_CL:PORT:ETAG_FILTER_CTRL */
336 #define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 20, 0, 1, 4)
338 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1)
339 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\
340 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
341 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\
342 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
344 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS BIT(0)
345 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\
346 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
347 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\
348 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
350 /* ANA_CL:PORT:VLAN_CTRL */
351 #define ANA_CL_VLAN_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 32, 0, 1, 4)
353 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26)
354 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\
355 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
356 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\
357 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
359 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP GENMASK(25, 23)
360 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\
361 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
362 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\
363 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
365 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI BIT(22)
366 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\
367 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
368 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\
369 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
371 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA BIT(21)
372 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\
373 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
374 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\
375 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
377 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL BIT(20)
378 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\
379 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
380 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\
381 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
383 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA BIT(19)
384 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\
385 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
386 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\
387 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
389 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT GENMASK(18, 17)
390 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\
391 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
392 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\
393 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
395 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE BIT(16)
396 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\
397 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
398 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\
399 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
401 #define ANA_CL_VLAN_CTRL_PORT_PCP GENMASK(15, 13)
402 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\
403 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x)
404 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\
405 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x)
407 #define ANA_CL_VLAN_CTRL_PORT_DEI BIT(12)
408 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\
409 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x)
410 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\
411 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x)
413 #define ANA_CL_VLAN_CTRL_PORT_VID GENMASK(11, 0)
414 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\
415 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x)
416 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\
417 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x)
419 /* ANA_CL:PORT:VLAN_CTRL_2 */
420 #define ANA_CL_VLAN_CTRL_2(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 36, 0, 1, 4)
422 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0)
423 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\
424 FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
425 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\
426 FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
428 /* ANA_CL:PORT:CAPTURE_BPDU_CFG */
429 #define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 196, 0, 1, 4)
431 /* ANA_CL:COMMON:OWN_UPSID */
432 #define ANA_CL_OWN_UPSID(r) __REG(TARGET_ANA_CL, 0, 1, 166912, 0, 1, 756, 0, r, 3, 4)
434 #define ANA_CL_OWN_UPSID_OWN_UPSID GENMASK(4, 0)
435 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\
436 FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x)
437 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\
438 FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x)
440 /* ANA_L2:COMMON:AUTO_LRN_CFG */
441 #define ANA_L2_AUTO_LRN_CFG __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4)
443 /* ANA_L2:COMMON:AUTO_LRN_CFG1 */
444 #define ANA_L2_AUTO_LRN_CFG1 __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4)
446 /* ANA_L2:COMMON:AUTO_LRN_CFG2 */
447 #define ANA_L2_AUTO_LRN_CFG2 __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4)
449 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2 BIT(0)
450 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\
451 FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
452 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\
453 FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
455 /* ANA_L2:COMMON:OWN_UPSID */
456 #define ANA_L2_OWN_UPSID(r) __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 672, r, 3, 4)
458 #define ANA_L2_OWN_UPSID_OWN_UPSID GENMASK(4, 0)
459 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\
460 FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x)
461 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\
462 FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x)
464 /* ANA_L3:COMMON:VLAN_CTRL */
465 #define ANA_L3_VLAN_CTRL __REG(TARGET_ANA_L3, 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4)
467 #define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0)
468 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\
469 FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
470 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\
471 FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
473 /* ANA_L3:VLAN:VLAN_CFG */
474 #define ANA_L3_VLAN_CFG(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 8, 0, 1, 4)
476 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR GENMASK(30, 24)
477 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\
478 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
479 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\
480 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
482 #define ANA_L3_VLAN_CFG_VLAN_FID GENMASK(20, 8)
483 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\
484 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x)
485 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\
486 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x)
488 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA BIT(6)
489 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\
490 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
491 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\
492 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
494 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA BIT(5)
495 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\
496 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
497 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\
498 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
500 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS BIT(4)
501 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\
502 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
503 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\
504 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
506 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS BIT(3)
507 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\
508 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
509 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\
510 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
512 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA BIT(2)
513 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\
514 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
515 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\
516 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
518 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA BIT(1)
519 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\
520 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
521 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\
522 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
524 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA BIT(0)
525 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\
526 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
527 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\
528 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
530 /* ANA_L3:VLAN:VLAN_MASK_CFG */
531 #define ANA_L3_VLAN_MASK_CFG(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 16, 0, 1, 4)
533 /* ANA_L3:VLAN:VLAN_MASK_CFG1 */
534 #define ANA_L3_VLAN_MASK_CFG1(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 20, 0, 1, 4)
536 /* ANA_L3:VLAN:VLAN_MASK_CFG2 */
537 #define ANA_L3_VLAN_MASK_CFG2(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 24, 0, 1, 4)
539 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2 BIT(0)
540 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\
541 FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
542 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\
543 FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
545 /* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */
546 #define ASM_RX_IN_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 0, 0, 1, 4)
548 /* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */
549 #define ASM_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 4, 0, 1, 4)
551 /* ASM:DEV_STATISTICS:RX_PAUSE_CNT */
552 #define ASM_RX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 8, 0, 1, 4)
554 /* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */
555 #define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 12, 0, 1, 4)
557 /* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */
558 #define ASM_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 16, 0, 1, 4)
560 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */
561 #define ASM_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 20, 0, 1, 4)
563 /* ASM:DEV_STATISTICS:RX_UC_CNT */
564 #define ASM_RX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 24, 0, 1, 4)
566 /* ASM:DEV_STATISTICS:RX_MC_CNT */
567 #define ASM_RX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 28, 0, 1, 4)
569 /* ASM:DEV_STATISTICS:RX_BC_CNT */
570 #define ASM_RX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 32, 0, 1, 4)
572 /* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */
573 #define ASM_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 36, 0, 1, 4)
575 /* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */
576 #define ASM_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 40, 0, 1, 4)
578 /* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */
579 #define ASM_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 44, 0, 1, 4)
581 /* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */
582 #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 48, 0, 1, 4)
584 /* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */
585 #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 52, 0, 1, 4)
587 /* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */
588 #define ASM_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 56, 0, 1, 4)
590 /* ASM:DEV_STATISTICS:RX_JABBERS_CNT */
591 #define ASM_RX_JABBERS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 60, 0, 1, 4)
593 /* ASM:DEV_STATISTICS:RX_SIZE64_CNT */
594 #define ASM_RX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 64, 0, 1, 4)
596 /* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */
597 #define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 68, 0, 1, 4)
599 /* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */
600 #define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 72, 0, 1, 4)
602 /* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */
603 #define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 76, 0, 1, 4)
605 /* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */
606 #define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 80, 0, 1, 4)
608 /* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */
609 #define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 84, 0, 1, 4)
611 /* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */
612 #define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 88, 0, 1, 4)
614 /* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */
615 #define ASM_RX_IPG_SHRINK_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 92, 0, 1, 4)
617 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */
618 #define ASM_TX_OUT_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 96, 0, 1, 4)
620 /* ASM:DEV_STATISTICS:TX_PAUSE_CNT */
621 #define ASM_TX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 100, 0, 1, 4)
623 /* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */
624 #define ASM_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 104, 0, 1, 4)
626 /* ASM:DEV_STATISTICS:TX_UC_CNT */
627 #define ASM_TX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 108, 0, 1, 4)
629 /* ASM:DEV_STATISTICS:TX_MC_CNT */
630 #define ASM_TX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 112, 0, 1, 4)
632 /* ASM:DEV_STATISTICS:TX_BC_CNT */
633 #define ASM_TX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 116, 0, 1, 4)
635 /* ASM:DEV_STATISTICS:TX_SIZE64_CNT */
636 #define ASM_TX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 120, 0, 1, 4)
638 /* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */
639 #define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 124, 0, 1, 4)
641 /* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */
642 #define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 128, 0, 1, 4)
644 /* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */
645 #define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 132, 0, 1, 4)
647 /* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */
648 #define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 136, 0, 1, 4)
650 /* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */
651 #define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 140, 0, 1, 4)
653 /* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */
654 #define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 144, 0, 1, 4)
656 /* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */
657 #define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 148, 0, 1, 4)
659 /* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */
660 #define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 152, 0, 1, 4)
662 /* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */
663 #define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 156, 0, 1, 4)
665 /* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */
666 #define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 160, 0, 1, 4)
668 /* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */
669 #define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 164, 0, 1, 4)
671 /* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */
672 #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 168, 0, 1, 4)
674 /* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */
675 #define ASM_PMAC_RX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 172, 0, 1, 4)
677 /* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */
678 #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 176, 0, 1, 4)
680 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */
681 #define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 180, 0, 1, 4)
683 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */
684 #define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 184, 0, 1, 4)
686 /* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */
687 #define ASM_PMAC_RX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 188, 0, 1, 4)
689 /* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */
690 #define ASM_PMAC_RX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 192, 0, 1, 4)
692 /* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */
693 #define ASM_PMAC_RX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 196, 0, 1, 4)
695 /* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */
696 #define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 200, 0, 1, 4)
698 /* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */
699 #define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 204, 0, 1, 4)
701 /* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */
702 #define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 208, 0, 1, 4)
704 /* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */
705 #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 212, 0, 1, 4)
707 /* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */
708 #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 216, 0, 1, 4)
710 /* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */
711 #define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 220, 0, 1, 4)
713 /* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */
714 #define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 224, 0, 1, 4)
716 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */
717 #define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 228, 0, 1, 4)
719 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */
720 #define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 232, 0, 1, 4)
722 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */
723 #define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 236, 0, 1, 4)
725 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */
726 #define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 240, 0, 1, 4)
728 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */
729 #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 244, 0, 1, 4)
731 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */
732 #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 248, 0, 1, 4)
734 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */
735 #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 252, 0, 1, 4)
737 /* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */
738 #define ASM_PMAC_TX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 256, 0, 1, 4)
740 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */
741 #define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 260, 0, 1, 4)
743 /* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */
744 #define ASM_PMAC_TX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 264, 0, 1, 4)
746 /* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */
747 #define ASM_PMAC_TX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 268, 0, 1, 4)
749 /* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */
750 #define ASM_PMAC_TX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 272, 0, 1, 4)
752 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */
753 #define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 276, 0, 1, 4)
755 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */
756 #define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 280, 0, 1, 4)
758 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */
759 #define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 284, 0, 1, 4)
761 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */
762 #define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 288, 0, 1, 4)
764 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */
765 #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 292, 0, 1, 4)
767 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */
768 #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 296, 0, 1, 4)
770 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */
771 #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 300, 0, 1, 4)
773 /* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */
774 #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 304, 0, 1, 4)
776 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */
777 #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 308, 0, 1, 4)
779 /* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */
780 #define ASM_MM_RX_SMD_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 312, 0, 1, 4)
782 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */
783 #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 316, 0, 1, 4)
785 /* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */
786 #define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 320, 0, 1, 4)
788 /* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */
789 #define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 324, 0, 1, 4)
791 /* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */
792 #define ASM_TX_MULTI_COLL_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 328, 0, 1, 4)
794 /* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */
795 #define ASM_TX_LATE_COLL_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 332, 0, 1, 4)
797 /* ASM:DEV_STATISTICS:TX_XCOLL_CNT */
798 #define ASM_TX_XCOLL_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 336, 0, 1, 4)
800 /* ASM:DEV_STATISTICS:TX_DEFER_CNT */
801 #define ASM_TX_DEFER_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 340, 0, 1, 4)
803 /* ASM:DEV_STATISTICS:TX_XDEFER_CNT */
804 #define ASM_TX_XDEFER_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 344, 0, 1, 4)
806 /* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */
807 #define ASM_TX_BACKOFF1_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 348, 0, 1, 4)
809 /* ASM:DEV_STATISTICS:TX_CSENSE_CNT */
810 #define ASM_TX_CSENSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 352, 0, 1, 4)
812 /* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */
813 #define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 356, 0, 1, 4)
815 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0)
816 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\
817 FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
818 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\
819 FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
821 /* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */
822 #define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 360, 0, 1, 4)
824 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0)
825 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\
826 FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
827 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\
828 FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
830 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */
831 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 364, 0, 1, 4)
833 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0)
834 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\
835 FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
836 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\
837 FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
839 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */
840 #define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 368, 0, 1, 4)
842 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0)
843 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\
844 FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
845 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\
846 FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
848 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */
849 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 372, 0, 1, 4)
851 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0)
852 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\
853 FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
854 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\
855 FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
857 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */
858 #define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 376, 0, 1, 4)
860 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0)
861 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\
862 FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
863 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\
864 FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
866 /* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */
867 #define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 380, 0, 1, 4)
869 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0)
870 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\
871 FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
872 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\
873 FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
875 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */
876 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 384, 0, 1, 4)
878 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0)
879 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\
880 FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
881 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\
882 FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
884 /* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */
885 #define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 388, 0, 1, 4)
887 /* ASM:CFG:STAT_CFG */
888 #define ASM_STAT_CFG __REG(TARGET_ASM, 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4)
890 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT BIT(0)
891 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\
892 FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
893 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\
894 FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
896 /* ASM:CFG:PORT_CFG */
897 #define ASM_PORT_CFG(r) __REG(TARGET_ASM, 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4)
899 #define ASM_PORT_CFG_CSC_STAT_DIS BIT(12)
900 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\
901 FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x)
902 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\
903 FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x)
905 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA BIT(11)
906 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\
907 FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
908 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\
909 FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
911 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA BIT(10)
912 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\
913 FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
914 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\
915 FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
917 #define ASM_PORT_CFG_NO_PREAMBLE_ENA BIT(9)
918 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\
919 FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
920 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\
921 FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
923 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA BIT(8)
924 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\
925 FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
926 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\
927 FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
929 #define ASM_PORT_CFG_FRM_AGING_DIS BIT(7)
930 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\
931 FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x)
932 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\
933 FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x)
935 #define ASM_PORT_CFG_PAD_ENA BIT(6)
936 #define ASM_PORT_CFG_PAD_ENA_SET(x)\
937 FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x)
938 #define ASM_PORT_CFG_PAD_ENA_GET(x)\
939 FIELD_GET(ASM_PORT_CFG_PAD_ENA, x)
941 #define ASM_PORT_CFG_INJ_DISCARD_CFG GENMASK(5, 4)
942 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\
943 FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
944 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\
945 FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
947 #define ASM_PORT_CFG_INJ_FORMAT_CFG GENMASK(3, 2)
948 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\
949 FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
950 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\
951 FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
953 #define ASM_PORT_CFG_VSTAX2_AWR_ENA BIT(1)
954 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\
955 FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
956 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\
957 FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
959 #define ASM_PORT_CFG_PFRM_FLUSH BIT(0)
960 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\
961 FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x)
962 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\
963 FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x)
965 /* ASM:RAM_CTRL:RAM_INIT */
966 #define ASM_RAM_INIT __REG(TARGET_ASM, 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4)
968 #define ASM_RAM_INIT_RAM_INIT BIT(1)
969 #define ASM_RAM_INIT_RAM_INIT_SET(x)\
970 FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x)
971 #define ASM_RAM_INIT_RAM_INIT_GET(x)\
972 FIELD_GET(ASM_RAM_INIT_RAM_INIT, x)
974 #define ASM_RAM_INIT_RAM_CFG_HOOK BIT(0)
975 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\
976 FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x)
977 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\
978 FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x)
980 /* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */
981 #define CLKGEN_LCPLL1_CORE_CLK_CFG __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4)
983 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV GENMASK(7, 0)
984 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\
985 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
986 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\
987 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
989 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV GENMASK(10, 8)
990 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\
991 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
992 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\
993 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
995 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR BIT(11)
996 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\
997 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
998 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\
999 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
1001 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL GENMASK(13, 12)
1002 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\
1003 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
1004 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\
1005 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
1007 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA BIT(14)
1008 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\
1009 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
1010 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\
1011 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
1013 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA BIT(15)
1014 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\
1015 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
1016 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\
1017 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
1019 /* CPU:CPU_REGS:PROC_CTRL */
1020 #define CPU_PROC_CTRL __REG(TARGET_CPU, 0, 1, 0, 0, 1, 204, 176, 0, 1, 4)
1022 #define CPU_PROC_CTRL_AARCH64_MODE_ENA BIT(12)
1023 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\
1024 FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
1025 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\
1026 FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
1028 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS BIT(11)
1029 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\
1030 FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
1031 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\
1032 FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
1034 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS BIT(10)
1035 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\
1036 FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
1037 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\
1038 FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
1040 #define CPU_PROC_CTRL_BE_EXCEP_MODE BIT(9)
1041 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\
1042 FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
1043 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\
1044 FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
1046 #define CPU_PROC_CTRL_VINITHI BIT(8)
1047 #define CPU_PROC_CTRL_VINITHI_SET(x)\
1048 FIELD_PREP(CPU_PROC_CTRL_VINITHI, x)
1049 #define CPU_PROC_CTRL_VINITHI_GET(x)\
1050 FIELD_GET(CPU_PROC_CTRL_VINITHI, x)
1052 #define CPU_PROC_CTRL_CFGTE BIT(7)
1053 #define CPU_PROC_CTRL_CFGTE_SET(x)\
1054 FIELD_PREP(CPU_PROC_CTRL_CFGTE, x)
1055 #define CPU_PROC_CTRL_CFGTE_GET(x)\
1056 FIELD_GET(CPU_PROC_CTRL_CFGTE, x)
1058 #define CPU_PROC_CTRL_CP15S_DISABLE BIT(6)
1059 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\
1060 FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x)
1061 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\
1062 FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x)
1064 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE BIT(5)
1065 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\
1066 FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
1067 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\
1068 FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
1070 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA BIT(4)
1071 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\
1072 FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
1073 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\
1074 FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
1076 #define CPU_PROC_CTRL_ACP_AWCACHE BIT(3)
1077 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\
1078 FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x)
1079 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\
1080 FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x)
1082 #define CPU_PROC_CTRL_ACP_ARCACHE BIT(2)
1083 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\
1084 FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x)
1085 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\
1086 FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x)
1088 #define CPU_PROC_CTRL_L2_FLUSH_REQ BIT(1)
1089 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\
1090 FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
1091 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\
1092 FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
1094 #define CPU_PROC_CTRL_ACP_DISABLE BIT(0)
1095 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\
1096 FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x)
1097 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\
1098 FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x)
1100 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
1101 #define DEV10G_MAC_ENA_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 0, 0, 1, 4)
1103 #define DEV10G_MAC_ENA_CFG_RX_ENA BIT(4)
1104 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\
1105 FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x)
1106 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\
1107 FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x)
1109 #define DEV10G_MAC_ENA_CFG_TX_ENA BIT(0)
1110 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\
1111 FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x)
1112 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\
1113 FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x)
1115 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
1116 #define DEV10G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 8, 0, 1, 4)
1118 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16)
1119 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
1120 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1121 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
1122 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1124 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)
1125 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
1126 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
1127 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
1128 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
1130 /* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */
1131 #define DEV10G_MAC_NUM_TAGS_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 12, 0, 1, 4)
1133 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0)
1134 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\
1135 FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
1136 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\
1137 FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
1139 /* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */
1140 #define DEV10G_MAC_TAGS_CFG(t, r) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 16, r, 3, 4)
1142 #define DEV10G_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16)
1143 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\
1144 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
1145 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\
1146 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
1148 #define DEV10G_MAC_TAGS_CFG_TAG_ENA BIT(4)
1149 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\
1150 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
1151 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\
1152 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
1154 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
1155 #define DEV10G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 28, 0, 1, 4)
1157 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24)
1158 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
1159 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1160 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
1161 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1163 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20)
1164 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
1165 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1166 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
1167 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1169 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16)
1170 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
1171 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1172 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
1173 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1175 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12)
1176 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
1177 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1178 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
1179 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1181 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8)
1182 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
1183 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1184 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
1185 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1187 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4)
1188 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
1189 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1190 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
1191 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1193 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0)
1194 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
1195 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1196 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
1197 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1199 /* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */
1200 #define DEV10G_MAC_TX_MONITOR_STICKY(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 48, 0, 1, 4)
1202 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4)
1203 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\
1204 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
1205 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\
1206 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
1208 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY BIT(3)
1209 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\
1210 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
1211 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\
1212 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
1214 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY BIT(2)
1215 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\
1216 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
1217 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\
1218 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
1220 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1)
1221 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\
1222 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
1223 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\
1224 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
1226 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY BIT(0)
1227 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\
1228 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
1229 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\
1230 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
1232 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */
1233 #define DEV10G_DEV_RST_CTRL(t) __REG(TARGET_DEV10G, t, 12, 436, 0, 1, 52, 0, 0, 1, 4)
1235 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28)
1236 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
1237 FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1238 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
1239 FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1241 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27)
1242 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
1243 FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1244 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
1245 FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1247 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)
1248 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
1249 FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1250 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
1251 FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1253 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23)
1254 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
1255 FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1256 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
1257 FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1259 #define DEV10G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)
1260 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
1261 FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
1262 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
1263 FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
1265 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST BIT(12)
1266 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
1267 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
1268 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
1269 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
1271 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST BIT(8)
1272 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
1273 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
1274 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
1275 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
1277 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST BIT(4)
1278 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
1279 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
1280 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
1281 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
1283 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST BIT(0)
1284 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
1285 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
1286 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
1287 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
1289 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */
1290 #define DEV10G_PCS25G_CFG(t) __REG(TARGET_DEV10G, t, 12, 488, 0, 1, 32, 0, 0, 1, 4)
1292 #define DEV10G_PCS25G_CFG_PCS25G_ENA BIT(0)
1293 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\
1294 FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
1295 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\
1296 FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
1298 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
1299 #define DEV25G_MAC_ENA_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4)
1301 #define DEV25G_MAC_ENA_CFG_RX_ENA BIT(4)
1302 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\
1303 FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x)
1304 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\
1305 FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x)
1307 #define DEV25G_MAC_ENA_CFG_TX_ENA BIT(0)
1308 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\
1309 FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x)
1310 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\
1311 FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x)
1313 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
1314 #define DEV25G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4)
1316 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16)
1317 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
1318 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1319 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
1320 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1322 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)
1323 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
1324 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
1325 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
1326 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
1328 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
1329 #define DEV25G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4)
1331 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24)
1332 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
1333 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1334 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
1335 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1337 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20)
1338 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
1339 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1340 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
1341 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1343 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16)
1344 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
1345 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1346 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
1347 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1349 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12)
1350 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
1351 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1352 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
1353 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1355 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8)
1356 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
1357 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1358 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
1359 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1361 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4)
1362 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
1363 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1364 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
1365 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1367 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0)
1368 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
1369 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1370 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
1371 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1373 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */
1374 #define DEV25G_DEV_RST_CTRL(t) __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4)
1376 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28)
1377 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
1378 FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1379 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
1380 FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1382 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27)
1383 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
1384 FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1385 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
1386 FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1388 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)
1389 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
1390 FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1391 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
1392 FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1394 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23)
1395 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
1396 FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1397 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
1398 FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1400 #define DEV25G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)
1401 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
1402 FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
1403 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
1404 FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
1406 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST BIT(12)
1407 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
1408 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
1409 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
1410 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
1412 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST BIT(8)
1413 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
1414 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
1415 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
1416 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
1418 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST BIT(4)
1419 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
1420 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
1421 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
1422 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
1424 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST BIT(0)
1425 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
1426 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
1427 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
1428 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
1430 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */
1431 #define DEV25G_PCS25G_CFG(t) __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4)
1433 #define DEV25G_PCS25G_CFG_PCS25G_ENA BIT(0)
1434 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\
1435 FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
1436 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\
1437 FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
1439 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */
1440 #define DEV25G_PCS25G_SD_CFG(t) __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4)
1442 #define DEV25G_PCS25G_SD_CFG_SD_SEL BIT(8)
1443 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\
1444 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
1445 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\
1446 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
1448 #define DEV25G_PCS25G_SD_CFG_SD_POL BIT(4)
1449 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\
1450 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x)
1451 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\
1452 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x)
1454 #define DEV25G_PCS25G_SD_CFG_SD_ENA BIT(0)
1455 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\
1456 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
1457 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\
1458 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
1460 /* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */
1461 #define DEV2G5_DEV_RST_CTRL(t) __REG(TARGET_DEV2G5, t, 65, 0, 0, 1, 36, 0, 0, 1, 4)
1463 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23)
1464 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
1465 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1466 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
1467 FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1469 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)
1470 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\
1471 FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
1472 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\
1473 FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
1475 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST BIT(17)
1476 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\
1477 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
1478 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\
1479 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
1481 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST BIT(16)
1482 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\
1483 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
1484 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\
1485 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
1487 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST BIT(12)
1488 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
1489 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
1490 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
1491 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
1493 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST BIT(8)
1494 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
1495 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
1496 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
1497 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
1499 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST BIT(4)
1500 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
1501 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
1502 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
1503 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
1505 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST BIT(0)
1506 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
1507 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
1508 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
1509 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
1511 /* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */
1512 #define DEV2G5_MAC_ENA_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 0, 0, 1, 4)
1514 #define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4)
1515 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\
1516 FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
1517 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\
1518 FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
1520 #define DEV2G5_MAC_ENA_CFG_TX_ENA BIT(0)
1521 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\
1522 FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
1523 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\
1524 FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
1526 /* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */
1527 #define DEV2G5_MAC_MODE_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 4, 0, 1, 4)
1529 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8)
1530 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\
1531 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
1532 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\
1533 FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
1535 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
1536 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\
1537 FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
1538 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\
1539 FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
1541 #define DEV2G5_MAC_MODE_CFG_FDX_ENA BIT(0)
1542 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\
1543 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
1544 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\
1545 FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
1547 /* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
1548 #define DEV2G5_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 8, 0, 1, 4)
1550 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)
1551 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
1552 FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
1553 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
1554 FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
1556 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */
1557 #define DEV2G5_MAC_TAGS_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 12, 0, 1, 4)
1559 #define DEV2G5_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16)
1560 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\
1561 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
1562 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\
1563 FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
1565 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3)
1566 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\
1567 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
1568 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\
1569 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
1571 #define DEV2G5_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1)
1572 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\
1573 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
1574 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\
1575 FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
1577 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0)
1578 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\
1579 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
1580 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\
1581 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
1583 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */
1584 #define DEV2G5_MAC_TAGS_CFG2(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 16, 0, 1, 4)
1586 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 GENMASK(31, 16)
1587 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\
1588 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
1589 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\
1590 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
1592 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2 GENMASK(15, 0)
1593 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\
1594 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
1595 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\
1596 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
1598 /* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
1599 #define DEV2G5_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 20, 0, 1, 4)
1601 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0)
1602 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\
1603 FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
1604 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\
1605 FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
1607 /* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */
1608 #define DEV2G5_MAC_IFG_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 24, 0, 1, 4)
1610 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
1611 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\
1612 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
1613 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\
1614 FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
1616 #define DEV2G5_MAC_IFG_CFG_TX_IFG GENMASK(12, 8)
1617 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\
1618 FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
1619 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\
1620 FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
1622 #define DEV2G5_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4)
1623 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\
1624 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
1625 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\
1626 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
1628 #define DEV2G5_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0)
1629 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\
1630 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
1631 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\
1632 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
1634 /* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */
1635 #define DEV2G5_MAC_HDX_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 28, 0, 1, 4)
1637 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26)
1638 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\
1639 FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
1640 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\
1641 FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
1643 #define DEV2G5_MAC_HDX_CFG_SEED GENMASK(23, 16)
1644 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\
1645 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x)
1646 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\
1647 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x)
1649 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD BIT(12)
1650 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\
1651 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
1652 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\
1653 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
1655 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8)
1656 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\
1657 FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
1658 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\
1659 FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
1661 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS GENMASK(6, 0)
1662 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\
1663 FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
1664 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\
1665 FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
1667 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */
1668 #define DEV2G5_PCS1G_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 0, 0, 1, 4)
1670 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE BIT(4)
1671 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\
1672 FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
1673 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\
1674 FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
1676 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1)
1677 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\
1678 FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
1679 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\
1680 FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
1682 #define DEV2G5_PCS1G_CFG_PCS_ENA BIT(0)
1683 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\
1684 FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x)
1685 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\
1686 FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x)
1688 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */
1689 #define DEV2G5_PCS1G_MODE_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 4, 0, 1, 4)
1691 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
1692 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\
1693 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
1694 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\
1695 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
1697 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1)
1698 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\
1699 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
1700 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\
1701 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
1703 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
1704 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\
1705 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
1706 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\
1707 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
1709 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */
1710 #define DEV2G5_PCS1G_SD_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 8, 0, 1, 4)
1712 #define DEV2G5_PCS1G_SD_CFG_SD_SEL BIT(8)
1713 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\
1714 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
1715 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\
1716 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
1718 #define DEV2G5_PCS1G_SD_CFG_SD_POL BIT(4)
1719 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\
1720 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
1721 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\
1722 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
1724 #define DEV2G5_PCS1G_SD_CFG_SD_ENA BIT(0)
1725 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\
1726 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
1727 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\
1728 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
1730 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */
1731 #define DEV2G5_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 12, 0, 1, 4)
1733 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16)
1734 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\
1735 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
1736 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\
1737 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
1739 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
1740 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\
1741 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
1742 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\
1743 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
1745 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
1746 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\
1747 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
1748 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\
1749 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
1751 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA BIT(0)
1752 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\
1753 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
1754 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\
1755 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
1757 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */
1758 #define DEV2G5_PCS1G_LB_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 20, 0, 1, 4)
1760 #define DEV2G5_PCS1G_LB_CFG_RA_ENA BIT(4)
1761 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\
1762 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
1763 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\
1764 FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
1766 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1)
1767 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\
1768 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
1769 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\
1770 FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
1772 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0)
1773 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\
1774 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
1775 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\
1776 FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
1778 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */
1779 #define DEV2G5_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 32, 0, 1, 4)
1781 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY GENMASK(31, 16)
1782 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\
1783 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
1784 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\
1785 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
1787 #define DEV2G5_PCS1G_ANEG_STATUS_PR BIT(4)
1788 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\
1789 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
1790 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\
1791 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
1793 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3)
1794 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\
1795 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
1796 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\
1797 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
1799 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
1800 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\
1801 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
1802 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\
1803 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
1805 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */
1806 #define DEV2G5_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 40, 0, 1, 4)
1808 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR GENMASK(15, 12)
1809 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\
1810 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
1811 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\
1812 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
1814 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8)
1815 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\
1816 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
1817 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\
1818 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
1820 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
1821 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\
1822 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
1823 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\
1824 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
1826 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0)
1827 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\
1828 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
1829 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\
1830 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
1832 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */
1833 #define DEV2G5_PCS1G_STICKY(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 48, 0, 1, 4)
1835 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
1836 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\
1837 FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
1838 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\
1839 FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
1841 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0)
1842 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\
1843 FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
1844 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\
1845 FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
1847 /* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */
1848 #define DEV2G5_PCS_FX100_CFG(t) __REG(TARGET_DEV2G5, t, 65, 164, 0, 1, 4, 0, 0, 1, 4)
1850 #define DEV2G5_PCS_FX100_CFG_SD_SEL BIT(26)
1851 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\
1852 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
1853 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\
1854 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
1856 #define DEV2G5_PCS_FX100_CFG_SD_POL BIT(25)
1857 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\
1858 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x)
1859 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\
1860 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x)
1862 #define DEV2G5_PCS_FX100_CFG_SD_ENA BIT(24)
1863 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\
1864 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
1865 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\
1866 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
1868 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA BIT(20)
1869 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\
1870 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
1871 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\
1872 FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
1874 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA BIT(16)
1875 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\
1876 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
1877 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\
1878 FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
1880 #define DEV2G5_PCS_FX100_CFG_RXBITSEL GENMASK(15, 12)
1881 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\
1882 FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
1883 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\
1884 FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
1886 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG GENMASK(10, 9)
1887 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\
1888 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
1889 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\
1890 FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
1892 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8)
1893 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\
1894 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
1895 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\
1896 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
1898 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER GENMASK(7, 4)
1899 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\
1900 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
1901 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\
1902 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
1904 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3)
1905 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\
1906 FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
1907 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\
1908 FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
1910 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA BIT(2)
1911 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\
1912 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
1913 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\
1914 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
1916 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA BIT(1)
1917 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\
1918 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
1919 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\
1920 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
1922 #define DEV2G5_PCS_FX100_CFG_PCS_ENA BIT(0)
1923 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\
1924 FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
1925 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\
1926 FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
1928 /* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */
1929 #define DEV2G5_PCS_FX100_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 168, 0, 1, 4, 0, 0, 1, 4)
1931 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP GENMASK(11, 8)
1932 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\
1933 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
1934 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\
1935 FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
1937 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7)
1938 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\
1939 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
1940 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\
1941 FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
1943 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6)
1944 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\
1945 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
1946 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\
1947 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
1949 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5)
1950 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\
1951 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
1952 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\
1953 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
1955 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)
1956 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\
1957 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
1958 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\
1959 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
1961 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS BIT(2)
1962 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\
1963 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
1964 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\
1965 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
1967 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1)
1968 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\
1969 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
1970 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\
1971 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
1973 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS BIT(0)
1974 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\
1975 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
1976 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\
1977 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
1979 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
1980 #define DEV5G_MAC_ENA_CFG(t) __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 0, 0, 1, 4)
1982 #define DEV5G_MAC_ENA_CFG_RX_ENA BIT(4)
1983 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\
1984 FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x)
1985 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\
1986 FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x)
1988 #define DEV5G_MAC_ENA_CFG_TX_ENA BIT(0)
1989 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\
1990 FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x)
1991 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\
1992 FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x)
1994 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
1995 #define DEV5G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 8, 0, 1, 4)
1997 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16)
1998 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
1999 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2000 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
2001 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2003 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)
2004 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
2005 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
2006 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
2007 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
2009 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
2010 #define DEV5G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 28, 0, 1, 4)
2012 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24)
2013 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
2014 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2015 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
2016 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2018 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20)
2019 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
2020 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2021 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
2022 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2024 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16)
2025 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
2026 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2027 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
2028 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2030 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12)
2031 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
2032 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2033 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
2034 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2036 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8)
2037 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
2038 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2039 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
2040 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2042 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4)
2043 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
2044 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2045 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
2046 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2048 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0)
2049 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
2050 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2051 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
2052 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2054 /* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */
2055 #define DEV5G_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 0, 0, 1, 4)
2057 /* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */
2058 #define DEV5G_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 4, 0, 1, 4)
2060 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */
2061 #define DEV5G_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 8, 0, 1, 4)
2063 /* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */
2064 #define DEV5G_RX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 12, 0, 1, 4)
2066 /* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */
2067 #define DEV5G_RX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 16, 0, 1, 4)
2069 /* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */
2070 #define DEV5G_RX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 20, 0, 1, 4)
2072 /* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */
2073 #define DEV5G_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 24, 0, 1, 4)
2075 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */
2076 #define DEV5G_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 28, 0, 1, 4)
2078 /* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */
2079 #define DEV5G_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 32, 0, 1, 4)
2081 /* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */
2082 #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 36, 0, 1, 4)
2084 /* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */
2085 #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 40, 0, 1, 4)
2087 /* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */
2088 #define DEV5G_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 44, 0, 1, 4)
2090 /* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */
2091 #define DEV5G_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 48, 0, 1, 4)
2093 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */
2094 #define DEV5G_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 52, 0, 1, 4)
2096 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */
2097 #define DEV5G_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 56, 0, 1, 4)
2099 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */
2100 #define DEV5G_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 60, 0, 1, 4)
2102 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */
2103 #define DEV5G_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 64, 0, 1, 4)
2105 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */
2106 #define DEV5G_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 68, 0, 1, 4)
2108 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */
2109 #define DEV5G_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 72, 0, 1, 4)
2111 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */
2112 #define DEV5G_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 76, 0, 1, 4)
2114 /* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */
2115 #define DEV5G_RX_IPG_SHRINK_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 80, 0, 1, 4)
2117 /* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */
2118 #define DEV5G_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 84, 0, 1, 4)
2120 /* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */
2121 #define DEV5G_TX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 88, 0, 1, 4)
2123 /* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */
2124 #define DEV5G_TX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 92, 0, 1, 4)
2126 /* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */
2127 #define DEV5G_TX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 96, 0, 1, 4)
2129 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */
2130 #define DEV5G_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 100, 0, 1, 4)
2132 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */
2133 #define DEV5G_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 104, 0, 1, 4)
2135 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */
2136 #define DEV5G_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 108, 0, 1, 4)
2138 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */
2139 #define DEV5G_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 112, 0, 1, 4)
2141 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */
2142 #define DEV5G_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 116, 0, 1, 4)
2144 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */
2145 #define DEV5G_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 120, 0, 1, 4)
2147 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */
2148 #define DEV5G_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 124, 0, 1, 4)
2150 /* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */
2151 #define DEV5G_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 128, 0, 1, 4)
2153 /* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */
2154 #define DEV5G_RX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 132, 0, 1, 4)
2156 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */
2157 #define DEV5G_RX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 136, 0, 1, 4)
2159 /* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */
2160 #define DEV5G_TX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 140, 0, 1, 4)
2162 /* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */
2163 #define DEV5G_TX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 144, 0, 1, 4)
2165 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */
2166 #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 148, 0, 1, 4)
2168 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */
2169 #define DEV5G_PMAC_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 152, 0, 1, 4)
2171 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */
2172 #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 156, 0, 1, 4)
2174 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */
2175 #define DEV5G_PMAC_RX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 160, 0, 1, 4)
2177 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */
2178 #define DEV5G_PMAC_RX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 164, 0, 1, 4)
2180 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */
2181 #define DEV5G_PMAC_RX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 168, 0, 1, 4)
2183 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */
2184 #define DEV5G_PMAC_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 172, 0, 1, 4)
2186 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */
2187 #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 176, 0, 1, 4)
2189 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */
2190 #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 180, 0, 1, 4)
2192 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */
2193 #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\
2194 t, 13, 60, 0, 1, 312, 184, 0, 1, 4)
2196 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */
2197 #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\
2198 t, 13, 60, 0, 1, 312, 188, 0, 1, 4)
2200 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */
2201 #define DEV5G_PMAC_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 192, 0, 1, 4)
2203 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */
2204 #define DEV5G_PMAC_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 196, 0, 1, 4)
2206 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */
2207 #define DEV5G_PMAC_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 200, 0, 1, 4)
2209 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */
2210 #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 204, 0, 1, 4)
2212 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */
2213 #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 208, 0, 1, 4)
2215 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */
2216 #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 212, 0, 1, 4)
2218 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */
2219 #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 216, 0, 1, 4)
2221 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */
2222 #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 220, 0, 1, 4)
2224 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */
2225 #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 224, 0, 1, 4)
2227 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */
2228 #define DEV5G_PMAC_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 228, 0, 1, 4)
2230 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */
2231 #define DEV5G_PMAC_TX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 232, 0, 1, 4)
2233 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */
2234 #define DEV5G_PMAC_TX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 236, 0, 1, 4)
2236 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */
2237 #define DEV5G_PMAC_TX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 240, 0, 1, 4)
2239 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */
2240 #define DEV5G_PMAC_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 244, 0, 1, 4)
2242 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */
2243 #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 248, 0, 1, 4)
2245 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */
2246 #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 252, 0, 1, 4)
2248 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */
2249 #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 256, 0, 1, 4)
2251 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */
2252 #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 260, 0, 1, 4)
2254 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */
2255 #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 264, 0, 1, 4)
2257 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */
2258 #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 268, 0, 1, 4)
2260 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */
2261 #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 272, 0, 1, 4)
2263 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */
2264 #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 276, 0, 1, 4)
2266 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */
2267 #define DEV5G_MM_RX_SMD_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 280, 0, 1, 4)
2269 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */
2270 #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 284, 0, 1, 4)
2272 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */
2273 #define DEV5G_MM_RX_MERGE_FRAG_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 288, 0, 1, 4)
2275 /* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */
2276 #define DEV5G_MM_TX_PFRAGMENT_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 292, 0, 1, 4)
2278 /* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */
2279 #define DEV5G_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 296, 0, 1, 4)
2281 /* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */
2282 #define DEV5G_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 300, 0, 1, 4)
2284 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */
2285 #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 304, 0, 1, 4)
2287 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */
2288 #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 308, 0, 1, 4)
2290 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */
2291 #define DEV5G_RX_IN_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 0, 0, 1, 4)
2293 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */
2294 #define DEV5G_RX_IN_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 4, 0, 1, 4)
2296 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0)
2297 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\
2298 FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2299 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\
2300 FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2302 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */
2303 #define DEV5G_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 8, 0, 1, 4)
2305 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */
2306 #define DEV5G_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 12, 0, 1, 4)
2308 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0)
2309 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\
2310 FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2311 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\
2312 FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2314 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */
2315 #define DEV5G_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 16, 0, 1, 4)
2317 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */
2318 #define DEV5G_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 20, 0, 1, 4)
2320 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0)
2321 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\
2322 FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2323 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\
2324 FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2326 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */
2327 #define DEV5G_TX_OUT_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 24, 0, 1, 4)
2329 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */
2330 #define DEV5G_TX_OUT_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 28, 0, 1, 4)
2332 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0)
2333 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\
2334 FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2335 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\
2336 FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2338 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */
2339 #define DEV5G_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 32, 0, 1, 4)
2341 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */
2342 #define DEV5G_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 36, 0, 1, 4)
2344 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0)
2345 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\
2346 FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2347 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\
2348 FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2350 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */
2351 #define DEV5G_PMAC_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 40, 0, 1, 4)
2353 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */
2354 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 44, 0, 1, 4)
2356 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0)
2357 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\
2358 FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2359 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\
2360 FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2362 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */
2363 #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 48, 0, 1, 4)
2365 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */
2366 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 52, 0, 1, 4)
2368 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0)
2369 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\
2370 FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2371 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\
2372 FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2374 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */
2375 #define DEV5G_PMAC_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 56, 0, 1, 4)
2377 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */
2378 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 60, 0, 1, 4)
2380 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0)
2381 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\
2382 FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2383 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\
2384 FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2386 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */
2387 #define DEV5G_DEV_RST_CTRL(t) __REG(TARGET_DEV5G, t, 13, 436, 0, 1, 52, 0, 0, 1, 4)
2389 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28)
2390 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
2391 FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2392 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
2393 FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2395 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27)
2396 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
2397 FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2398 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
2399 FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2401 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)
2402 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
2403 FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2404 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
2405 FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2407 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23)
2408 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
2409 FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2410 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
2411 FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2413 #define DEV5G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)
2414 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
2415 FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
2416 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
2417 FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
2419 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST BIT(12)
2420 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
2421 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
2422 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
2423 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
2425 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST BIT(8)
2426 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
2427 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
2428 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
2429 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
2431 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST BIT(4)
2432 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
2433 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
2434 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
2435 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
2437 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST BIT(0)
2438 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
2439 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
2440 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
2441 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
2443 /* DSM:RAM_CTRL:RAM_INIT */
2444 #define DSM_RAM_INIT __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
2446 #define DSM_RAM_INIT_RAM_INIT BIT(1)
2447 #define DSM_RAM_INIT_RAM_INIT_SET(x)\
2448 FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x)
2449 #define DSM_RAM_INIT_RAM_INIT_GET(x)\
2450 FIELD_GET(DSM_RAM_INIT_RAM_INIT, x)
2452 #define DSM_RAM_INIT_RAM_CFG_HOOK BIT(0)
2453 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\
2454 FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x)
2455 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\
2456 FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x)
2458 /* DSM:CFG:BUF_CFG */
2459 #define DSM_BUF_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r, 67, 4)
2461 #define DSM_BUF_CFG_CSC_STAT_DIS BIT(13)
2462 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\
2463 FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x)
2464 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\
2465 FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x)
2467 #define DSM_BUF_CFG_AGING_ENA BIT(12)
2468 #define DSM_BUF_CFG_AGING_ENA_SET(x)\
2469 FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x)
2470 #define DSM_BUF_CFG_AGING_ENA_GET(x)\
2471 FIELD_GET(DSM_BUF_CFG_AGING_ENA, x)
2473 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS BIT(11)
2474 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\
2475 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
2476 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\
2477 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
2479 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT GENMASK(10, 0)
2480 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\
2481 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
2482 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\
2483 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
2485 /* DSM:CFG:DEV_TX_STOP_WM_CFG */
2486 #define DSM_DEV_TX_STOP_WM_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4)
2488 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA BIT(9)
2489 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\
2490 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
2491 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\
2492 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
2494 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA BIT(8)
2495 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\
2496 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
2497 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\
2498 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
2500 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM GENMASK(7, 1)
2501 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\
2502 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
2503 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\
2504 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
2506 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR BIT(0)
2507 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\
2508 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
2509 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\
2510 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
2512 /* DSM:CFG:RX_PAUSE_CFG */
2513 #define DSM_RX_PAUSE_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1628, r, 67, 4)
2515 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1)
2516 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\
2517 FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
2518 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\
2519 FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
2521 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL BIT(0)
2522 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\
2523 FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
2524 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\
2525 FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
2527 /* DSM:CFG:MAC_CFG */
2528 #define DSM_MAC_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2432, r, 67, 4)
2530 #define DSM_MAC_CFG_TX_PAUSE_VAL GENMASK(31, 16)
2531 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\
2532 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x)
2533 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\
2534 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x)
2536 #define DSM_MAC_CFG_HDX_BACKPREASSURE BIT(2)
2537 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\
2538 FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
2539 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\
2540 FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
2542 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE BIT(1)
2543 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\
2544 FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
2545 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\
2546 FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
2548 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF BIT(0)
2549 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\
2550 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
2551 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\
2552 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
2554 /* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */
2555 #define DSM_MAC_ADDR_BASE_HIGH_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2700, r, 65, 4)
2557 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0)
2558 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\
2559 FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
2560 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\
2561 FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
2563 /* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */
2564 #define DSM_MAC_ADDR_BASE_LOW_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2960, r, 65, 4)
2566 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW GENMASK(23, 0)
2567 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\
2568 FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
2569 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\
2570 FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
2572 /* DSM:CFG:TAXI_CAL_CFG */
2573 #define DSM_TAXI_CAL_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4)
2575 #define DSM_TAXI_CAL_CFG_CAL_IDX GENMASK(20, 15)
2576 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\
2577 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x)
2578 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\
2579 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x)
2581 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN GENMASK(14, 9)
2582 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\
2583 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
2584 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\
2585 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
2587 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL GENMASK(8, 5)
2588 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\
2589 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
2590 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\
2591 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
2593 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL GENMASK(4, 1)
2594 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\
2595 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
2596 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\
2597 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
2599 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA BIT(0)
2600 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\
2601 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
2602 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\
2603 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
2605 /* EACL:POL_CFG:POL_EACL_CFG */
2606 #define EACL_POL_EACL_CFG __REG(TARGET_EACL, 0, 1, 150608, 0, 1, 780, 768, 0, 1, 4)
2608 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED BIT(5)
2609 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\
2610 FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
2611 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\
2612 FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
2614 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY BIT(4)
2615 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\
2616 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
2617 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\
2618 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
2620 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY BIT(3)
2621 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\
2622 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
2623 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\
2624 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
2626 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE BIT(2)
2627 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\
2628 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
2629 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\
2630 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
2632 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN BIT(1)
2633 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\
2634 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
2635 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\
2636 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
2638 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT BIT(0)
2639 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\
2640 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
2641 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\
2642 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
2644 /* EACL:RAM_CTRL:RAM_INIT */
2645 #define EACL_RAM_INIT __REG(TARGET_EACL, 0, 1, 118736, 0, 1, 4, 0, 0, 1, 4)
2647 #define EACL_RAM_INIT_RAM_INIT BIT(1)
2648 #define EACL_RAM_INIT_RAM_INIT_SET(x)\
2649 FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x)
2650 #define EACL_RAM_INIT_RAM_INIT_GET(x)\
2651 FIELD_GET(EACL_RAM_INIT_RAM_INIT, x)
2653 #define EACL_RAM_INIT_RAM_CFG_HOOK BIT(0)
2654 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\
2655 FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x)
2656 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\
2657 FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x)
2659 /* FDMA:FDMA:FDMA_CH_ACTIVATE */
2660 #define FDMA_CH_ACTIVATE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4)
2662 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0)
2663 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\
2664 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
2665 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\
2666 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
2668 /* FDMA:FDMA:FDMA_CH_RELOAD */
2669 #define FDMA_CH_RELOAD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4)
2671 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0)
2672 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\
2673 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x)
2674 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\
2675 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x)
2677 /* FDMA:FDMA:FDMA_CH_DISABLE */
2678 #define FDMA_CH_DISABLE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4)
2680 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0)
2681 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\
2682 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x)
2683 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\
2684 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x)
2686 /* FDMA:FDMA:FDMA_DCB_LLP */
2687 #define FDMA_DCB_LLP(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4)
2689 /* FDMA:FDMA:FDMA_DCB_LLP1 */
2690 #define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4)
2692 /* FDMA:FDMA:FDMA_DCB_LLP_PREV */
2693 #define FDMA_DCB_LLP_PREV(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 116, r, 8, 4)
2695 /* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */
2696 #define FDMA_DCB_LLP_PREV1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 148, r, 8, 4)
2698 /* FDMA:FDMA:FDMA_CH_CFG */
2699 #define FDMA_CH_CFG(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4)
2701 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE BIT(7)
2702 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\
2703 FIELD_PREP(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
2704 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\
2705 FIELD_GET(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
2707 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(6)
2708 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\
2709 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
2710 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\
2711 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
2713 #define FDMA_CH_CFG_CH_INJ_PORT BIT(5)
2714 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\
2715 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x)
2716 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\
2717 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x)
2719 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(4, 1)
2720 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\
2721 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
2722 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\
2723 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
2725 #define FDMA_CH_CFG_CH_MEM BIT(0)
2726 #define FDMA_CH_CFG_CH_MEM_SET(x)\
2727 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
2728 #define FDMA_CH_CFG_CH_MEM_GET(x)\
2729 FIELD_GET(FDMA_CH_CFG_CH_MEM, x)
2731 /* FDMA:FDMA:FDMA_CH_TRANSLATE */
2732 #define FDMA_CH_TRANSLATE(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 256, r, 8, 4)
2734 #define FDMA_CH_TRANSLATE_OFFSET GENMASK(15, 0)
2735 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\
2736 FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x)
2737 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\
2738 FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x)
2740 /* FDMA:FDMA:FDMA_XTR_CFG */
2741 #define FDMA_XTR_CFG __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 364, 0, 1, 4)
2743 #define FDMA_XTR_CFG_XTR_FIFO_WM GENMASK(15, 11)
2744 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\
2745 FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x)
2746 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\
2747 FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x)
2749 #define FDMA_XTR_CFG_XTR_ARB_SAT GENMASK(10, 0)
2750 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\
2751 FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x)
2752 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\
2753 FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x)
2755 /* FDMA:FDMA:FDMA_PORT_CTRL */
2756 #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4)
2758 #define FDMA_PORT_CTRL_INJ_STOP BIT(4)
2759 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\
2760 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x)
2761 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\
2762 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x)
2764 #define FDMA_PORT_CTRL_INJ_STOP_FORCE BIT(3)
2765 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\
2766 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
2767 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\
2768 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
2770 #define FDMA_PORT_CTRL_XTR_STOP BIT(2)
2771 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\
2772 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x)
2773 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\
2774 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x)
2776 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY BIT(1)
2777 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\
2778 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
2779 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\
2780 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
2782 #define FDMA_PORT_CTRL_XTR_BUF_RST BIT(0)
2783 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\
2784 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x)
2785 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\
2786 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x)
2788 /* FDMA:FDMA:FDMA_INTR_DCB */
2789 #define FDMA_INTR_DCB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 384, 0, 1, 4)
2791 #define FDMA_INTR_DCB_INTR_DCB GENMASK(7, 0)
2792 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\
2793 FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x)
2794 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\
2795 FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x)
2797 /* FDMA:FDMA:FDMA_INTR_DCB_ENA */
2798 #define FDMA_INTR_DCB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 388, 0, 1, 4)
2800 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA GENMASK(7, 0)
2801 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\
2802 FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
2803 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\
2804 FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
2806 /* FDMA:FDMA:FDMA_INTR_DB */
2807 #define FDMA_INTR_DB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4)
2809 #define FDMA_INTR_DB_INTR_DB GENMASK(7, 0)
2810 #define FDMA_INTR_DB_INTR_DB_SET(x)\
2811 FIELD_PREP(FDMA_INTR_DB_INTR_DB, x)
2812 #define FDMA_INTR_DB_INTR_DB_GET(x)\
2813 FIELD_GET(FDMA_INTR_DB_INTR_DB, x)
2815 /* FDMA:FDMA:FDMA_INTR_DB_ENA */
2816 #define FDMA_INTR_DB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4)
2818 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0)
2819 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\
2820 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
2821 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\
2822 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
2824 /* FDMA:FDMA:FDMA_INTR_ERR */
2825 #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4)
2827 #define FDMA_INTR_ERR_INTR_PORT_ERR GENMASK(9, 8)
2828 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\
2829 FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x)
2830 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\
2831 FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x)
2833 #define FDMA_INTR_ERR_INTR_CH_ERR GENMASK(7, 0)
2834 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\
2835 FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x)
2836 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\
2837 FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x)
2839 /* FDMA:FDMA:FDMA_ERRORS */
2840 #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4)
2842 #define FDMA_ERRORS_ERR_XTR_WR GENMASK(31, 30)
2843 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\
2844 FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x)
2845 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\
2846 FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x)
2848 #define FDMA_ERRORS_ERR_XTR_OVF GENMASK(29, 28)
2849 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\
2850 FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x)
2851 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\
2852 FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x)
2854 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF GENMASK(27, 26)
2855 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\
2856 FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
2857 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\
2858 FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
2860 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL GENMASK(25, 24)
2861 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\
2862 FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
2863 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\
2864 FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
2866 #define FDMA_ERRORS_ERR_DCB_RD GENMASK(23, 16)
2867 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\
2868 FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x)
2869 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\
2870 FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x)
2872 #define FDMA_ERRORS_ERR_INJ_RD GENMASK(15, 10)
2873 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\
2874 FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x)
2875 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\
2876 FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x)
2878 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC GENMASK(9, 8)
2879 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\
2880 FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
2881 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\
2882 FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
2884 #define FDMA_ERRORS_ERR_CH_WR GENMASK(7, 0)
2885 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\
2886 FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x)
2887 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\
2888 FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x)
2890 /* FDMA:FDMA:FDMA_ERRORS_2 */
2891 #define FDMA_ERRORS_2 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 416, 0, 1, 4)
2893 #define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0)
2894 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\
2895 FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
2896 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\
2897 FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
2899 /* FDMA:FDMA:FDMA_CTRL */
2900 #define FDMA_CTRL __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 424, 0, 1, 4)
2902 #define FDMA_CTRL_NRESET BIT(0)
2903 #define FDMA_CTRL_NRESET_SET(x)\
2904 FIELD_PREP(FDMA_CTRL_NRESET, x)
2905 #define FDMA_CTRL_NRESET_GET(x)\
2906 FIELD_GET(FDMA_CTRL_NRESET, x)
2908 /* DEVCPU_GCB:CHIP_REGS:CHIP_ID */
2909 #define GCB_CHIP_ID __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 0, 0, 1, 4)
2911 #define GCB_CHIP_ID_REV_ID GENMASK(31, 28)
2912 #define GCB_CHIP_ID_REV_ID_SET(x)\
2913 FIELD_PREP(GCB_CHIP_ID_REV_ID, x)
2914 #define GCB_CHIP_ID_REV_ID_GET(x)\
2915 FIELD_GET(GCB_CHIP_ID_REV_ID, x)
2917 #define GCB_CHIP_ID_PART_ID GENMASK(27, 12)
2918 #define GCB_CHIP_ID_PART_ID_SET(x)\
2919 FIELD_PREP(GCB_CHIP_ID_PART_ID, x)
2920 #define GCB_CHIP_ID_PART_ID_GET(x)\
2921 FIELD_GET(GCB_CHIP_ID_PART_ID, x)
2923 #define GCB_CHIP_ID_MFG_ID GENMASK(11, 1)
2924 #define GCB_CHIP_ID_MFG_ID_SET(x)\
2925 FIELD_PREP(GCB_CHIP_ID_MFG_ID, x)
2926 #define GCB_CHIP_ID_MFG_ID_GET(x)\
2927 FIELD_GET(GCB_CHIP_ID_MFG_ID, x)
2929 #define GCB_CHIP_ID_ONE BIT(0)
2930 #define GCB_CHIP_ID_ONE_SET(x)\
2931 FIELD_PREP(GCB_CHIP_ID_ONE, x)
2932 #define GCB_CHIP_ID_ONE_GET(x)\
2933 FIELD_GET(GCB_CHIP_ID_ONE, x)
2935 /* DEVCPU_GCB:CHIP_REGS:SOFT_RST */
2936 #define GCB_SOFT_RST __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 8, 0, 1, 4)
2938 #define GCB_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
2939 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\
2940 FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
2941 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\
2942 FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
2944 #define GCB_SOFT_RST_SOFT_SWC_RST BIT(1)
2945 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\
2946 FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x)
2947 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\
2948 FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x)
2950 #define GCB_SOFT_RST_SOFT_CHIP_RST BIT(0)
2951 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\
2952 FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x)
2953 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\
2954 FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x)
2956 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */
2957 #define GCB_HW_SGPIO_SD_CFG __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 20, 0, 1, 4)
2959 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1)
2960 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\
2961 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
2962 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\
2963 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
2965 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL BIT(0)
2966 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\
2967 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
2968 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\
2969 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
2971 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */
2972 #define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 24, r, 65, 4)
2974 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL GENMASK(8, 0)
2975 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\
2976 FIELD_PREP(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
2977 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\
2978 FIELD_GET(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
2980 /* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */
2981 #define GCB_SIO_CLOCK(g) __REG(TARGET_GCB, 0, 1, 876, g, 3, 280, 20, 0, 1, 4)
2983 #define GCB_SIO_CLOCK_SIO_CLK_FREQ GENMASK(19, 8)
2984 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\
2985 FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
2986 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\
2987 FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
2989 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD GENMASK(7, 0)
2990 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\
2991 FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
2992 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\
2993 FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
2995 /* HSCH:HSCH_MISC:SYS_CLK_PER */
2996 #define HSCH_SYS_CLK_PER __REG(TARGET_HSCH, 0, 1, 163104, 0, 1, 648, 640, 0, 1, 4)
2998 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS GENMASK(7, 0)
2999 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_SET(x)\
3000 FIELD_PREP(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, x)
3001 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_GET(x)\
3002 FIELD_GET(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, x)
3004 /* HSCH:SYSTEM:FLUSH_CTRL */
3005 #define HSCH_FLUSH_CTRL __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 4, 0, 1, 4)
3007 #define HSCH_FLUSH_CTRL_FLUSH_ENA BIT(27)
3008 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\
3009 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
3010 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\
3011 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
3013 #define HSCH_FLUSH_CTRL_FLUSH_SRC BIT(26)
3014 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\
3015 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
3016 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\
3017 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
3019 #define HSCH_FLUSH_CTRL_FLUSH_DST BIT(25)
3020 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\
3021 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x)
3022 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\
3023 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x)
3025 #define HSCH_FLUSH_CTRL_FLUSH_PORT GENMASK(24, 18)
3026 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\
3027 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
3028 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\
3029 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
3031 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE BIT(17)
3032 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\
3033 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
3034 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\
3035 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
3037 #define HSCH_FLUSH_CTRL_FLUSH_SE BIT(16)
3038 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\
3039 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x)
3040 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\
3041 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x)
3043 #define HSCH_FLUSH_CTRL_FLUSH_HIER GENMASK(15, 0)
3044 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\
3045 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
3046 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\
3047 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
3049 /* HSCH:SYSTEM:PORT_MODE */
3050 #define HSCH_PORT_MODE(r) __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 8, r, 70, 4)
3052 #define HSCH_PORT_MODE_DEQUEUE_DIS BIT(4)
3053 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\
3054 FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x)
3055 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\
3056 FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x)
3058 #define HSCH_PORT_MODE_AGE_DIS BIT(3)
3059 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\
3060 FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x)
3061 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\
3062 FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x)
3064 #define HSCH_PORT_MODE_TRUNC_ENA BIT(2)
3065 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\
3066 FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x)
3067 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\
3068 FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x)
3070 #define HSCH_PORT_MODE_EIR_REMARK_ENA BIT(1)
3071 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\
3072 FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
3073 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\
3074 FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
3076 #define HSCH_PORT_MODE_CPU_PRIO_MODE BIT(0)
3077 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\
3078 FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
3079 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\
3080 FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
3082 /* HSCH:SYSTEM:OUTB_SHARE_ENA */
3083 #define HSCH_OUTB_SHARE_ENA(r) __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 288, r, 5, 4)
3085 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA GENMASK(7, 0)
3086 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\
3087 FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
3088 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\
3089 FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
3091 /* HSCH:MMGT:RESET_CFG */
3092 #define HSCH_RESET_CFG __REG(TARGET_HSCH, 0, 1, 162368, 0, 1, 16, 8, 0, 1, 4)
3094 #define HSCH_RESET_CFG_CORE_ENA BIT(0)
3095 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\
3096 FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x)
3097 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\
3098 FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x)
3100 /* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */
3101 #define HSCH_TAS_STATEMACHINE_CFG __REG(TARGET_HSCH, 0, 1, 162384, 0, 1, 12, 8, 0, 1, 4)
3103 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY GENMASK(7, 0)
3104 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\
3105 FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
3106 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\
3107 FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
3109 /* LRN:COMMON:COMMON_ACCESS_CTRL */
3110 #define LRN_COMMON_ACCESS_CTRL __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)
3112 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20)
3113 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\
3114 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
3115 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\
3116 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
3118 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE BIT(19)
3119 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\
3120 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
3121 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\
3122 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
3124 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW GENMASK(18, 5)
3125 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\
3126 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
3127 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\
3128 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
3130 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1)
3131 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\
3132 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
3133 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\
3134 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
3136 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0)
3137 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\
3138 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
3139 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\
3140 FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
3142 /* LRN:COMMON:MAC_ACCESS_CFG_0 */
3143 #define LRN_MAC_ACCESS_CFG_0 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4)
3145 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID GENMASK(28, 16)
3146 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\
3147 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
3148 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\
3149 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
3151 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB GENMASK(15, 0)
3152 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\
3153 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
3154 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\
3155 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
3157 /* LRN:COMMON:MAC_ACCESS_CFG_1 */
3158 #define LRN_MAC_ACCESS_CFG_1 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4)
3160 /* LRN:COMMON:MAC_ACCESS_CFG_2 */
3161 #define LRN_MAC_ACCESS_CFG_2 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4)
3163 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28)
3164 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\
3165 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
3166 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\
3167 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
3169 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL BIT(27)
3170 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\
3171 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
3172 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\
3173 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
3175 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU GENMASK(26, 24)
3176 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\
3177 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
3178 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\
3179 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
3181 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY BIT(23)
3182 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\
3183 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
3184 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\
3185 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
3187 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE BIT(22)
3188 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\
3189 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
3190 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\
3191 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
3193 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR BIT(21)
3194 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\
3195 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
3196 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\
3197 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
3199 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG GENMASK(20, 19)
3200 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\
3201 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
3202 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\
3203 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
3205 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL GENMASK(18, 17)
3206 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\
3207 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
3208 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\
3209 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
3211 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED BIT(16)
3212 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\
3213 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
3214 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\
3215 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
3217 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD BIT(15)
3218 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\
3219 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
3220 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\
3221 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
3223 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE GENMASK(14, 12)
3224 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\
3225 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
3226 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\
3227 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
3229 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR GENMASK(11, 0)
3230 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\
3231 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
3232 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\
3233 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
3235 /* LRN:COMMON:MAC_ACCESS_CFG_3 */
3236 #define LRN_MAC_ACCESS_CFG_3 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 16, 0, 1, 4)
3238 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX GENMASK(10, 0)
3239 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\
3240 FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
3241 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\
3242 FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
3244 /* LRN:COMMON:SCAN_NEXT_CFG */
3245 #define LRN_SCAN_NEXT_CFG __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4)
3247 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19)
3248 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\
3249 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
3250 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\
3251 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
3253 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL GENMASK(18, 17)
3254 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\
3255 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
3256 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\
3257 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
3259 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL GENMASK(16, 15)
3260 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\
3261 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
3262 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\
3263 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
3265 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA BIT(14)
3266 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\
3267 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
3268 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\
3269 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
3271 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA BIT(13)
3272 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\
3273 FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
3274 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\
3275 FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
3277 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA BIT(12)
3278 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\
3279 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
3280 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\
3281 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
3283 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA BIT(11)
3284 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\
3285 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
3286 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\
3287 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
3289 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA BIT(10)
3290 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\
3291 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
3292 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\
3293 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
3295 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA BIT(9)
3296 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\
3297 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
3298 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\
3299 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
3301 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA BIT(8)
3302 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\
3303 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
3304 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\
3305 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
3307 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA BIT(7)
3308 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\
3309 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
3310 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\
3311 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
3313 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK GENMASK(6, 3)
3314 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\
3315 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
3316 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\
3317 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
3319 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA BIT(2)
3320 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\
3321 FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
3322 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\
3323 FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
3325 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA BIT(1)
3326 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\
3327 FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
3328 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\
3329 FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
3331 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA BIT(0)
3332 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\
3333 FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
3334 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\
3335 FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
3337 /* LRN:COMMON:SCAN_NEXT_CFG_1 */
3338 #define LRN_SCAN_NEXT_CFG_1 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 24, 0, 1, 4)
3340 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR GENMASK(30, 16)
3341 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\
3342 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
3343 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\
3344 FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
3346 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK GENMASK(14, 0)
3347 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\
3348 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
3349 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\
3350 FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
3352 /* LRN:COMMON:AUTOAGE_CFG */
3353 #define LRN_AUTOAGE_CFG(r) __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 36, r, 4, 4)
3355 #define LRN_AUTOAGE_CFG_UNIT_SIZE GENMASK(29, 28)
3356 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\
3357 FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
3358 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\
3359 FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
3361 #define LRN_AUTOAGE_CFG_PERIOD_VAL GENMASK(27, 0)
3362 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\
3363 FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
3364 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\
3365 FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
3367 /* LRN:COMMON:AUTOAGE_CFG_1 */
3368 #define LRN_AUTOAGE_CFG_1 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 52, 0, 1, 4)
3370 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA BIT(25)
3371 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\
3372 FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
3373 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\
3374 FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
3376 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN GENMASK(24, 15)
3377 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\
3378 FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
3379 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\
3380 FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
3382 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS GENMASK(14, 7)
3383 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\
3384 FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
3385 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\
3386 FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
3388 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA BIT(6)
3389 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\
3390 FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
3391 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\
3392 FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
3394 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT GENMASK(5, 2)
3395 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\
3396 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
3397 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\
3398 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
3400 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT BIT(1)
3401 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\
3402 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
3403 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\
3404 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
3406 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA BIT(0)
3407 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\
3408 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
3409 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\
3410 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
3412 /* LRN:COMMON:AUTOAGE_CFG_2 */
3413 #define LRN_AUTOAGE_CFG_2 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 56, 0, 1, 4)
3415 #define LRN_AUTOAGE_CFG_2_NEXT_ROW GENMASK(17, 4)
3416 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\
3417 FIELD_PREP(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
3418 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\
3419 FIELD_GET(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
3421 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS GENMASK(3, 0)
3422 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\
3423 FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
3424 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\
3425 FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
3427 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */
3428 #define PCEP_RCTRL_2_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4)
3430 #define PCEP_RCTRL_2_OUT_0_MSG_CODE GENMASK(7, 0)
3431 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\
3432 FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
3433 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\
3434 FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
3436 #define PCEP_RCTRL_2_OUT_0_TAG GENMASK(15, 8)
3437 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\
3438 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x)
3439 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\
3440 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x)
3442 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN BIT(16)
3443 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\
3444 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
3445 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\
3446 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
3448 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS BIT(19)
3449 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\
3450 FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
3451 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\
3452 FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
3454 #define PCEP_RCTRL_2_OUT_0_SNP BIT(20)
3455 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\
3456 FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x)
3457 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\
3458 FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x)
3460 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD BIT(22)
3461 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\
3462 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
3463 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\
3464 FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
3466 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN BIT(23)
3467 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\
3468 FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
3469 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\
3470 FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
3472 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE BIT(28)
3473 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\
3474 FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
3475 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\
3476 FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
3478 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE BIT(29)
3479 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\
3480 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
3481 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\
3482 FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
3484 #define PCEP_RCTRL_2_OUT_0_REGION_EN BIT(31)
3485 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\
3486 FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
3487 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\
3488 FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
3490 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */
3491 #define PCEP_ADDR_LWR_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4)
3493 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW GENMASK(15, 0)
3494 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\
3495 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
3496 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\
3497 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
3499 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW GENMASK(31, 16)
3500 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\
3501 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
3502 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\
3503 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
3505 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */
3506 #define PCEP_ADDR_UPR_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4)
3508 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */
3509 #define PCEP_ADDR_LIM_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4)
3511 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW GENMASK(15, 0)
3512 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\
3513 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
3514 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\
3515 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
3517 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW GENMASK(31, 16)
3518 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\
3519 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
3520 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\
3521 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
3523 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */
3524 #define PCEP_ADDR_LWR_TGT_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4)
3526 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */
3527 #define PCEP_ADDR_UPR_TGT_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4)
3529 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */
3530 #define PCEP_ADDR_UPR_LIM_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4)
3532 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0)
3533 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\
3534 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
3535 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\
3536 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
3538 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW GENMASK(31, 2)
3539 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\
3540 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
3541 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\
3542 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
3544 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */
3545 #define PCS10G_BR_PCS_CFG(t) __REG(TARGET_PCS10G_BR, t, 12, 0, 0, 1, 56, 0, 0, 1, 4)
3547 #define PCS10G_BR_PCS_CFG_PCS_ENA BIT(31)
3548 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\
3549 FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x)
3550 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\
3551 FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x)
3553 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30)
3554 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
3555 FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3556 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
3557 FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3559 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24)
3560 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
3561 FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
3562 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
3563 FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
3565 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP BIT(18)
3566 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
3567 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
3568 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
3569 FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
3571 #define PCS10G_BR_PCS_CFG_RESYNC_ENA BIT(15)
3572 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
3573 FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
3574 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
3575 FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
3577 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS BIT(14)
3578 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
3579 FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
3580 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
3581 FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
3583 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE BIT(13)
3584 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
3585 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
3586 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
3587 FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
3589 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12)
3590 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
3591 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3592 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
3593 FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3595 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP BIT(7)
3596 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
3597 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
3598 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
3599 FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
3601 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6)
3602 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
3603 FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3604 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
3605 FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3607 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE BIT(4)
3608 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
3609 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
3610 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
3611 FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
3613 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3)
3614 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
3615 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3616 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
3617 FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3619 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */
3620 #define PCS10G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS10G_BR, t, 12, 0, 0, 1, 56, 4, 0, 1, 4)
3622 #define PCS10G_BR_PCS_SD_CFG_SD_SEL BIT(8)
3623 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
3624 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
3625 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
3626 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
3628 #define PCS10G_BR_PCS_SD_CFG_SD_POL BIT(4)
3629 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\
3630 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
3631 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\
3632 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
3634 #define PCS10G_BR_PCS_SD_CFG_SD_ENA BIT(0)
3635 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
3636 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
3637 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
3638 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
3640 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */
3641 #define PCS25G_BR_PCS_CFG(t) __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 0, 0, 1, 4)
3643 #define PCS25G_BR_PCS_CFG_PCS_ENA BIT(31)
3644 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\
3645 FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x)
3646 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\
3647 FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x)
3649 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30)
3650 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
3651 FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3652 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
3653 FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3655 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24)
3656 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
3657 FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
3658 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
3659 FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
3661 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP BIT(18)
3662 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
3663 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
3664 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
3665 FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
3667 #define PCS25G_BR_PCS_CFG_RESYNC_ENA BIT(15)
3668 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
3669 FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
3670 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
3671 FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
3673 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS BIT(14)
3674 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
3675 FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
3676 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
3677 FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
3679 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE BIT(13)
3680 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
3681 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
3682 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
3683 FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
3685 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12)
3686 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
3687 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3688 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
3689 FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3691 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP BIT(7)
3692 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
3693 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
3694 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
3695 FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
3697 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6)
3698 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
3699 FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3700 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
3701 FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3703 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE BIT(4)
3704 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
3705 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
3706 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
3707 FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
3709 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3)
3710 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
3711 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3712 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
3713 FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3715 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */
3716 #define PCS25G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 4, 0, 1, 4)
3718 #define PCS25G_BR_PCS_SD_CFG_SD_SEL BIT(8)
3719 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
3720 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
3721 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
3722 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
3724 #define PCS25G_BR_PCS_SD_CFG_SD_POL BIT(4)
3725 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\
3726 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
3727 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\
3728 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
3730 #define PCS25G_BR_PCS_SD_CFG_SD_ENA BIT(0)
3731 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
3732 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
3733 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
3734 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
3736 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */
3737 #define PCS5G_BR_PCS_CFG(t) __REG(TARGET_PCS5G_BR, t, 13, 0, 0, 1, 56, 0, 0, 1, 4)
3739 #define PCS5G_BR_PCS_CFG_PCS_ENA BIT(31)
3740 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\
3741 FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x)
3742 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\
3743 FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x)
3745 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30)
3746 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
3747 FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3748 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
3749 FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3751 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24)
3752 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
3753 FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
3754 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
3755 FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
3757 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP BIT(18)
3758 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
3759 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
3760 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
3761 FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
3763 #define PCS5G_BR_PCS_CFG_RESYNC_ENA BIT(15)
3764 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
3765 FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
3766 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
3767 FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
3769 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS BIT(14)
3770 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
3771 FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
3772 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
3773 FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
3775 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE BIT(13)
3776 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
3777 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
3778 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
3779 FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
3781 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12)
3782 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
3783 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3784 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
3785 FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3787 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP BIT(7)
3788 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
3789 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
3790 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
3791 FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
3793 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6)
3794 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
3795 FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3796 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
3797 FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3799 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE BIT(4)
3800 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
3801 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
3802 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
3803 FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
3805 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3)
3806 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
3807 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3808 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
3809 FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3811 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */
3812 #define PCS5G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS5G_BR, t, 13, 0, 0, 1, 56, 4, 0, 1, 4)
3814 #define PCS5G_BR_PCS_SD_CFG_SD_SEL BIT(8)
3815 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
3816 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
3817 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
3818 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
3820 #define PCS5G_BR_PCS_SD_CFG_SD_POL BIT(4)
3821 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\
3822 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
3823 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\
3824 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
3826 #define PCS5G_BR_PCS_SD_CFG_SD_ENA BIT(0)
3827 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
3828 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
3829 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
3830 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
3832 /* PORT_CONF:HW_CFG:DEV5G_MODES */
3833 #define PORT_CONF_DEV5G_MODES __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4)
3835 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE BIT(0)
3836 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\
3837 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
3838 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\
3839 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
3841 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1)
3842 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\
3843 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
3844 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\
3845 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
3847 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE BIT(2)
3848 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\
3849 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
3850 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\
3851 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
3853 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE BIT(3)
3854 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\
3855 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
3856 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\
3857 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
3859 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE BIT(4)
3860 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\
3861 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
3862 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\
3863 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
3865 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE BIT(5)
3866 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\
3867 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
3868 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\
3869 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
3871 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE BIT(6)
3872 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\
3873 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
3874 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\
3875 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
3877 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE BIT(7)
3878 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\
3879 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
3880 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\
3881 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
3883 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE BIT(8)
3884 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\
3885 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
3886 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\
3887 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
3889 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE BIT(9)
3890 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\
3891 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
3892 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\
3893 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
3895 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE BIT(10)
3896 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\
3897 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
3898 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\
3899 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
3901 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE BIT(11)
3902 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\
3903 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
3904 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\
3905 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
3907 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE BIT(12)
3908 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\
3909 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
3910 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\
3911 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
3913 /* PORT_CONF:HW_CFG:DEV10G_MODES */
3914 #define PORT_CONF_DEV10G_MODES __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4)
3916 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE BIT(0)
3917 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\
3918 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
3919 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\
3920 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
3922 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1)
3923 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\
3924 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
3925 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\
3926 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
3928 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE BIT(2)
3929 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\
3930 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
3931 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\
3932 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
3934 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE BIT(3)
3935 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\
3936 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
3937 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\
3938 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
3940 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE BIT(4)
3941 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\
3942 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
3943 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\
3944 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
3946 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE BIT(5)
3947 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\
3948 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
3949 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\
3950 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
3952 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE BIT(6)
3953 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\
3954 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
3955 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\
3956 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
3958 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE BIT(7)
3959 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\
3960 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
3961 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\
3962 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
3964 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE BIT(8)
3965 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\
3966 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
3967 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\
3968 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
3970 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE BIT(9)
3971 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\
3972 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
3973 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\
3974 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
3976 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE BIT(10)
3977 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\
3978 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
3979 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\
3980 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
3982 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE BIT(11)
3983 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\
3984 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
3985 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\
3986 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
3988 /* PORT_CONF:HW_CFG:DEV25G_MODES */
3989 #define PORT_CONF_DEV25G_MODES __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4)
3991 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE BIT(0)
3992 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\
3993 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
3994 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\
3995 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
3997 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE BIT(1)
3998 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\
3999 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
4000 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\
4001 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
4003 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE BIT(2)
4004 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\
4005 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
4006 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\
4007 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
4009 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE BIT(3)
4010 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\
4011 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
4012 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\
4013 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
4015 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE BIT(4)
4016 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\
4017 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
4018 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\
4019 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
4021 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE BIT(5)
4022 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\
4023 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
4024 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\
4025 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
4027 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE BIT(6)
4028 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\
4029 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
4030 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\
4031 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
4033 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE BIT(7)
4034 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\
4035 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
4036 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\
4037 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
4039 /* PORT_CONF:HW_CFG:QSGMII_ENA */
4040 #define PORT_CONF_QSGMII_ENA __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4)
4042 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0 BIT(0)
4043 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\
4044 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
4045 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\
4046 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
4048 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1 BIT(1)
4049 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\
4050 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
4051 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\
4052 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
4054 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2 BIT(2)
4055 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\
4056 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
4057 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\
4058 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
4060 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3 BIT(3)
4061 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\
4062 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
4063 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\
4064 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
4066 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4 BIT(4)
4067 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\
4068 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
4069 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\
4070 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
4072 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5 BIT(5)
4073 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\
4074 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
4075 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\
4076 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
4078 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6 BIT(6)
4079 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\
4080 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
4081 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\
4082 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
4084 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7 BIT(7)
4085 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\
4086 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
4087 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\
4088 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
4090 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8 BIT(8)
4091 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\
4092 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
4093 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\
4094 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
4096 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9 BIT(9)
4097 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\
4098 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
4099 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\
4100 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
4102 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10 BIT(10)
4103 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\
4104 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
4105 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\
4106 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
4108 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11 BIT(11)
4109 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\
4110 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
4111 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\
4112 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
4114 /* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */
4115 #define PORT_CONF_USGMII_CFG(g) __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4)
4117 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM BIT(9)
4118 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\
4119 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
4120 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\
4121 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
4123 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM BIT(8)
4124 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\
4125 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
4126 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\
4127 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
4129 #define PORT_CONF_USGMII_CFG_FLIP_LANES BIT(7)
4130 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\
4131 FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
4132 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\
4133 FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
4135 #define PORT_CONF_USGMII_CFG_SHYST_DIS BIT(6)
4136 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\
4137 FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
4138 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\
4139 FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
4141 #define PORT_CONF_USGMII_CFG_E_DET_ENA BIT(5)
4142 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\
4143 FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
4144 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\
4145 FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
4147 #define PORT_CONF_USGMII_CFG_USE_I1_ENA BIT(4)
4148 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\
4149 FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
4150 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\
4151 FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
4153 #define PORT_CONF_USGMII_CFG_QUAD_MODE BIT(1)
4154 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\
4155 FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
4156 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\
4157 FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
4159 /* QFWD:SYSTEM:SWITCH_PORT_MODE */
4160 #define QFWD_SWITCH_PORT_MODE(r) __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, 70, 4)
4162 #define QFWD_SWITCH_PORT_MODE_PORT_ENA BIT(19)
4163 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\
4164 FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
4165 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\
4166 FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
4168 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY GENMASK(18, 10)
4169 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\
4170 FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
4171 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\
4172 FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
4174 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD GENMASK(9, 6)
4175 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\
4176 FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
4177 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\
4178 FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
4180 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(5)
4181 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\
4182 FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
4183 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\
4184 FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
4186 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING BIT(4)
4187 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\
4188 FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
4189 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\
4190 FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
4192 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING BIT(3)
4193 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\
4194 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
4195 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\
4196 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
4198 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE BIT(2)
4199 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\
4200 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
4201 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\
4202 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
4204 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS BIT(1)
4205 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\
4206 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
4207 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\
4208 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
4210 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE BIT(0)
4211 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\
4212 FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
4213 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\
4214 FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
4216 /* QRES:RES_CTRL:RES_CFG */
4217 #define QRES_RES_CFG(g) __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 0, 0, 1, 4)
4219 #define QRES_RES_CFG_WM_HIGH GENMASK(11, 0)
4220 #define QRES_RES_CFG_WM_HIGH_SET(x)\
4221 FIELD_PREP(QRES_RES_CFG_WM_HIGH, x)
4222 #define QRES_RES_CFG_WM_HIGH_GET(x)\
4223 FIELD_GET(QRES_RES_CFG_WM_HIGH, x)
4225 /* QRES:RES_CTRL:RES_STAT */
4226 #define QRES_RES_STAT(g) __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 4, 0, 1, 4)
4228 #define QRES_RES_STAT_MAXUSE GENMASK(20, 0)
4229 #define QRES_RES_STAT_MAXUSE_SET(x)\
4230 FIELD_PREP(QRES_RES_STAT_MAXUSE, x)
4231 #define QRES_RES_STAT_MAXUSE_GET(x)\
4232 FIELD_GET(QRES_RES_STAT_MAXUSE, x)
4234 /* QRES:RES_CTRL:RES_STAT_CUR */
4235 #define QRES_RES_STAT_CUR(g) __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 8, 0, 1, 4)
4237 #define QRES_RES_STAT_CUR_INUSE GENMASK(20, 0)
4238 #define QRES_RES_STAT_CUR_INUSE_SET(x)\
4239 FIELD_PREP(QRES_RES_STAT_CUR_INUSE, x)
4240 #define QRES_RES_STAT_CUR_INUSE_GET(x)\
4241 FIELD_GET(QRES_RES_STAT_CUR_INUSE, x)
4243 /* DEVCPU_QS:XTR:XTR_GRP_CFG */
4244 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
4246 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2)
4247 #define QS_XTR_GRP_CFG_MODE_SET(x)\
4248 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
4249 #define QS_XTR_GRP_CFG_MODE_GET(x)\
4250 FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
4252 #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
4253 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\
4254 FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
4255 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\
4256 FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
4258 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
4259 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\
4260 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
4261 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\
4262 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
4264 /* DEVCPU_QS:XTR:XTR_RD */
4265 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
4267 /* DEVCPU_QS:XTR:XTR_FLUSH */
4268 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
4270 #define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
4271 #define QS_XTR_FLUSH_FLUSH_SET(x)\
4272 FIELD_PREP(QS_XTR_FLUSH_FLUSH, x)
4273 #define QS_XTR_FLUSH_FLUSH_GET(x)\
4274 FIELD_GET(QS_XTR_FLUSH_FLUSH, x)
4276 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */
4277 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
4279 #define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0)
4280 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\
4281 FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
4282 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\
4283 FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
4285 /* DEVCPU_QS:INJ:INJ_GRP_CFG */
4286 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
4288 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2)
4289 #define QS_INJ_GRP_CFG_MODE_SET(x)\
4290 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
4291 #define QS_INJ_GRP_CFG_MODE_GET(x)\
4292 FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
4294 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
4295 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\
4296 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
4297 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\
4298 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
4300 /* DEVCPU_QS:INJ:INJ_WR */
4301 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4)
4303 /* DEVCPU_QS:INJ:INJ_CTRL */
4304 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4)
4306 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21)
4307 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\
4308 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
4309 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\
4310 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)
4312 #define QS_INJ_CTRL_ABORT BIT(20)
4313 #define QS_INJ_CTRL_ABORT_SET(x)\
4314 FIELD_PREP(QS_INJ_CTRL_ABORT, x)
4315 #define QS_INJ_CTRL_ABORT_GET(x)\
4316 FIELD_GET(QS_INJ_CTRL_ABORT, x)
4318 #define QS_INJ_CTRL_EOF BIT(19)
4319 #define QS_INJ_CTRL_EOF_SET(x)\
4320 FIELD_PREP(QS_INJ_CTRL_EOF, x)
4321 #define QS_INJ_CTRL_EOF_GET(x)\
4322 FIELD_GET(QS_INJ_CTRL_EOF, x)
4324 #define QS_INJ_CTRL_SOF BIT(18)
4325 #define QS_INJ_CTRL_SOF_SET(x)\
4326 FIELD_PREP(QS_INJ_CTRL_SOF, x)
4327 #define QS_INJ_CTRL_SOF_GET(x)\
4328 FIELD_GET(QS_INJ_CTRL_SOF, x)
4330 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16)
4331 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\
4332 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
4333 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\
4334 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)
4336 /* DEVCPU_QS:INJ:INJ_STATUS */
4337 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)
4339 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4)
4340 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\
4341 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
4342 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\
4343 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)
4345 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2)
4346 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\
4347 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
4348 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\
4349 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)
4351 #define QS_INJ_STATUS_INJ_IN_PROGRESS GENMASK(1, 0)
4352 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\
4353 FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
4354 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\
4355 FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
4357 /* QSYS:PAUSE_CFG:PAUSE_CFG */
4358 #define QSYS_PAUSE_CFG(r) __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 0, r, 70, 4)
4360 #define QSYS_PAUSE_CFG_PAUSE_START GENMASK(25, 14)
4361 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\
4362 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_START, x)
4363 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\
4364 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_START, x)
4366 #define QSYS_PAUSE_CFG_PAUSE_STOP GENMASK(13, 2)
4367 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\
4368 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_STOP, x)
4369 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\
4370 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_STOP, x)
4372 #define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1)
4373 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\
4374 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x)
4375 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\
4376 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x)
4378 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA BIT(0)
4379 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\
4380 FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
4381 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\
4382 FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
4384 /* QSYS:PAUSE_CFG:ATOP */
4385 #define QSYS_ATOP(r) __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 284, r, 70, 4)
4387 #define QSYS_ATOP_ATOP GENMASK(11, 0)
4388 #define QSYS_ATOP_ATOP_SET(x)\
4389 FIELD_PREP(QSYS_ATOP_ATOP, x)
4390 #define QSYS_ATOP_ATOP_GET(x)\
4391 FIELD_GET(QSYS_ATOP_ATOP, x)
4393 /* QSYS:PAUSE_CFG:FWD_PRESSURE */
4394 #define QSYS_FWD_PRESSURE(r) __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 564, r, 70, 4)
4396 #define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1)
4397 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\
4398 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
4399 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\
4400 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
4402 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS BIT(0)
4403 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\
4404 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
4405 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\
4406 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
4408 /* QSYS:PAUSE_CFG:ATOP_TOT_CFG */
4409 #define QSYS_ATOP_TOT_CFG __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 844, 0, 1, 4)
4411 #define QSYS_ATOP_TOT_CFG_ATOP_TOT GENMASK(11, 0)
4412 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\
4413 FIELD_PREP(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
4414 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\
4415 FIELD_GET(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
4417 /* QSYS:CALCFG:CAL_AUTO */
4418 #define QSYS_CAL_AUTO(r) __REG(TARGET_QSYS, 0, 1, 2304, 0, 1, 40, 0, r, 7, 4)
4420 #define QSYS_CAL_AUTO_CAL_AUTO GENMASK(29, 0)
4421 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\
4422 FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x)
4423 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\
4424 FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x)
4426 /* QSYS:CALCFG:CAL_CTRL */
4427 #define QSYS_CAL_CTRL __REG(TARGET_QSYS, 0, 1, 2304, 0, 1, 40, 36, 0, 1, 4)
4429 #define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11)
4430 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\
4431 FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x)
4432 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\
4433 FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x)
4435 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE GENMASK(10, 1)
4436 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\
4437 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
4438 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\
4439 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
4441 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR BIT(0)
4442 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\
4443 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
4444 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\
4445 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
4447 /* QSYS:RAM_CTRL:RAM_INIT */
4448 #define QSYS_RAM_INIT __REG(TARGET_QSYS, 0, 1, 2344, 0, 1, 4, 0, 0, 1, 4)
4450 #define QSYS_RAM_INIT_RAM_INIT BIT(1)
4451 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\
4452 FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x)
4453 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\
4454 FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x)
4456 #define QSYS_RAM_INIT_RAM_CFG_HOOK BIT(0)
4457 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4458 FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
4459 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4460 FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
4462 /* REW:COMMON:OWN_UPSID */
4463 #define REW_OWN_UPSID(r) __REG(TARGET_REW, 0, 1, 387264, 0, 1, 1232, 0, r, 3, 4)
4465 #define REW_OWN_UPSID_OWN_UPSID GENMASK(4, 0)
4466 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\
4467 FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x)
4468 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\
4469 FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x)
4471 /* REW:PORT:PORT_VLAN_CFG */
4472 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 0, 0, 1, 4)
4474 #define REW_PORT_VLAN_CFG_PORT_PCP GENMASK(15, 13)
4475 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\
4476 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x)
4477 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\
4478 FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x)
4480 #define REW_PORT_VLAN_CFG_PORT_DEI BIT(12)
4481 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\
4482 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x)
4483 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\
4484 FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x)
4486 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0)
4487 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\
4488 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x)
4489 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\
4490 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x)
4492 /* REW:PORT:TAG_CTRL */
4493 #define REW_TAG_CTRL(g) __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 132, 0, 1, 4)
4495 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED BIT(13)
4496 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\
4497 FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
4498 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\
4499 FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
4501 #define REW_TAG_CTRL_TAG_CFG GENMASK(12, 11)
4502 #define REW_TAG_CTRL_TAG_CFG_SET(x)\
4503 FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x)
4504 #define REW_TAG_CTRL_TAG_CFG_GET(x)\
4505 FIELD_GET(REW_TAG_CTRL_TAG_CFG, x)
4507 #define REW_TAG_CTRL_TAG_TPID_CFG GENMASK(10, 8)
4508 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\
4509 FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x)
4510 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\
4511 FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x)
4513 #define REW_TAG_CTRL_TAG_VID_CFG GENMASK(7, 6)
4514 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\
4515 FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x)
4516 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\
4517 FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x)
4519 #define REW_TAG_CTRL_TAG_PCP_CFG GENMASK(5, 3)
4520 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\
4521 FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x)
4522 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\
4523 FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x)
4525 #define REW_TAG_CTRL_TAG_DEI_CFG GENMASK(2, 0)
4526 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\
4527 FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x)
4528 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\
4529 FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x)
4531 /* REW:RAM_CTRL:RAM_INIT */
4532 #define REW_RAM_INIT __REG(TARGET_REW, 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4)
4534 #define REW_RAM_INIT_RAM_INIT BIT(1)
4535 #define REW_RAM_INIT_RAM_INIT_SET(x)\
4536 FIELD_PREP(REW_RAM_INIT_RAM_INIT, x)
4537 #define REW_RAM_INIT_RAM_INIT_GET(x)\
4538 FIELD_GET(REW_RAM_INIT_RAM_INIT, x)
4540 #define REW_RAM_INIT_RAM_CFG_HOOK BIT(0)
4541 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4542 FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x)
4543 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4544 FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x)
4546 /* VCAP_SUPER:RAM_CTRL:RAM_INIT */
4547 #define VCAP_SUPER_RAM_INIT __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4)
4549 #define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1)
4550 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\
4551 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
4552 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\
4553 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
4555 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK BIT(0)
4556 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4557 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
4558 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4559 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
4561 /* VOP:RAM_CTRL:RAM_INIT */
4562 #define VOP_RAM_INIT __REG(TARGET_VOP, 0, 1, 279176, 0, 1, 4, 0, 0, 1, 4)
4564 #define VOP_RAM_INIT_RAM_INIT BIT(1)
4565 #define VOP_RAM_INIT_RAM_INIT_SET(x)\
4566 FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x)
4567 #define VOP_RAM_INIT_RAM_INIT_GET(x)\
4568 FIELD_GET(VOP_RAM_INIT_RAM_INIT, x)
4570 #define VOP_RAM_INIT_RAM_CFG_HOOK BIT(0)
4571 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4572 FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x)
4573 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4574 FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x)
4576 /* XQS:SYSTEM:STAT_CFG */
4577 #define XQS_STAT_CFG __REG(TARGET_XQS, 0, 1, 6768, 0, 1, 872, 860, 0, 1, 4)
4579 #define XQS_STAT_CFG_STAT_CLEAR_SHOT GENMASK(21, 18)
4580 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\
4581 FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
4582 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\
4583 FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
4585 #define XQS_STAT_CFG_STAT_VIEW GENMASK(17, 5)
4586 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\
4587 FIELD_PREP(XQS_STAT_CFG_STAT_VIEW, x)
4588 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\
4589 FIELD_GET(XQS_STAT_CFG_STAT_VIEW, x)
4591 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY BIT(4)
4592 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\
4593 FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
4594 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\
4595 FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
4597 #define XQS_STAT_CFG_STAT_WRAP_DIS GENMASK(3, 0)
4598 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\
4599 FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x)
4600 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\
4601 FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x)
4603 /* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */
4604 #define XQS_QLIMIT_SHR_TOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 0, 0, 1, 4)
4606 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP GENMASK(14, 0)
4607 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\
4608 FIELD_PREP(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
4609 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\
4610 FIELD_GET(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
4612 /* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */
4613 #define XQS_QLIMIT_SHR_ATOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 4, 0, 1, 4)
4615 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP GENMASK(14, 0)
4616 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\
4617 FIELD_PREP(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
4618 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\
4619 FIELD_GET(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
4621 /* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */
4622 #define XQS_QLIMIT_SHR_CTOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 8, 0, 1, 4)
4624 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP GENMASK(14, 0)
4625 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\
4626 FIELD_PREP(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
4627 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\
4628 FIELD_GET(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
4630 /* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */
4631 #define XQS_QLIMIT_SHR_QLIM_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 12, 0, 1, 4)
4633 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM GENMASK(14, 0)
4634 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\
4635 FIELD_PREP(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
4636 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\
4637 FIELD_GET(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
4640 #define XQS_CNT(g) __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4)
4642 #endif /* _SPARX5_MAIN_REGS_H_ */