1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/net/ethernet/micrel/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
5 * Copyright (c) 2009-2010 Micrel, Inc.
6 * Tristram Ha <Tristram.Ha@micrel.com>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/mii.h>
19 #include <linux/platform_device.h>
20 #include <linux/ethtool.h>
21 #include <linux/etherdevice.h>
24 #include <linux/if_vlan.h>
25 #include <linux/crc32.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <linux/micrel_phy.h>
33 #define KS_DMA_TX_CTRL 0x0000
34 #define DMA_TX_ENABLE 0x00000001
35 #define DMA_TX_CRC_ENABLE 0x00000002
36 #define DMA_TX_PAD_ENABLE 0x00000004
37 #define DMA_TX_LOOPBACK 0x00000100
38 #define DMA_TX_FLOW_ENABLE 0x00000200
39 #define DMA_TX_CSUM_IP 0x00010000
40 #define DMA_TX_CSUM_TCP 0x00020000
41 #define DMA_TX_CSUM_UDP 0x00040000
42 #define DMA_TX_BURST_SIZE 0x3F000000
44 #define KS_DMA_RX_CTRL 0x0004
45 #define DMA_RX_ENABLE 0x00000001
46 #define KS884X_DMA_RX_MULTICAST 0x00000002
47 #define DMA_RX_PROMISCUOUS 0x00000004
48 #define DMA_RX_ERROR 0x00000008
49 #define DMA_RX_UNICAST 0x00000010
50 #define DMA_RX_ALL_MULTICAST 0x00000020
51 #define DMA_RX_BROADCAST 0x00000040
52 #define DMA_RX_FLOW_ENABLE 0x00000200
53 #define DMA_RX_CSUM_IP 0x00010000
54 #define DMA_RX_CSUM_TCP 0x00020000
55 #define DMA_RX_CSUM_UDP 0x00040000
56 #define DMA_RX_BURST_SIZE 0x3F000000
58 #define DMA_BURST_SHIFT 24
59 #define DMA_BURST_DEFAULT 8
61 #define KS_DMA_TX_START 0x0008
62 #define KS_DMA_RX_START 0x000C
63 #define DMA_START 0x00000001
65 #define KS_DMA_TX_ADDR 0x0010
66 #define KS_DMA_RX_ADDR 0x0014
68 #define DMA_ADDR_LIST_MASK 0xFFFFFFFC
69 #define DMA_ADDR_LIST_SHIFT 2
72 #define KS884X_MULTICAST_0_OFFSET 0x0020
73 #define KS884X_MULTICAST_1_OFFSET 0x0021
74 #define KS884X_MULTICAST_2_OFFSET 0x0022
75 #define KS884x_MULTICAST_3_OFFSET 0x0023
77 #define KS884X_MULTICAST_4_OFFSET 0x0024
78 #define KS884X_MULTICAST_5_OFFSET 0x0025
79 #define KS884X_MULTICAST_6_OFFSET 0x0026
80 #define KS884X_MULTICAST_7_OFFSET 0x0027
82 /* Interrupt Registers */
85 #define KS884X_INTERRUPTS_ENABLE 0x0028
87 #define KS884X_INTERRUPTS_STATUS 0x002C
89 #define KS884X_INT_RX_STOPPED 0x02000000
90 #define KS884X_INT_TX_STOPPED 0x04000000
91 #define KS884X_INT_RX_OVERRUN 0x08000000
92 #define KS884X_INT_TX_EMPTY 0x10000000
93 #define KS884X_INT_RX 0x20000000
94 #define KS884X_INT_TX 0x40000000
95 #define KS884X_INT_PHY 0x80000000
97 #define KS884X_INT_RX_MASK \
98 (KS884X_INT_RX | KS884X_INT_RX_OVERRUN)
99 #define KS884X_INT_TX_MASK \
100 (KS884X_INT_TX | KS884X_INT_TX_EMPTY)
101 #define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY)
103 /* MAC Additional Station Address */
106 #define KS_ADD_ADDR_0_LO 0x0080
108 #define KS_ADD_ADDR_0_HI 0x0084
110 #define KS_ADD_ADDR_1_LO 0x0088
112 #define KS_ADD_ADDR_1_HI 0x008C
114 #define KS_ADD_ADDR_2_LO 0x0090
116 #define KS_ADD_ADDR_2_HI 0x0094
118 #define KS_ADD_ADDR_3_LO 0x0098
120 #define KS_ADD_ADDR_3_HI 0x009C
122 #define KS_ADD_ADDR_4_LO 0x00A0
124 #define KS_ADD_ADDR_4_HI 0x00A4
126 #define KS_ADD_ADDR_5_LO 0x00A8
128 #define KS_ADD_ADDR_5_HI 0x00AC
130 #define KS_ADD_ADDR_6_LO 0x00B0
132 #define KS_ADD_ADDR_6_HI 0x00B4
134 #define KS_ADD_ADDR_7_LO 0x00B8
136 #define KS_ADD_ADDR_7_HI 0x00BC
138 #define KS_ADD_ADDR_8_LO 0x00C0
140 #define KS_ADD_ADDR_8_HI 0x00C4
142 #define KS_ADD_ADDR_9_LO 0x00C8
144 #define KS_ADD_ADDR_9_HI 0x00CC
146 #define KS_ADD_ADDR_A_LO 0x00D0
148 #define KS_ADD_ADDR_A_HI 0x00D4
150 #define KS_ADD_ADDR_B_LO 0x00D8
152 #define KS_ADD_ADDR_B_HI 0x00DC
154 #define KS_ADD_ADDR_C_LO 0x00E0
156 #define KS_ADD_ADDR_C_HI 0x00E4
158 #define KS_ADD_ADDR_D_LO 0x00E8
160 #define KS_ADD_ADDR_D_HI 0x00EC
162 #define KS_ADD_ADDR_E_LO 0x00F0
164 #define KS_ADD_ADDR_E_HI 0x00F4
166 #define KS_ADD_ADDR_F_LO 0x00F8
168 #define KS_ADD_ADDR_F_HI 0x00FC
170 #define ADD_ADDR_HI_MASK 0x0000FFFF
171 #define ADD_ADDR_ENABLE 0x80000000
172 #define ADD_ADDR_INCR 8
174 /* Miscellaneous Registers */
177 #define KS884X_ADDR_0_OFFSET 0x0200
178 #define KS884X_ADDR_1_OFFSET 0x0201
180 #define KS884X_ADDR_2_OFFSET 0x0202
181 #define KS884X_ADDR_3_OFFSET 0x0203
183 #define KS884X_ADDR_4_OFFSET 0x0204
184 #define KS884X_ADDR_5_OFFSET 0x0205
187 #define KS884X_BUS_CTRL_OFFSET 0x0210
189 #define BUS_SPEED_125_MHZ 0x0000
190 #define BUS_SPEED_62_5_MHZ 0x0001
191 #define BUS_SPEED_41_66_MHZ 0x0002
192 #define BUS_SPEED_25_MHZ 0x0003
195 #define KS884X_EEPROM_CTRL_OFFSET 0x0212
197 #define EEPROM_CHIP_SELECT 0x0001
198 #define EEPROM_SERIAL_CLOCK 0x0002
199 #define EEPROM_DATA_OUT 0x0004
200 #define EEPROM_DATA_IN 0x0008
201 #define EEPROM_ACCESS_ENABLE 0x0010
204 #define KS884X_MEM_INFO_OFFSET 0x0214
206 #define RX_MEM_TEST_FAILED 0x0008
207 #define RX_MEM_TEST_FINISHED 0x0010
208 #define TX_MEM_TEST_FAILED 0x0800
209 #define TX_MEM_TEST_FINISHED 0x1000
212 #define KS884X_GLOBAL_CTRL_OFFSET 0x0216
213 #define GLOBAL_SOFTWARE_RESET 0x0001
215 #define KS8841_POWER_MANAGE_OFFSET 0x0218
218 #define KS8841_WOL_CTRL_OFFSET 0x021A
219 #define KS8841_WOL_MAGIC_ENABLE 0x0080
220 #define KS8841_WOL_FRAME3_ENABLE 0x0008
221 #define KS8841_WOL_FRAME2_ENABLE 0x0004
222 #define KS8841_WOL_FRAME1_ENABLE 0x0002
223 #define KS8841_WOL_FRAME0_ENABLE 0x0001
226 #define KS8841_WOL_FRAME_CRC_OFFSET 0x0220
227 #define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224
228 #define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228
231 #define KS884X_IACR_P 0x04A0
232 #define KS884X_IACR_OFFSET KS884X_IACR_P
235 #define KS884X_IADR1_P 0x04A2
236 #define KS884X_IADR2_P 0x04A4
237 #define KS884X_IADR3_P 0x04A6
238 #define KS884X_IADR4_P 0x04A8
239 #define KS884X_IADR5_P 0x04AA
241 #define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P
242 #define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1)
244 #define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P
245 #define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1)
246 #define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P
247 #define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1)
248 #define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P
249 #define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1)
250 #define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P
251 #define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1)
252 #define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P
255 #define KS884X_P1MBCR_P 0x04D0
256 #define KS884X_P1MBSR_P 0x04D2
257 #define KS884X_PHY1ILR_P 0x04D4
258 #define KS884X_PHY1IHR_P 0x04D6
259 #define KS884X_P1ANAR_P 0x04D8
260 #define KS884X_P1ANLPR_P 0x04DA
263 #define KS884X_P2MBCR_P 0x04E0
264 #define KS884X_P2MBSR_P 0x04E2
265 #define KS884X_PHY2ILR_P 0x04E4
266 #define KS884X_PHY2IHR_P 0x04E6
267 #define KS884X_P2ANAR_P 0x04E8
268 #define KS884X_P2ANLPR_P 0x04EA
270 #define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P
271 #define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P)
273 #define KS884X_PHY_CTRL_OFFSET 0x00
275 #define KS884X_PHY_STATUS_OFFSET 0x02
277 #define KS884X_PHY_ID_1_OFFSET 0x04
278 #define KS884X_PHY_ID_2_OFFSET 0x06
280 #define KS884X_PHY_AUTO_NEG_OFFSET 0x08
282 #define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
285 #define KS884X_P1VCT_P 0x04F0
286 #define KS884X_P1PHYCTRL_P 0x04F2
289 #define KS884X_P2VCT_P 0x04F4
290 #define KS884X_P2PHYCTRL_P 0x04F6
292 #define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P
293 #define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P)
295 #define KS884X_PHY_LINK_MD_OFFSET 0x00
297 #define PHY_START_CABLE_DIAG 0x8000
298 #define PHY_CABLE_DIAG_RESULT 0x6000
299 #define PHY_CABLE_STAT_NORMAL 0x0000
300 #define PHY_CABLE_STAT_OPEN 0x2000
301 #define PHY_CABLE_STAT_SHORT 0x4000
302 #define PHY_CABLE_STAT_FAILED 0x6000
303 #define PHY_CABLE_10M_SHORT 0x1000
304 #define PHY_CABLE_FAULT_COUNTER 0x01FF
306 #define KS884X_PHY_PHY_CTRL_OFFSET 0x02
308 #define PHY_STAT_REVERSED_POLARITY 0x0020
309 #define PHY_STAT_MDIX 0x0010
310 #define PHY_FORCE_LINK 0x0008
311 #define PHY_POWER_SAVING_DISABLE 0x0004
312 #define PHY_REMOTE_LOOPBACK 0x0002
315 #define KS884X_SIDER_P 0x0400
316 #define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P
317 #define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1)
319 #define REG_FAMILY_ID 0x88
321 #define REG_CHIP_ID_41 0x8810
322 #define REG_CHIP_ID_42 0x8800
324 #define KS884X_CHIP_ID_MASK_41 0xFF10
325 #define KS884X_CHIP_ID_MASK 0xFFF0
326 #define KS884X_CHIP_ID_SHIFT 4
327 #define KS884X_REVISION_MASK 0x000E
328 #define KS884X_REVISION_SHIFT 1
329 #define KS8842_START 0x0001
331 #define CHIP_IP_41_M 0x8810
332 #define CHIP_IP_42_M 0x8800
333 #define CHIP_IP_61_M 0x8890
334 #define CHIP_IP_62_M 0x8880
336 #define CHIP_IP_41_P 0x8850
337 #define CHIP_IP_42_P 0x8840
338 #define CHIP_IP_61_P 0x88D0
339 #define CHIP_IP_62_P 0x88C0
342 #define KS8842_SGCR1_P 0x0402
343 #define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P
345 #define SWITCH_PASS_ALL 0x8000
346 #define SWITCH_TX_FLOW_CTRL 0x2000
347 #define SWITCH_RX_FLOW_CTRL 0x1000
348 #define SWITCH_CHECK_LENGTH 0x0800
349 #define SWITCH_AGING_ENABLE 0x0400
350 #define SWITCH_FAST_AGING 0x0200
351 #define SWITCH_AGGR_BACKOFF 0x0100
352 #define SWITCH_PASS_PAUSE 0x0008
353 #define SWITCH_LINK_AUTO_AGING 0x0001
356 #define KS8842_SGCR2_P 0x0404
357 #define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P
359 #define SWITCH_VLAN_ENABLE 0x8000
360 #define SWITCH_IGMP_SNOOP 0x4000
361 #define IPV6_MLD_SNOOP_ENABLE 0x2000
362 #define IPV6_MLD_SNOOP_OPTION 0x1000
363 #define PRIORITY_SCHEME_SELECT 0x0800
364 #define SWITCH_MIRROR_RX_TX 0x0100
365 #define UNICAST_VLAN_BOUNDARY 0x0080
366 #define MULTICAST_STORM_DISABLE 0x0040
367 #define SWITCH_BACK_PRESSURE 0x0020
368 #define FAIR_FLOW_CTRL 0x0010
369 #define NO_EXC_COLLISION_DROP 0x0008
370 #define SWITCH_HUGE_PACKET 0x0004
371 #define SWITCH_LEGAL_PACKET 0x0002
372 #define SWITCH_BUF_RESERVE 0x0001
375 #define KS8842_SGCR3_P 0x0406
376 #define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P
378 #define BROADCAST_STORM_RATE_LO 0xFF00
379 #define SWITCH_REPEATER 0x0080
380 #define SWITCH_HALF_DUPLEX 0x0040
381 #define SWITCH_FLOW_CTRL 0x0020
382 #define SWITCH_10_MBIT 0x0010
383 #define SWITCH_REPLACE_NULL_VID 0x0008
384 #define BROADCAST_STORM_RATE_HI 0x0007
386 #define BROADCAST_STORM_RATE 0x07FF
389 #define KS8842_SGCR4_P 0x0408
392 #define KS8842_SGCR5_P 0x040A
393 #define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P
395 #define LED_MODE 0x8200
396 #define LED_SPEED_DUPLEX_ACT 0x0000
397 #define LED_SPEED_DUPLEX_LINK_ACT 0x8000
398 #define LED_DUPLEX_10_100 0x0200
401 #define KS8842_SGCR6_P 0x0410
402 #define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P
404 #define KS8842_PRIORITY_MASK 3
405 #define KS8842_PRIORITY_SHIFT 2
408 #define KS8842_SGCR7_P 0x0412
409 #define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P
411 #define SWITCH_UNK_DEF_PORT_ENABLE 0x0008
412 #define SWITCH_UNK_DEF_PORT_3 0x0004
413 #define SWITCH_UNK_DEF_PORT_2 0x0002
414 #define SWITCH_UNK_DEF_PORT_1 0x0001
417 #define KS8842_MACAR1_P 0x0470
418 #define KS8842_MACAR2_P 0x0472
419 #define KS8842_MACAR3_P 0x0474
420 #define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P
421 #define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1)
422 #define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P
423 #define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1)
424 #define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P
425 #define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1)
428 #define KS8842_TOSR1_P 0x0480
429 #define KS8842_TOSR2_P 0x0482
430 #define KS8842_TOSR3_P 0x0484
431 #define KS8842_TOSR4_P 0x0486
432 #define KS8842_TOSR5_P 0x0488
433 #define KS8842_TOSR6_P 0x048A
434 #define KS8842_TOSR7_P 0x0490
435 #define KS8842_TOSR8_P 0x0492
436 #define KS8842_TOS_1_OFFSET KS8842_TOSR1_P
437 #define KS8842_TOS_2_OFFSET KS8842_TOSR2_P
438 #define KS8842_TOS_3_OFFSET KS8842_TOSR3_P
439 #define KS8842_TOS_4_OFFSET KS8842_TOSR4_P
440 #define KS8842_TOS_5_OFFSET KS8842_TOSR5_P
441 #define KS8842_TOS_6_OFFSET KS8842_TOSR6_P
443 #define KS8842_TOS_7_OFFSET KS8842_TOSR7_P
444 #define KS8842_TOS_8_OFFSET KS8842_TOSR8_P
447 #define KS8842_P1CR1_P 0x0500
448 #define KS8842_P1CR2_P 0x0502
449 #define KS8842_P1VIDR_P 0x0504
450 #define KS8842_P1CR3_P 0x0506
451 #define KS8842_P1IRCR_P 0x0508
452 #define KS8842_P1ERCR_P 0x050A
453 #define KS884X_P1SCSLMD_P 0x0510
454 #define KS884X_P1CR4_P 0x0512
455 #define KS884X_P1SR_P 0x0514
458 #define KS8842_P2CR1_P 0x0520
459 #define KS8842_P2CR2_P 0x0522
460 #define KS8842_P2VIDR_P 0x0524
461 #define KS8842_P2CR3_P 0x0526
462 #define KS8842_P2IRCR_P 0x0528
463 #define KS8842_P2ERCR_P 0x052A
464 #define KS884X_P2SCSLMD_P 0x0530
465 #define KS884X_P2CR4_P 0x0532
466 #define KS884X_P2SR_P 0x0534
469 #define KS8842_P3CR1_P 0x0540
470 #define KS8842_P3CR2_P 0x0542
471 #define KS8842_P3VIDR_P 0x0544
472 #define KS8842_P3CR3_P 0x0546
473 #define KS8842_P3IRCR_P 0x0548
474 #define KS8842_P3ERCR_P 0x054A
476 #define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P
477 #define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P
478 #define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P
480 #define PORT_CTRL_ADDR(port, addr) \
481 (addr = KS8842_PORT_1_CTRL_1 + (port) * \
482 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
484 #define KS8842_PORT_CTRL_1_OFFSET 0x00
486 #define PORT_BROADCAST_STORM 0x0080
487 #define PORT_DIFFSERV_ENABLE 0x0040
488 #define PORT_802_1P_ENABLE 0x0020
489 #define PORT_BASED_PRIORITY_MASK 0x0018
490 #define PORT_BASED_PRIORITY_BASE 0x0003
491 #define PORT_BASED_PRIORITY_SHIFT 3
492 #define PORT_BASED_PRIORITY_0 0x0000
493 #define PORT_BASED_PRIORITY_1 0x0008
494 #define PORT_BASED_PRIORITY_2 0x0010
495 #define PORT_BASED_PRIORITY_3 0x0018
496 #define PORT_INSERT_TAG 0x0004
497 #define PORT_REMOVE_TAG 0x0002
498 #define PORT_PRIO_QUEUE_ENABLE 0x0001
500 #define KS8842_PORT_CTRL_2_OFFSET 0x02
502 #define PORT_INGRESS_VLAN_FILTER 0x4000
503 #define PORT_DISCARD_NON_VID 0x2000
504 #define PORT_FORCE_FLOW_CTRL 0x1000
505 #define PORT_BACK_PRESSURE 0x0800
506 #define PORT_TX_ENABLE 0x0400
507 #define PORT_RX_ENABLE 0x0200
508 #define PORT_LEARN_DISABLE 0x0100
509 #define PORT_MIRROR_SNIFFER 0x0080
510 #define PORT_MIRROR_RX 0x0040
511 #define PORT_MIRROR_TX 0x0020
512 #define PORT_USER_PRIORITY_CEILING 0x0008
513 #define PORT_VLAN_MEMBERSHIP 0x0007
515 #define KS8842_PORT_CTRL_VID_OFFSET 0x04
517 #define PORT_DEFAULT_VID 0x0001
519 #define KS8842_PORT_CTRL_3_OFFSET 0x06
521 #define PORT_INGRESS_LIMIT_MODE 0x000C
522 #define PORT_INGRESS_ALL 0x0000
523 #define PORT_INGRESS_UNICAST 0x0004
524 #define PORT_INGRESS_MULTICAST 0x0008
525 #define PORT_INGRESS_BROADCAST 0x000C
526 #define PORT_COUNT_IFG 0x0002
527 #define PORT_COUNT_PREAMBLE 0x0001
529 #define KS8842_PORT_IN_RATE_OFFSET 0x08
530 #define KS8842_PORT_OUT_RATE_OFFSET 0x0A
532 #define PORT_PRIORITY_RATE 0x0F
533 #define PORT_PRIORITY_RATE_SHIFT 4
535 #define KS884X_PORT_LINK_MD 0x10
537 #define PORT_CABLE_10M_SHORT 0x8000
538 #define PORT_CABLE_DIAG_RESULT 0x6000
539 #define PORT_CABLE_STAT_NORMAL 0x0000
540 #define PORT_CABLE_STAT_OPEN 0x2000
541 #define PORT_CABLE_STAT_SHORT 0x4000
542 #define PORT_CABLE_STAT_FAILED 0x6000
543 #define PORT_START_CABLE_DIAG 0x1000
544 #define PORT_FORCE_LINK 0x0800
545 #define PORT_POWER_SAVING_DISABLE 0x0400
546 #define PORT_PHY_REMOTE_LOOPBACK 0x0200
547 #define PORT_CABLE_FAULT_COUNTER 0x01FF
549 #define KS884X_PORT_CTRL_4_OFFSET 0x12
551 #define PORT_LED_OFF 0x8000
552 #define PORT_TX_DISABLE 0x4000
553 #define PORT_AUTO_NEG_RESTART 0x2000
554 #define PORT_REMOTE_FAULT_DISABLE 0x1000
555 #define PORT_POWER_DOWN 0x0800
556 #define PORT_AUTO_MDIX_DISABLE 0x0400
557 #define PORT_FORCE_MDIX 0x0200
558 #define PORT_LOOPBACK 0x0100
559 #define PORT_AUTO_NEG_ENABLE 0x0080
560 #define PORT_FORCE_100_MBIT 0x0040
561 #define PORT_FORCE_FULL_DUPLEX 0x0020
562 #define PORT_AUTO_NEG_SYM_PAUSE 0x0010
563 #define PORT_AUTO_NEG_100BTX_FD 0x0008
564 #define PORT_AUTO_NEG_100BTX 0x0004
565 #define PORT_AUTO_NEG_10BT_FD 0x0002
566 #define PORT_AUTO_NEG_10BT 0x0001
568 #define KS884X_PORT_STATUS_OFFSET 0x14
570 #define PORT_HP_MDIX 0x8000
571 #define PORT_REVERSED_POLARITY 0x2000
572 #define PORT_RX_FLOW_CTRL 0x0800
573 #define PORT_TX_FLOW_CTRL 0x1000
574 #define PORT_STATUS_SPEED_100MBIT 0x0400
575 #define PORT_STATUS_FULL_DUPLEX 0x0200
576 #define PORT_REMOTE_FAULT 0x0100
577 #define PORT_MDIX_STATUS 0x0080
578 #define PORT_AUTO_NEG_COMPLETE 0x0040
579 #define PORT_STATUS_LINK_GOOD 0x0020
580 #define PORT_REMOTE_SYM_PAUSE 0x0010
581 #define PORT_REMOTE_100BTX_FD 0x0008
582 #define PORT_REMOTE_100BTX 0x0004
583 #define PORT_REMOTE_10BT_FD 0x0002
584 #define PORT_REMOTE_10BT 0x0001
587 #define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
588 #define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000
589 #define STATIC_MAC_TABLE_VALID 00-00080000-00000000
590 #define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000
591 #define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000
592 #define STATIC_MAC_TABLE_FID 00-03C00000-00000000
595 #define STATIC_MAC_TABLE_ADDR 0x0000FFFF
596 #define STATIC_MAC_TABLE_FWD_PORTS 0x00070000
597 #define STATIC_MAC_TABLE_VALID 0x00080000
598 #define STATIC_MAC_TABLE_OVERRIDE 0x00100000
599 #define STATIC_MAC_TABLE_USE_FID 0x00200000
600 #define STATIC_MAC_TABLE_FID 0x03C00000
602 #define STATIC_MAC_FWD_PORTS_SHIFT 16
603 #define STATIC_MAC_FID_SHIFT 22
606 #define VLAN_TABLE_VID 00-00000000-00000FFF
607 #define VLAN_TABLE_FID 00-00000000-0000F000
608 #define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000
609 #define VLAN_TABLE_VALID 00-00000000-00080000
612 #define VLAN_TABLE_VID 0x00000FFF
613 #define VLAN_TABLE_FID 0x0000F000
614 #define VLAN_TABLE_MEMBERSHIP 0x00070000
615 #define VLAN_TABLE_VALID 0x00080000
617 #define VLAN_TABLE_FID_SHIFT 12
618 #define VLAN_TABLE_MEMBERSHIP_SHIFT 16
621 #define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
622 #define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000
623 #define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000
624 #define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000
625 #define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000
626 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000
627 #define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000
628 #define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000
631 #define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
632 #define DYNAMIC_MAC_TABLE_FID 0x000F0000
633 #define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000
634 #define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000
635 #define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000
637 #define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03
638 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04
639 #define DYNAMIC_MAC_TABLE_RESERVED 0x78
640 #define DYNAMIC_MAC_TABLE_NOT_READY 0x80
642 #define DYNAMIC_MAC_FID_SHIFT 16
643 #define DYNAMIC_MAC_SRC_PORT_SHIFT 20
644 #define DYNAMIC_MAC_TIMESTAMP_SHIFT 22
645 #define DYNAMIC_MAC_ENTRIES_SHIFT 24
646 #define DYNAMIC_MAC_ENTRIES_H_SHIFT 8
649 #define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
650 #define MIB_COUNTER_VALID 00-00000000-40000000
651 #define MIB_COUNTER_OVERFLOW 00-00000000-80000000
654 #define MIB_COUNTER_VALUE 0x3FFFFFFF
655 #define MIB_COUNTER_VALID 0x40000000
656 #define MIB_COUNTER_OVERFLOW 0x80000000
658 #define MIB_PACKET_DROPPED 0x0000FFFF
660 #define KS_MIB_PACKET_DROPPED_TX_0 0x100
661 #define KS_MIB_PACKET_DROPPED_TX_1 0x101
662 #define KS_MIB_PACKET_DROPPED_TX 0x102
663 #define KS_MIB_PACKET_DROPPED_RX_0 0x103
664 #define KS_MIB_PACKET_DROPPED_RX_1 0x104
665 #define KS_MIB_PACKET_DROPPED_RX 0x105
667 /* Change default LED mode. */
668 #define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT
670 #define MAC_ADDR_ORDER(i) (ETH_ALEN - 1 - (i))
672 #define MAX_ETHERNET_BODY_SIZE 1500
673 #define ETHERNET_HEADER_SIZE (14 + VLAN_HLEN)
675 #define MAX_ETHERNET_PACKET_SIZE \
676 (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE)
678 #define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4)
679 #define MAX_RX_BUF_SIZE (1912 + 4)
681 #define ADDITIONAL_ENTRIES 16
682 #define MAX_MULTICAST_LIST 32
684 #define HW_MULTICAST_SIZE 8
686 #define HW_TO_DEV_PORT(port) (port - 1)
698 /* total transmit errors */
699 OID_COUNTER_XMIT_ERROR,
701 /* total receive errors */
702 OID_COUNTER_RCV_ERROR,
708 * Hardware descriptor definitions
711 #define DESC_ALIGNMENT 16
712 #define BUFFER_ALIGNMENT 8
714 #define NUM_OF_RX_DESC 64
715 #define NUM_OF_TX_DESC 64
717 #define KS_DESC_RX_FRAME_LEN 0x000007FF
718 #define KS_DESC_RX_FRAME_TYPE 0x00008000
719 #define KS_DESC_RX_ERROR_CRC 0x00010000
720 #define KS_DESC_RX_ERROR_RUNT 0x00020000
721 #define KS_DESC_RX_ERROR_TOO_LONG 0x00040000
722 #define KS_DESC_RX_ERROR_PHY 0x00080000
723 #define KS884X_DESC_RX_PORT_MASK 0x00300000
724 #define KS_DESC_RX_MULTICAST 0x01000000
725 #define KS_DESC_RX_ERROR 0x02000000
726 #define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000
727 #define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000
728 #define KS_DESC_RX_ERROR_CSUM_IP 0x10000000
729 #define KS_DESC_RX_LAST 0x20000000
730 #define KS_DESC_RX_FIRST 0x40000000
731 #define KS_DESC_RX_ERROR_COND \
732 (KS_DESC_RX_ERROR_CRC | \
733 KS_DESC_RX_ERROR_RUNT | \
734 KS_DESC_RX_ERROR_PHY | \
735 KS_DESC_RX_ERROR_TOO_LONG)
737 #define KS_DESC_HW_OWNED 0x80000000
739 #define KS_DESC_BUF_SIZE 0x000007FF
740 #define KS884X_DESC_TX_PORT_MASK 0x00300000
741 #define KS_DESC_END_OF_RING 0x02000000
742 #define KS_DESC_TX_CSUM_GEN_UDP 0x04000000
743 #define KS_DESC_TX_CSUM_GEN_TCP 0x08000000
744 #define KS_DESC_TX_CSUM_GEN_IP 0x10000000
745 #define KS_DESC_TX_LAST 0x20000000
746 #define KS_DESC_TX_FIRST 0x40000000
747 #define KS_DESC_TX_INTERRUPT 0x80000000
749 #define KS_DESC_PORT_SHIFT 20
751 #define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE)
753 #define KS_DESC_TX_MASK \
754 (KS_DESC_TX_INTERRUPT | \
757 KS_DESC_TX_CSUM_GEN_IP | \
758 KS_DESC_TX_CSUM_GEN_TCP | \
759 KS_DESC_TX_CSUM_GEN_UDP | \
762 struct ksz_desc_rx_stat {
763 #ifdef __BIG_ENDIAN_BITFIELD
800 struct ksz_desc_tx_stat {
801 #ifdef __BIG_ENDIAN_BITFIELD
810 struct ksz_desc_rx_buf {
811 #ifdef __BIG_ENDIAN_BITFIELD
824 struct ksz_desc_tx_buf {
825 #ifdef __BIG_ENDIAN_BITFIELD
853 struct ksz_desc_rx_stat rx;
854 struct ksz_desc_tx_stat tx;
859 struct ksz_desc_rx_buf rx;
860 struct ksz_desc_tx_buf tx;
865 * struct ksz_hw_desc - Hardware descriptor data structure
866 * @ctrl: Descriptor control value.
867 * @buf: Descriptor buffer value.
868 * @addr: Physical address of memory buffer.
869 * @next: Pointer to next hardware descriptor.
872 union desc_stat ctrl;
879 * struct ksz_sw_desc - Software descriptor data structure
880 * @ctrl: Descriptor control value.
881 * @buf: Descriptor buffer value.
882 * @buf_size: Current buffers size value in hardware descriptor.
885 union desc_stat ctrl;
891 * struct ksz_dma_buf - OS dependent DMA buffer data structure
892 * @skb: Associated socket buffer.
893 * @dma: Associated physical DMA address.
894 * @len: Actual len used.
903 * struct ksz_desc - Descriptor structure
904 * @phw: Hardware descriptor pointer to uncached physical memory.
905 * @sw: Cached memory to hold hardware descriptor values for
907 * @dma_buf: Operating system dependent data structure to hold physical
908 * memory buffer allocation information.
911 struct ksz_hw_desc *phw;
912 struct ksz_sw_desc sw;
913 struct ksz_dma_buf dma_buf;
916 #define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf))
919 * struct ksz_desc_info - Descriptor information data structure
920 * @ring: First descriptor in the ring.
921 * @cur: Current descriptor being manipulated.
922 * @ring_virt: First hardware descriptor in the ring.
923 * @ring_phys: The physical address of the first descriptor of the ring.
924 * @size: Size of hardware descriptor.
925 * @alloc: Number of descriptors allocated.
926 * @avail: Number of descriptors available for use.
927 * @last: Index for last descriptor released to hardware.
928 * @next: Index for next descriptor available for use.
929 * @mask: Mask for index wrapping.
931 struct ksz_desc_info {
932 struct ksz_desc *ring;
933 struct ksz_desc *cur;
934 struct ksz_hw_desc *ring_virt;
945 * KSZ8842 switch definitions
949 TABLE_STATIC_MAC = 0,
955 #define LEARNED_MAC_TABLE_ENTRIES 1024
956 #define STATIC_MAC_TABLE_ENTRIES 8
959 * struct ksz_mac_table - Static MAC table data structure
960 * @mac_addr: MAC address to filter.
963 * @ports: Port membership.
964 * @override: Override setting.
965 * @use_fid: FID use setting.
966 * @valid: Valid setting indicating the entry is being used.
968 struct ksz_mac_table {
969 u8 mac_addr[ETH_ALEN];
978 #define VLAN_TABLE_ENTRIES 16
981 * struct ksz_vlan_table - VLAN table data structure
984 * @member: Port membership.
986 struct ksz_vlan_table {
992 #define DIFFSERV_ENTRIES 64
993 #define PRIO_802_1P_ENTRIES 8
994 #define PRIO_QUEUES 4
996 #define SWITCH_PORT_NUM 2
997 #define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1)
998 #define HOST_MASK (1 << SWITCH_PORT_NUM)
1002 #define OTHER_PORT 1
1003 #define HOST_PORT SWITCH_PORT_NUM
1005 #define PORT_COUNTER_NUM 0x20
1006 #define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2)
1008 #define MIB_COUNTER_RX_LO_PRIORITY 0x00
1009 #define MIB_COUNTER_RX_HI_PRIORITY 0x01
1010 #define MIB_COUNTER_RX_UNDERSIZE 0x02
1011 #define MIB_COUNTER_RX_FRAGMENT 0x03
1012 #define MIB_COUNTER_RX_OVERSIZE 0x04
1013 #define MIB_COUNTER_RX_JABBER 0x05
1014 #define MIB_COUNTER_RX_SYMBOL_ERR 0x06
1015 #define MIB_COUNTER_RX_CRC_ERR 0x07
1016 #define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08
1017 #define MIB_COUNTER_RX_CTRL_8808 0x09
1018 #define MIB_COUNTER_RX_PAUSE 0x0A
1019 #define MIB_COUNTER_RX_BROADCAST 0x0B
1020 #define MIB_COUNTER_RX_MULTICAST 0x0C
1021 #define MIB_COUNTER_RX_UNICAST 0x0D
1022 #define MIB_COUNTER_RX_OCTET_64 0x0E
1023 #define MIB_COUNTER_RX_OCTET_65_127 0x0F
1024 #define MIB_COUNTER_RX_OCTET_128_255 0x10
1025 #define MIB_COUNTER_RX_OCTET_256_511 0x11
1026 #define MIB_COUNTER_RX_OCTET_512_1023 0x12
1027 #define MIB_COUNTER_RX_OCTET_1024_1522 0x13
1028 #define MIB_COUNTER_TX_LO_PRIORITY 0x14
1029 #define MIB_COUNTER_TX_HI_PRIORITY 0x15
1030 #define MIB_COUNTER_TX_LATE_COLLISION 0x16
1031 #define MIB_COUNTER_TX_PAUSE 0x17
1032 #define MIB_COUNTER_TX_BROADCAST 0x18
1033 #define MIB_COUNTER_TX_MULTICAST 0x19
1034 #define MIB_COUNTER_TX_UNICAST 0x1A
1035 #define MIB_COUNTER_TX_DEFERRED 0x1B
1036 #define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C
1037 #define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1038 #define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1039 #define MIB_COUNTER_TX_MULTI_COLLISION 0x1F
1041 #define MIB_COUNTER_RX_DROPPED_PACKET 0x20
1042 #define MIB_COUNTER_TX_DROPPED_PACKET 0x21
1045 * struct ksz_port_mib - Port MIB data structure
1046 * @cnt_ptr: Current pointer to MIB counter index.
1047 * @link_down: Indication the link has just gone down.
1048 * @state: Connection status of the port.
1049 * @mib_start: The starting counter index. Some ports do not start at 0.
1050 * @counter: 64-bit MIB counter value.
1051 * @dropped: Temporary buffer to remember last read packet dropped values.
1053 * MIB counters needs to be read periodically so that counters do not get
1054 * overflowed and give incorrect values. A right balance is needed to
1055 * satisfy this condition and not waste too much CPU time.
1057 * It is pointless to read MIB counters when the port is disconnected. The
1058 * @state provides the connection status so that MIB counters are read only
1059 * when the port is connected. The @link_down indicates the port is just
1060 * disconnected so that all MIB counters are read one last time to update the
1063 struct ksz_port_mib {
1069 u64 counter[TOTAL_PORT_COUNTER_NUM];
1074 * struct ksz_port_cfg - Port configuration data structure
1076 * @member: Port membership.
1077 * @port_prio: Port priority.
1078 * @rx_rate: Receive priority rate.
1079 * @tx_rate: Transmit priority rate.
1080 * @stp_state: Current Spanning Tree Protocol state.
1082 struct ksz_port_cfg {
1086 u32 rx_rate[PRIO_QUEUES];
1087 u32 tx_rate[PRIO_QUEUES];
1092 * struct ksz_switch - KSZ8842 switch data structure
1093 * @mac_table: MAC table entries information.
1094 * @vlan_table: VLAN table entries information.
1095 * @port_cfg: Port configuration information.
1096 * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS
1097 * (bit7 ~ bit2) field.
1098 * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p
1099 * Tag priority field.
1100 * @br_addr: Bridge address. Used for STP.
1101 * @other_addr: Other MAC address. Used for multiple network device mode.
1102 * @broad_per: Broadcast storm percentage.
1103 * @member: Current port membership. Used for STP.
1106 struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES];
1107 struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES];
1108 struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM];
1110 u8 diffserv[DIFFSERV_ENTRIES];
1111 u8 p_802_1p[PRIO_802_1P_ENTRIES];
1113 u8 br_addr[ETH_ALEN];
1114 u8 other_addr[ETH_ALEN];
1120 #define TX_RATE_UNIT 10000
1123 * struct ksz_port_info - Port information data structure
1124 * @state: Connection status of the port.
1125 * @tx_rate: Transmit rate divided by 10000 to get Mbit.
1126 * @duplex: Duplex mode.
1127 * @advertised: Advertised auto-negotiation setting. Used to determine link.
1128 * @partner: Auto-negotiation partner setting. Used to determine link.
1129 * @port_id: Port index to access actual hardware register.
1130 * @pdev: Pointer to OS dependent network device.
1132 struct ksz_port_info {
1142 #define MAX_TX_HELD_SIZE 52000
1144 /* Hardware features and bug fixes. */
1145 #define LINK_INT_WORKING (1 << 0)
1146 #define SMALL_PACKET_TX_BUG (1 << 1)
1147 #define HALF_DUPLEX_SIGNAL_BUG (1 << 2)
1148 #define RX_HUGE_FRAME (1 << 4)
1149 #define STP_SUPPORT (1 << 8)
1151 /* Software overrides. */
1152 #define PAUSE_FLOW_CTRL (1 << 0)
1153 #define FAST_AGING (1 << 1)
1156 * struct ksz_hw - KSZ884X hardware data structure
1157 * @io: Virtual address assigned.
1158 * @ksz_switch: Pointer to KSZ8842 switch.
1159 * @port_info: Port information.
1160 * @port_mib: Port MIB information.
1161 * @dev_count: Number of network devices this hardware supports.
1162 * @dst_ports: Destination ports in switch for transmission.
1163 * @id: Hardware ID. Used for display only.
1164 * @mib_cnt: Number of MIB counters this hardware has.
1165 * @mib_port_cnt: Number of ports with MIB counters.
1166 * @tx_cfg: Cached transmit control settings.
1167 * @rx_cfg: Cached receive control settings.
1168 * @intr_mask: Current interrupt mask.
1169 * @intr_set: Current interrup set.
1170 * @intr_blocked: Interrupt blocked.
1171 * @rx_desc_info: Receive descriptor information.
1172 * @tx_desc_info: Transmit descriptor information.
1173 * @tx_int_cnt: Transmit interrupt count. Used for TX optimization.
1174 * @tx_int_mask: Transmit interrupt mask. Used for TX optimization.
1175 * @tx_size: Transmit data size. Used for TX optimization.
1176 * The maximum is defined by MAX_TX_HELD_SIZE.
1177 * @perm_addr: Permanent MAC address.
1178 * @override_addr: Overridden MAC address.
1179 * @address: Additional MAC address entries.
1180 * @addr_list_size: Additional MAC address list size.
1181 * @mac_override: Indication of MAC address overridden.
1182 * @promiscuous: Counter to keep track of promiscuous mode set.
1183 * @all_multi: Counter to keep track of all multicast mode set.
1184 * @multi_list: Multicast address entries.
1185 * @multi_bits: Cached multicast hash table settings.
1186 * @multi_list_size: Multicast address list size.
1187 * @enabled: Indication of hardware enabled.
1188 * @rx_stop: Indication of receive process stop.
1190 * @features: Hardware features to enable.
1191 * @overrides: Hardware features to override.
1192 * @parent: Pointer to parent, network device private structure.
1197 struct ksz_switch *ksz_switch;
1198 struct ksz_port_info port_info[SWITCH_PORT_NUM];
1199 struct ksz_port_mib port_mib[TOTAL_PORT_NUM];
1212 struct ksz_desc_info rx_desc_info;
1213 struct ksz_desc_info tx_desc_info;
1219 u8 perm_addr[ETH_ALEN];
1220 u8 override_addr[ETH_ALEN];
1221 u8 address[ADDITIONAL_ENTRIES][ETH_ALEN];
1226 u8 multi_list[MAX_MULTICAST_LIST][ETH_ALEN];
1227 u8 multi_bits[HW_MULTICAST_SIZE];
1248 * struct ksz_port - Virtual port data structure
1249 * @duplex: Duplex mode setting. 1 for half duplex, 2 for full
1250 * duplex, and 0 for auto, which normally results in full
1252 * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and
1253 * 0 for auto, which normally results in 100 Mbit.
1254 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for
1256 * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow
1257 * control, and PHY_FLOW_CTRL for flow control.
1258 * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100
1260 * @first_port: Index of first port this port supports.
1261 * @mib_port_cnt: Number of ports with MIB counters.
1262 * @port_cnt: Number of ports this port supports.
1263 * @counter: Port statistics counter.
1264 * @hw: Pointer to hardware structure.
1265 * @linked: Pointer to port information linked to this port.
1276 u64 counter[OID_COUNTER_LAST];
1279 struct ksz_port_info *linked;
1283 * struct ksz_timer_info - Timer information data structure
1284 * @timer: Kernel timer.
1285 * @cnt: Running timer counter.
1286 * @max: Number of times to run timer; -1 for infinity.
1287 * @period: Timer period in jiffies.
1289 struct ksz_timer_info {
1290 struct timer_list timer;
1297 * struct ksz_shared_mem - OS dependent shared memory data structure
1298 * @dma_addr: Physical DMA address allocated.
1299 * @alloc_size: Allocation size.
1300 * @phys: Actual physical address used.
1301 * @alloc_virt: Virtual address allocated.
1302 * @virt: Actual virtual address used.
1304 struct ksz_shared_mem {
1305 dma_addr_t dma_addr;
1313 * struct ksz_counter_info - OS dependent counter information data structure
1314 * @counter: Wait queue to wakeup after counters are read.
1315 * @time: Next time in jiffies to read counter.
1316 * @read: Indication of counters read in full or not.
1318 struct ksz_counter_info {
1319 wait_queue_head_t counter;
1325 * struct dev_info - Network device information data structure
1326 * @dev: Pointer to network device.
1327 * @pdev: Pointer to PCI device.
1328 * @hw: Hardware structure.
1329 * @desc_pool: Physical memory used for descriptor pool.
1330 * @hwlock: Spinlock to prevent hardware from accessing.
1331 * @lock: Mutex lock to prevent device from accessing.
1332 * @dev_rcv: Receive process function used.
1333 * @last_skb: Socket buffer allocated for descriptor rx fragments.
1334 * @skb_index: Buffer index for receiving fragments.
1335 * @skb_len: Buffer length for receiving fragments.
1336 * @mib_read: Workqueue to read MIB counters.
1337 * @mib_timer_info: Timer to read MIB counters.
1338 * @counter: Used for MIB reading.
1339 * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE;
1340 * the maximum is MAX_RX_BUF_SIZE.
1341 * @opened: Counter to keep track of device open.
1342 * @rx_tasklet: Receive processing tasklet.
1343 * @tx_tasklet: Transmit processing tasklet.
1344 * @wol_enable: Wake-on-LAN enable set by ethtool.
1345 * @wol_support: Wake-on-LAN support used by ethtool.
1346 * @pme_wait: Used for KSZ8841 power management.
1349 struct net_device *dev;
1350 struct pci_dev *pdev;
1353 struct ksz_shared_mem desc_pool;
1358 int (*dev_rcv)(struct dev_info *);
1360 struct sk_buff *last_skb;
1364 struct work_struct mib_read;
1365 struct ksz_timer_info mib_timer_info;
1366 struct ksz_counter_info counter[TOTAL_PORT_NUM];
1371 struct tasklet_struct rx_tasklet;
1372 struct tasklet_struct tx_tasklet;
1376 unsigned long pme_wait;
1380 * struct dev_priv - Network device private data structure
1381 * @adapter: Adapter device information.
1382 * @port: Port information.
1383 * @monitor_timer_info: Timer to monitor ports.
1384 * @proc_sem: Semaphore for proc accessing.
1386 * @mii_if: MII interface information.
1387 * @advertising: Temporary variable to store advertised settings.
1388 * @msg_enable: The message flags controlling driver output.
1389 * @media_state: The connection status of the device.
1390 * @multicast: The all multicast state of the device.
1391 * @promiscuous: The promiscuous state of the device.
1394 struct dev_info *adapter;
1395 struct ksz_port port;
1396 struct ksz_timer_info monitor_timer_info;
1398 struct semaphore proc_sem;
1401 struct mii_if_info mii_if;
1410 #define DRV_NAME "KSZ884X PCI"
1411 #define DEVICE_NAME "KSZ884x PCI"
1412 #define DRV_VERSION "1.0.0"
1413 #define DRV_RELDATE "Feb 8, 2010"
1415 static char version[] =
1416 "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")";
1418 static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1421 * Interrupt processing primary routines
1424 static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt)
1426 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
1429 static inline void hw_dis_intr(struct ksz_hw *hw)
1431 hw->intr_blocked = hw->intr_mask;
1432 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
1433 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1436 static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt)
1438 hw->intr_set = interrupt;
1439 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
1442 static inline void hw_ena_intr(struct ksz_hw *hw)
1444 hw->intr_blocked = 0;
1445 hw_set_intr(hw, hw->intr_mask);
1448 static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit)
1450 hw->intr_mask &= ~(bit);
1453 static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt)
1457 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1458 hw->intr_set = read_intr & ~interrupt;
1459 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1460 hw_dis_intr_bit(hw, interrupt);
1464 * hw_turn_on_intr - turn on specified interrupts
1465 * @hw: The hardware instance.
1466 * @bit: The interrupt bits to be on.
1468 * This routine turns on the specified interrupts in the interrupt mask so that
1469 * those interrupts will be enabled.
1471 static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit)
1473 hw->intr_mask |= bit;
1475 if (!hw->intr_blocked)
1476 hw_set_intr(hw, hw->intr_mask);
1479 static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt)
1483 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1484 hw->intr_set = read_intr | interrupt;
1485 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1488 static inline void hw_read_intr(struct ksz_hw *hw, uint *status)
1490 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS);
1491 *status = *status & hw->intr_set;
1494 static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt)
1501 * hw_block_intr - block hardware interrupts
1502 * @hw: The hardware instance.
1504 * This function blocks all interrupts of the hardware and returns the current
1505 * interrupt enable mask so that interrupts can be restored later.
1507 * Return the current interrupt enable mask.
1509 static uint hw_block_intr(struct ksz_hw *hw)
1513 if (!hw->intr_blocked) {
1515 interrupt = hw->intr_blocked;
1521 * Hardware descriptor routines
1524 static inline void reset_desc(struct ksz_desc *desc, union desc_stat status)
1526 status.rx.hw_owned = 0;
1527 desc->phw->ctrl.data = cpu_to_le32(status.data);
1530 static inline void release_desc(struct ksz_desc *desc)
1532 desc->sw.ctrl.tx.hw_owned = 1;
1533 if (desc->sw.buf_size != desc->sw.buf.data) {
1534 desc->sw.buf_size = desc->sw.buf.data;
1535 desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data);
1537 desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data);
1540 static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc)
1542 *desc = &info->ring[info->last];
1544 info->last &= info->mask;
1546 (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK;
1549 static inline void set_rx_buf(struct ksz_desc *desc, u32 addr)
1551 desc->phw->addr = cpu_to_le32(addr);
1554 static inline void set_rx_len(struct ksz_desc *desc, u32 len)
1556 desc->sw.buf.rx.buf_size = len;
1559 static inline void get_tx_pkt(struct ksz_desc_info *info,
1560 struct ksz_desc **desc)
1562 *desc = &info->ring[info->next];
1564 info->next &= info->mask;
1566 (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK;
1569 static inline void set_tx_buf(struct ksz_desc *desc, u32 addr)
1571 desc->phw->addr = cpu_to_le32(addr);
1574 static inline void set_tx_len(struct ksz_desc *desc, u32 len)
1576 desc->sw.buf.tx.buf_size = len;
1579 /* Switch functions */
1581 #define TABLE_READ 0x10
1582 #define TABLE_SEL_SHIFT 2
1584 #define HW_DELAY(hw, reg) \
1586 readw(hw->io + reg); \
1590 * sw_r_table - read 4 bytes of data from switch table
1591 * @hw: The hardware instance.
1592 * @table: The table selector.
1593 * @addr: The address of the table entry.
1594 * @data: Buffer to store the read data.
1596 * This routine reads 4 bytes of data from the table of the switch.
1597 * Hardware interrupts are disabled to minimize corruption of read data.
1599 static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1604 ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr;
1606 interrupt = hw_block_intr(hw);
1608 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1609 HW_DELAY(hw, KS884X_IACR_OFFSET);
1610 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1612 hw_restore_intr(hw, interrupt);
1616 * sw_w_table_64 - write 8 bytes of data to the switch table
1617 * @hw: The hardware instance.
1618 * @table: The table selector.
1619 * @addr: The address of the table entry.
1620 * @data_hi: The high part of data to be written (bit63 ~ bit32).
1621 * @data_lo: The low part of data to be written (bit31 ~ bit0).
1623 * This routine writes 8 bytes of data to the table of the switch.
1624 * Hardware interrupts are disabled to minimize corruption of written data.
1626 static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi,
1632 ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr;
1634 interrupt = hw_block_intr(hw);
1636 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
1637 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
1639 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1640 HW_DELAY(hw, KS884X_IACR_OFFSET);
1642 hw_restore_intr(hw, interrupt);
1646 * sw_w_sta_mac_table - write to the static MAC table
1647 * @hw: The hardware instance.
1648 * @addr: The address of the table entry.
1649 * @mac_addr: The MAC address.
1650 * @ports: The port members.
1651 * @override: The flag to override the port receive/transmit settings.
1652 * @valid: The flag to indicate entry is valid.
1653 * @use_fid: The flag to indicate the FID is valid.
1654 * @fid: The FID value.
1656 * This routine writes an entry of the static MAC table of the switch. It
1657 * calls sw_w_table_64() to write the data.
1659 static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr,
1660 u8 ports, int override, int valid, int use_fid, u8 fid)
1665 data_lo = ((u32) mac_addr[2] << 24) |
1666 ((u32) mac_addr[3] << 16) |
1667 ((u32) mac_addr[4] << 8) | mac_addr[5];
1668 data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1];
1669 data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT;
1672 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
1674 data_hi |= STATIC_MAC_TABLE_USE_FID;
1675 data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT;
1678 data_hi |= STATIC_MAC_TABLE_VALID;
1680 sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo);
1684 * sw_r_vlan_table - read from the VLAN table
1685 * @hw: The hardware instance.
1686 * @addr: The address of the table entry.
1687 * @vid: Buffer to store the VID.
1688 * @fid: Buffer to store the VID.
1689 * @member: Buffer to store the port membership.
1691 * This function reads an entry of the VLAN table of the switch. It calls
1692 * sw_r_table() to get the data.
1694 * Return 0 if the entry is valid; otherwise -1.
1696 static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid,
1701 sw_r_table(hw, TABLE_VLAN, addr, &data);
1702 if (data & VLAN_TABLE_VALID) {
1703 *vid = (u16)(data & VLAN_TABLE_VID);
1704 *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT);
1705 *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >>
1706 VLAN_TABLE_MEMBERSHIP_SHIFT);
1713 * port_r_mib_cnt - read MIB counter
1714 * @hw: The hardware instance.
1715 * @port: The port index.
1716 * @addr: The address of the counter.
1717 * @cnt: Buffer to store the counter.
1719 * This routine reads a MIB counter of the port.
1720 * Hardware interrupts are disabled to minimize corruption of read data.
1722 static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt)
1729 ctrl_addr = addr + PORT_COUNTER_NUM * port;
1731 interrupt = hw_block_intr(hw);
1733 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8);
1734 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1735 HW_DELAY(hw, KS884X_IACR_OFFSET);
1737 for (timeout = 100; timeout > 0; timeout--) {
1738 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1740 if (data & MIB_COUNTER_VALID) {
1741 if (data & MIB_COUNTER_OVERFLOW)
1742 *cnt += MIB_COUNTER_VALUE + 1;
1743 *cnt += data & MIB_COUNTER_VALUE;
1748 hw_restore_intr(hw, interrupt);
1752 * port_r_mib_pkt - read dropped packet counts
1753 * @hw: The hardware instance.
1754 * @port: The port index.
1756 * @cnt: Buffer to store the receive and transmit dropped packet counts.
1758 * This routine reads the dropped packet counts of the port.
1759 * Hardware interrupts are disabled to minimize corruption of read data.
1761 static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt)
1769 index = KS_MIB_PACKET_DROPPED_RX_0 + port;
1771 interrupt = hw_block_intr(hw);
1773 ctrl_addr = (u16) index;
1774 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ)
1776 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1777 HW_DELAY(hw, KS884X_IACR_OFFSET);
1778 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1780 hw_restore_intr(hw, interrupt);
1782 data &= MIB_PACKET_DROPPED;
1787 data += MIB_PACKET_DROPPED + 1;
1793 index -= KS_MIB_PACKET_DROPPED_TX -
1794 KS_MIB_PACKET_DROPPED_TX_0 + 1;
1795 } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port);
1799 * port_r_cnt - read MIB counters periodically
1800 * @hw: The hardware instance.
1801 * @port: The port index.
1803 * This routine is used to read the counters of the port periodically to avoid
1804 * counter overflow. The hardware should be acquired first before calling this
1807 * Return non-zero when not all counters not read.
1809 static int port_r_cnt(struct ksz_hw *hw, int port)
1811 struct ksz_port_mib *mib = &hw->port_mib[port];
1813 if (mib->mib_start < PORT_COUNTER_NUM)
1814 while (mib->cnt_ptr < PORT_COUNTER_NUM) {
1815 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1816 &mib->counter[mib->cnt_ptr]);
1819 if (hw->mib_cnt > PORT_COUNTER_NUM)
1820 port_r_mib_pkt(hw, port, mib->dropped,
1821 &mib->counter[PORT_COUNTER_NUM]);
1827 * port_init_cnt - initialize MIB counter values
1828 * @hw: The hardware instance.
1829 * @port: The port index.
1831 * This routine is used to initialize all counters to zero if the hardware
1832 * cannot do it after reset.
1834 static void port_init_cnt(struct ksz_hw *hw, int port)
1836 struct ksz_port_mib *mib = &hw->port_mib[port];
1839 if (mib->mib_start < PORT_COUNTER_NUM)
1841 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1842 &mib->counter[mib->cnt_ptr]);
1844 } while (mib->cnt_ptr < PORT_COUNTER_NUM);
1845 if (hw->mib_cnt > PORT_COUNTER_NUM)
1846 port_r_mib_pkt(hw, port, mib->dropped,
1847 &mib->counter[PORT_COUNTER_NUM]);
1848 memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
1857 * port_chk - check port register bits
1858 * @hw: The hardware instance.
1859 * @port: The port index.
1860 * @offset: The offset of the port register.
1861 * @bits: The data bits to check.
1863 * This function checks whether the specified bits of the port register are set
1866 * Return 0 if the bits are not set.
1868 static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits)
1873 PORT_CTRL_ADDR(port, addr);
1875 data = readw(hw->io + addr);
1876 return (data & bits) == bits;
1880 * port_cfg - set port register bits
1881 * @hw: The hardware instance.
1882 * @port: The port index.
1883 * @offset: The offset of the port register.
1884 * @bits: The data bits to set.
1885 * @set: The flag indicating whether the bits are to be set or not.
1887 * This routine sets or resets the specified bits of the port register.
1889 static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits,
1895 PORT_CTRL_ADDR(port, addr);
1897 data = readw(hw->io + addr);
1902 writew(data, hw->io + addr);
1906 * port_chk_shift - check port bit
1907 * @hw: The hardware instance.
1908 * @port: The port index.
1909 * @addr: The offset of the register.
1910 * @shift: Number of bits to shift.
1912 * This function checks whether the specified port is set in the register or
1915 * Return 0 if the port is not set.
1917 static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift)
1920 u16 bit = 1 << port;
1922 data = readw(hw->io + addr);
1924 return (data & bit) == bit;
1928 * port_cfg_shift - set port bit
1929 * @hw: The hardware instance.
1930 * @port: The port index.
1931 * @addr: The offset of the register.
1932 * @shift: Number of bits to shift.
1933 * @set: The flag indicating whether the port is to be set or not.
1935 * This routine sets or resets the specified port in the register.
1937 static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift,
1941 u16 bits = 1 << port;
1943 data = readw(hw->io + addr);
1949 writew(data, hw->io + addr);
1953 * port_r8 - read byte from port register
1954 * @hw: The hardware instance.
1955 * @port: The port index.
1956 * @offset: The offset of the port register.
1957 * @data: Buffer to store the data.
1959 * This routine reads a byte from the port register.
1961 static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data)
1965 PORT_CTRL_ADDR(port, addr);
1967 *data = readb(hw->io + addr);
1971 * port_r16 - read word from port register.
1972 * @hw: The hardware instance.
1973 * @port: The port index.
1974 * @offset: The offset of the port register.
1975 * @data: Buffer to store the data.
1977 * This routine reads a word from the port register.
1979 static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data)
1983 PORT_CTRL_ADDR(port, addr);
1985 *data = readw(hw->io + addr);
1989 * port_w16 - write word to port register.
1990 * @hw: The hardware instance.
1991 * @port: The port index.
1992 * @offset: The offset of the port register.
1993 * @data: Data to write.
1995 * This routine writes a word to the port register.
1997 static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data)
2001 PORT_CTRL_ADDR(port, addr);
2003 writew(data, hw->io + addr);
2007 * sw_chk - check switch register bits
2008 * @hw: The hardware instance.
2009 * @addr: The address of the switch register.
2010 * @bits: The data bits to check.
2012 * This function checks whether the specified bits of the switch register are
2015 * Return 0 if the bits are not set.
2017 static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits)
2021 data = readw(hw->io + addr);
2022 return (data & bits) == bits;
2026 * sw_cfg - set switch register bits
2027 * @hw: The hardware instance.
2028 * @addr: The address of the switch register.
2029 * @bits: The data bits to set.
2030 * @set: The flag indicating whether the bits are to be set or not.
2032 * This function sets or resets the specified bits of the switch register.
2034 static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set)
2038 data = readw(hw->io + addr);
2043 writew(data, hw->io + addr);
2048 static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set)
2051 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set);
2054 static inline int port_chk_broad_storm(struct ksz_hw *hw, int p)
2056 return port_chk(hw, p,
2057 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM);
2060 /* Driver set switch broadcast storm protection at 10% rate. */
2061 #define BROADCAST_STORM_PROTECTION_RATE 10
2063 /* 148,800 frames * 67 ms / 100 */
2064 #define BROADCAST_STORM_VALUE 9969
2067 * sw_cfg_broad_storm - configure broadcast storm threshold
2068 * @hw: The hardware instance.
2069 * @percent: Broadcast storm threshold in percent of transmit rate.
2071 * This routine configures the broadcast storm threshold of the switch.
2073 static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2076 u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100);
2078 if (value > BROADCAST_STORM_RATE)
2079 value = BROADCAST_STORM_RATE;
2081 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2082 data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI);
2083 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8);
2084 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2088 * sw_get_broad_storm - get broadcast storm threshold
2089 * @hw: The hardware instance.
2090 * @percent: Buffer to store the broadcast storm threshold percentage.
2092 * This routine retrieves the broadcast storm threshold of the switch.
2094 static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent)
2099 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2100 num = (data & BROADCAST_STORM_RATE_HI);
2102 num |= (data & BROADCAST_STORM_RATE_LO) >> 8;
2103 num = DIV_ROUND_CLOSEST(num * 100, BROADCAST_STORM_VALUE);
2104 *percent = (u8) num;
2108 * sw_dis_broad_storm - disable broadstorm
2109 * @hw: The hardware instance.
2110 * @port: The port index.
2112 * This routine disables the broadcast storm limit function of the switch.
2114 static void sw_dis_broad_storm(struct ksz_hw *hw, int port)
2116 port_cfg_broad_storm(hw, port, 0);
2120 * sw_ena_broad_storm - enable broadcast storm
2121 * @hw: The hardware instance.
2122 * @port: The port index.
2124 * This routine enables the broadcast storm limit function of the switch.
2126 static void sw_ena_broad_storm(struct ksz_hw *hw, int port)
2128 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2129 port_cfg_broad_storm(hw, port, 1);
2133 * sw_init_broad_storm - initialize broadcast storm
2134 * @hw: The hardware instance.
2136 * This routine initializes the broadcast storm limit function of the switch.
2138 static void sw_init_broad_storm(struct ksz_hw *hw)
2142 hw->ksz_switch->broad_per = 1;
2143 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2144 for (port = 0; port < TOTAL_PORT_NUM; port++)
2145 sw_dis_broad_storm(hw, port);
2146 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1);
2150 * hw_cfg_broad_storm - configure broadcast storm
2151 * @hw: The hardware instance.
2152 * @percent: Broadcast storm threshold in percent of transmit rate.
2154 * This routine configures the broadcast storm threshold of the switch.
2155 * It is called by user functions. The hardware should be acquired first.
2157 static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2162 sw_cfg_broad_storm(hw, percent);
2163 sw_get_broad_storm(hw, &percent);
2164 hw->ksz_switch->broad_per = percent;
2168 * sw_dis_prio_rate - disable switch priority rate
2169 * @hw: The hardware instance.
2170 * @port: The port index.
2172 * This routine disables the priority rate function of the switch.
2174 static void sw_dis_prio_rate(struct ksz_hw *hw, int port)
2178 PORT_CTRL_ADDR(port, addr);
2179 addr += KS8842_PORT_IN_RATE_OFFSET;
2180 writel(0, hw->io + addr);
2184 * sw_init_prio_rate - initialize switch prioirty rate
2185 * @hw: The hardware instance.
2187 * This routine initializes the priority rate function of the switch.
2189 static void sw_init_prio_rate(struct ksz_hw *hw)
2193 struct ksz_switch *sw = hw->ksz_switch;
2195 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2196 for (prio = 0; prio < PRIO_QUEUES; prio++) {
2197 sw->port_cfg[port].rx_rate[prio] =
2198 sw->port_cfg[port].tx_rate[prio] = 0;
2200 sw_dis_prio_rate(hw, port);
2206 static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set)
2209 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set);
2212 static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set)
2215 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL, set);
2218 static inline int port_chk_back_pressure(struct ksz_hw *hw, int p)
2220 return port_chk(hw, p,
2221 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE);
2224 static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p)
2226 return port_chk(hw, p,
2227 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL);
2232 static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set)
2235 KS8842_PORT_CTRL_2_OFFSET, PORT_RX_ENABLE, set);
2238 static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set)
2241 KS8842_PORT_CTRL_2_OFFSET, PORT_TX_ENABLE, set);
2244 static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set)
2246 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set);
2249 static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw)
2251 if (!(hw->overrides & FAST_AGING)) {
2252 sw_cfg_fast_aging(hw, 1);
2254 sw_cfg_fast_aging(hw, 0);
2260 static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert)
2263 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG, insert);
2266 static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove)
2269 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG, remove);
2272 static inline int port_chk_ins_tag(struct ksz_hw *hw, int p)
2274 return port_chk(hw, p,
2275 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG);
2278 static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p)
2280 return port_chk(hw, p,
2281 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG);
2284 static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set)
2287 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID, set);
2290 static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set)
2293 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER, set);
2296 static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p)
2298 return port_chk(hw, p,
2299 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID);
2302 static inline int port_chk_in_filter(struct ksz_hw *hw, int p)
2304 return port_chk(hw, p,
2305 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER);
2310 static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set)
2313 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set);
2316 static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set)
2319 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set);
2322 static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set)
2325 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set);
2328 static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set)
2330 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set);
2333 static void sw_init_mirror(struct ksz_hw *hw)
2337 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2338 port_cfg_mirror_sniffer(hw, port, 0);
2339 port_cfg_mirror_rx(hw, port, 0);
2340 port_cfg_mirror_tx(hw, port, 0);
2342 sw_cfg_mirror_rx_tx(hw, 0);
2345 static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set)
2347 sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2348 SWITCH_UNK_DEF_PORT_ENABLE, set);
2351 static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw)
2353 return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2354 SWITCH_UNK_DEF_PORT_ENABLE);
2357 static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set)
2359 port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set);
2362 static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port)
2364 return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0);
2369 static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set)
2372 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set);
2375 static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set)
2378 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set);
2381 static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set)
2384 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set);
2387 static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set)
2390 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set);
2393 static inline int port_chk_diffserv(struct ksz_hw *hw, int p)
2395 return port_chk(hw, p,
2396 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE);
2399 static inline int port_chk_802_1p(struct ksz_hw *hw, int p)
2401 return port_chk(hw, p,
2402 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE);
2405 static inline int port_chk_replace_vid(struct ksz_hw *hw, int p)
2407 return port_chk(hw, p,
2408 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING);
2411 static inline int port_chk_prio(struct ksz_hw *hw, int p)
2413 return port_chk(hw, p,
2414 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE);
2418 * sw_dis_diffserv - disable switch DiffServ priority
2419 * @hw: The hardware instance.
2420 * @port: The port index.
2422 * This routine disables the DiffServ priority function of the switch.
2424 static void sw_dis_diffserv(struct ksz_hw *hw, int port)
2426 port_cfg_diffserv(hw, port, 0);
2430 * sw_dis_802_1p - disable switch 802.1p priority
2431 * @hw: The hardware instance.
2432 * @port: The port index.
2434 * This routine disables the 802.1p priority function of the switch.
2436 static void sw_dis_802_1p(struct ksz_hw *hw, int port)
2438 port_cfg_802_1p(hw, port, 0);
2442 * sw_cfg_replace_null_vid -
2443 * @hw: The hardware instance.
2444 * @set: The flag to disable or enable.
2447 static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set)
2449 sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set);
2453 * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping
2454 * @hw: The hardware instance.
2455 * @port: The port index.
2456 * @set: The flag to disable or enable.
2458 * This routine enables the 802.1p priority re-mapping function of the switch.
2459 * That allows 802.1p priority field to be replaced with the port's default
2460 * tag's priority value if the ingress packet's 802.1p priority has a higher
2461 * priority than port's default tag's priority.
2463 static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set)
2465 port_cfg_replace_vid(hw, port, set);
2469 * sw_cfg_port_based - configure switch port based priority
2470 * @hw: The hardware instance.
2471 * @port: The port index.
2472 * @prio: The priority to set.
2474 * This routine configures the port based priority of the switch.
2476 static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio)
2480 if (prio > PORT_BASED_PRIORITY_BASE)
2481 prio = PORT_BASED_PRIORITY_BASE;
2483 hw->ksz_switch->port_cfg[port].port_prio = prio;
2485 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data);
2486 data &= ~PORT_BASED_PRIORITY_MASK;
2487 data |= prio << PORT_BASED_PRIORITY_SHIFT;
2488 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data);
2492 * sw_dis_multi_queue - disable transmit multiple queues
2493 * @hw: The hardware instance.
2494 * @port: The port index.
2496 * This routine disables the transmit multiple queues selection of the switch
2497 * port. Only single transmit queue on the port.
2499 static void sw_dis_multi_queue(struct ksz_hw *hw, int port)
2501 port_cfg_prio(hw, port, 0);
2505 * sw_init_prio - initialize switch priority
2506 * @hw: The hardware instance.
2508 * This routine initializes the switch QoS priority functions.
2510 static void sw_init_prio(struct ksz_hw *hw)
2514 struct ksz_switch *sw = hw->ksz_switch;
2517 * Init all the 802.1p tag priority value to be assigned to different
2520 sw->p_802_1p[0] = 0;
2521 sw->p_802_1p[1] = 0;
2522 sw->p_802_1p[2] = 1;
2523 sw->p_802_1p[3] = 1;
2524 sw->p_802_1p[4] = 2;
2525 sw->p_802_1p[5] = 2;
2526 sw->p_802_1p[6] = 3;
2527 sw->p_802_1p[7] = 3;
2530 * Init all the DiffServ priority value to be assigned to priority
2533 for (tos = 0; tos < DIFFSERV_ENTRIES; tos++)
2534 sw->diffserv[tos] = 0;
2536 /* All QoS functions disabled. */
2537 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2538 sw_dis_multi_queue(hw, port);
2539 sw_dis_diffserv(hw, port);
2540 sw_dis_802_1p(hw, port);
2541 sw_cfg_replace_vid(hw, port, 0);
2543 sw->port_cfg[port].port_prio = 0;
2544 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio);
2546 sw_cfg_replace_null_vid(hw, 0);
2550 * port_get_def_vid - get port default VID.
2551 * @hw: The hardware instance.
2552 * @port: The port index.
2553 * @vid: Buffer to store the VID.
2555 * This routine retrieves the default VID of the port.
2557 static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid)
2561 PORT_CTRL_ADDR(port, addr);
2562 addr += KS8842_PORT_CTRL_VID_OFFSET;
2563 *vid = readw(hw->io + addr);
2567 * sw_init_vlan - initialize switch VLAN
2568 * @hw: The hardware instance.
2570 * This routine initializes the VLAN function of the switch.
2572 static void sw_init_vlan(struct ksz_hw *hw)
2576 struct ksz_switch *sw = hw->ksz_switch;
2578 /* Read 16 VLAN entries from device's VLAN table. */
2579 for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) {
2580 sw_r_vlan_table(hw, entry,
2581 &sw->vlan_table[entry].vid,
2582 &sw->vlan_table[entry].fid,
2583 &sw->vlan_table[entry].member);
2586 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2587 port_get_def_vid(hw, port, &sw->port_cfg[port].vid);
2588 sw->port_cfg[port].member = PORT_MASK;
2593 * sw_cfg_port_base_vlan - configure port-based VLAN membership
2594 * @hw: The hardware instance.
2595 * @port: The port index.
2596 * @member: The port-based VLAN membership.
2598 * This routine configures the port-based VLAN membership of the port.
2600 static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member)
2605 PORT_CTRL_ADDR(port, addr);
2606 addr += KS8842_PORT_CTRL_2_OFFSET;
2608 data = readb(hw->io + addr);
2609 data &= ~PORT_VLAN_MEMBERSHIP;
2610 data |= (member & PORT_MASK);
2611 writeb(data, hw->io + addr);
2613 hw->ksz_switch->port_cfg[port].member = member;
2617 * sw_get_addr - get the switch MAC address.
2618 * @hw: The hardware instance.
2619 * @mac_addr: Buffer to store the MAC address.
2621 * This function retrieves the MAC address of the switch.
2623 static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr)
2627 for (i = 0; i < 6; i += 2) {
2628 mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2629 mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2634 * sw_set_addr - configure switch MAC address
2635 * @hw: The hardware instance.
2636 * @mac_addr: The MAC address.
2638 * This function configures the MAC address of the switch.
2640 static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr)
2644 for (i = 0; i < 6; i += 2) {
2645 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2646 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2651 * sw_set_global_ctrl - set switch global control
2652 * @hw: The hardware instance.
2654 * This routine sets the global control of the switch function.
2656 static void sw_set_global_ctrl(struct ksz_hw *hw)
2660 /* Enable switch MII flow control. */
2661 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2662 data |= SWITCH_FLOW_CTRL;
2663 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2665 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2667 /* Enable aggressive back off algorithm in half duplex mode. */
2668 data |= SWITCH_AGGR_BACKOFF;
2670 /* Enable automatic fast aging when link changed detected. */
2671 data |= SWITCH_AGING_ENABLE;
2672 data |= SWITCH_LINK_AUTO_AGING;
2674 if (hw->overrides & FAST_AGING)
2675 data |= SWITCH_FAST_AGING;
2677 data &= ~SWITCH_FAST_AGING;
2678 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2680 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2682 /* Enable no excessive collision drop. */
2683 data |= NO_EXC_COLLISION_DROP;
2684 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2688 STP_STATE_DISABLED = 0,
2689 STP_STATE_LISTENING,
2691 STP_STATE_FORWARDING,
2697 * port_set_stp_state - configure port spanning tree state
2698 * @hw: The hardware instance.
2699 * @port: The port index.
2700 * @state: The spanning tree state.
2702 * This routine configures the spanning tree state of the port.
2704 static void port_set_stp_state(struct ksz_hw *hw, int port, int state)
2708 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data);
2710 case STP_STATE_DISABLED:
2711 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2712 data |= PORT_LEARN_DISABLE;
2714 case STP_STATE_LISTENING:
2716 * No need to turn on transmit because of port direct mode.
2717 * Turning on receive is required if static MAC table is not setup.
2719 data &= ~PORT_TX_ENABLE;
2720 data |= PORT_RX_ENABLE;
2721 data |= PORT_LEARN_DISABLE;
2723 case STP_STATE_LEARNING:
2724 data &= ~PORT_TX_ENABLE;
2725 data |= PORT_RX_ENABLE;
2726 data &= ~PORT_LEARN_DISABLE;
2728 case STP_STATE_FORWARDING:
2729 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2730 data &= ~PORT_LEARN_DISABLE;
2732 case STP_STATE_BLOCKED:
2734 * Need to setup static MAC table with override to keep receiving BPDU
2735 * messages. See sw_init_stp routine.
2737 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2738 data |= PORT_LEARN_DISABLE;
2740 case STP_STATE_SIMPLE:
2741 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2742 data |= PORT_LEARN_DISABLE;
2745 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data);
2746 hw->ksz_switch->port_cfg[port].stp_state = state;
2750 #define BROADCAST_ENTRY 1
2751 #define BRIDGE_ADDR_ENTRY 2
2752 #define IPV6_ADDR_ENTRY 3
2755 * sw_clr_sta_mac_table - clear static MAC table
2756 * @hw: The hardware instance.
2758 * This routine clears the static MAC table.
2760 static void sw_clr_sta_mac_table(struct ksz_hw *hw)
2762 struct ksz_mac_table *entry;
2765 for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) {
2766 entry = &hw->ksz_switch->mac_table[i];
2767 sw_w_sta_mac_table(hw, i,
2768 entry->mac_addr, entry->ports,
2770 entry->use_fid, entry->fid);
2775 * sw_init_stp - initialize switch spanning tree support
2776 * @hw: The hardware instance.
2778 * This routine initializes the spanning tree support of the switch.
2780 static void sw_init_stp(struct ksz_hw *hw)
2782 struct ksz_mac_table *entry;
2784 entry = &hw->ksz_switch->mac_table[STP_ENTRY];
2785 entry->mac_addr[0] = 0x01;
2786 entry->mac_addr[1] = 0x80;
2787 entry->mac_addr[2] = 0xC2;
2788 entry->mac_addr[3] = 0x00;
2789 entry->mac_addr[4] = 0x00;
2790 entry->mac_addr[5] = 0x00;
2791 entry->ports = HOST_MASK;
2792 entry->override = 1;
2794 sw_w_sta_mac_table(hw, STP_ENTRY,
2795 entry->mac_addr, entry->ports,
2796 entry->override, entry->valid,
2797 entry->use_fid, entry->fid);
2801 * sw_block_addr - block certain packets from the host port
2802 * @hw: The hardware instance.
2804 * This routine blocks certain packets from reaching to the host port.
2806 static void sw_block_addr(struct ksz_hw *hw)
2808 struct ksz_mac_table *entry;
2811 for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) {
2812 entry = &hw->ksz_switch->mac_table[i];
2814 sw_w_sta_mac_table(hw, i,
2815 entry->mac_addr, entry->ports,
2816 entry->override, entry->valid,
2817 entry->use_fid, entry->fid);
2821 static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
2823 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2826 static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data)
2828 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2831 static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data)
2833 *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET);
2836 static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data)
2838 *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2841 static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data)
2843 writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2846 static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data)
2848 *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET);
2851 static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data)
2853 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2856 static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data)
2858 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2861 static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data)
2863 *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2866 static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data)
2868 writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2871 static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data)
2873 *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2876 static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data)
2878 writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2882 * hw_r_phy - read data from PHY register
2883 * @hw: The hardware instance.
2884 * @port: Port to read.
2885 * @reg: PHY register to read.
2886 * @val: Buffer to store the read data.
2888 * This routine reads data from the PHY register.
2890 static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val)
2894 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2895 *val = readw(hw->io + phy);
2899 * hw_w_phy - write data to PHY register
2900 * @hw: The hardware instance.
2901 * @port: Port to write.
2902 * @reg: PHY register to write.
2903 * @val: Word data to write.
2905 * This routine writes data to the PHY register.
2907 static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val)
2911 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2912 writew(val, hw->io + phy);
2916 * EEPROM access functions
2919 #define AT93C_CODE 0
2920 #define AT93C_WR_OFF 0x00
2921 #define AT93C_WR_ALL 0x10
2922 #define AT93C_ER_ALL 0x20
2923 #define AT93C_WR_ON 0x30
2925 #define AT93C_WRITE 1
2926 #define AT93C_READ 2
2927 #define AT93C_ERASE 3
2929 #define EEPROM_DELAY 4
2931 static inline void drop_gpio(struct ksz_hw *hw, u8 gpio)
2935 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
2937 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
2940 static inline void raise_gpio(struct ksz_hw *hw, u8 gpio)
2944 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
2946 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
2949 static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio)
2953 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
2954 return (u8)(data & gpio);
2957 static void eeprom_clk(struct ksz_hw *hw)
2959 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
2960 udelay(EEPROM_DELAY);
2961 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
2962 udelay(EEPROM_DELAY);
2965 static u16 spi_r(struct ksz_hw *hw)
2970 for (i = 15; i >= 0; i--) {
2971 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
2972 udelay(EEPROM_DELAY);
2974 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0;
2976 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
2977 udelay(EEPROM_DELAY);
2982 static void spi_w(struct ksz_hw *hw, u16 data)
2986 for (i = 15; i >= 0; i--) {
2987 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
2988 drop_gpio(hw, EEPROM_DATA_OUT);
2993 static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg)
2997 /* Initial start bit */
2998 raise_gpio(hw, EEPROM_DATA_OUT);
3001 /* AT93C operation */
3002 for (i = 1; i >= 0; i--) {
3003 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3004 drop_gpio(hw, EEPROM_DATA_OUT);
3008 /* Address location */
3009 for (i = 5; i >= 0; i--) {
3010 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3011 drop_gpio(hw, EEPROM_DATA_OUT);
3016 #define EEPROM_DATA_RESERVED 0
3017 #define EEPROM_DATA_MAC_ADDR_0 1
3018 #define EEPROM_DATA_MAC_ADDR_1 2
3019 #define EEPROM_DATA_MAC_ADDR_2 3
3020 #define EEPROM_DATA_SUBSYS_ID 4
3021 #define EEPROM_DATA_SUBSYS_VEN_ID 5
3022 #define EEPROM_DATA_PM_CAP 6
3024 /* User defined EEPROM data */
3025 #define EEPROM_DATA_OTHER_MAC_ADDR 9
3028 * eeprom_read - read from AT93C46 EEPROM
3029 * @hw: The hardware instance.
3030 * @reg: The register offset.
3032 * This function reads a word from the AT93C46 EEPROM.
3034 * Return the data value.
3036 static u16 eeprom_read(struct ksz_hw *hw, u8 reg)
3040 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3042 spi_reg(hw, AT93C_READ, reg);
3045 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3051 * eeprom_write - write to AT93C46 EEPROM
3052 * @hw: The hardware instance.
3053 * @reg: The register offset.
3054 * @data: The data value.
3056 * This procedure writes a word to the AT93C46 EEPROM.
3058 static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data)
3062 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3065 spi_reg(hw, AT93C_CODE, AT93C_WR_ON);
3066 drop_gpio(hw, EEPROM_CHIP_SELECT);
3069 /* Erase the register. */
3070 raise_gpio(hw, EEPROM_CHIP_SELECT);
3071 spi_reg(hw, AT93C_ERASE, reg);
3072 drop_gpio(hw, EEPROM_CHIP_SELECT);
3075 /* Check operation complete. */
3076 raise_gpio(hw, EEPROM_CHIP_SELECT);
3081 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3082 drop_gpio(hw, EEPROM_CHIP_SELECT);
3085 /* Write the register. */
3086 raise_gpio(hw, EEPROM_CHIP_SELECT);
3087 spi_reg(hw, AT93C_WRITE, reg);
3089 drop_gpio(hw, EEPROM_CHIP_SELECT);
3092 /* Check operation complete. */
3093 raise_gpio(hw, EEPROM_CHIP_SELECT);
3098 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3099 drop_gpio(hw, EEPROM_CHIP_SELECT);
3102 /* Disable write. */
3103 raise_gpio(hw, EEPROM_CHIP_SELECT);
3104 spi_reg(hw, AT93C_CODE, AT93C_WR_OFF);
3106 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3110 * Link detection routines
3113 static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl)
3115 ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE;
3116 switch (port->flow_ctrl) {
3118 ctrl |= PORT_AUTO_NEG_SYM_PAUSE;
3120 /* Not supported. */
3129 static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx)
3134 rx_cfg = hw->rx_cfg;
3135 tx_cfg = hw->tx_cfg;
3137 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
3139 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
3141 hw->tx_cfg |= DMA_TX_FLOW_ENABLE;
3143 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3145 if (rx_cfg != hw->rx_cfg)
3146 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3147 if (tx_cfg != hw->tx_cfg)
3148 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3152 static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port,
3153 u16 local, u16 remote)
3158 if (hw->overrides & PAUSE_FLOW_CTRL)
3162 if (port->force_link)
3164 if (remote & LPA_PAUSE_CAP) {
3165 if (local & ADVERTISE_PAUSE_CAP) {
3167 } else if ((remote & LPA_PAUSE_ASYM) &&
3169 (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) ==
3170 ADVERTISE_PAUSE_ASYM) {
3173 } else if (remote & LPA_PAUSE_ASYM) {
3174 if ((local & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM))
3175 == (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM))
3178 if (!hw->ksz_switch)
3179 set_flow_ctrl(hw, rx, tx);
3182 static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port,
3183 struct ksz_port_info *info, u16 link_status)
3185 if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) &&
3186 !(hw->overrides & PAUSE_FLOW_CTRL)) {
3187 u32 cfg = hw->tx_cfg;
3189 /* Disable flow control in the half duplex mode. */
3190 if (1 == info->duplex)
3191 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3192 if (hw->enabled && cfg != hw->tx_cfg)
3193 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3198 * port_get_link_speed - get current link status
3199 * @port: The port instance.
3201 * This routine reads PHY registers to determine the current link status of the
3204 static void port_get_link_speed(struct ksz_port *port)
3207 struct ksz_port_info *info;
3208 struct ksz_port_info *linked = NULL;
3209 struct ksz_hw *hw = port->hw;
3218 interrupt = hw_block_intr(hw);
3220 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3221 info = &hw->port_info[p];
3222 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3223 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3226 * Link status is changing all the time even when there is no
3229 remote = status & (PORT_AUTO_NEG_COMPLETE |
3230 PORT_STATUS_LINK_GOOD);
3233 /* No change to status. */
3234 if (local == info->advertised && remote == info->partner)
3237 info->advertised = local;
3238 info->partner = remote;
3239 if (status & PORT_STATUS_LINK_GOOD) {
3241 /* Remember the first linked port. */
3245 info->tx_rate = 10 * TX_RATE_UNIT;
3246 if (status & PORT_STATUS_SPEED_100MBIT)
3247 info->tx_rate = 100 * TX_RATE_UNIT;
3250 if (status & PORT_STATUS_FULL_DUPLEX)
3253 if (media_connected != info->state) {
3254 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET,
3256 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET,
3258 determine_flow_ctrl(hw, port, data, status);
3259 if (hw->ksz_switch) {
3260 port_cfg_back_pressure(hw, p,
3261 (1 == info->duplex));
3264 port_cfg_change(hw, port, info, status);
3266 info->state = media_connected;
3268 if (media_disconnected != info->state) {
3271 /* Indicate the link just goes down. */
3272 hw->port_mib[p].link_down = 1;
3274 info->state = media_disconnected;
3276 hw->port_mib[p].state = (u8) info->state;
3279 if (linked && media_disconnected == port->linked->state)
3280 port->linked = linked;
3282 hw_restore_intr(hw, interrupt);
3285 #define PHY_RESET_TIMEOUT 10
3288 * port_set_link_speed - set port speed
3289 * @port: The port instance.
3291 * This routine sets the link speed of the switch ports.
3293 static void port_set_link_speed(struct ksz_port *port)
3295 struct ksz_hw *hw = port->hw;
3302 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3303 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3304 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3307 if (status & PORT_STATUS_LINK_GOOD)
3310 data |= PORT_AUTO_NEG_ENABLE;
3311 data = advertised_flow_ctrl(port, data);
3313 data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX |
3314 PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT;
3316 /* Check if manual configuration is specified by the user. */
3317 if (port->speed || port->duplex) {
3318 if (10 == port->speed)
3319 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3320 PORT_AUTO_NEG_100BTX);
3321 else if (100 == port->speed)
3322 data &= ~(PORT_AUTO_NEG_10BT_FD |
3323 PORT_AUTO_NEG_10BT);
3324 if (1 == port->duplex)
3325 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3326 PORT_AUTO_NEG_10BT_FD);
3327 else if (2 == port->duplex)
3328 data &= ~(PORT_AUTO_NEG_100BTX |
3329 PORT_AUTO_NEG_10BT);
3332 data |= PORT_AUTO_NEG_RESTART;
3333 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data);
3339 * port_force_link_speed - force port speed
3340 * @port: The port instance.
3342 * This routine forces the link speed of the switch ports.
3344 static void port_force_link_speed(struct ksz_port *port)
3346 struct ksz_hw *hw = port->hw;
3352 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3353 phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL;
3354 hw_r_phy_ctrl(hw, phy, &data);
3356 data &= ~BMCR_ANENABLE;
3358 if (10 == port->speed)
3359 data &= ~BMCR_SPEED100;
3360 else if (100 == port->speed)
3361 data |= BMCR_SPEED100;
3362 if (1 == port->duplex)
3363 data &= ~BMCR_FULLDPLX;
3364 else if (2 == port->duplex)
3365 data |= BMCR_FULLDPLX;
3366 hw_w_phy_ctrl(hw, phy, data);
3370 static void port_set_power_saving(struct ksz_port *port, int enable)
3372 struct ksz_hw *hw = port->hw;
3376 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++)
3378 KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable);
3382 * KSZ8841 power management functions
3386 * hw_chk_wol_pme_status - check PMEN pin
3387 * @hw: The hardware instance.
3389 * This function is used to check PMEN pin is asserted.
3391 * Return 1 if PMEN pin is asserted; otherwise, 0.
3393 static int hw_chk_wol_pme_status(struct ksz_hw *hw)
3395 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3396 struct pci_dev *pdev = hw_priv->pdev;
3401 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3402 return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
3406 * hw_clr_wol_pme_status - clear PMEN pin
3407 * @hw: The hardware instance.
3409 * This routine is used to clear PME_Status to deassert PMEN pin.
3411 static void hw_clr_wol_pme_status(struct ksz_hw *hw)
3413 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3414 struct pci_dev *pdev = hw_priv->pdev;
3420 /* Clear PME_Status to deassert PMEN pin. */
3421 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3422 data |= PCI_PM_CTRL_PME_STATUS;
3423 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3427 * hw_cfg_wol_pme - enable or disable Wake-on-LAN
3428 * @hw: The hardware instance.
3429 * @set: The flag indicating whether to enable or disable.
3431 * This routine is used to enable or disable Wake-on-LAN.
3433 static void hw_cfg_wol_pme(struct ksz_hw *hw, int set)
3435 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3436 struct pci_dev *pdev = hw_priv->pdev;
3441 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3442 data &= ~PCI_PM_CTRL_STATE_MASK;
3444 data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot;
3446 data &= ~PCI_PM_CTRL_PME_ENABLE;
3447 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3451 * hw_cfg_wol - configure Wake-on-LAN features
3452 * @hw: The hardware instance.
3453 * @frame: The pattern frame bit.
3454 * @set: The flag indicating whether to enable or disable.
3456 * This routine is used to enable or disable certain Wake-on-LAN features.
3458 static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set)
3462 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET);
3467 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET);
3471 * hw_set_wol_frame - program Wake-on-LAN pattern
3472 * @hw: The hardware instance.
3473 * @i: The frame index.
3474 * @mask_size: The size of the mask.
3475 * @mask: Mask to ignore certain bytes in the pattern.
3476 * @frame_size: The size of the frame.
3477 * @pattern: The frame data.
3479 * This routine is used to program Wake-on-LAN pattern.
3481 static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
3482 const u8 *mask, uint frame_size, const u8 *pattern)
3492 if (frame_size > mask_size * 8)
3493 frame_size = mask_size * 8;
3494 if (frame_size > 64)
3498 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i);
3499 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i);
3501 bits = len = from = to = 0;
3505 data[to++] = pattern[from];
3511 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i
3519 } while (from < (int) frame_size);
3521 bits = mask[len - 1];
3524 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len -
3527 crc = ether_crc(to, data);
3528 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i);
3532 * hw_add_wol_arp - add ARP pattern
3533 * @hw: The hardware instance.
3534 * @ip_addr: The IPv4 address assigned to the device.
3536 * This routine is used to add ARP pattern for waking up the host.
3538 static void hw_add_wol_arp(struct ksz_hw *hw, const u8 *ip_addr)
3540 static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
3542 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
3543 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3545 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01,
3546 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3547 0x00, 0x00, 0x00, 0x00,
3548 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3549 0x00, 0x00, 0x00, 0x00 };
3551 memcpy(&pattern[38], ip_addr, 4);
3552 hw_set_wol_frame(hw, 3, 6, mask, 42, pattern);
3556 * hw_add_wol_bcast - add broadcast pattern
3557 * @hw: The hardware instance.
3559 * This routine is used to add broadcast pattern for waking up the host.
3561 static void hw_add_wol_bcast(struct ksz_hw *hw)
3563 static const u8 mask[] = { 0x3F };
3564 static const u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3566 hw_set_wol_frame(hw, 2, 1, mask, ETH_ALEN, pattern);
3570 * hw_add_wol_mcast - add multicast pattern
3571 * @hw: The hardware instance.
3573 * This routine is used to add multicast pattern for waking up the host.
3575 * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used
3576 * by IPv6 ping command. Note that multicast packets are filtred through the
3577 * multicast hash table, so not all multicast packets can wake up the host.
3579 static void hw_add_wol_mcast(struct ksz_hw *hw)
3581 static const u8 mask[] = { 0x3F };
3582 u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 };
3584 memcpy(&pattern[3], &hw->override_addr[3], 3);
3585 hw_set_wol_frame(hw, 1, 1, mask, 6, pattern);
3589 * hw_add_wol_ucast - add unicast pattern
3590 * @hw: The hardware instance.
3592 * This routine is used to add unicast pattern to wakeup the host.
3594 * It is assumed the unicast packet is directed to the device, as the hardware
3595 * can only receive them in normal case.
3597 static void hw_add_wol_ucast(struct ksz_hw *hw)
3599 static const u8 mask[] = { 0x3F };
3601 hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr);
3605 * hw_enable_wol - enable Wake-on-LAN
3606 * @hw: The hardware instance.
3607 * @wol_enable: The Wake-on-LAN settings.
3608 * @net_addr: The IPv4 address assigned to the device.
3610 * This routine is used to enable Wake-on-LAN depending on driver settings.
3612 static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, const u8 *net_addr)
3614 hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC));
3615 hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST));
3616 hw_add_wol_ucast(hw);
3617 hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST));
3618 hw_add_wol_mcast(hw);
3619 hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST));
3620 hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP));
3621 hw_add_wol_arp(hw, net_addr);
3625 * hw_init - check driver is correct for the hardware
3626 * @hw: The hardware instance.
3628 * This function checks the hardware is correct for this driver and sets the
3629 * hardware up for proper initialization.
3631 * Return number of ports or 0 if not right.
3633 static int hw_init(struct ksz_hw *hw)
3639 /* Set bus speed to 125MHz. */
3640 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET);
3642 /* Check KSZ884x chip ID. */
3643 data = readw(hw->io + KS884X_CHIP_ID_OFFSET);
3645 revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT;
3646 data &= KS884X_CHIP_ID_MASK_41;
3647 if (REG_CHIP_ID_41 == data)
3649 else if (REG_CHIP_ID_42 == data)
3654 /* Setup hardware features or bug workarounds. */
3655 if (revision <= 1) {
3656 hw->features |= SMALL_PACKET_TX_BUG;
3658 hw->features |= HALF_DUPLEX_SIGNAL_BUG;
3664 * hw_reset - reset the hardware
3665 * @hw: The hardware instance.
3667 * This routine resets the hardware.
3669 static void hw_reset(struct ksz_hw *hw)
3671 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3673 /* Wait for device to reset. */
3676 /* Write 0 to clear device reset. */
3677 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3681 * hw_setup - setup the hardware
3682 * @hw: The hardware instance.
3684 * This routine setup the hardware for proper operation.
3686 static void hw_setup(struct ksz_hw *hw)
3691 /* Change default LED mode. */
3692 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3694 data |= SET_DEFAULT_LED;
3695 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3698 /* Setup transmit control. */
3699 hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE |
3700 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE);
3702 /* Setup receive control. */
3703 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3704 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE);
3705 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3707 /* Hardware cannot handle UDP packet in IP fragments. */
3708 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3711 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3712 if (hw->promiscuous)
3713 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3717 * hw_setup_intr - setup interrupt mask
3718 * @hw: The hardware instance.
3720 * This routine setup the interrupt mask for proper operation.
3722 static void hw_setup_intr(struct ksz_hw *hw)
3724 hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN;
3727 static void ksz_check_desc_num(struct ksz_desc_info *info)
3729 #define MIN_DESC_SHIFT 2
3731 int alloc = info->alloc;
3735 while (!(alloc & 1)) {
3739 if (alloc != 1 || shift < MIN_DESC_SHIFT) {
3740 pr_alert("Hardware descriptor numbers not right!\n");
3745 if (shift < MIN_DESC_SHIFT)
3746 shift = MIN_DESC_SHIFT;
3748 info->alloc = alloc;
3750 info->mask = info->alloc - 1;
3753 static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit)
3756 u32 phys = desc_info->ring_phys;
3757 struct ksz_hw_desc *desc = desc_info->ring_virt;
3758 struct ksz_desc *cur = desc_info->ring;
3759 struct ksz_desc *previous = NULL;
3761 for (i = 0; i < desc_info->alloc; i++) {
3763 phys += desc_info->size;
3765 previous->phw->next = cpu_to_le32(phys);
3767 previous->phw->next = cpu_to_le32(desc_info->ring_phys);
3768 previous->sw.buf.rx.end_of_ring = 1;
3769 previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data);
3771 desc_info->avail = desc_info->alloc;
3772 desc_info->last = desc_info->next = 0;
3774 desc_info->cur = desc_info->ring;
3778 * hw_set_desc_base - set descriptor base addresses
3779 * @hw: The hardware instance.
3780 * @tx_addr: The transmit descriptor base.
3781 * @rx_addr: The receive descriptor base.
3783 * This routine programs the descriptor base addresses after reset.
3785 static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr)
3787 /* Set base address of Tx/Rx descriptors. */
3788 writel(tx_addr, hw->io + KS_DMA_TX_ADDR);
3789 writel(rx_addr, hw->io + KS_DMA_RX_ADDR);
3792 static void hw_reset_pkts(struct ksz_desc_info *info)
3794 info->cur = info->ring;
3795 info->avail = info->alloc;
3796 info->last = info->next = 0;
3799 static inline void hw_resume_rx(struct ksz_hw *hw)
3801 writel(DMA_START, hw->io + KS_DMA_RX_START);
3805 * hw_start_rx - start receiving
3806 * @hw: The hardware instance.
3808 * This routine starts the receive function of the hardware.
3810 static void hw_start_rx(struct ksz_hw *hw)
3812 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3814 /* Notify when the receive stops. */
3815 hw->intr_mask |= KS884X_INT_RX_STOPPED;
3817 writel(DMA_START, hw->io + KS_DMA_RX_START);
3818 hw_ack_intr(hw, KS884X_INT_RX_STOPPED);
3821 /* Variable overflows. */
3822 if (0 == hw->rx_stop)
3827 * hw_stop_rx - stop receiving
3828 * @hw: The hardware instance.
3830 * This routine stops the receive function of the hardware.
3832 static void hw_stop_rx(struct ksz_hw *hw)
3835 hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED);
3836 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
3840 * hw_start_tx - start transmitting
3841 * @hw: The hardware instance.
3843 * This routine starts the transmit function of the hardware.
3845 static void hw_start_tx(struct ksz_hw *hw)
3847 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3851 * hw_stop_tx - stop transmitting
3852 * @hw: The hardware instance.
3854 * This routine stops the transmit function of the hardware.
3856 static void hw_stop_tx(struct ksz_hw *hw)
3858 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL);
3862 * hw_disable - disable hardware
3863 * @hw: The hardware instance.
3865 * This routine disables the hardware.
3867 static void hw_disable(struct ksz_hw *hw)
3875 * hw_enable - enable hardware
3876 * @hw: The hardware instance.
3878 * This routine enables the hardware.
3880 static void hw_enable(struct ksz_hw *hw)
3888 * hw_alloc_pkt - allocate enough descriptors for transmission
3889 * @hw: The hardware instance.
3890 * @length: The length of the packet.
3891 * @physical: Number of descriptors required.
3893 * This function allocates descriptors for transmission.
3895 * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3897 static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical)
3899 /* Always leave one descriptor free. */
3900 if (hw->tx_desc_info.avail <= 1)
3903 /* Allocate a descriptor for transmission and mark it current. */
3904 get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur);
3905 hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1;
3907 /* Keep track of number of transmit descriptors used so far. */
3909 hw->tx_size += length;
3911 /* Cannot hold on too much data. */
3912 if (hw->tx_size >= MAX_TX_HELD_SIZE)
3913 hw->tx_int_cnt = hw->tx_int_mask + 1;
3915 if (physical > hw->tx_desc_info.avail)
3918 return hw->tx_desc_info.avail;
3922 * hw_send_pkt - mark packet for transmission
3923 * @hw: The hardware instance.
3925 * This routine marks the packet for transmission in PCI version.
3927 static void hw_send_pkt(struct ksz_hw *hw)
3929 struct ksz_desc *cur = hw->tx_desc_info.cur;
3931 cur->sw.buf.tx.last_seg = 1;
3933 /* Interrupt only after specified number of descriptors used. */
3934 if (hw->tx_int_cnt > hw->tx_int_mask) {
3935 cur->sw.buf.tx.intr = 1;
3940 /* KSZ8842 supports port directed transmission. */
3941 cur->sw.buf.tx.dest_port = hw->dst_ports;
3945 writel(0, hw->io + KS_DMA_TX_START);
3948 static int empty_addr(u8 *addr)
3950 u32 *addr1 = (u32 *) addr;
3951 u16 *addr2 = (u16 *) &addr[4];
3953 return 0 == *addr1 && 0 == *addr2;
3957 * hw_set_addr - set MAC address
3958 * @hw: The hardware instance.
3960 * This routine programs the MAC address of the hardware when the address is
3963 static void hw_set_addr(struct ksz_hw *hw)
3967 for (i = 0; i < ETH_ALEN; i++)
3968 writeb(hw->override_addr[MAC_ADDR_ORDER(i)],
3969 hw->io + KS884X_ADDR_0_OFFSET + i);
3971 sw_set_addr(hw, hw->override_addr);
3975 * hw_read_addr - read MAC address
3976 * @hw: The hardware instance.
3978 * This routine retrieves the MAC address of the hardware.
3980 static void hw_read_addr(struct ksz_hw *hw)
3984 for (i = 0; i < ETH_ALEN; i++)
3985 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io +
3986 KS884X_ADDR_0_OFFSET + i);
3988 if (!hw->mac_override) {
3989 memcpy(hw->override_addr, hw->perm_addr, ETH_ALEN);
3990 if (empty_addr(hw->override_addr)) {
3991 memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS, ETH_ALEN);
3992 memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS,
3994 hw->override_addr[5] += hw->id;
4000 static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr)
4007 for (i = 0; i < 2; i++) {
4009 mac_addr_hi |= mac_addr[i];
4011 mac_addr_hi |= ADD_ADDR_ENABLE;
4013 for (i = 2; i < 6; i++) {
4015 mac_addr_lo |= mac_addr[i];
4017 index *= ADD_ADDR_INCR;
4019 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO);
4020 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI);
4023 static void hw_set_add_addr(struct ksz_hw *hw)
4027 for (i = 0; i < ADDITIONAL_ENTRIES; i++) {
4028 if (empty_addr(hw->address[i]))
4029 writel(0, hw->io + ADD_ADDR_INCR * i +
4032 hw_ena_add_addr(hw, i, hw->address[i]);
4036 static int hw_add_addr(struct ksz_hw *hw, const u8 *mac_addr)
4039 int j = ADDITIONAL_ENTRIES;
4041 if (ether_addr_equal(hw->override_addr, mac_addr))
4043 for (i = 0; i < hw->addr_list_size; i++) {
4044 if (ether_addr_equal(hw->address[i], mac_addr))
4046 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i]))
4049 if (j < ADDITIONAL_ENTRIES) {
4050 memcpy(hw->address[j], mac_addr, ETH_ALEN);
4051 hw_ena_add_addr(hw, j, hw->address[j]);
4057 static int hw_del_addr(struct ksz_hw *hw, const u8 *mac_addr)
4061 for (i = 0; i < hw->addr_list_size; i++) {
4062 if (ether_addr_equal(hw->address[i], mac_addr)) {
4063 eth_zero_addr(hw->address[i]);
4064 writel(0, hw->io + ADD_ADDR_INCR * i +
4073 * hw_clr_multicast - clear multicast addresses
4074 * @hw: The hardware instance.
4076 * This routine removes all multicast addresses set in the hardware.
4078 static void hw_clr_multicast(struct ksz_hw *hw)
4082 for (i = 0; i < HW_MULTICAST_SIZE; i++) {
4083 hw->multi_bits[i] = 0;
4085 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i);
4090 * hw_set_grp_addr - set multicast addresses
4091 * @hw: The hardware instance.
4093 * This routine programs multicast addresses for the hardware to accept those
4096 static void hw_set_grp_addr(struct ksz_hw *hw)
4103 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE);
4105 for (i = 0; i < hw->multi_list_size; i++) {
4106 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f;
4107 index = position >> 3;
4108 value = 1 << (position & 7);
4109 hw->multi_bits[index] |= (u8) value;
4112 for (i = 0; i < HW_MULTICAST_SIZE; i++)
4113 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET +
4118 * hw_set_multicast - enable or disable all multicast receiving
4119 * @hw: The hardware instance.
4120 * @multicast: To turn on or off the all multicast feature.
4122 * This routine enables/disables the hardware to accept all multicast packets.
4124 static void hw_set_multicast(struct ksz_hw *hw, u8 multicast)
4126 /* Stop receiving for reconfiguration. */
4130 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
4132 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
4139 * hw_set_promiscuous - enable or disable promiscuous receiving
4140 * @hw: The hardware instance.
4141 * @prom: To turn on or off the promiscuous feature.
4143 * This routine enables/disables the hardware to accept all packets.
4145 static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom)
4147 /* Stop receiving for reconfiguration. */
4151 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
4153 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
4160 * sw_enable - enable the switch
4161 * @hw: The hardware instance.
4162 * @enable: The flag to enable or disable the switch
4164 * This routine is used to enable/disable the switch in KSZ8842.
4166 static void sw_enable(struct ksz_hw *hw, int enable)
4170 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4171 if (hw->dev_count > 1) {
4172 /* Set port-base vlan membership with host port. */
4173 sw_cfg_port_base_vlan(hw, port,
4174 HOST_MASK | (1 << port));
4175 port_set_stp_state(hw, port, STP_STATE_DISABLED);
4177 sw_cfg_port_base_vlan(hw, port, PORT_MASK);
4178 port_set_stp_state(hw, port, STP_STATE_FORWARDING);
4181 if (hw->dev_count > 1)
4182 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
4184 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING);
4187 enable = KS8842_START;
4188 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET);
4192 * sw_setup - setup the switch
4193 * @hw: The hardware instance.
4195 * This routine setup the hardware switch engine for default operation.
4197 static void sw_setup(struct ksz_hw *hw)
4201 sw_set_global_ctrl(hw);
4203 /* Enable switch broadcast storm protection at 10% percent rate. */
4204 sw_init_broad_storm(hw);
4205 hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE);
4206 for (port = 0; port < SWITCH_PORT_NUM; port++)
4207 sw_ena_broad_storm(hw, port);
4213 sw_init_prio_rate(hw);
4217 if (hw->features & STP_SUPPORT)
4219 if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
4220 SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL))
4221 hw->overrides |= PAUSE_FLOW_CTRL;
4226 * ksz_start_timer - start kernel timer
4227 * @info: Kernel timer information.
4228 * @time: The time tick.
4230 * This routine starts the kernel timer after the specified time tick.
4232 static void ksz_start_timer(struct ksz_timer_info *info, int time)
4235 info->timer.expires = jiffies + time;
4236 add_timer(&info->timer);
4243 * ksz_stop_timer - stop kernel timer
4244 * @info: Kernel timer information.
4246 * This routine stops the kernel timer.
4248 static void ksz_stop_timer(struct ksz_timer_info *info)
4252 del_timer_sync(&info->timer);
4256 static void ksz_init_timer(struct ksz_timer_info *info, int period,
4257 void (*function)(struct timer_list *))
4260 info->period = period;
4261 timer_setup(&info->timer, function, 0);
4264 static void ksz_update_timer(struct ksz_timer_info *info)
4267 if (info->max > 0) {
4268 if (info->cnt < info->max) {
4269 info->timer.expires = jiffies + info->period;
4270 add_timer(&info->timer);
4273 } else if (info->max < 0) {
4274 info->timer.expires = jiffies + info->period;
4275 add_timer(&info->timer);
4280 * ksz_alloc_soft_desc - allocate software descriptors
4281 * @desc_info: Descriptor information structure.
4282 * @transmit: Indication that descriptors are for transmit.
4284 * This local function allocates software descriptors for manipulation in
4287 * Return 0 if successful.
4289 static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit)
4291 desc_info->ring = kcalloc(desc_info->alloc, sizeof(struct ksz_desc),
4293 if (!desc_info->ring)
4295 hw_init_desc(desc_info, transmit);
4300 * ksz_alloc_desc - allocate hardware descriptors
4301 * @adapter: Adapter information structure.
4303 * This local function allocates hardware descriptors for receiving and
4306 * Return 0 if successful.
4308 static int ksz_alloc_desc(struct dev_info *adapter)
4310 struct ksz_hw *hw = &adapter->hw;
4313 /* Allocate memory for RX & TX descriptors. */
4314 adapter->desc_pool.alloc_size =
4315 hw->rx_desc_info.size * hw->rx_desc_info.alloc +
4316 hw->tx_desc_info.size * hw->tx_desc_info.alloc +
4319 adapter->desc_pool.alloc_virt =
4320 dma_alloc_coherent(&adapter->pdev->dev,
4321 adapter->desc_pool.alloc_size,
4322 &adapter->desc_pool.dma_addr, GFP_KERNEL);
4323 if (adapter->desc_pool.alloc_virt == NULL) {
4324 adapter->desc_pool.alloc_size = 0;
4328 /* Align to the next cache line boundary. */
4329 offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ?
4331 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0);
4332 adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset;
4333 adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset;
4335 /* Allocate receive/transmit descriptors. */
4336 hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *)
4337 adapter->desc_pool.virt;
4338 hw->rx_desc_info.ring_phys = adapter->desc_pool.phys;
4339 offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size;
4340 hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *)
4341 (adapter->desc_pool.virt + offset);
4342 hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset;
4344 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0))
4346 if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1))
4353 * free_dma_buf - release DMA buffer resources
4354 * @adapter: Adapter information structure.
4355 * @dma_buf: pointer to buf
4356 * @direction: to or from device
4358 * This routine is just a helper function to release the DMA buffer resources.
4360 static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf,
4363 dma_unmap_single(&adapter->pdev->dev, dma_buf->dma, dma_buf->len,
4365 dev_kfree_skb(dma_buf->skb);
4366 dma_buf->skb = NULL;
4371 * ksz_init_rx_buffers - initialize receive descriptors
4372 * @adapter: Adapter information structure.
4374 * This routine initializes DMA buffers for receiving.
4376 static void ksz_init_rx_buffers(struct dev_info *adapter)
4379 struct ksz_desc *desc;
4380 struct ksz_dma_buf *dma_buf;
4381 struct ksz_hw *hw = &adapter->hw;
4382 struct ksz_desc_info *info = &hw->rx_desc_info;
4384 for (i = 0; i < hw->rx_desc_info.alloc; i++) {
4385 get_rx_pkt(info, &desc);
4387 dma_buf = DMA_BUFFER(desc);
4388 if (dma_buf->skb && dma_buf->len != adapter->mtu)
4389 free_dma_buf(adapter, dma_buf, DMA_FROM_DEVICE);
4390 dma_buf->len = adapter->mtu;
4392 dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC);
4393 if (dma_buf->skb && !dma_buf->dma)
4394 dma_buf->dma = dma_map_single(&adapter->pdev->dev,
4395 skb_tail_pointer(dma_buf->skb),
4399 /* Set descriptor. */
4400 set_rx_buf(desc, dma_buf->dma);
4401 set_rx_len(desc, dma_buf->len);
4407 * ksz_alloc_mem - allocate memory for hardware descriptors
4408 * @adapter: Adapter information structure.
4410 * This function allocates memory for use by hardware descriptors for receiving
4413 * Return 0 if successful.
4415 static int ksz_alloc_mem(struct dev_info *adapter)
4417 struct ksz_hw *hw = &adapter->hw;
4419 /* Determine the number of receive and transmit descriptors. */
4420 hw->rx_desc_info.alloc = NUM_OF_RX_DESC;
4421 hw->tx_desc_info.alloc = NUM_OF_TX_DESC;
4423 /* Determine how many descriptors to skip transmit interrupt. */
4425 hw->tx_int_mask = NUM_OF_TX_DESC / 4;
4426 if (hw->tx_int_mask > 8)
4427 hw->tx_int_mask = 8;
4428 while (hw->tx_int_mask) {
4430 hw->tx_int_mask >>= 1;
4432 if (hw->tx_int_cnt) {
4433 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1;
4437 /* Determine the descriptor size. */
4438 hw->rx_desc_info.size =
4439 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4440 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4441 hw->tx_desc_info.size =
4442 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4443 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4444 if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc))
4445 pr_alert("Hardware descriptor size not right!\n");
4446 ksz_check_desc_num(&hw->rx_desc_info);
4447 ksz_check_desc_num(&hw->tx_desc_info);
4449 /* Allocate descriptors. */
4450 if (ksz_alloc_desc(adapter))
4457 * ksz_free_desc - free software and hardware descriptors
4458 * @adapter: Adapter information structure.
4460 * This local routine frees the software and hardware descriptors allocated by
4463 static void ksz_free_desc(struct dev_info *adapter)
4465 struct ksz_hw *hw = &adapter->hw;
4467 /* Reset descriptor. */
4468 hw->rx_desc_info.ring_virt = NULL;
4469 hw->tx_desc_info.ring_virt = NULL;
4470 hw->rx_desc_info.ring_phys = 0;
4471 hw->tx_desc_info.ring_phys = 0;
4474 if (adapter->desc_pool.alloc_virt)
4475 dma_free_coherent(&adapter->pdev->dev,
4476 adapter->desc_pool.alloc_size,
4477 adapter->desc_pool.alloc_virt,
4478 adapter->desc_pool.dma_addr);
4480 /* Reset resource pool. */
4481 adapter->desc_pool.alloc_size = 0;
4482 adapter->desc_pool.alloc_virt = NULL;
4484 kfree(hw->rx_desc_info.ring);
4485 hw->rx_desc_info.ring = NULL;
4486 kfree(hw->tx_desc_info.ring);
4487 hw->tx_desc_info.ring = NULL;
4491 * ksz_free_buffers - free buffers used in the descriptors
4492 * @adapter: Adapter information structure.
4493 * @desc_info: Descriptor information structure.
4494 * @direction: to or from device
4496 * This local routine frees buffers used in the DMA buffers.
4498 static void ksz_free_buffers(struct dev_info *adapter,
4499 struct ksz_desc_info *desc_info, int direction)
4502 struct ksz_dma_buf *dma_buf;
4503 struct ksz_desc *desc = desc_info->ring;
4505 for (i = 0; i < desc_info->alloc; i++) {
4506 dma_buf = DMA_BUFFER(desc);
4508 free_dma_buf(adapter, dma_buf, direction);
4514 * ksz_free_mem - free all resources used by descriptors
4515 * @adapter: Adapter information structure.
4517 * This local routine frees all the resources allocated by ksz_alloc_mem().
4519 static void ksz_free_mem(struct dev_info *adapter)
4521 /* Free transmit buffers. */
4522 ksz_free_buffers(adapter, &adapter->hw.tx_desc_info, DMA_TO_DEVICE);
4524 /* Free receive buffers. */
4525 ksz_free_buffers(adapter, &adapter->hw.rx_desc_info, DMA_FROM_DEVICE);
4527 /* Free descriptors. */
4528 ksz_free_desc(adapter);
4531 static void get_mib_counters(struct ksz_hw *hw, int first, int cnt,
4537 struct ksz_port_mib *port_mib;
4539 memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
4540 for (i = 0, port = first; i < cnt; i++, port++) {
4541 port_mib = &hw->port_mib[port];
4542 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++)
4543 counter[mib] += port_mib->counter[mib];
4548 * send_packet - send packet
4549 * @skb: Socket buffer.
4550 * @dev: Network device.
4552 * This routine is used to send a packet out to the network.
4554 static void send_packet(struct sk_buff *skb, struct net_device *dev)
4556 struct ksz_desc *desc;
4557 struct ksz_desc *first;
4558 struct dev_priv *priv = netdev_priv(dev);
4559 struct dev_info *hw_priv = priv->adapter;
4560 struct ksz_hw *hw = &hw_priv->hw;
4561 struct ksz_desc_info *info = &hw->tx_desc_info;
4562 struct ksz_dma_buf *dma_buf;
4564 int last_frag = skb_shinfo(skb)->nr_frags;
4567 * KSZ8842 with multiple device interfaces needs to be told which port
4570 if (hw->dev_count > 1)
4571 hw->dst_ports = 1 << priv->port.first_port;
4573 /* Hardware will pad the length to 60. */
4576 /* Remember the very first descriptor. */
4580 dma_buf = DMA_BUFFER(desc);
4583 skb_frag_t *this_frag;
4585 dma_buf->len = skb_headlen(skb);
4587 dma_buf->dma = dma_map_single(&hw_priv->pdev->dev, skb->data,
4588 dma_buf->len, DMA_TO_DEVICE);
4589 set_tx_buf(desc, dma_buf->dma);
4590 set_tx_len(desc, dma_buf->len);
4594 this_frag = &skb_shinfo(skb)->frags[frag];
4596 /* Get a new descriptor. */
4597 get_tx_pkt(info, &desc);
4599 /* Keep track of descriptors used so far. */
4602 dma_buf = DMA_BUFFER(desc);
4603 dma_buf->len = skb_frag_size(this_frag);
4605 dma_buf->dma = dma_map_single(&hw_priv->pdev->dev,
4606 skb_frag_address(this_frag),
4609 set_tx_buf(desc, dma_buf->dma);
4610 set_tx_len(desc, dma_buf->len);
4613 if (frag == last_frag)
4616 /* Do not release the last descriptor here. */
4620 /* current points to the last descriptor. */
4623 /* Release the first descriptor. */
4624 release_desc(first);
4628 dma_buf->dma = dma_map_single(&hw_priv->pdev->dev, skb->data,
4629 dma_buf->len, DMA_TO_DEVICE);
4630 set_tx_buf(desc, dma_buf->dma);
4631 set_tx_len(desc, dma_buf->len);
4634 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4635 (desc)->sw.buf.tx.csum_gen_tcp = 1;
4636 (desc)->sw.buf.tx.csum_gen_udp = 1;
4640 * The last descriptor holds the packet so that it can be returned to
4641 * network subsystem after all descriptors are transmitted.
4647 /* Update transmit statistics. */
4648 dev->stats.tx_packets++;
4649 dev->stats.tx_bytes += len;
4653 * transmit_cleanup - clean up transmit descriptors
4654 * @hw_priv: Network device.
4655 * @normal: break if owned
4657 * This routine is called to clean up the transmitted buffers.
4659 static void transmit_cleanup(struct dev_info *hw_priv, int normal)
4662 union desc_stat status;
4663 struct ksz_hw *hw = &hw_priv->hw;
4664 struct ksz_desc_info *info = &hw->tx_desc_info;
4665 struct ksz_desc *desc;
4666 struct ksz_dma_buf *dma_buf;
4667 struct net_device *dev = NULL;
4669 spin_lock_irq(&hw_priv->hwlock);
4672 while (info->avail < info->alloc) {
4673 /* Get next descriptor which is not hardware owned. */
4674 desc = &info->ring[last];
4675 status.data = le32_to_cpu(desc->phw->ctrl.data);
4676 if (status.tx.hw_owned) {
4680 reset_desc(desc, status);
4683 dma_buf = DMA_BUFFER(desc);
4684 dma_unmap_single(&hw_priv->pdev->dev, dma_buf->dma,
4685 dma_buf->len, DMA_TO_DEVICE);
4687 /* This descriptor contains the last buffer in the packet. */
4689 dev = dma_buf->skb->dev;
4691 /* Release the packet back to network subsystem. */
4692 dev_kfree_skb_irq(dma_buf->skb);
4693 dma_buf->skb = NULL;
4696 /* Free the transmitted descriptor. */
4702 spin_unlock_irq(&hw_priv->hwlock);
4704 /* Notify the network subsystem that the packet has been sent. */
4706 netif_trans_update(dev);
4710 * tx_done - transmit done processing
4711 * @hw_priv: Network device.
4713 * This routine is called when the transmit interrupt is triggered, indicating
4714 * either a packet is sent successfully or there are transmit errors.
4716 static void tx_done(struct dev_info *hw_priv)
4718 struct ksz_hw *hw = &hw_priv->hw;
4721 transmit_cleanup(hw_priv, 1);
4723 for (port = 0; port < hw->dev_count; port++) {
4724 struct net_device *dev = hw->port_info[port].pdev;
4726 if (netif_running(dev) && netif_queue_stopped(dev))
4727 netif_wake_queue(dev);
4731 static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb)
4733 skb->dev = old->dev;
4734 skb->protocol = old->protocol;
4735 skb->ip_summed = old->ip_summed;
4736 skb->csum = old->csum;
4737 skb_set_network_header(skb, ETH_HLEN);
4739 dev_consume_skb_any(old);
4743 * netdev_tx - send out packet
4744 * @skb: Socket buffer.
4745 * @dev: Network device.
4747 * This function is used by the upper network layer to send out a packet.
4749 * Return 0 if successful; otherwise an error code indicating failure.
4751 static netdev_tx_t netdev_tx(struct sk_buff *skb, struct net_device *dev)
4753 struct dev_priv *priv = netdev_priv(dev);
4754 struct dev_info *hw_priv = priv->adapter;
4755 struct ksz_hw *hw = &hw_priv->hw;
4760 if (hw->features & SMALL_PACKET_TX_BUG) {
4761 struct sk_buff *org_skb = skb;
4763 if (skb->len <= 48) {
4764 if (skb_end_pointer(skb) - skb->data >= 50) {
4765 memset(&skb->data[skb->len], 0, 50 - skb->len);
4768 skb = netdev_alloc_skb(dev, 50);
4770 return NETDEV_TX_BUSY;
4771 memcpy(skb->data, org_skb->data, org_skb->len);
4772 memset(&skb->data[org_skb->len], 0,
4775 copy_old_skb(org_skb, skb);
4780 spin_lock_irq(&hw_priv->hwlock);
4782 num = skb_shinfo(skb)->nr_frags + 1;
4783 left = hw_alloc_pkt(hw, skb->len, num);
4786 (CHECKSUM_PARTIAL == skb->ip_summed &&
4787 skb->protocol == htons(ETH_P_IPV6))) {
4788 struct sk_buff *org_skb = skb;
4790 skb = netdev_alloc_skb(dev, org_skb->len);
4792 rc = NETDEV_TX_BUSY;
4795 skb_copy_and_csum_dev(org_skb, skb->data);
4796 org_skb->ip_summed = CHECKSUM_NONE;
4797 skb->len = org_skb->len;
4798 copy_old_skb(org_skb, skb);
4800 send_packet(skb, dev);
4802 netif_stop_queue(dev);
4804 /* Stop the transmit queue until packet is allocated. */
4805 netif_stop_queue(dev);
4806 rc = NETDEV_TX_BUSY;
4809 spin_unlock_irq(&hw_priv->hwlock);
4815 * netdev_tx_timeout - transmit timeout processing
4816 * @dev: Network device.
4817 * @txqueue: index of hanging queue
4819 * This routine is called when the transmit timer expires. That indicates the
4820 * hardware is not running correctly because transmit interrupts are not
4821 * triggered to free up resources so that the transmit routine can continue
4822 * sending out packets. The hardware is reset to correct the problem.
4824 static void netdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
4826 static unsigned long last_reset;
4828 struct dev_priv *priv = netdev_priv(dev);
4829 struct dev_info *hw_priv = priv->adapter;
4830 struct ksz_hw *hw = &hw_priv->hw;
4833 if (hw->dev_count > 1) {
4835 * Only reset the hardware if time between calls is long
4838 if (time_before_eq(jiffies, last_reset + dev->watchdog_timeo))
4842 last_reset = jiffies;
4847 transmit_cleanup(hw_priv, 0);
4848 hw_reset_pkts(&hw->rx_desc_info);
4849 hw_reset_pkts(&hw->tx_desc_info);
4850 ksz_init_rx_buffers(hw_priv);
4854 hw_set_desc_base(hw,
4855 hw->tx_desc_info.ring_phys,
4856 hw->rx_desc_info.ring_phys);
4859 hw_set_multicast(hw, hw->all_multi);
4860 else if (hw->multi_list_size)
4861 hw_set_grp_addr(hw);
4863 if (hw->dev_count > 1) {
4864 hw_set_add_addr(hw);
4865 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4866 struct net_device *port_dev;
4868 port_set_stp_state(hw, port,
4869 STP_STATE_DISABLED);
4871 port_dev = hw->port_info[port].pdev;
4872 if (netif_running(port_dev))
4873 port_set_stp_state(hw, port,
4882 netif_trans_update(dev);
4883 netif_wake_queue(dev);
4886 static inline void csum_verified(struct sk_buff *skb)
4888 unsigned short protocol;
4891 protocol = skb->protocol;
4892 skb_reset_network_header(skb);
4893 iph = (struct iphdr *) skb_network_header(skb);
4894 if (protocol == htons(ETH_P_8021Q)) {
4895 protocol = iph->tot_len;
4896 skb_set_network_header(skb, VLAN_HLEN);
4897 iph = (struct iphdr *) skb_network_header(skb);
4899 if (protocol == htons(ETH_P_IP)) {
4900 if (iph->protocol == IPPROTO_TCP)
4901 skb->ip_summed = CHECKSUM_UNNECESSARY;
4905 static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw,
4906 struct ksz_desc *desc, union desc_stat status)
4909 struct dev_priv *priv = netdev_priv(dev);
4910 struct dev_info *hw_priv = priv->adapter;
4911 struct ksz_dma_buf *dma_buf;
4912 struct sk_buff *skb;
4914 /* Received length includes 4-byte CRC. */
4915 packet_len = status.rx.frame_len - 4;
4917 dma_buf = DMA_BUFFER(desc);
4918 dma_sync_single_for_cpu(&hw_priv->pdev->dev, dma_buf->dma,
4919 packet_len + 4, DMA_FROM_DEVICE);
4922 /* skb->data != skb->head */
4923 skb = netdev_alloc_skb(dev, packet_len + 2);
4925 dev->stats.rx_dropped++;
4930 * Align socket buffer in 4-byte boundary for better
4933 skb_reserve(skb, 2);
4935 skb_put_data(skb, dma_buf->skb->data, packet_len);
4938 skb->protocol = eth_type_trans(skb, dev);
4940 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
4943 /* Update receive statistics. */
4944 dev->stats.rx_packets++;
4945 dev->stats.rx_bytes += packet_len;
4947 /* Notify upper layer for received packet. */
4953 static int dev_rcv_packets(struct dev_info *hw_priv)
4956 union desc_stat status;
4957 struct ksz_hw *hw = &hw_priv->hw;
4958 struct net_device *dev = hw->port_info[0].pdev;
4959 struct ksz_desc_info *info = &hw->rx_desc_info;
4960 int left = info->alloc;
4961 struct ksz_desc *desc;
4966 /* Get next descriptor which is not hardware owned. */
4967 desc = &info->ring[next];
4968 status.data = le32_to_cpu(desc->phw->ctrl.data);
4969 if (status.rx.hw_owned)
4972 /* Status valid only when last descriptor bit is set. */
4973 if (status.rx.last_desc && status.rx.first_desc) {
4974 if (rx_proc(dev, hw, desc, status))
4975 goto release_packet;
4989 static int port_rcv_packets(struct dev_info *hw_priv)
4992 union desc_stat status;
4993 struct ksz_hw *hw = &hw_priv->hw;
4994 struct net_device *dev = hw->port_info[0].pdev;
4995 struct ksz_desc_info *info = &hw->rx_desc_info;
4996 int left = info->alloc;
4997 struct ksz_desc *desc;
5002 /* Get next descriptor which is not hardware owned. */
5003 desc = &info->ring[next];
5004 status.data = le32_to_cpu(desc->phw->ctrl.data);
5005 if (status.rx.hw_owned)
5008 if (hw->dev_count > 1) {
5009 /* Get received port number. */
5010 int p = HW_TO_DEV_PORT(status.rx.src_port);
5012 dev = hw->port_info[p].pdev;
5013 if (!netif_running(dev))
5014 goto release_packet;
5017 /* Status valid only when last descriptor bit is set. */
5018 if (status.rx.last_desc && status.rx.first_desc) {
5019 if (rx_proc(dev, hw, desc, status))
5020 goto release_packet;
5034 static int dev_rcv_special(struct dev_info *hw_priv)
5037 union desc_stat status;
5038 struct ksz_hw *hw = &hw_priv->hw;
5039 struct net_device *dev = hw->port_info[0].pdev;
5040 struct ksz_desc_info *info = &hw->rx_desc_info;
5041 int left = info->alloc;
5042 struct ksz_desc *desc;
5047 /* Get next descriptor which is not hardware owned. */
5048 desc = &info->ring[next];
5049 status.data = le32_to_cpu(desc->phw->ctrl.data);
5050 if (status.rx.hw_owned)
5053 if (hw->dev_count > 1) {
5054 /* Get received port number. */
5055 int p = HW_TO_DEV_PORT(status.rx.src_port);
5057 dev = hw->port_info[p].pdev;
5058 if (!netif_running(dev))
5059 goto release_packet;
5062 /* Status valid only when last descriptor bit is set. */
5063 if (status.rx.last_desc && status.rx.first_desc) {
5065 * Receive without error. With receive errors
5066 * disabled, packets with receive errors will be
5067 * dropped, so no need to check the error bit.
5069 if (!status.rx.error || (status.data &
5070 KS_DESC_RX_ERROR_COND) ==
5071 KS_DESC_RX_ERROR_TOO_LONG) {
5072 if (rx_proc(dev, hw, desc, status))
5073 goto release_packet;
5076 struct dev_priv *priv = netdev_priv(dev);
5078 /* Update receive error statistics. */
5079 priv->port.counter[OID_COUNTER_RCV_ERROR]++;
5093 static void rx_proc_task(struct tasklet_struct *t)
5095 struct dev_info *hw_priv = from_tasklet(hw_priv, t, rx_tasklet);
5096 struct ksz_hw *hw = &hw_priv->hw;
5100 if (unlikely(!hw_priv->dev_rcv(hw_priv))) {
5102 /* In case receive process is suspended because of overrun. */
5105 /* tasklets are interruptible. */
5106 spin_lock_irq(&hw_priv->hwlock);
5107 hw_turn_on_intr(hw, KS884X_INT_RX_MASK);
5108 spin_unlock_irq(&hw_priv->hwlock);
5110 hw_ack_intr(hw, KS884X_INT_RX);
5111 tasklet_schedule(&hw_priv->rx_tasklet);
5115 static void tx_proc_task(struct tasklet_struct *t)
5117 struct dev_info *hw_priv = from_tasklet(hw_priv, t, tx_tasklet);
5118 struct ksz_hw *hw = &hw_priv->hw;
5120 hw_ack_intr(hw, KS884X_INT_TX_MASK);
5124 /* tasklets are interruptible. */
5125 spin_lock_irq(&hw_priv->hwlock);
5126 hw_turn_on_intr(hw, KS884X_INT_TX);
5127 spin_unlock_irq(&hw_priv->hwlock);
5130 static inline void handle_rx_stop(struct ksz_hw *hw)
5132 /* Receive just has been stopped. */
5133 if (0 == hw->rx_stop)
5134 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5135 else if (hw->rx_stop > 1) {
5136 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
5139 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5143 /* Receive just has been started. */
5148 * netdev_intr - interrupt handling
5149 * @irq: Interrupt number.
5150 * @dev_id: Network device.
5152 * This function is called by upper network layer to signal interrupt.
5154 * Return IRQ_HANDLED if interrupt is handled.
5156 static irqreturn_t netdev_intr(int irq, void *dev_id)
5158 uint int_enable = 0;
5159 struct net_device *dev = (struct net_device *) dev_id;
5160 struct dev_priv *priv = netdev_priv(dev);
5161 struct dev_info *hw_priv = priv->adapter;
5162 struct ksz_hw *hw = &hw_priv->hw;
5164 spin_lock(&hw_priv->hwlock);
5166 hw_read_intr(hw, &int_enable);
5168 /* Not our interrupt! */
5170 spin_unlock(&hw_priv->hwlock);
5175 hw_ack_intr(hw, int_enable);
5176 int_enable &= hw->intr_mask;
5178 if (unlikely(int_enable & KS884X_INT_TX_MASK)) {
5179 hw_dis_intr_bit(hw, KS884X_INT_TX_MASK);
5180 tasklet_schedule(&hw_priv->tx_tasklet);
5183 if (likely(int_enable & KS884X_INT_RX)) {
5184 hw_dis_intr_bit(hw, KS884X_INT_RX);
5185 tasklet_schedule(&hw_priv->rx_tasklet);
5188 if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) {
5189 dev->stats.rx_fifo_errors++;
5193 if (unlikely(int_enable & KS884X_INT_PHY)) {
5194 struct ksz_port *port = &priv->port;
5196 hw->features |= LINK_INT_WORKING;
5197 port_get_link_speed(port);
5200 if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) {
5205 if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) {
5208 hw->intr_mask &= ~KS884X_INT_TX_STOPPED;
5209 pr_info("Tx stopped\n");
5210 data = readl(hw->io + KS_DMA_TX_CTRL);
5211 if (!(data & DMA_TX_ENABLE))
5212 pr_info("Tx disabled\n");
5219 spin_unlock(&hw_priv->hwlock);
5225 * Linux network device functions
5229 #ifdef CONFIG_NET_POLL_CONTROLLER
5230 static void netdev_netpoll(struct net_device *dev)
5232 struct dev_priv *priv = netdev_priv(dev);
5233 struct dev_info *hw_priv = priv->adapter;
5235 hw_dis_intr(&hw_priv->hw);
5236 netdev_intr(dev->irq, dev);
5240 static void bridge_change(struct ksz_hw *hw)
5244 struct ksz_switch *sw = hw->ksz_switch;
5246 /* No ports in forwarding state. */
5248 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
5251 for (port = 0; port < SWITCH_PORT_NUM; port++) {
5252 if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state)
5253 member = HOST_MASK | sw->member;
5255 member = HOST_MASK | (1 << port);
5256 if (member != sw->port_cfg[port].member)
5257 sw_cfg_port_base_vlan(hw, port, member);
5262 * netdev_close - close network device
5263 * @dev: Network device.
5265 * This function process the close operation of network device. This is caused
5266 * by the user command "ifconfig ethX down."
5268 * Return 0 if successful; otherwise an error code indicating failure.
5270 static int netdev_close(struct net_device *dev)
5272 struct dev_priv *priv = netdev_priv(dev);
5273 struct dev_info *hw_priv = priv->adapter;
5274 struct ksz_port *port = &priv->port;
5275 struct ksz_hw *hw = &hw_priv->hw;
5278 netif_stop_queue(dev);
5280 ksz_stop_timer(&priv->monitor_timer_info);
5282 /* Need to shut the port manually in multiple device interfaces mode. */
5283 if (hw->dev_count > 1) {
5284 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED);
5286 /* Port is closed. Need to change bridge setting. */
5287 if (hw->features & STP_SUPPORT) {
5288 pi = 1 << port->first_port;
5289 if (hw->ksz_switch->member & pi) {
5290 hw->ksz_switch->member &= ~pi;
5295 if (port->first_port > 0)
5296 hw_del_addr(hw, dev->dev_addr);
5297 if (!hw_priv->wol_enable)
5298 port_set_power_saving(port, true);
5300 if (priv->multicast)
5302 if (priv->promiscuous)
5306 if (!(hw_priv->opened)) {
5307 ksz_stop_timer(&hw_priv->mib_timer_info);
5308 flush_work(&hw_priv->mib_read);
5312 hw_clr_multicast(hw);
5314 /* Delay for receive task to stop scheduling itself. */
5317 tasklet_kill(&hw_priv->rx_tasklet);
5318 tasklet_kill(&hw_priv->tx_tasklet);
5319 free_irq(dev->irq, hw_priv->dev);
5321 transmit_cleanup(hw_priv, 0);
5322 hw_reset_pkts(&hw->rx_desc_info);
5323 hw_reset_pkts(&hw->tx_desc_info);
5325 /* Clean out static MAC table when the switch is shutdown. */
5326 if (hw->features & STP_SUPPORT)
5327 sw_clr_sta_mac_table(hw);
5333 static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw)
5335 if (hw->ksz_switch) {
5338 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5339 if (hw->features & RX_HUGE_FRAME)
5340 data |= SWITCH_HUGE_PACKET;
5342 data &= ~SWITCH_HUGE_PACKET;
5343 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5345 if (hw->features & RX_HUGE_FRAME) {
5346 hw->rx_cfg |= DMA_RX_ERROR;
5347 hw_priv->dev_rcv = dev_rcv_special;
5349 hw->rx_cfg &= ~DMA_RX_ERROR;
5350 if (hw->dev_count > 1)
5351 hw_priv->dev_rcv = port_rcv_packets;
5353 hw_priv->dev_rcv = dev_rcv_packets;
5357 static int prepare_hardware(struct net_device *dev)
5359 struct dev_priv *priv = netdev_priv(dev);
5360 struct dev_info *hw_priv = priv->adapter;
5361 struct ksz_hw *hw = &hw_priv->hw;
5364 /* Remember the network device that requests interrupts. */
5366 rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev);
5369 tasklet_setup(&hw_priv->rx_tasklet, rx_proc_task);
5370 tasklet_setup(&hw_priv->tx_tasklet, tx_proc_task);
5372 hw->promiscuous = 0;
5374 hw->multi_list_size = 0;
5378 hw_set_desc_base(hw,
5379 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys);
5381 hw_cfg_huge_frame(hw_priv, hw);
5382 ksz_init_rx_buffers(hw_priv);
5386 static void set_media_state(struct net_device *dev, int media_state)
5388 struct dev_priv *priv = netdev_priv(dev);
5390 if (media_state == priv->media_state)
5391 netif_carrier_on(dev);
5393 netif_carrier_off(dev);
5394 netif_info(priv, link, dev, "link %s\n",
5395 media_state == priv->media_state ? "on" : "off");
5399 * netdev_open - open network device
5400 * @dev: Network device.
5402 * This function process the open operation of network device. This is caused
5403 * by the user command "ifconfig ethX up."
5405 * Return 0 if successful; otherwise an error code indicating failure.
5407 static int netdev_open(struct net_device *dev)
5409 struct dev_priv *priv = netdev_priv(dev);
5410 struct dev_info *hw_priv = priv->adapter;
5411 struct ksz_hw *hw = &hw_priv->hw;
5412 struct ksz_port *port = &priv->port;
5413 unsigned long next_jiffies;
5418 next_jiffies = jiffies + HZ * 2;
5419 priv->multicast = 0;
5420 priv->promiscuous = 0;
5422 /* Reset device statistics. */
5423 memset(&dev->stats, 0, sizeof(struct net_device_stats));
5424 memset((void *) port->counter, 0,
5425 (sizeof(u64) * OID_COUNTER_LAST));
5427 if (!(hw_priv->opened)) {
5428 rc = prepare_hardware(dev);
5431 for (i = 0; i < hw->mib_port_cnt; i++) {
5432 next_jiffies += HZ * 1;
5433 hw_priv->counter[i].time = next_jiffies;
5434 hw->port_mib[i].state = media_disconnected;
5435 port_init_cnt(hw, i);
5438 hw->port_mib[HOST_PORT].state = media_connected;
5440 hw_add_wol_bcast(hw);
5441 hw_cfg_wol_pme(hw, 0);
5442 hw_clr_wol_pme_status(&hw_priv->hw);
5445 port_set_power_saving(port, false);
5447 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
5449 * Initialize to invalid value so that link detection
5452 hw->port_info[p].partner = 0xFF;
5453 hw->port_info[p].state = media_disconnected;
5456 /* Need to open the port in multiple device interfaces mode. */
5457 if (hw->dev_count > 1) {
5458 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE);
5459 if (port->first_port > 0)
5460 hw_add_addr(hw, dev->dev_addr);
5463 port_get_link_speed(port);
5464 if (port->force_link)
5465 port_force_link_speed(port);
5467 port_set_link_speed(port);
5469 if (!(hw_priv->opened)) {
5474 if (hw->mib_port_cnt)
5475 ksz_start_timer(&hw_priv->mib_timer_info,
5476 hw_priv->mib_timer_info.period);
5481 ksz_start_timer(&priv->monitor_timer_info,
5482 priv->monitor_timer_info.period);
5484 priv->media_state = port->linked->state;
5486 set_media_state(dev, media_connected);
5487 netif_start_queue(dev);
5492 /* RX errors = rx_errors */
5493 /* RX dropped = rx_dropped */
5494 /* RX overruns = rx_fifo_errors */
5495 /* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */
5496 /* TX errors = tx_errors */
5497 /* TX dropped = tx_dropped */
5498 /* TX overruns = tx_fifo_errors */
5499 /* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */
5500 /* collisions = collisions */
5503 * netdev_query_statistics - query network device statistics
5504 * @dev: Network device.
5506 * This function returns the statistics of the network device. The device
5507 * needs not be opened.
5509 * Return network device statistics.
5511 static struct net_device_stats *netdev_query_statistics(struct net_device *dev)
5513 struct dev_priv *priv = netdev_priv(dev);
5514 struct ksz_port *port = &priv->port;
5515 struct ksz_hw *hw = &priv->adapter->hw;
5516 struct ksz_port_mib *mib;
5520 dev->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR];
5521 dev->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR];
5523 /* Reset to zero to add count later. */
5524 dev->stats.multicast = 0;
5525 dev->stats.collisions = 0;
5526 dev->stats.rx_length_errors = 0;
5527 dev->stats.rx_crc_errors = 0;
5528 dev->stats.rx_frame_errors = 0;
5529 dev->stats.tx_window_errors = 0;
5531 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
5532 mib = &hw->port_mib[p];
5534 dev->stats.multicast += (unsigned long)
5535 mib->counter[MIB_COUNTER_RX_MULTICAST];
5537 dev->stats.collisions += (unsigned long)
5538 mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION];
5540 dev->stats.rx_length_errors += (unsigned long)(
5541 mib->counter[MIB_COUNTER_RX_UNDERSIZE] +
5542 mib->counter[MIB_COUNTER_RX_FRAGMENT] +
5543 mib->counter[MIB_COUNTER_RX_OVERSIZE] +
5544 mib->counter[MIB_COUNTER_RX_JABBER]);
5545 dev->stats.rx_crc_errors += (unsigned long)
5546 mib->counter[MIB_COUNTER_RX_CRC_ERR];
5547 dev->stats.rx_frame_errors += (unsigned long)(
5548 mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] +
5549 mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]);
5551 dev->stats.tx_window_errors += (unsigned long)
5552 mib->counter[MIB_COUNTER_TX_LATE_COLLISION];
5559 * netdev_set_mac_address - set network device MAC address
5560 * @dev: Network device.
5561 * @addr: Buffer of MAC address.
5563 * This function is used to set the MAC address of the network device.
5565 * Return 0 to indicate success.
5567 static int netdev_set_mac_address(struct net_device *dev, void *addr)
5569 struct dev_priv *priv = netdev_priv(dev);
5570 struct dev_info *hw_priv = priv->adapter;
5571 struct ksz_hw *hw = &hw_priv->hw;
5572 struct sockaddr *mac = addr;
5575 if (priv->port.first_port > 0)
5576 hw_del_addr(hw, dev->dev_addr);
5578 hw->mac_override = 1;
5579 memcpy(hw->override_addr, mac->sa_data, ETH_ALEN);
5582 eth_hw_addr_set(dev, mac->sa_data);
5584 interrupt = hw_block_intr(hw);
5586 if (priv->port.first_port > 0)
5587 hw_add_addr(hw, dev->dev_addr);
5590 hw_restore_intr(hw, interrupt);
5595 static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv,
5596 struct ksz_hw *hw, int promiscuous)
5598 if (promiscuous != priv->promiscuous) {
5599 u8 prev_state = hw->promiscuous;
5605 priv->promiscuous = promiscuous;
5607 /* Turn on/off promiscuous mode. */
5608 if (hw->promiscuous <= 1 && prev_state <= 1)
5609 hw_set_promiscuous(hw, hw->promiscuous);
5612 * Port is not in promiscuous mode, meaning it is released
5615 if ((hw->features & STP_SUPPORT) && !promiscuous &&
5616 netif_is_bridge_port(dev)) {
5617 struct ksz_switch *sw = hw->ksz_switch;
5618 int port = priv->port.first_port;
5620 port_set_stp_state(hw, port, STP_STATE_DISABLED);
5622 if (sw->member & port) {
5623 sw->member &= ~port;
5630 static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw,
5633 if (multicast != priv->multicast) {
5634 u8 all_multi = hw->all_multi;
5640 priv->multicast = multicast;
5642 /* Turn on/off all multicast mode. */
5643 if (hw->all_multi <= 1 && all_multi <= 1)
5644 hw_set_multicast(hw, hw->all_multi);
5649 * netdev_set_rx_mode
5650 * @dev: Network device.
5652 * This routine is used to set multicast addresses or put the network device
5653 * into promiscuous mode.
5655 static void netdev_set_rx_mode(struct net_device *dev)
5657 struct dev_priv *priv = netdev_priv(dev);
5658 struct dev_info *hw_priv = priv->adapter;
5659 struct ksz_hw *hw = &hw_priv->hw;
5660 struct netdev_hw_addr *ha;
5661 int multicast = (dev->flags & IFF_ALLMULTI);
5663 dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC));
5665 if (hw_priv->hw.dev_count > 1)
5666 multicast |= (dev->flags & IFF_MULTICAST);
5667 dev_set_multicast(priv, hw, multicast);
5669 /* Cannot use different hashes in multiple device interfaces mode. */
5670 if (hw_priv->hw.dev_count > 1)
5673 if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) {
5676 /* List too big to support so turn on all multicast mode. */
5677 if (netdev_mc_count(dev) > MAX_MULTICAST_LIST) {
5678 if (MAX_MULTICAST_LIST != hw->multi_list_size) {
5679 hw->multi_list_size = MAX_MULTICAST_LIST;
5681 hw_set_multicast(hw, hw->all_multi);
5686 netdev_for_each_mc_addr(ha, dev) {
5687 if (i >= MAX_MULTICAST_LIST)
5689 memcpy(hw->multi_list[i++], ha->addr, ETH_ALEN);
5691 hw->multi_list_size = (u8) i;
5692 hw_set_grp_addr(hw);
5694 if (MAX_MULTICAST_LIST == hw->multi_list_size) {
5696 hw_set_multicast(hw, hw->all_multi);
5698 hw->multi_list_size = 0;
5699 hw_clr_multicast(hw);
5703 static int netdev_change_mtu(struct net_device *dev, int new_mtu)
5705 struct dev_priv *priv = netdev_priv(dev);
5706 struct dev_info *hw_priv = priv->adapter;
5707 struct ksz_hw *hw = &hw_priv->hw;
5710 if (netif_running(dev))
5713 /* Cannot use different MTU in multiple device interfaces mode. */
5714 if (hw->dev_count > 1)
5715 if (dev != hw_priv->dev)
5718 hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4;
5719 if (hw_mtu > REGULAR_RX_BUF_SIZE) {
5720 hw->features |= RX_HUGE_FRAME;
5721 hw_mtu = MAX_RX_BUF_SIZE;
5723 hw->features &= ~RX_HUGE_FRAME;
5724 hw_mtu = REGULAR_RX_BUF_SIZE;
5726 hw_mtu = (hw_mtu + 3) & ~3;
5727 hw_priv->mtu = hw_mtu;
5734 * netdev_ioctl - I/O control processing
5735 * @dev: Network device.
5736 * @ifr: Interface request structure.
5737 * @cmd: I/O control code.
5739 * This function is used to process I/O control calls.
5741 * Return 0 to indicate success.
5743 static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5745 struct dev_priv *priv = netdev_priv(dev);
5746 struct dev_info *hw_priv = priv->adapter;
5747 struct ksz_hw *hw = &hw_priv->hw;
5748 struct ksz_port *port = &priv->port;
5750 struct mii_ioctl_data *data = if_mii(ifr);
5752 if (down_interruptible(&priv->proc_sem))
5753 return -ERESTARTSYS;
5756 /* Get address of MII PHY in use. */
5758 data->phy_id = priv->id;
5761 /* Read MII PHY register. */
5763 if (data->phy_id != priv->id || data->reg_num >= 6)
5766 hw_r_phy(hw, port->linked->port_id, data->reg_num,
5770 /* Write MII PHY register. */
5772 if (!capable(CAP_NET_ADMIN))
5774 else if (data->phy_id != priv->id || data->reg_num >= 6)
5777 hw_w_phy(hw, port->linked->port_id, data->reg_num,
5782 result = -EOPNOTSUPP;
5785 up(&priv->proc_sem);
5795 * mdio_read - read PHY register
5796 * @dev: Network device.
5797 * @phy_id: The PHY id.
5798 * @reg_num: The register number.
5800 * This function returns the PHY register value.
5802 * Return the register value.
5804 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
5806 struct dev_priv *priv = netdev_priv(dev);
5807 struct ksz_port *port = &priv->port;
5808 struct ksz_hw *hw = port->hw;
5811 hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out);
5816 * mdio_write - set PHY register
5817 * @dev: Network device.
5818 * @phy_id: The PHY id.
5819 * @reg_num: The register number.
5820 * @val: The register value.
5822 * This procedure sets the PHY register value.
5824 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
5826 struct dev_priv *priv = netdev_priv(dev);
5827 struct ksz_port *port = &priv->port;
5828 struct ksz_hw *hw = port->hw;
5832 for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++)
5833 hw_w_phy(hw, pi, reg_num << 1, val);
5840 #define EEPROM_SIZE 0x40
5842 static u16 eeprom_data[EEPROM_SIZE] = { 0 };
5844 #define ADVERTISED_ALL \
5845 (ADVERTISED_10baseT_Half | \
5846 ADVERTISED_10baseT_Full | \
5847 ADVERTISED_100baseT_Half | \
5848 ADVERTISED_100baseT_Full)
5850 /* These functions use the MII functions in mii.c. */
5853 * netdev_get_link_ksettings - get network device settings
5854 * @dev: Network device.
5855 * @cmd: Ethtool command.
5857 * This function queries the PHY and returns its state in the ethtool command.
5859 * Return 0 if successful; otherwise an error code.
5861 static int netdev_get_link_ksettings(struct net_device *dev,
5862 struct ethtool_link_ksettings *cmd)
5864 struct dev_priv *priv = netdev_priv(dev);
5865 struct dev_info *hw_priv = priv->adapter;
5867 mutex_lock(&hw_priv->lock);
5868 mii_ethtool_get_link_ksettings(&priv->mii_if, cmd);
5869 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP);
5870 mutex_unlock(&hw_priv->lock);
5872 /* Save advertised settings for workaround in next function. */
5873 ethtool_convert_link_mode_to_legacy_u32(&priv->advertising,
5874 cmd->link_modes.advertising);
5880 * netdev_set_link_ksettings - set network device settings
5881 * @dev: Network device.
5882 * @cmd: Ethtool command.
5884 * This function sets the PHY according to the ethtool command.
5886 * Return 0 if successful; otherwise an error code.
5888 static int netdev_set_link_ksettings(struct net_device *dev,
5889 const struct ethtool_link_ksettings *cmd)
5891 struct dev_priv *priv = netdev_priv(dev);
5892 struct dev_info *hw_priv = priv->adapter;
5893 struct ksz_port *port = &priv->port;
5894 struct ethtool_link_ksettings copy_cmd;
5895 u32 speed = cmd->base.speed;
5899 ethtool_convert_link_mode_to_legacy_u32(&advertising,
5900 cmd->link_modes.advertising);
5903 * ethtool utility does not change advertised setting if auto
5904 * negotiation is not specified explicitly.
5906 if (cmd->base.autoneg && priv->advertising == advertising) {
5907 advertising |= ADVERTISED_ALL;
5910 ~(ADVERTISED_100baseT_Full |
5911 ADVERTISED_100baseT_Half);
5912 else if (100 == speed)
5914 ~(ADVERTISED_10baseT_Full |
5915 ADVERTISED_10baseT_Half);
5916 if (0 == cmd->base.duplex)
5918 ~(ADVERTISED_100baseT_Full |
5919 ADVERTISED_10baseT_Full);
5920 else if (1 == cmd->base.duplex)
5922 ~(ADVERTISED_100baseT_Half |
5923 ADVERTISED_10baseT_Half);
5925 mutex_lock(&hw_priv->lock);
5926 if (cmd->base.autoneg &&
5927 (advertising & ADVERTISED_ALL) == ADVERTISED_ALL) {
5930 port->force_link = 0;
5932 port->duplex = cmd->base.duplex + 1;
5934 port->speed = speed;
5935 if (cmd->base.autoneg)
5936 port->force_link = 0;
5938 port->force_link = 1;
5941 memcpy(©_cmd, cmd, sizeof(copy_cmd));
5942 ethtool_convert_legacy_u32_to_link_mode(copy_cmd.link_modes.advertising,
5944 rc = mii_ethtool_set_link_ksettings(
5946 (const struct ethtool_link_ksettings *)©_cmd);
5947 mutex_unlock(&hw_priv->lock);
5952 * netdev_nway_reset - restart auto-negotiation
5953 * @dev: Network device.
5955 * This function restarts the PHY for auto-negotiation.
5957 * Return 0 if successful; otherwise an error code.
5959 static int netdev_nway_reset(struct net_device *dev)
5961 struct dev_priv *priv = netdev_priv(dev);
5962 struct dev_info *hw_priv = priv->adapter;
5965 mutex_lock(&hw_priv->lock);
5966 rc = mii_nway_restart(&priv->mii_if);
5967 mutex_unlock(&hw_priv->lock);
5972 * netdev_get_link - get network device link status
5973 * @dev: Network device.
5975 * This function gets the link status from the PHY.
5977 * Return true if PHY is linked and false otherwise.
5979 static u32 netdev_get_link(struct net_device *dev)
5981 struct dev_priv *priv = netdev_priv(dev);
5984 rc = mii_link_ok(&priv->mii_if);
5989 * netdev_get_drvinfo - get network driver information
5990 * @dev: Network device.
5991 * @info: Ethtool driver info data structure.
5993 * This procedure returns the driver information.
5995 static void netdev_get_drvinfo(struct net_device *dev,
5996 struct ethtool_drvinfo *info)
5998 struct dev_priv *priv = netdev_priv(dev);
5999 struct dev_info *hw_priv = priv->adapter;
6001 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
6002 strscpy(info->version, DRV_VERSION, sizeof(info->version));
6003 strscpy(info->bus_info, pci_name(hw_priv->pdev),
6004 sizeof(info->bus_info));
6007 static struct hw_regs {
6010 } hw_regs_range[] = {
6011 { KS_DMA_TX_CTRL, KS884X_INTERRUPTS_STATUS },
6012 { KS_ADD_ADDR_0_LO, KS_ADD_ADDR_F_HI },
6013 { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET },
6014 { KS884X_SIDER_P, KS8842_SGCR7_P },
6015 { KS8842_MACAR1_P, KS8842_TOSR8_P },
6016 { KS884X_P1MBCR_P, KS8842_P3ERCR_P },
6021 * netdev_get_regs_len - get length of register dump
6022 * @dev: Network device.
6024 * This function returns the length of the register dump.
6026 * Return length of the register dump.
6028 static int netdev_get_regs_len(struct net_device *dev)
6030 struct hw_regs *range = hw_regs_range;
6031 int regs_len = 0x10 * sizeof(u32);
6033 while (range->end > range->start) {
6034 regs_len += (range->end - range->start + 3) / 4 * 4;
6041 * netdev_get_regs - get register dump
6042 * @dev: Network device.
6043 * @regs: Ethtool registers data structure.
6044 * @ptr: Buffer to store the register values.
6046 * This procedure dumps the register values in the provided buffer.
6048 static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs,
6051 struct dev_priv *priv = netdev_priv(dev);
6052 struct dev_info *hw_priv = priv->adapter;
6053 struct ksz_hw *hw = &hw_priv->hw;
6054 int *buf = (int *) ptr;
6055 struct hw_regs *range = hw_regs_range;
6058 mutex_lock(&hw_priv->lock);
6060 for (len = 0; len < 0x40; len += 4) {
6061 pci_read_config_dword(hw_priv->pdev, len, buf);
6064 while (range->end > range->start) {
6065 for (len = range->start; len < range->end; len += 4) {
6066 *buf = readl(hw->io + len);
6071 mutex_unlock(&hw_priv->lock);
6074 #define WOL_SUPPORT \
6075 (WAKE_PHY | WAKE_MAGIC | \
6076 WAKE_UCAST | WAKE_MCAST | \
6077 WAKE_BCAST | WAKE_ARP)
6080 * netdev_get_wol - get Wake-on-LAN support
6081 * @dev: Network device.
6082 * @wol: Ethtool Wake-on-LAN data structure.
6084 * This procedure returns Wake-on-LAN support.
6086 static void netdev_get_wol(struct net_device *dev,
6087 struct ethtool_wolinfo *wol)
6089 struct dev_priv *priv = netdev_priv(dev);
6090 struct dev_info *hw_priv = priv->adapter;
6092 wol->supported = hw_priv->wol_support;
6093 wol->wolopts = hw_priv->wol_enable;
6094 memset(&wol->sopass, 0, sizeof(wol->sopass));
6098 * netdev_set_wol - set Wake-on-LAN support
6099 * @dev: Network device.
6100 * @wol: Ethtool Wake-on-LAN data structure.
6102 * This function sets Wake-on-LAN support.
6104 * Return 0 if successful; otherwise an error code.
6106 static int netdev_set_wol(struct net_device *dev,
6107 struct ethtool_wolinfo *wol)
6109 struct dev_priv *priv = netdev_priv(dev);
6110 struct dev_info *hw_priv = priv->adapter;
6112 /* Need to find a way to retrieve the device IP address. */
6113 static const u8 net_addr[] = { 192, 168, 1, 1 };
6115 if (wol->wolopts & ~hw_priv->wol_support)
6118 hw_priv->wol_enable = wol->wolopts;
6120 /* Link wakeup cannot really be disabled. */
6122 hw_priv->wol_enable |= WAKE_PHY;
6123 hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr);
6128 * netdev_get_msglevel - get debug message level
6129 * @dev: Network device.
6131 * This function returns current debug message level.
6133 * Return current debug message flags.
6135 static u32 netdev_get_msglevel(struct net_device *dev)
6137 struct dev_priv *priv = netdev_priv(dev);
6139 return priv->msg_enable;
6143 * netdev_set_msglevel - set debug message level
6144 * @dev: Network device.
6145 * @value: Debug message flags.
6147 * This procedure sets debug message level.
6149 static void netdev_set_msglevel(struct net_device *dev, u32 value)
6151 struct dev_priv *priv = netdev_priv(dev);
6153 priv->msg_enable = value;
6157 * netdev_get_eeprom_len - get EEPROM length
6158 * @dev: Network device.
6160 * This function returns the length of the EEPROM.
6162 * Return length of the EEPROM.
6164 static int netdev_get_eeprom_len(struct net_device *dev)
6166 return EEPROM_SIZE * 2;
6169 #define EEPROM_MAGIC 0x10A18842
6172 * netdev_get_eeprom - get EEPROM data
6173 * @dev: Network device.
6174 * @eeprom: Ethtool EEPROM data structure.
6175 * @data: Buffer to store the EEPROM data.
6177 * This function dumps the EEPROM data in the provided buffer.
6179 * Return 0 if successful; otherwise an error code.
6181 static int netdev_get_eeprom(struct net_device *dev,
6182 struct ethtool_eeprom *eeprom, u8 *data)
6184 struct dev_priv *priv = netdev_priv(dev);
6185 struct dev_info *hw_priv = priv->adapter;
6186 u8 *eeprom_byte = (u8 *) eeprom_data;
6190 len = (eeprom->offset + eeprom->len + 1) / 2;
6191 for (i = eeprom->offset / 2; i < len; i++)
6192 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6193 eeprom->magic = EEPROM_MAGIC;
6194 memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len);
6200 * netdev_set_eeprom - write EEPROM data
6201 * @dev: Network device.
6202 * @eeprom: Ethtool EEPROM data structure.
6203 * @data: Data buffer.
6205 * This function modifies the EEPROM data one byte at a time.
6207 * Return 0 if successful; otherwise an error code.
6209 static int netdev_set_eeprom(struct net_device *dev,
6210 struct ethtool_eeprom *eeprom, u8 *data)
6212 struct dev_priv *priv = netdev_priv(dev);
6213 struct dev_info *hw_priv = priv->adapter;
6214 u16 eeprom_word[EEPROM_SIZE];
6215 u8 *eeprom_byte = (u8 *) eeprom_word;
6219 if (eeprom->magic != EEPROM_MAGIC)
6222 len = (eeprom->offset + eeprom->len + 1) / 2;
6223 for (i = eeprom->offset / 2; i < len; i++)
6224 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6225 memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2);
6226 memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len);
6227 for (i = 0; i < EEPROM_SIZE; i++)
6228 if (eeprom_word[i] != eeprom_data[i]) {
6229 eeprom_data[i] = eeprom_word[i];
6230 eeprom_write(&hw_priv->hw, i, eeprom_data[i]);
6237 * netdev_get_pauseparam - get flow control parameters
6238 * @dev: Network device.
6239 * @pause: Ethtool PAUSE settings data structure.
6241 * This procedure returns the PAUSE control flow settings.
6243 static void netdev_get_pauseparam(struct net_device *dev,
6244 struct ethtool_pauseparam *pause)
6246 struct dev_priv *priv = netdev_priv(dev);
6247 struct dev_info *hw_priv = priv->adapter;
6248 struct ksz_hw *hw = &hw_priv->hw;
6250 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1;
6251 if (!hw->ksz_switch) {
6253 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
6255 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0;
6258 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6259 SWITCH_RX_FLOW_CTRL)) ? 1 : 0;
6261 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6262 SWITCH_TX_FLOW_CTRL)) ? 1 : 0;
6267 * netdev_set_pauseparam - set flow control parameters
6268 * @dev: Network device.
6269 * @pause: Ethtool PAUSE settings data structure.
6271 * This function sets the PAUSE control flow settings.
6272 * Not implemented yet.
6274 * Return 0 if successful; otherwise an error code.
6276 static int netdev_set_pauseparam(struct net_device *dev,
6277 struct ethtool_pauseparam *pause)
6279 struct dev_priv *priv = netdev_priv(dev);
6280 struct dev_info *hw_priv = priv->adapter;
6281 struct ksz_hw *hw = &hw_priv->hw;
6282 struct ksz_port *port = &priv->port;
6284 mutex_lock(&hw_priv->lock);
6285 if (pause->autoneg) {
6286 if (!pause->rx_pause && !pause->tx_pause)
6287 port->flow_ctrl = PHY_NO_FLOW_CTRL;
6289 port->flow_ctrl = PHY_FLOW_CTRL;
6290 hw->overrides &= ~PAUSE_FLOW_CTRL;
6291 port->force_link = 0;
6292 if (hw->ksz_switch) {
6293 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6294 SWITCH_RX_FLOW_CTRL, 1);
6295 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6296 SWITCH_TX_FLOW_CTRL, 1);
6298 port_set_link_speed(port);
6300 hw->overrides |= PAUSE_FLOW_CTRL;
6301 if (hw->ksz_switch) {
6302 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6303 SWITCH_RX_FLOW_CTRL, pause->rx_pause);
6304 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6305 SWITCH_TX_FLOW_CTRL, pause->tx_pause);
6307 set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause);
6309 mutex_unlock(&hw_priv->lock);
6315 * netdev_get_ringparam - get tx/rx ring parameters
6316 * @dev: Network device.
6317 * @ring: Ethtool RING settings data structure.
6318 * @kernel_ring: Ethtool external RING settings data structure.
6319 * @extack: Netlink handle.
6321 * This procedure returns the TX/RX ring settings.
6323 static void netdev_get_ringparam(struct net_device *dev,
6324 struct ethtool_ringparam *ring,
6325 struct kernel_ethtool_ringparam *kernel_ring,
6326 struct netlink_ext_ack *extack)
6328 struct dev_priv *priv = netdev_priv(dev);
6329 struct dev_info *hw_priv = priv->adapter;
6330 struct ksz_hw *hw = &hw_priv->hw;
6332 ring->tx_max_pending = (1 << 9);
6333 ring->tx_pending = hw->tx_desc_info.alloc;
6334 ring->rx_max_pending = (1 << 9);
6335 ring->rx_pending = hw->rx_desc_info.alloc;
6338 #define STATS_LEN (TOTAL_PORT_COUNTER_NUM)
6341 char string[ETH_GSTRING_LEN];
6342 } ethtool_stats_keys[STATS_LEN] = {
6343 { "rx_lo_priority_octets" },
6344 { "rx_hi_priority_octets" },
6345 { "rx_undersize_packets" },
6347 { "rx_oversize_packets" },
6349 { "rx_symbol_errors" },
6350 { "rx_crc_errors" },
6351 { "rx_align_errors" },
6352 { "rx_mac_ctrl_packets" },
6353 { "rx_pause_packets" },
6354 { "rx_bcast_packets" },
6355 { "rx_mcast_packets" },
6356 { "rx_ucast_packets" },
6357 { "rx_64_or_less_octet_packets" },
6358 { "rx_65_to_127_octet_packets" },
6359 { "rx_128_to_255_octet_packets" },
6360 { "rx_256_to_511_octet_packets" },
6361 { "rx_512_to_1023_octet_packets" },
6362 { "rx_1024_to_1522_octet_packets" },
6364 { "tx_lo_priority_octets" },
6365 { "tx_hi_priority_octets" },
6366 { "tx_late_collisions" },
6367 { "tx_pause_packets" },
6368 { "tx_bcast_packets" },
6369 { "tx_mcast_packets" },
6370 { "tx_ucast_packets" },
6372 { "tx_total_collisions" },
6373 { "tx_excessive_collisions" },
6374 { "tx_single_collisions" },
6375 { "tx_mult_collisions" },
6382 * netdev_get_strings - get statistics identity strings
6383 * @dev: Network device.
6384 * @stringset: String set identifier.
6385 * @buf: Buffer to store the strings.
6387 * This procedure returns the strings used to identify the statistics.
6389 static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6391 struct dev_priv *priv = netdev_priv(dev);
6392 struct dev_info *hw_priv = priv->adapter;
6393 struct ksz_hw *hw = &hw_priv->hw;
6395 if (ETH_SS_STATS == stringset)
6396 memcpy(buf, ðtool_stats_keys,
6397 ETH_GSTRING_LEN * hw->mib_cnt);
6401 * netdev_get_sset_count - get statistics size
6402 * @dev: Network device.
6403 * @sset: The statistics set number.
6405 * This function returns the size of the statistics to be reported.
6407 * Return size of the statistics to be reported.
6409 static int netdev_get_sset_count(struct net_device *dev, int sset)
6411 struct dev_priv *priv = netdev_priv(dev);
6412 struct dev_info *hw_priv = priv->adapter;
6413 struct ksz_hw *hw = &hw_priv->hw;
6424 * netdev_get_ethtool_stats - get network device statistics
6425 * @dev: Network device.
6426 * @stats: Ethtool statistics data structure.
6427 * @data: Buffer to store the statistics.
6429 * This procedure returns the statistics.
6431 static void netdev_get_ethtool_stats(struct net_device *dev,
6432 struct ethtool_stats *stats, u64 *data)
6434 struct dev_priv *priv = netdev_priv(dev);
6435 struct dev_info *hw_priv = priv->adapter;
6436 struct ksz_hw *hw = &hw_priv->hw;
6437 struct ksz_port *port = &priv->port;
6438 int n_stats = stats->n_stats;
6442 u64 counter[TOTAL_PORT_COUNTER_NUM];
6444 mutex_lock(&hw_priv->lock);
6445 n = SWITCH_PORT_NUM;
6446 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
6447 if (media_connected == hw->port_mib[p].state) {
6448 hw_priv->counter[p].read = 1;
6450 /* Remember first port that requests read. */
6451 if (n == SWITCH_PORT_NUM)
6455 mutex_unlock(&hw_priv->lock);
6457 if (n < SWITCH_PORT_NUM)
6458 schedule_work(&hw_priv->mib_read);
6460 if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) {
6462 wait_event_interruptible_timeout(
6463 hw_priv->counter[p].counter,
6464 2 == hw_priv->counter[p].read,
6467 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) {
6469 wait_event_interruptible_timeout(
6470 hw_priv->counter[p].counter,
6471 2 == hw_priv->counter[p].read,
6473 } else if (hw->port_mib[p].cnt_ptr) {
6474 wait_event_interruptible_timeout(
6475 hw_priv->counter[p].counter,
6476 2 == hw_priv->counter[p].read,
6481 get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter);
6486 for (i = 0; i < n; i++)
6487 *data++ = counter[i];
6491 * netdev_set_features - set receive checksum support
6492 * @dev: Network device.
6493 * @features: New device features (offloads).
6495 * This function sets receive checksum support setting.
6497 * Return 0 if successful; otherwise an error code.
6499 static int netdev_set_features(struct net_device *dev,
6500 netdev_features_t features)
6502 struct dev_priv *priv = netdev_priv(dev);
6503 struct dev_info *hw_priv = priv->adapter;
6504 struct ksz_hw *hw = &hw_priv->hw;
6506 mutex_lock(&hw_priv->lock);
6508 /* see note in hw_setup() */
6509 if (features & NETIF_F_RXCSUM)
6510 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP;
6512 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
6515 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
6517 mutex_unlock(&hw_priv->lock);
6522 static const struct ethtool_ops netdev_ethtool_ops = {
6523 .nway_reset = netdev_nway_reset,
6524 .get_link = netdev_get_link,
6525 .get_drvinfo = netdev_get_drvinfo,
6526 .get_regs_len = netdev_get_regs_len,
6527 .get_regs = netdev_get_regs,
6528 .get_wol = netdev_get_wol,
6529 .set_wol = netdev_set_wol,
6530 .get_msglevel = netdev_get_msglevel,
6531 .set_msglevel = netdev_set_msglevel,
6532 .get_eeprom_len = netdev_get_eeprom_len,
6533 .get_eeprom = netdev_get_eeprom,
6534 .set_eeprom = netdev_set_eeprom,
6535 .get_pauseparam = netdev_get_pauseparam,
6536 .set_pauseparam = netdev_set_pauseparam,
6537 .get_ringparam = netdev_get_ringparam,
6538 .get_strings = netdev_get_strings,
6539 .get_sset_count = netdev_get_sset_count,
6540 .get_ethtool_stats = netdev_get_ethtool_stats,
6541 .get_link_ksettings = netdev_get_link_ksettings,
6542 .set_link_ksettings = netdev_set_link_ksettings,
6546 * Hardware monitoring
6549 static void update_link(struct net_device *dev, struct dev_priv *priv,
6550 struct ksz_port *port)
6552 if (priv->media_state != port->linked->state) {
6553 priv->media_state = port->linked->state;
6554 if (netif_running(dev))
6555 set_media_state(dev, media_connected);
6559 static void mib_read_work(struct work_struct *work)
6561 struct dev_info *hw_priv =
6562 container_of(work, struct dev_info, mib_read);
6563 struct ksz_hw *hw = &hw_priv->hw;
6564 unsigned long next_jiffies;
6565 struct ksz_port_mib *mib;
6568 next_jiffies = jiffies;
6569 for (i = 0; i < hw->mib_port_cnt; i++) {
6570 mib = &hw->port_mib[i];
6572 /* Reading MIB counters or requested to read. */
6573 if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) {
6575 /* Need to process receive interrupt. */
6576 if (port_r_cnt(hw, i))
6578 hw_priv->counter[i].read = 0;
6580 /* Finish reading counters. */
6581 if (0 == mib->cnt_ptr) {
6582 hw_priv->counter[i].read = 2;
6583 wake_up_interruptible(
6584 &hw_priv->counter[i].counter);
6586 } else if (time_after_eq(jiffies, hw_priv->counter[i].time)) {
6587 /* Only read MIB counters when the port is connected. */
6588 if (media_connected == mib->state)
6589 hw_priv->counter[i].read = 1;
6590 next_jiffies += HZ * 1 * hw->mib_port_cnt;
6591 hw_priv->counter[i].time = next_jiffies;
6593 /* Port is just disconnected. */
6594 } else if (mib->link_down) {
6597 /* Read counters one last time after link is lost. */
6598 hw_priv->counter[i].read = 1;
6603 static void mib_monitor(struct timer_list *t)
6605 struct dev_info *hw_priv = from_timer(hw_priv, t, mib_timer_info.timer);
6607 mib_read_work(&hw_priv->mib_read);
6609 /* This is used to verify Wake-on-LAN is working. */
6610 if (hw_priv->pme_wait) {
6611 if (time_is_before_eq_jiffies(hw_priv->pme_wait)) {
6612 hw_clr_wol_pme_status(&hw_priv->hw);
6613 hw_priv->pme_wait = 0;
6615 } else if (hw_chk_wol_pme_status(&hw_priv->hw)) {
6617 /* PME is asserted. Wait 2 seconds to clear it. */
6618 hw_priv->pme_wait = jiffies + HZ * 2;
6621 ksz_update_timer(&hw_priv->mib_timer_info);
6625 * dev_monitor - periodic monitoring
6626 * @t: timer list containing a network device pointer.
6628 * This routine is run in a kernel timer to monitor the network device.
6630 static void dev_monitor(struct timer_list *t)
6632 struct dev_priv *priv = from_timer(priv, t, monitor_timer_info.timer);
6633 struct net_device *dev = priv->mii_if.dev;
6634 struct dev_info *hw_priv = priv->adapter;
6635 struct ksz_hw *hw = &hw_priv->hw;
6636 struct ksz_port *port = &priv->port;
6638 if (!(hw->features & LINK_INT_WORKING))
6639 port_get_link_speed(port);
6640 update_link(dev, priv, port);
6642 ksz_update_timer(&priv->monitor_timer_info);
6646 * Linux network device interface functions
6649 /* Driver exported variables */
6651 static int msg_enable;
6653 static char *macaddr = ":";
6654 static char *mac1addr = ":";
6657 * This enables multiple network device mode for KSZ8842, which contains a
6658 * switch with two physical ports. Some users like to take control of the
6659 * ports for running Spanning Tree Protocol. The driver will create an
6660 * additional eth? device for the other port.
6662 * Some limitations are the network devices cannot have different MTU and
6663 * multicast hash tables.
6665 static int multi_dev;
6668 * As most users select multiple network device mode to use Spanning Tree
6669 * Protocol, this enables a feature in which most unicast and multicast packets
6670 * are forwarded inside the switch and not passed to the host. Only packets
6671 * that need the host's attention are passed to it. This prevents the host
6672 * wasting CPU time to examine each and every incoming packets and do the
6673 * forwarding itself.
6675 * As the hack requires the private bridge header, the driver cannot compile
6676 * with just the kernel headers.
6678 * Enabling STP support also turns on multiple network device mode.
6683 * This enables fast aging in the KSZ8842 switch. Not sure what situation
6684 * needs that. However, fast aging is used to flush the dynamic MAC table when
6685 * STP support is enabled.
6687 static int fast_aging;
6690 * netdev_init - initialize network device.
6691 * @dev: Network device.
6693 * This function initializes the network device.
6695 * Return 0 if successful; otherwise an error code indicating failure.
6697 static int __init netdev_init(struct net_device *dev)
6699 struct dev_priv *priv = netdev_priv(dev);
6701 /* 500 ms timeout */
6702 ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000,
6705 /* 500 ms timeout */
6706 dev->watchdog_timeo = HZ / 2;
6708 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_RXCSUM;
6711 * Hardware does not really support IPv6 checksum generation, but
6712 * driver actually runs faster with this on.
6714 dev->hw_features |= NETIF_F_IPV6_CSUM;
6716 dev->features |= dev->hw_features;
6718 sema_init(&priv->proc_sem, 1);
6720 priv->mii_if.phy_id_mask = 0x1;
6721 priv->mii_if.reg_num_mask = 0x7;
6722 priv->mii_if.dev = dev;
6723 priv->mii_if.mdio_read = mdio_read;
6724 priv->mii_if.mdio_write = mdio_write;
6725 priv->mii_if.phy_id = priv->port.first_port + 1;
6727 priv->msg_enable = netif_msg_init(msg_enable,
6728 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK));
6733 static const struct net_device_ops netdev_ops = {
6734 .ndo_init = netdev_init,
6735 .ndo_open = netdev_open,
6736 .ndo_stop = netdev_close,
6737 .ndo_get_stats = netdev_query_statistics,
6738 .ndo_start_xmit = netdev_tx,
6739 .ndo_tx_timeout = netdev_tx_timeout,
6740 .ndo_change_mtu = netdev_change_mtu,
6741 .ndo_set_features = netdev_set_features,
6742 .ndo_set_mac_address = netdev_set_mac_address,
6743 .ndo_validate_addr = eth_validate_addr,
6744 .ndo_eth_ioctl = netdev_ioctl,
6745 .ndo_set_rx_mode = netdev_set_rx_mode,
6746 #ifdef CONFIG_NET_POLL_CONTROLLER
6747 .ndo_poll_controller = netdev_netpoll,
6751 static void netdev_free(struct net_device *dev)
6753 if (dev->watchdog_timeo)
6754 unregister_netdev(dev);
6759 struct platform_info {
6760 struct dev_info dev_info;
6761 struct net_device *netdev[SWITCH_PORT_NUM];
6764 static int net_device_present;
6766 static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port)
6773 i = j = num = got_num = 0;
6774 while (j < ETH_ALEN) {
6779 digit = hex_to_bin(macaddr[i]);
6781 num = num * 16 + digit;
6782 else if (':' == macaddr[i])
6791 if (MAIN_PORT == port) {
6792 hw_priv->hw.override_addr[j++] = (u8) num;
6793 hw_priv->hw.override_addr[5] +=
6796 hw_priv->hw.ksz_switch->other_addr[j++] =
6798 hw_priv->hw.ksz_switch->other_addr[5] +=
6805 if (ETH_ALEN == j) {
6806 if (MAIN_PORT == port)
6807 hw_priv->hw.mac_override = 1;
6811 #define KS884X_DMA_MASK (~0x0UL)
6813 static void read_other_addr(struct ksz_hw *hw)
6817 struct ksz_switch *sw = hw->ksz_switch;
6819 for (i = 0; i < 3; i++)
6820 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR);
6821 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) {
6822 sw->other_addr[5] = (u8) data[0];
6823 sw->other_addr[4] = (u8)(data[0] >> 8);
6824 sw->other_addr[3] = (u8) data[1];
6825 sw->other_addr[2] = (u8)(data[1] >> 8);
6826 sw->other_addr[1] = (u8) data[2];
6827 sw->other_addr[0] = (u8)(data[2] >> 8);
6831 #ifndef PCI_VENDOR_ID_MICREL_KS
6832 #define PCI_VENDOR_ID_MICREL_KS 0x16c6
6835 static int pcidev_init(struct pci_dev *pdev, const struct pci_device_id *id)
6837 struct net_device *dev;
6838 struct dev_priv *priv;
6839 struct dev_info *hw_priv;
6841 struct platform_info *info;
6842 struct ksz_port *port;
6843 unsigned long reg_base;
6844 unsigned long reg_len;
6851 char banner[sizeof(version)];
6852 struct ksz_switch *sw = NULL;
6854 result = pci_enable_device(pdev);
6860 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) ||
6861 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)))
6864 reg_base = pci_resource_start(pdev, 0);
6865 reg_len = pci_resource_len(pdev, 0);
6866 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0)
6869 if (!request_mem_region(reg_base, reg_len, DRV_NAME))
6871 pci_set_master(pdev);
6875 info = kzalloc(sizeof(struct platform_info), GFP_KERNEL);
6877 goto pcidev_init_dev_err;
6879 hw_priv = &info->dev_info;
6880 hw_priv->pdev = pdev;
6884 hw->io = ioremap(reg_base, reg_len);
6886 goto pcidev_init_io_err;
6890 if (msg_enable & NETIF_MSG_PROBE)
6891 pr_alert("chip not detected\n");
6893 goto pcidev_init_alloc_err;
6896 snprintf(banner, sizeof(banner), "%s", version);
6897 banner[13] = cnt + '0'; /* Replace x in "Micrel KSZ884x" */
6898 dev_info(&hw_priv->pdev->dev, "%s\n", banner);
6899 dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq);
6901 /* Assume device is KSZ8841. */
6905 hw->addr_list_size = 0;
6906 hw->mib_cnt = PORT_COUNTER_NUM;
6907 hw->mib_port_cnt = 1;
6909 /* KSZ8842 has a switch with multiple ports. */
6912 hw->overrides |= FAST_AGING;
6914 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM;
6916 /* Multiple network device interfaces are required. */
6918 hw->dev_count = SWITCH_PORT_NUM;
6919 hw->addr_list_size = SWITCH_PORT_NUM - 1;
6922 /* Single network device has multiple ports. */
6923 if (1 == hw->dev_count) {
6924 port_count = SWITCH_PORT_NUM;
6925 mib_port_count = SWITCH_PORT_NUM;
6927 hw->mib_port_cnt = TOTAL_PORT_NUM;
6928 hw->ksz_switch = kzalloc(sizeof(struct ksz_switch), GFP_KERNEL);
6929 if (!hw->ksz_switch)
6930 goto pcidev_init_alloc_err;
6932 sw = hw->ksz_switch;
6934 for (i = 0; i < hw->mib_port_cnt; i++)
6935 hw->port_mib[i].mib_start = 0;
6937 hw->parent = hw_priv;
6939 /* Default MTU is 1500. */
6940 hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3;
6942 if (ksz_alloc_mem(hw_priv))
6943 goto pcidev_init_mem_err;
6945 hw_priv->hw.id = net_device_present;
6947 spin_lock_init(&hw_priv->hwlock);
6948 mutex_init(&hw_priv->lock);
6950 for (i = 0; i < TOTAL_PORT_NUM; i++)
6951 init_waitqueue_head(&hw_priv->counter[i].counter);
6953 if (macaddr[0] != ':')
6954 get_mac_addr(hw_priv, macaddr, MAIN_PORT);
6956 /* Read MAC address and initialize override address if not overridden. */
6959 /* Multiple device interfaces mode requires a second MAC address. */
6960 if (hw->dev_count > 1) {
6961 memcpy(sw->other_addr, hw->override_addr, ETH_ALEN);
6962 read_other_addr(hw);
6963 if (mac1addr[0] != ':')
6964 get_mac_addr(hw_priv, mac1addr, OTHER_PORT);
6971 hw_priv->wol_support = WOL_SUPPORT;
6972 hw_priv->wol_enable = 0;
6975 INIT_WORK(&hw_priv->mib_read, mib_read_work);
6977 /* 500 ms timeout */
6978 ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000,
6981 for (i = 0; i < hw->dev_count; i++) {
6982 dev = alloc_etherdev(sizeof(struct dev_priv));
6984 goto pcidev_init_reg_err;
6985 SET_NETDEV_DEV(dev, &pdev->dev);
6986 info->netdev[i] = dev;
6988 priv = netdev_priv(dev);
6989 priv->adapter = hw_priv;
6990 priv->id = net_device_present++;
6993 port->port_cnt = port_count;
6994 port->mib_port_cnt = mib_port_count;
6995 port->first_port = i;
6996 port->flow_ctrl = PHY_FLOW_CTRL;
6999 port->linked = &hw->port_info[port->first_port];
7001 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) {
7002 hw->port_info[pi].port_id = pi;
7003 hw->port_info[pi].pdev = dev;
7004 hw->port_info[pi].state = media_disconnected;
7007 dev->mem_start = (unsigned long) hw->io;
7008 dev->mem_end = dev->mem_start + reg_len - 1;
7009 dev->irq = pdev->irq;
7011 eth_hw_addr_set(dev, hw_priv->hw.override_addr);
7015 ether_addr_copy(addr, sw->other_addr);
7016 if (ether_addr_equal(sw->other_addr, hw->override_addr))
7017 addr[5] += port->first_port;
7018 eth_hw_addr_set(dev, addr);
7021 dev->netdev_ops = &netdev_ops;
7022 dev->ethtool_ops = &netdev_ethtool_ops;
7024 /* MTU range: 60 - 1894 */
7025 dev->min_mtu = ETH_ZLEN;
7026 dev->max_mtu = MAX_RX_BUF_SIZE -
7027 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7029 if (register_netdev(dev))
7030 goto pcidev_init_reg_err;
7031 port_set_power_saving(port, true);
7034 pci_dev_get(hw_priv->pdev);
7035 pci_set_drvdata(pdev, info);
7038 pcidev_init_reg_err:
7039 for (i = 0; i < hw->dev_count; i++) {
7040 if (info->netdev[i]) {
7041 netdev_free(info->netdev[i]);
7042 info->netdev[i] = NULL;
7046 pcidev_init_mem_err:
7047 ksz_free_mem(hw_priv);
7048 kfree(hw->ksz_switch);
7050 pcidev_init_alloc_err:
7056 pcidev_init_dev_err:
7057 release_mem_region(reg_base, reg_len);
7062 static void pcidev_exit(struct pci_dev *pdev)
7065 struct platform_info *info = pci_get_drvdata(pdev);
7066 struct dev_info *hw_priv = &info->dev_info;
7068 release_mem_region(pci_resource_start(pdev, 0),
7069 pci_resource_len(pdev, 0));
7070 for (i = 0; i < hw_priv->hw.dev_count; i++) {
7071 if (info->netdev[i])
7072 netdev_free(info->netdev[i]);
7075 iounmap(hw_priv->hw.io);
7076 ksz_free_mem(hw_priv);
7077 kfree(hw_priv->hw.ksz_switch);
7078 pci_dev_put(hw_priv->pdev);
7082 static int __maybe_unused pcidev_resume(struct device *dev_d)
7085 struct platform_info *info = dev_get_drvdata(dev_d);
7086 struct dev_info *hw_priv = &info->dev_info;
7087 struct ksz_hw *hw = &hw_priv->hw;
7089 device_wakeup_disable(dev_d);
7091 if (hw_priv->wol_enable)
7092 hw_cfg_wol_pme(hw, 0);
7093 for (i = 0; i < hw->dev_count; i++) {
7094 if (info->netdev[i]) {
7095 struct net_device *dev = info->netdev[i];
7097 if (netif_running(dev)) {
7099 netif_device_attach(dev);
7106 static int __maybe_unused pcidev_suspend(struct device *dev_d)
7109 struct platform_info *info = dev_get_drvdata(dev_d);
7110 struct dev_info *hw_priv = &info->dev_info;
7111 struct ksz_hw *hw = &hw_priv->hw;
7113 /* Need to find a way to retrieve the device IP address. */
7114 static const u8 net_addr[] = { 192, 168, 1, 1 };
7116 for (i = 0; i < hw->dev_count; i++) {
7117 if (info->netdev[i]) {
7118 struct net_device *dev = info->netdev[i];
7120 if (netif_running(dev)) {
7121 netif_device_detach(dev);
7126 if (hw_priv->wol_enable) {
7127 hw_enable_wol(hw, hw_priv->wol_enable, net_addr);
7128 hw_cfg_wol_pme(hw, 1);
7131 device_wakeup_enable(dev_d);
7135 static char pcidev_name[] = "ksz884xp";
7137 static const struct pci_device_id pcidev_table[] = {
7138 { PCI_VENDOR_ID_MICREL_KS, 0x8841,
7139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7140 { PCI_VENDOR_ID_MICREL_KS, 0x8842,
7141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7145 MODULE_DEVICE_TABLE(pci, pcidev_table);
7147 static SIMPLE_DEV_PM_OPS(pcidev_pm_ops, pcidev_suspend, pcidev_resume);
7149 static struct pci_driver pci_device_driver = {
7150 .driver.pm = &pcidev_pm_ops,
7151 .name = pcidev_name,
7152 .id_table = pcidev_table,
7153 .probe = pcidev_init,
7154 .remove = pcidev_exit
7157 module_pci_driver(pci_device_driver);
7159 MODULE_DESCRIPTION("KSZ8841/2 PCI network driver");
7160 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>");
7161 MODULE_LICENSE("GPL");
7163 module_param_named(message, msg_enable, int, 0);
7164 MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
7166 module_param(macaddr, charp, 0);
7167 module_param(mac1addr, charp, 0);
7168 module_param(fast_aging, int, 0);
7169 module_param(multi_dev, int, 0);
7170 module_param(stp, int, 0);
7171 MODULE_PARM_DESC(macaddr, "MAC address");
7172 MODULE_PARM_DESC(mac1addr, "Second MAC address");
7173 MODULE_PARM_DESC(fast_aging, "Fast aging");
7174 MODULE_PARM_DESC(multi_dev, "Multiple device interfaces");
7175 MODULE_PARM_DESC(stp, "STP support");