1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
8 #include <linux/netdevice.h>
9 #include <linux/ethtool.h>
10 #include <linux/etherdevice.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
24 static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
25 static const char mlxsw_sx_driver_version[] = "1.0";
30 struct mlxsw_sx_port **ports;
31 struct mlxsw_core *core;
32 const struct mlxsw_bus_info *bus_info;
36 struct mlxsw_sx_port_pcpu_stats {
41 struct u64_stats_sync syncp;
45 struct mlxsw_sx_port {
46 struct net_device *dev;
47 struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
48 struct mlxsw_sx *mlxsw_sx;
59 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
62 * Packet control type.
63 * 0 - Ethernet control (e.g. EMADs, LACP)
66 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
69 * Packet protocol type. Must be set to 1 (Ethernet).
71 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
74 * Egress TClass to be used on the egress device on the egress port.
75 * The MSB is specified in the 'ctclass3' field.
76 * Range is 0-15, where 15 is the highest priority.
78 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
81 * Switch partition ID.
83 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
86 * Destination local port for unicast packets.
87 * Destination multicast ID for multicast packets.
89 * Control packets are directed to a specific egress port, while data
90 * packets are transmitted through the CPU port (0) into the switch partition,
91 * where forwarding rules are applied.
93 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
96 * See field 'etclass'.
98 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
101 * RDQ for control packets sent to remote CPU.
102 * Must be set to 0x1F for EMADs, otherwise 0.
104 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
107 * Signature control for packets going to CPU. Must be set to 0.
109 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
112 * Stacking protocl signature. Must be set to 0xE0E0.
114 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
119 MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
122 * EMAD bit. Must be set for EMADs.
124 MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
128 * 6 - Control packets
130 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
132 static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
133 const struct mlxsw_tx_info *tx_info)
135 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
136 bool is_emad = tx_info->is_emad;
138 memset(txhdr, 0, MLXSW_TXHDR_LEN);
140 /* We currently set default values for the egress tclass (QoS). */
141 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
142 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
143 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
144 mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
145 MLXSW_TXHDR_ETCLASS_5);
146 mlxsw_tx_hdr_swid_set(txhdr, 0);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
149 mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
150 MLXSW_TXHDR_RDQ_OTHER);
151 mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
152 mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
153 mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
154 mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
155 MLXSW_TXHDR_NOT_EMAD);
156 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
159 static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
162 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
163 char paos_pl[MLXSW_REG_PAOS_LEN];
165 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
166 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
167 MLXSW_PORT_ADMIN_STATUS_DOWN);
168 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
171 static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
174 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
175 char paos_pl[MLXSW_REG_PAOS_LEN];
179 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
180 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
183 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
184 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP;
188 static int __mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port,
191 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
192 char pmtu_pl[MLXSW_REG_PMTU_LEN];
196 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
197 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
200 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
205 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
206 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
209 static int mlxsw_sx_port_mtu_eth_set(struct mlxsw_sx_port *mlxsw_sx_port,
212 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
213 return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
216 static int mlxsw_sx_port_mtu_ib_set(struct mlxsw_sx_port *mlxsw_sx_port,
219 return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
222 static int mlxsw_sx_port_ib_port_set(struct mlxsw_sx_port *mlxsw_sx_port,
225 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
226 char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
229 mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sx_port->local_port);
230 mlxsw_reg_plib_ib_port_set(plib_pl, ib_port);
231 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(plib), plib_pl);
235 static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
237 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
238 char pspa_pl[MLXSW_REG_PSPA_LEN];
240 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
241 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
245 mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
247 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
248 char sspr_pl[MLXSW_REG_SSPR_LEN];
250 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
251 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
254 static int mlxsw_sx_port_module_info_get(struct mlxsw_sx *mlxsw_sx,
255 u8 local_port, u8 *p_module,
258 char pmlp_pl[MLXSW_REG_PMLP_LEN];
261 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
262 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
265 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
266 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
270 static int mlxsw_sx_port_open(struct net_device *dev)
272 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
275 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
278 netif_start_queue(dev);
282 static int mlxsw_sx_port_stop(struct net_device *dev)
284 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
286 netif_stop_queue(dev);
287 return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
290 static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
291 struct net_device *dev)
293 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
294 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
295 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
296 const struct mlxsw_tx_info tx_info = {
297 .local_port = mlxsw_sx_port->local_port,
303 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
304 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
305 dev_kfree_skb_any(skb);
309 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
311 if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
312 return NETDEV_TX_BUSY;
314 mlxsw_sx_txhdr_construct(skb, &tx_info);
315 /* TX header is consumed by HW on the way so we shouldn't count its
316 * bytes as being sent.
318 len = skb->len - MLXSW_TXHDR_LEN;
319 /* Due to a race we might fail here because of a full queue. In that
320 * unlikely case we simply drop the packet.
322 err = mlxsw_core_skb_transmit(mlxsw_sx->core, skb, &tx_info);
325 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
326 u64_stats_update_begin(&pcpu_stats->syncp);
327 pcpu_stats->tx_packets++;
328 pcpu_stats->tx_bytes += len;
329 u64_stats_update_end(&pcpu_stats->syncp);
331 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
332 dev_kfree_skb_any(skb);
337 static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
339 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
342 err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, mtu);
350 mlxsw_sx_port_get_stats64(struct net_device *dev,
351 struct rtnl_link_stats64 *stats)
353 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
354 struct mlxsw_sx_port_pcpu_stats *p;
355 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
360 for_each_possible_cpu(i) {
361 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
363 start = u64_stats_fetch_begin_irq(&p->syncp);
364 rx_packets = p->rx_packets;
365 rx_bytes = p->rx_bytes;
366 tx_packets = p->tx_packets;
367 tx_bytes = p->tx_bytes;
368 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
370 stats->rx_packets += rx_packets;
371 stats->rx_bytes += rx_bytes;
372 stats->tx_packets += tx_packets;
373 stats->tx_bytes += tx_bytes;
374 /* tx_dropped is u32, updated without syncp protection. */
375 tx_dropped += p->tx_dropped;
377 stats->tx_dropped = tx_dropped;
380 static struct devlink_port *
381 mlxsw_sx_port_get_devlink_port(struct net_device *dev)
383 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
384 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
386 return mlxsw_core_port_devlink_port_get(mlxsw_sx->core,
387 mlxsw_sx_port->local_port);
390 static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
391 .ndo_open = mlxsw_sx_port_open,
392 .ndo_stop = mlxsw_sx_port_stop,
393 .ndo_start_xmit = mlxsw_sx_port_xmit,
394 .ndo_change_mtu = mlxsw_sx_port_change_mtu,
395 .ndo_get_stats64 = mlxsw_sx_port_get_stats64,
396 .ndo_get_devlink_port = mlxsw_sx_port_get_devlink_port,
399 static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
400 struct ethtool_drvinfo *drvinfo)
402 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
403 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
405 strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
406 strlcpy(drvinfo->version, mlxsw_sx_driver_version,
407 sizeof(drvinfo->version));
408 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
410 mlxsw_sx->bus_info->fw_rev.major,
411 mlxsw_sx->bus_info->fw_rev.minor,
412 mlxsw_sx->bus_info->fw_rev.subminor);
413 strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
414 sizeof(drvinfo->bus_info));
417 struct mlxsw_sx_port_hw_stats {
418 char str[ETH_GSTRING_LEN];
419 u64 (*getter)(const char *payload);
422 static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
424 .str = "a_frames_transmitted_ok",
425 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
428 .str = "a_frames_received_ok",
429 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
432 .str = "a_frame_check_sequence_errors",
433 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
436 .str = "a_alignment_errors",
437 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
440 .str = "a_octets_transmitted_ok",
441 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
444 .str = "a_octets_received_ok",
445 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
448 .str = "a_multicast_frames_xmitted_ok",
449 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
452 .str = "a_broadcast_frames_xmitted_ok",
453 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
456 .str = "a_multicast_frames_received_ok",
457 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
460 .str = "a_broadcast_frames_received_ok",
461 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
464 .str = "a_in_range_length_errors",
465 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
468 .str = "a_out_of_range_length_field",
469 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
472 .str = "a_frame_too_long_errors",
473 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
476 .str = "a_symbol_error_during_carrier",
477 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
480 .str = "a_mac_control_frames_transmitted",
481 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
484 .str = "a_mac_control_frames_received",
485 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
488 .str = "a_unsupported_opcodes_received",
489 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
492 .str = "a_pause_mac_ctrl_frames_received",
493 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
496 .str = "a_pause_mac_ctrl_frames_xmitted",
497 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
501 #define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
503 static void mlxsw_sx_port_get_strings(struct net_device *dev,
504 u32 stringset, u8 *data)
511 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
512 memcpy(p, mlxsw_sx_port_hw_stats[i].str,
514 p += ETH_GSTRING_LEN;
520 static void mlxsw_sx_port_get_stats(struct net_device *dev,
521 struct ethtool_stats *stats, u64 *data)
523 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
524 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
525 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
529 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port,
530 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
531 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
532 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
533 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
536 static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
540 return MLXSW_SX_PORT_HW_STATS_LEN;
546 struct mlxsw_sx_port_link_mode {
553 static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
555 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
556 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
557 .supported = SUPPORTED_1000baseKX_Full,
558 .advertised = ADVERTISED_1000baseKX_Full,
562 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
563 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
564 .supported = SUPPORTED_10000baseKX4_Full,
565 .advertised = ADVERTISED_10000baseKX4_Full,
569 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
570 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
571 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
572 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
573 .supported = SUPPORTED_10000baseKR_Full,
574 .advertised = ADVERTISED_10000baseKR_Full,
578 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
579 .supported = SUPPORTED_40000baseCR4_Full,
580 .advertised = ADVERTISED_40000baseCR4_Full,
584 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
585 .supported = SUPPORTED_40000baseKR4_Full,
586 .advertised = ADVERTISED_40000baseKR4_Full,
590 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
591 .supported = SUPPORTED_40000baseSR4_Full,
592 .advertised = ADVERTISED_40000baseSR4_Full,
596 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
597 .supported = SUPPORTED_40000baseLR4_Full,
598 .advertised = ADVERTISED_40000baseLR4_Full,
602 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
603 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
604 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
608 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
609 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
610 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
614 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
615 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
616 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
621 #define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
622 #define MLXSW_SX_PORT_BASE_SPEED 10000 /* Mb/s */
624 static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
626 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
627 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
628 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
629 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
630 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
631 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
632 return SUPPORTED_FIBRE;
634 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
635 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
636 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
637 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
638 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
639 return SUPPORTED_Backplane;
643 static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
648 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
649 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
650 modes |= mlxsw_sx_port_link_mode[i].supported;
655 static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
660 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
661 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
662 modes |= mlxsw_sx_port_link_mode[i].advertised;
667 static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
668 struct ethtool_link_ksettings *cmd)
670 u32 speed = SPEED_UNKNOWN;
671 u8 duplex = DUPLEX_UNKNOWN;
677 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
678 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
679 speed = mlxsw_sx_port_link_mode[i].speed;
680 duplex = DUPLEX_FULL;
685 cmd->base.speed = speed;
686 cmd->base.duplex = duplex;
689 static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
691 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
692 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
693 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
694 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
697 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
698 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
699 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
702 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
703 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
704 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
705 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
712 mlxsw_sx_port_get_link_ksettings(struct net_device *dev,
713 struct ethtool_link_ksettings *cmd)
715 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
716 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
717 char ptys_pl[MLXSW_REG_PTYS_LEN];
721 u32 supported, advertising, lp_advertising;
724 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
725 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
727 netdev_err(dev, "Failed to get proto");
730 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap,
731 ð_proto_admin, ð_proto_oper);
733 supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
734 mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
735 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
736 advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
737 mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
738 eth_proto_oper, cmd);
740 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
741 cmd->base.port = mlxsw_sx_port_connector_port(eth_proto_oper);
742 lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
744 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
746 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
748 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
754 static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
759 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
760 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
761 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
766 static u32 mlxsw_sx_to_ptys_speed(u32 speed)
771 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
772 if (speed == mlxsw_sx_port_link_mode[i].speed)
773 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
778 static u32 mlxsw_sx_to_ptys_upper_speed(u32 upper_speed)
783 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
784 if (mlxsw_sx_port_link_mode[i].speed <= upper_speed)
785 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
791 mlxsw_sx_port_set_link_ksettings(struct net_device *dev,
792 const struct ethtool_link_ksettings *cmd)
794 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
795 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
796 char ptys_pl[MLXSW_REG_PTYS_LEN];
805 speed = cmd->base.speed;
807 ethtool_convert_link_mode_to_legacy_u32(&advertising,
808 cmd->link_modes.advertising);
810 eth_proto_new = cmd->base.autoneg == AUTONEG_ENABLE ?
811 mlxsw_sx_to_ptys_advert_link(advertising) :
812 mlxsw_sx_to_ptys_speed(speed);
814 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
815 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
817 netdev_err(dev, "Failed to get proto");
820 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin,
823 eth_proto_new = eth_proto_new & eth_proto_cap;
824 if (!eth_proto_new) {
825 netdev_err(dev, "Not supported proto admin requested");
828 if (eth_proto_new == eth_proto_admin)
831 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
832 eth_proto_new, true);
833 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
835 netdev_err(dev, "Failed to set proto admin");
839 err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
841 netdev_err(dev, "Failed to get oper status");
847 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
849 netdev_err(dev, "Failed to set admin status");
853 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
855 netdev_err(dev, "Failed to set admin status");
862 static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
863 .get_drvinfo = mlxsw_sx_port_get_drvinfo,
864 .get_link = ethtool_op_get_link,
865 .get_strings = mlxsw_sx_port_get_strings,
866 .get_ethtool_stats = mlxsw_sx_port_get_stats,
867 .get_sset_count = mlxsw_sx_port_get_sset_count,
868 .get_link_ksettings = mlxsw_sx_port_get_link_ksettings,
869 .set_link_ksettings = mlxsw_sx_port_set_link_ksettings,
872 static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
874 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
877 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
880 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
884 static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
886 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
887 struct net_device *dev = mlxsw_sx_port->dev;
888 char ppad_pl[MLXSW_REG_PPAD_LEN];
891 mlxsw_reg_ppad_pack(ppad_pl, false, 0);
892 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
895 mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
896 /* The last byte value in base mac address is guaranteed
897 * to be such it does not overflow when adding local_port
900 dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
904 static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
905 u16 vid, enum mlxsw_reg_spms_state state)
907 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
911 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
914 mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port);
915 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
916 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
921 static int mlxsw_sx_port_ib_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
922 u16 speed, u16 width)
924 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
925 char ptys_pl[MLXSW_REG_PTYS_LEN];
927 mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sx_port->local_port, speed,
929 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
933 mlxsw_sx_port_speed_by_width_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 width)
935 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
936 u32 upper_speed = MLXSW_SX_PORT_BASE_SPEED * width;
937 char ptys_pl[MLXSW_REG_PTYS_LEN];
940 eth_proto_admin = mlxsw_sx_to_ptys_upper_speed(upper_speed);
941 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
942 eth_proto_admin, true);
943 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
947 mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
948 enum mlxsw_reg_spmlr_learn_mode mode)
950 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
951 char spmlr_pl[MLXSW_REG_SPMLR_LEN];
953 mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
954 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
957 static int __mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
960 struct mlxsw_sx_port *mlxsw_sx_port;
961 struct net_device *dev;
964 dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
967 SET_NETDEV_DEV(dev, mlxsw_sx->bus_info->dev);
968 dev_net_set(dev, mlxsw_core_net(mlxsw_sx->core));
969 mlxsw_sx_port = netdev_priv(dev);
970 mlxsw_sx_port->dev = dev;
971 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
972 mlxsw_sx_port->local_port = local_port;
973 mlxsw_sx_port->mapping.module = module;
975 mlxsw_sx_port->pcpu_stats =
976 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
977 if (!mlxsw_sx_port->pcpu_stats) {
979 goto err_alloc_stats;
982 dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
983 dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
985 err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
987 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
988 mlxsw_sx_port->local_port);
989 goto err_dev_addr_get;
992 netif_carrier_off(dev);
994 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
995 NETIF_F_VLAN_CHALLENGED;
998 dev->max_mtu = ETH_MAX_MTU;
1000 /* Each packet needs to have a Tx header (metadata) on top all other
1003 dev->needed_headroom = MLXSW_TXHDR_LEN;
1005 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1007 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1008 mlxsw_sx_port->local_port);
1009 goto err_port_system_port_mapping_set;
1012 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1014 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1015 mlxsw_sx_port->local_port);
1016 goto err_port_swid_set;
1019 err = mlxsw_sx_port_speed_by_width_set(mlxsw_sx_port, width);
1021 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1022 mlxsw_sx_port->local_port);
1023 goto err_port_speed_set;
1026 err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, ETH_DATA_LEN);
1028 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1029 mlxsw_sx_port->local_port);
1030 goto err_port_mtu_set;
1033 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1035 goto err_port_admin_status_set;
1037 err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1038 MLXSW_PORT_DEFAULT_VID,
1039 MLXSW_REG_SPMS_STATE_FORWARDING);
1041 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1042 mlxsw_sx_port->local_port);
1043 goto err_port_stp_state_set;
1046 err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1047 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1049 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1050 mlxsw_sx_port->local_port);
1051 goto err_port_mac_learning_mode_set;
1054 err = register_netdev(dev);
1056 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1057 mlxsw_sx_port->local_port);
1058 goto err_register_netdev;
1061 mlxsw_core_port_eth_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1062 mlxsw_sx_port, dev);
1063 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1066 err_register_netdev:
1067 err_port_mac_learning_mode_set:
1068 err_port_stp_state_set:
1069 err_port_admin_status_set:
1072 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1074 err_port_system_port_mapping_set:
1076 free_percpu(mlxsw_sx_port->pcpu_stats);
1082 static int mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1083 u8 module, u8 width)
1087 err = mlxsw_core_port_init(mlxsw_sx->core, local_port,
1088 module + 1, false, 0, false, 0,
1089 mlxsw_sx->hw_id, sizeof(mlxsw_sx->hw_id));
1091 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to init core port\n",
1095 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module, width);
1097 goto err_port_create;
1102 mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1106 static void __mlxsw_sx_port_eth_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1108 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1110 mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1111 unregister_netdev(mlxsw_sx_port->dev); /* This calls ndo_stop */
1112 mlxsw_sx->ports[local_port] = NULL;
1113 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1114 free_percpu(mlxsw_sx_port->pcpu_stats);
1115 free_netdev(mlxsw_sx_port->dev);
1118 static bool mlxsw_sx_port_created(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1120 return mlxsw_sx->ports[local_port] != NULL;
1123 static int __mlxsw_sx_port_ib_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1124 u8 module, u8 width)
1126 struct mlxsw_sx_port *mlxsw_sx_port;
1129 mlxsw_sx_port = kzalloc(sizeof(*mlxsw_sx_port), GFP_KERNEL);
1132 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
1133 mlxsw_sx_port->local_port = local_port;
1134 mlxsw_sx_port->mapping.module = module;
1136 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1138 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1139 mlxsw_sx_port->local_port);
1140 goto err_port_system_port_mapping_set;
1143 /* Adding port to Infiniband swid (1) */
1144 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 1);
1146 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1147 mlxsw_sx_port->local_port);
1148 goto err_port_swid_set;
1151 /* Expose the IB port number as it's front panel name */
1152 err = mlxsw_sx_port_ib_port_set(mlxsw_sx_port, module + 1);
1154 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set IB port\n",
1155 mlxsw_sx_port->local_port);
1156 goto err_port_ib_set;
1159 /* Supports all speeds from SDR to FDR (bitmask) and support bus width
1160 * of 1x, 2x and 4x (3 bits bitmask)
1162 err = mlxsw_sx_port_ib_speed_set(mlxsw_sx_port,
1163 MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
1166 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1167 mlxsw_sx_port->local_port);
1168 goto err_port_speed_set;
1171 /* Change to the maximum MTU the device supports, the SMA will take
1172 * care of the active MTU
1174 err = mlxsw_sx_port_mtu_ib_set(mlxsw_sx_port, MLXSW_IB_DEFAULT_MTU);
1176 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1177 mlxsw_sx_port->local_port);
1178 goto err_port_mtu_set;
1181 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
1183 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
1184 mlxsw_sx_port->local_port);
1185 goto err_port_admin_set;
1188 mlxsw_core_port_ib_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1190 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1197 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1199 err_port_system_port_mapping_set:
1200 kfree(mlxsw_sx_port);
1204 static void __mlxsw_sx_port_ib_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1206 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1208 mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1209 mlxsw_sx->ports[local_port] = NULL;
1210 mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1211 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1212 kfree(mlxsw_sx_port);
1215 static void __mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1217 enum devlink_port_type port_type =
1218 mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1220 if (port_type == DEVLINK_PORT_TYPE_ETH)
1221 __mlxsw_sx_port_eth_remove(mlxsw_sx, local_port);
1222 else if (port_type == DEVLINK_PORT_TYPE_IB)
1223 __mlxsw_sx_port_ib_remove(mlxsw_sx, local_port);
1226 static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1228 __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1229 mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1232 static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1236 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sx->core); i++)
1237 if (mlxsw_sx_port_created(mlxsw_sx, i))
1238 mlxsw_sx_port_remove(mlxsw_sx, i);
1239 kfree(mlxsw_sx->ports);
1240 mlxsw_sx->ports = NULL;
1243 static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1245 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sx->core);
1251 alloc_size = sizeof(struct mlxsw_sx_port *) * max_ports;
1252 mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1253 if (!mlxsw_sx->ports)
1256 for (i = 1; i < max_ports; i++) {
1257 err = mlxsw_sx_port_module_info_get(mlxsw_sx, i, &module,
1260 goto err_port_module_info_get;
1263 err = mlxsw_sx_port_eth_create(mlxsw_sx, i, module, width);
1265 goto err_port_create;
1270 err_port_module_info_get:
1271 for (i--; i >= 1; i--)
1272 if (mlxsw_sx_port_created(mlxsw_sx, i))
1273 mlxsw_sx_port_remove(mlxsw_sx, i);
1274 kfree(mlxsw_sx->ports);
1275 mlxsw_sx->ports = NULL;
1279 static void mlxsw_sx_pude_eth_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1280 enum mlxsw_reg_pude_oper_status status)
1282 if (status == MLXSW_PORT_OPER_STATUS_UP) {
1283 netdev_info(mlxsw_sx_port->dev, "link up\n");
1284 netif_carrier_on(mlxsw_sx_port->dev);
1286 netdev_info(mlxsw_sx_port->dev, "link down\n");
1287 netif_carrier_off(mlxsw_sx_port->dev);
1291 static void mlxsw_sx_pude_ib_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1292 enum mlxsw_reg_pude_oper_status status)
1294 if (status == MLXSW_PORT_OPER_STATUS_UP)
1295 pr_info("ib link for port %d - up\n",
1296 mlxsw_sx_port->mapping.module + 1);
1298 pr_info("ib link for port %d - down\n",
1299 mlxsw_sx_port->mapping.module + 1);
1302 static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1303 char *pude_pl, void *priv)
1305 struct mlxsw_sx *mlxsw_sx = priv;
1306 struct mlxsw_sx_port *mlxsw_sx_port;
1307 enum mlxsw_reg_pude_oper_status status;
1308 enum devlink_port_type port_type;
1311 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1312 mlxsw_sx_port = mlxsw_sx->ports[local_port];
1313 if (!mlxsw_sx_port) {
1314 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1319 status = mlxsw_reg_pude_oper_status_get(pude_pl);
1320 port_type = mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1321 if (port_type == DEVLINK_PORT_TYPE_ETH)
1322 mlxsw_sx_pude_eth_event_func(mlxsw_sx_port, status);
1323 else if (port_type == DEVLINK_PORT_TYPE_IB)
1324 mlxsw_sx_pude_ib_event_func(mlxsw_sx_port, status);
1327 static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1330 struct mlxsw_sx *mlxsw_sx = priv;
1331 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1332 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1334 if (unlikely(!mlxsw_sx_port)) {
1335 dev_warn_ratelimited(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1340 skb->dev = mlxsw_sx_port->dev;
1342 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1343 u64_stats_update_begin(&pcpu_stats->syncp);
1344 pcpu_stats->rx_packets++;
1345 pcpu_stats->rx_bytes += skb->len;
1346 u64_stats_update_end(&pcpu_stats->syncp);
1348 skb->protocol = eth_type_trans(skb, skb->dev);
1349 netif_receive_skb(skb);
1352 static int mlxsw_sx_port_type_set(struct mlxsw_core *mlxsw_core, u8 local_port,
1353 enum devlink_port_type new_type)
1355 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1359 if (!mlxsw_sx->ports || !mlxsw_sx->ports[local_port]) {
1360 dev_err(mlxsw_sx->bus_info->dev, "Port number \"%d\" does not exist\n",
1365 if (new_type == DEVLINK_PORT_TYPE_AUTO)
1368 __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1369 err = mlxsw_sx_port_module_info_get(mlxsw_sx, local_port, &module,
1372 goto err_port_module_info_get;
1374 if (new_type == DEVLINK_PORT_TYPE_ETH)
1375 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module,
1377 else if (new_type == DEVLINK_PORT_TYPE_IB)
1378 err = __mlxsw_sx_port_ib_create(mlxsw_sx, local_port, module,
1381 err_port_module_info_get:
1386 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX = 1,
1387 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL = 2,
1390 #define MLXSW_SX_RXL(_trap_id) \
1391 MLXSW_RXL(mlxsw_sx_rx_listener_func, _trap_id, TRAP_TO_CPU, \
1392 false, SX2_RX, FORWARD)
1394 static const struct mlxsw_listener mlxsw_sx_listener[] = {
1395 MLXSW_EVENTL(mlxsw_sx_pude_event_func, PUDE, EMAD),
1396 MLXSW_SX_RXL(FDB_MC),
1399 MLXSW_SX_RXL(EAPOL),
1403 MLXSW_SX_RXL(RPVST),
1405 MLXSW_SX_RXL(IGMP_QUERY),
1406 MLXSW_SX_RXL(IGMP_V1_REPORT),
1407 MLXSW_SX_RXL(IGMP_V2_REPORT),
1408 MLXSW_SX_RXL(IGMP_V2_LEAVE),
1409 MLXSW_SX_RXL(IGMP_V3_REPORT),
1412 static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1414 char htgt_pl[MLXSW_REG_HTGT_LEN];
1418 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
1419 MLXSW_REG_HTGT_INVALID_POLICER,
1420 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1421 MLXSW_REG_HTGT_DEFAULT_TC);
1422 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1423 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX);
1425 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1429 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
1430 MLXSW_REG_HTGT_INVALID_POLICER,
1431 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1432 MLXSW_REG_HTGT_DEFAULT_TC);
1433 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1434 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL);
1436 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1440 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1441 err = mlxsw_core_trap_register(mlxsw_sx->core,
1442 &mlxsw_sx_listener[i],
1445 goto err_listener_register;
1450 err_listener_register:
1451 for (i--; i >= 0; i--) {
1452 mlxsw_core_trap_unregister(mlxsw_sx->core,
1453 &mlxsw_sx_listener[i],
1459 static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1463 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1464 mlxsw_core_trap_unregister(mlxsw_sx->core,
1465 &mlxsw_sx_listener[i],
1470 static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1472 char sfgc_pl[MLXSW_REG_SFGC_LEN];
1473 char sgcr_pl[MLXSW_REG_SGCR_LEN];
1477 /* Configure a flooding table, which includes only CPU port. */
1478 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1481 mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0,
1482 MLXSW_PORT_CPU_PORT, true);
1483 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1488 /* Flood different packet types using the flooding table. */
1489 mlxsw_reg_sfgc_pack(sfgc_pl,
1490 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1491 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1492 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1494 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1498 mlxsw_reg_sfgc_pack(sfgc_pl,
1499 MLXSW_REG_SFGC_TYPE_BROADCAST,
1500 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1501 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1503 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1507 mlxsw_reg_sfgc_pack(sfgc_pl,
1508 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1509 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1510 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1512 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1516 mlxsw_reg_sfgc_pack(sfgc_pl,
1517 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1518 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1519 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1521 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1525 mlxsw_reg_sfgc_pack(sfgc_pl,
1526 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1527 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1528 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1530 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1534 mlxsw_reg_sgcr_pack(sgcr_pl, true);
1535 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1538 static int mlxsw_sx_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
1540 char htgt_pl[MLXSW_REG_HTGT_LEN];
1542 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
1543 MLXSW_REG_HTGT_INVALID_POLICER,
1544 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1545 MLXSW_REG_HTGT_DEFAULT_TC);
1546 mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
1547 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1548 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD);
1549 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
1552 static int mlxsw_sx_init(struct mlxsw_core *mlxsw_core,
1553 const struct mlxsw_bus_info *mlxsw_bus_info,
1554 struct netlink_ext_ack *extack)
1556 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1559 mlxsw_sx->core = mlxsw_core;
1560 mlxsw_sx->bus_info = mlxsw_bus_info;
1562 err = mlxsw_sx_hw_id_get(mlxsw_sx);
1564 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1568 err = mlxsw_sx_ports_create(mlxsw_sx);
1570 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1574 err = mlxsw_sx_traps_init(mlxsw_sx);
1576 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps\n");
1577 goto err_listener_register;
1580 err = mlxsw_sx_flood_init(mlxsw_sx);
1582 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1583 goto err_flood_init;
1589 mlxsw_sx_traps_fini(mlxsw_sx);
1590 err_listener_register:
1591 mlxsw_sx_ports_remove(mlxsw_sx);
1595 static void mlxsw_sx_fini(struct mlxsw_core *mlxsw_core)
1597 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1599 mlxsw_sx_traps_fini(mlxsw_sx);
1600 mlxsw_sx_ports_remove(mlxsw_sx);
1603 static const struct mlxsw_config_profile mlxsw_sx_config_profile = {
1604 .used_max_vepa_channels = 1,
1605 .max_vepa_channels = 0,
1610 .used_max_system_port = 1,
1611 .max_system_port = 48000,
1612 .used_max_vlan_groups = 1,
1613 .max_vlan_groups = 127,
1614 .used_max_regions = 1,
1616 .used_flood_tables = 1,
1617 .max_flood_tables = 2,
1618 .max_vid_flood_tables = 1,
1619 .used_flood_mode = 1,
1621 .used_max_ib_mc = 1,
1628 .type = MLXSW_PORT_SWID_TYPE_ETH,
1632 .type = MLXSW_PORT_SWID_TYPE_IB,
1637 static struct mlxsw_driver mlxsw_sx_driver = {
1638 .kind = mlxsw_sx_driver_name,
1639 .priv_size = sizeof(struct mlxsw_sx),
1640 .init = mlxsw_sx_init,
1641 .fini = mlxsw_sx_fini,
1642 .basic_trap_groups_set = mlxsw_sx_basic_trap_groups_set,
1643 .txhdr_construct = mlxsw_sx_txhdr_construct,
1644 .txhdr_len = MLXSW_TXHDR_LEN,
1645 .profile = &mlxsw_sx_config_profile,
1646 .port_type_set = mlxsw_sx_port_type_set,
1649 static const struct pci_device_id mlxsw_sx_pci_id_table[] = {
1650 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
1654 static struct pci_driver mlxsw_sx_pci_driver = {
1655 .name = mlxsw_sx_driver_name,
1656 .id_table = mlxsw_sx_pci_id_table,
1659 static int __init mlxsw_sx_module_init(void)
1663 err = mlxsw_core_driver_register(&mlxsw_sx_driver);
1667 err = mlxsw_pci_driver_register(&mlxsw_sx_pci_driver);
1669 goto err_pci_driver_register;
1673 err_pci_driver_register:
1674 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1678 static void __exit mlxsw_sx_module_exit(void)
1680 mlxsw_pci_driver_unregister(&mlxsw_sx_pci_driver);
1681 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1684 module_init(mlxsw_sx_module_init);
1685 module_exit(mlxsw_sx_module_exit);
1687 MODULE_LICENSE("Dual BSD/GPL");
1688 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1689 MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1690 MODULE_DEVICE_TABLE(pci, mlxsw_sx_pci_id_table);