drivers/net/ethernet/mellanox/mlxsw/switchx2.c

   1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/types.h>
   7 #include <linux/pci.h>
   8 #include <linux/netdevice.h>
   9 #include <linux/etherdevice.h>
  10 #include <linux/slab.h>
  11 #include <linux/device.h>
  12 #include <linux/skbuff.h>
  13 #include <linux/if_vlan.h>
  14
  15 #include "pci.h"
  16 #include "core.h"
  17 #include "reg.h"
  18 #include "port.h"
  19 #include "trap.h"
  20 #include "txheader.h"
  21 #include "ib.h"
  22
  23 static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
  24 static const char mlxsw_sx_driver_version[] = "1.0";
  25
  26 struct mlxsw_sx_port;
  27
  28 struct mlxsw_sx {
  29         struct mlxsw_sx_port **ports;
  30         struct mlxsw_core *core;
  31         const struct mlxsw_bus_info *bus_info;
  32         u8 hw_id[ETH_ALEN];
  33 };
  34
  35 struct mlxsw_sx_port_pcpu_stats {
  36         u64                     rx_packets;
  37         u64                     rx_bytes;
  38         u64                     tx_packets;
  39         u64                     tx_bytes;
  40         struct u64_stats_sync   syncp;
  41         u32                     tx_dropped;
  42 };
  43
  44 struct mlxsw_sx_port {
  45         struct net_device *dev;
  46         struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
  47         struct mlxsw_sx *mlxsw_sx;
  48         u8 local_port;
  49         struct {
  50                 u8 module;
  51         } mapping;
  52 };
  53
  54 /* tx_hdr_version
  55  * Tx header version.
  56  * Must be set to 0.
  57  */
  58 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
  59
  60 /* tx_hdr_ctl
  61  * Packet control type.
  62  * 0 - Ethernet control (e.g. EMADs, LACP)
  63  * 1 - Ethernet data
  64  */
  65 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
  66
  67 /* tx_hdr_proto
  68  * Packet protocol type. Must be set to 1 (Ethernet).
  69  */
  70 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
  71
  72 /* tx_hdr_etclass
  73  * Egress TClass to be used on the egress device on the egress port.
  74  * The MSB is specified in the 'ctclass3' field.
  75  * Range is 0-15, where 15 is the highest priority.
  76  */
  77 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
  78
  79 /* tx_hdr_swid
  80  * Switch partition ID.
  81  */
  82 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
  83
  84 /* tx_hdr_port_mid
  85  * Destination local port for unicast packets.
  86  * Destination multicast ID for multicast packets.
  87  *
  88  * Control packets are directed to a specific egress port, while data
  89  * packets are transmitted through the CPU port (0) into the switch partition,
  90  * where forwarding rules are applied.
  91  */
  92 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
  93
  94 /* tx_hdr_ctclass3
  95  * See field 'etclass'.
  96  */
  97 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
  98
  99 /* tx_hdr_rdq
 100  * RDQ for control packets sent to remote CPU.
 101  * Must be set to 0x1F for EMADs, otherwise 0.
 102  */
 103 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
 104
 105 /* tx_hdr_cpu_sig
 106  * Signature control for packets going to CPU. Must be set to 0.
 107  */
 108 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
 109
 110 /* tx_hdr_sig
 111  * Stacking protocl signature. Must be set to 0xE0E0.
 112  */
 113 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
 114
 115 /* tx_hdr_stclass
 116  * Stacking TClass.
 117  */
 118 MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
 119
 120 /* tx_hdr_emad
 121  * EMAD bit. Must be set for EMADs.
 122  */
 123 MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
 124
 125 /* tx_hdr_type
 126  * 0 - Data packets
 127  * 6 - Control packets
 128  */
 129 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
 130
 131 static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
 132                                      const struct mlxsw_tx_info *tx_info)
 133 {
 134         char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
 135         bool is_emad = tx_info->is_emad;
 136
 137         memset(txhdr, 0, MLXSW_TXHDR_LEN);
 138
 139         /* We currently set default values for the egress tclass (QoS). */
 140         mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
 141         mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
 142         mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
 143         mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
 144                                                   MLXSW_TXHDR_ETCLASS_5);
 145         mlxsw_tx_hdr_swid_set(txhdr, 0);
 146         mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
 147         mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
 148         mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
 149                                               MLXSW_TXHDR_RDQ_OTHER);
 150         mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
 151         mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
 152         mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
 153         mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
 154                                                MLXSW_TXHDR_NOT_EMAD);
 155         mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
 156 }
 157
 158 static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
 159                                           bool is_up)
 160 {
 161         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 162         char paos_pl[MLXSW_REG_PAOS_LEN];
 163
 164         mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
 165                             is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
 166                             MLXSW_PORT_ADMIN_STATUS_DOWN);
 167         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
 168 }
 169
 170 static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
 171                                          bool *p_is_up)
 172 {
 173         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 174         char paos_pl[MLXSW_REG_PAOS_LEN];
 175         u8 oper_status;
 176         int err;
 177
 178         mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
 179         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
 180         if (err)
 181                 return err;
 182         oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
 183         *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
 184         return 0;
 185 }
 186
 187 static int __mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port,
 188                                    u16 mtu)
 189 {
 190         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 191         char pmtu_pl[MLXSW_REG_PMTU_LEN];
 192         int max_mtu;
 193         int err;
 194
 195         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
 196         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
 197         if (err)
 198                 return err;
 199         max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
 200
 201         if (mtu > max_mtu)
 202                 return -EINVAL;
 203
 204         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
 205         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
 206 }
 207
 208 static int mlxsw_sx_port_mtu_eth_set(struct mlxsw_sx_port *mlxsw_sx_port,
 209                                      u16 mtu)
 210 {
 211         mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
 212         return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
 213 }
 214
 215 static int mlxsw_sx_port_mtu_ib_set(struct mlxsw_sx_port *mlxsw_sx_port,
 216                                     u16 mtu)
 217 {
 218         return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
 219 }
 220
 221 static int mlxsw_sx_port_ib_port_set(struct mlxsw_sx_port *mlxsw_sx_port,
 222                                      u8 ib_port)
 223 {
 224         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 225         char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
 226         int err;
 227
 228         mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sx_port->local_port);
 229         mlxsw_reg_plib_ib_port_set(plib_pl, ib_port);
 230         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(plib), plib_pl);
 231         return err;
 232 }
 233
 234 static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
 235 {
 236         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 237         char pspa_pl[MLXSW_REG_PSPA_LEN];
 238
 239         mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
 240         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
 241 }
 242
 243 static int
 244 mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
 245 {
 246         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 247         char sspr_pl[MLXSW_REG_SSPR_LEN];
 248
 249         mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
 250         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
 251 }
 252
 253 static int mlxsw_sx_port_module_info_get(struct mlxsw_sx *mlxsw_sx,
 254                                          u8 local_port, u8 *p_module,
 255                                          u8 *p_width)
 256 {
 257         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 258         int err;
 259
 260         mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
 261         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
 262         if (err)
 263                 return err;
 264         *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
 265         *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
 266         return 0;
 267 }
 268
 269 static int mlxsw_sx_port_open(struct net_device *dev)
 270 {
 271         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 272         int err;
 273
 274         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
 275         if (err)
 276                 return err;
 277         netif_start_queue(dev);
 278         return 0;
 279 }
 280
 281 static int mlxsw_sx_port_stop(struct net_device *dev)
 282 {
 283         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 284
 285         netif_stop_queue(dev);
 286         return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
 287 }
 288
 289 static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
 290                                       struct net_device *dev)
 291 {
 292         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 293         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 294         struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
 295         const struct mlxsw_tx_info tx_info = {
 296                 .local_port = mlxsw_sx_port->local_port,
 297                 .is_emad = false,
 298         };
 299         u64 len;
 300         int err;
 301
 302         memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
 303
 304         if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
 305                 return NETDEV_TX_BUSY;
 306
 307         if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
 308                 struct sk_buff *skb_orig = skb;
 309
 310                 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
 311                 if (!skb) {
 312                         this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
 313                         dev_kfree_skb_any(skb_orig);
 314                         return NETDEV_TX_OK;
 315                 }
 316                 dev_consume_skb_any(skb_orig);
 317         }
 318         mlxsw_sx_txhdr_construct(skb, &tx_info);
 319         /* TX header is consumed by HW on the way so we shouldn't count its
 320          * bytes as being sent.
 321          */
 322         len = skb->len - MLXSW_TXHDR_LEN;
 323         /* Due to a race we might fail here because of a full queue. In that
 324          * unlikely case we simply drop the packet.
 325          */
 326         err = mlxsw_core_skb_transmit(mlxsw_sx->core, skb, &tx_info);
 327
 328         if (!err) {
 329                 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
 330                 u64_stats_update_begin(&pcpu_stats->syncp);
 331                 pcpu_stats->tx_packets++;
 332                 pcpu_stats->tx_bytes += len;
 333                 u64_stats_update_end(&pcpu_stats->syncp);
 334         } else {
 335                 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
 336                 dev_kfree_skb_any(skb);
 337         }
 338         return NETDEV_TX_OK;
 339 }
 340
 341 static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
 342 {
 343         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 344         int err;
 345
 346         err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, mtu);
 347         if (err)
 348                 return err;
 349         dev->mtu = mtu;
 350         return 0;
 351 }
 352
 353 static void
 354 mlxsw_sx_port_get_stats64(struct net_device *dev,
 355                           struct rtnl_link_stats64 *stats)
 356 {
 357         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 358         struct mlxsw_sx_port_pcpu_stats *p;
 359         u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
 360         u32 tx_dropped = 0;
 361         unsigned int start;
 362         int i;
 363
 364         for_each_possible_cpu(i) {
 365                 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
 366                 do {
 367                         start = u64_stats_fetch_begin_irq(&p->syncp);
 368                         rx_packets      = p->rx_packets;
 369                         rx_bytes        = p->rx_bytes;
 370                         tx_packets      = p->tx_packets;
 371                         tx_bytes        = p->tx_bytes;
 372                 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
 373
 374                 stats->rx_packets       += rx_packets;
 375                 stats->rx_bytes         += rx_bytes;
 376                 stats->tx_packets       += tx_packets;
 377                 stats->tx_bytes         += tx_bytes;
 378                 /* tx_dropped is u32, updated without syncp protection. */
 379                 tx_dropped      += p->tx_dropped;
 380         }
 381         stats->tx_dropped       = tx_dropped;
 382 }
 383
 384 static struct devlink_port *
 385 mlxsw_sx_port_get_devlink_port(struct net_device *dev)
 386 {
 387         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 388         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 389
 390         return mlxsw_core_port_devlink_port_get(mlxsw_sx->core,
 391                                                 mlxsw_sx_port->local_port);
 392 }
 393
 394 static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
 395         .ndo_open               = mlxsw_sx_port_open,
 396         .ndo_stop               = mlxsw_sx_port_stop,
 397         .ndo_start_xmit         = mlxsw_sx_port_xmit,
 398         .ndo_change_mtu         = mlxsw_sx_port_change_mtu,
 399         .ndo_get_stats64        = mlxsw_sx_port_get_stats64,
 400         .ndo_get_devlink_port   = mlxsw_sx_port_get_devlink_port,
 401 };
 402
 403 static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
 404                                       struct ethtool_drvinfo *drvinfo)
 405 {
 406         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 407         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 408
 409         strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
 410         strlcpy(drvinfo->version, mlxsw_sx_driver_version,
 411                 sizeof(drvinfo->version));
 412         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
 413                  "%d.%d.%d",
 414                  mlxsw_sx->bus_info->fw_rev.major,
 415                  mlxsw_sx->bus_info->fw_rev.minor,
 416                  mlxsw_sx->bus_info->fw_rev.subminor);
 417         strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
 418                 sizeof(drvinfo->bus_info));
 419 }
 420
 421 struct mlxsw_sx_port_hw_stats {
 422         char str[ETH_GSTRING_LEN];
 423         u64 (*getter)(const char *payload);
 424 };
 425
 426 static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
 427         {
 428                 .str = "a_frames_transmitted_ok",
 429                 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
 430         },
 431         {
 432                 .str = "a_frames_received_ok",
 433                 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
 434         },
 435         {
 436                 .str = "a_frame_check_sequence_errors",
 437                 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
 438         },
 439         {
 440                 .str = "a_alignment_errors",
 441                 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
 442         },
 443         {
 444                 .str = "a_octets_transmitted_ok",
 445                 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
 446         },
 447         {
 448                 .str = "a_octets_received_ok",
 449                 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
 450         },
 451         {
 452                 .str = "a_multicast_frames_xmitted_ok",
 453                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
 454         },
 455         {
 456                 .str = "a_broadcast_frames_xmitted_ok",
 457                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
 458         },
 459         {
 460                 .str = "a_multicast_frames_received_ok",
 461                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
 462         },
 463         {
 464                 .str = "a_broadcast_frames_received_ok",
 465                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
 466         },
 467         {
 468                 .str = "a_in_range_length_errors",
 469                 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
 470         },
 471         {
 472                 .str = "a_out_of_range_length_field",
 473                 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
 474         },
 475         {
 476                 .str = "a_frame_too_long_errors",
 477                 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
 478         },
 479         {
 480                 .str = "a_symbol_error_during_carrier",
 481                 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
 482         },
 483         {
 484                 .str = "a_mac_control_frames_transmitted",
 485                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
 486         },
 487         {
 488                 .str = "a_mac_control_frames_received",
 489                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
 490         },
 491         {
 492                 .str = "a_unsupported_opcodes_received",
 493                 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
 494         },
 495         {
 496                 .str = "a_pause_mac_ctrl_frames_received",
 497                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
 498         },
 499         {
 500                 .str = "a_pause_mac_ctrl_frames_xmitted",
 501                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
 502         },
 503 };
 504
 505 #define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
 506
 507 static void mlxsw_sx_port_get_strings(struct net_device *dev,
 508                                       u32 stringset, u8 *data)
 509 {
 510         u8 *p = data;
 511         int i;
 512
 513         switch (stringset) {
 514         case ETH_SS_STATS:
 515                 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
 516                         memcpy(p, mlxsw_sx_port_hw_stats[i].str,
 517                                ETH_GSTRING_LEN);
 518                         p += ETH_GSTRING_LEN;
 519                 }
 520                 break;
 521         }
 522 }
 523
 524 static void mlxsw_sx_port_get_stats(struct net_device *dev,
 525                                     struct ethtool_stats *stats, u64 *data)
 526 {
 527         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 528         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 529         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
 530         int i;
 531         int err;
 532
 533         mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port,
 534                              MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
 535         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
 536         for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
 537                 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
 538 }
 539
 540 static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
 541 {
 542         switch (sset) {
 543         case ETH_SS_STATS:
 544                 return MLXSW_SX_PORT_HW_STATS_LEN;
 545         default:
 546                 return -EOPNOTSUPP;
 547         }
 548 }
 549
 550 struct mlxsw_sx_port_link_mode {
 551         u32 mask;
 552         u32 supported;
 553         u32 advertised;
 554         u32 speed;
 555 };
 556
 557 static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
 558         {
 559                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
 560                 .supported      = SUPPORTED_100baseT_Full,
 561                 .advertised     = ADVERTISED_100baseT_Full,
 562                 .speed          = 100,
 563         },
 564         {
 565                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
 566                 .speed          = 100,
 567         },
 568         {
 569                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
 570                                   MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
 571                 .supported      = SUPPORTED_1000baseKX_Full,
 572                 .advertised     = ADVERTISED_1000baseKX_Full,
 573                 .speed          = 1000,
 574         },
 575         {
 576                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
 577                 .supported      = SUPPORTED_10000baseT_Full,
 578                 .advertised     = ADVERTISED_10000baseT_Full,
 579                 .speed          = 10000,
 580         },
 581         {
 582                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
 583                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
 584                 .supported      = SUPPORTED_10000baseKX4_Full,
 585                 .advertised     = ADVERTISED_10000baseKX4_Full,
 586                 .speed          = 10000,
 587         },
 588         {
 589                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
 590                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
 591                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
 592                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
 593                 .supported      = SUPPORTED_10000baseKR_Full,
 594                 .advertised     = ADVERTISED_10000baseKR_Full,
 595                 .speed          = 10000,
 596         },
 597         {
 598                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
 599                 .supported      = SUPPORTED_20000baseKR2_Full,
 600                 .advertised     = ADVERTISED_20000baseKR2_Full,
 601                 .speed          = 20000,
 602         },
 603         {
 604                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
 605                 .supported      = SUPPORTED_40000baseCR4_Full,
 606                 .advertised     = ADVERTISED_40000baseCR4_Full,
 607                 .speed          = 40000,
 608         },
 609         {
 610                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
 611                 .supported      = SUPPORTED_40000baseKR4_Full,
 612                 .advertised     = ADVERTISED_40000baseKR4_Full,
 613                 .speed          = 40000,
 614         },
 615         {
 616                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
 617                 .supported      = SUPPORTED_40000baseSR4_Full,
 618                 .advertised     = ADVERTISED_40000baseSR4_Full,
 619                 .speed          = 40000,
 620         },
 621         {
 622                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
 623                 .supported      = SUPPORTED_40000baseLR4_Full,
 624                 .advertised     = ADVERTISED_40000baseLR4_Full,
 625                 .speed          = 40000,
 626         },
 627         {
 628                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
 629                                   MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
 630                                   MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
 631                 .speed          = 25000,
 632         },
 633         {
 634                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
 635                                   MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
 636                                   MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
 637                 .speed          = 50000,
 638         },
 639         {
 640                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
 641                                   MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
 642                                   MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
 643                                   MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
 644                 .speed          = 100000,
 645         },
 646 };
 647
 648 #define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
 649 #define MLXSW_SX_PORT_BASE_SPEED 10000 /* Mb/s */
 650
 651 static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
 652 {
 653         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
 654                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
 655                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
 656                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
 657                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
 658                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
 659                 return SUPPORTED_FIBRE;
 660
 661         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
 662                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
 663                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
 664                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
 665                               MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
 666                 return SUPPORTED_Backplane;
 667         return 0;
 668 }
 669
 670 static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
 671 {
 672         u32 modes = 0;
 673         int i;
 674
 675         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 676                 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
 677                         modes |= mlxsw_sx_port_link_mode[i].supported;
 678         }
 679         return modes;
 680 }
 681
 682 static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
 683 {
 684         u32 modes = 0;
 685         int i;
 686
 687         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 688                 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
 689                         modes |= mlxsw_sx_port_link_mode[i].advertised;
 690         }
 691         return modes;
 692 }
 693
 694 static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
 695                                             struct ethtool_link_ksettings *cmd)
 696 {
 697         u32 speed = SPEED_UNKNOWN;
 698         u8 duplex = DUPLEX_UNKNOWN;
 699         int i;
 700
 701         if (!carrier_ok)
 702                 goto out;
 703
 704         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 705                 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
 706                         speed = mlxsw_sx_port_link_mode[i].speed;
 707                         duplex = DUPLEX_FULL;
 708                         break;
 709                 }
 710         }
 711 out:
 712         cmd->base.speed = speed;
 713         cmd->base.duplex = duplex;
 714 }
 715
 716 static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
 717 {
 718         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
 719                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
 720                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
 721                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
 722                 return PORT_FIBRE;
 723
 724         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
 725                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
 726                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
 727                 return PORT_DA;
 728
 729         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
 730                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
 731                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
 732                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
 733                 return PORT_NONE;
 734
 735         return PORT_OTHER;
 736 }
 737
 738 static int
 739 mlxsw_sx_port_get_link_ksettings(struct net_device *dev,
 740                                  struct ethtool_link_ksettings *cmd)
 741 {
 742         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 743         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 744         char ptys_pl[MLXSW_REG_PTYS_LEN];
 745         u32 eth_proto_cap;
 746         u32 eth_proto_admin;
 747         u32 eth_proto_oper;
 748         u32 supported, advertising, lp_advertising;
 749         int err;
 750
 751         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
 752         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 753         if (err) {
 754                 netdev_err(dev, "Failed to get proto");
 755                 return err;
 756         }
 757         mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap,
 758                                   &eth_proto_admin, &eth_proto_oper);
 759
 760         supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
 761                          mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
 762                          SUPPORTED_Pause | SUPPORTED_Asym_Pause;
 763         advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
 764         mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
 765                                         eth_proto_oper, cmd);
 766
 767         eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
 768         cmd->base.port = mlxsw_sx_port_connector_port(eth_proto_oper);
 769         lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
 770
 771         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
 772                                                 supported);
 773         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
 774                                                 advertising);
 775         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
 776                                                 lp_advertising);
 777
 778         return 0;
 779 }
 780
 781 static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
 782 {
 783         u32 ptys_proto = 0;
 784         int i;
 785
 786         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 787                 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
 788                         ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
 789         }
 790         return ptys_proto;
 791 }
 792
 793 static u32 mlxsw_sx_to_ptys_speed(u32 speed)
 794 {
 795         u32 ptys_proto = 0;
 796         int i;
 797
 798         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 799                 if (speed == mlxsw_sx_port_link_mode[i].speed)
 800                         ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
 801         }
 802         return ptys_proto;
 803 }
 804
 805 static u32 mlxsw_sx_to_ptys_upper_speed(u32 upper_speed)
 806 {
 807         u32 ptys_proto = 0;
 808         int i;
 809
 810         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 811                 if (mlxsw_sx_port_link_mode[i].speed <= upper_speed)
 812                         ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
 813         }
 814         return ptys_proto;
 815 }
 816
 817 static int
 818 mlxsw_sx_port_set_link_ksettings(struct net_device *dev,
 819                                  const struct ethtool_link_ksettings *cmd)
 820 {
 821         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 822         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 823         char ptys_pl[MLXSW_REG_PTYS_LEN];
 824         u32 speed;
 825         u32 eth_proto_new;
 826         u32 eth_proto_cap;
 827         u32 eth_proto_admin;
 828         u32 advertising;
 829         bool is_up;
 830         int err;
 831
 832         speed = cmd->base.speed;
 833
 834         ethtool_convert_link_mode_to_legacy_u32(&advertising,
 835                                                 cmd->link_modes.advertising);
 836
 837         eth_proto_new = cmd->base.autoneg == AUTONEG_ENABLE ?
 838                 mlxsw_sx_to_ptys_advert_link(advertising) :
 839                 mlxsw_sx_to_ptys_speed(speed);
 840
 841         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
 842         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 843         if (err) {
 844                 netdev_err(dev, "Failed to get proto");
 845                 return err;
 846         }
 847         mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
 848                                   NULL);
 849
 850         eth_proto_new = eth_proto_new & eth_proto_cap;
 851         if (!eth_proto_new) {
 852                 netdev_err(dev, "Not supported proto admin requested");
 853                 return -EINVAL;
 854         }
 855         if (eth_proto_new == eth_proto_admin)
 856                 return 0;
 857
 858         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
 859                                 eth_proto_new, true);
 860         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 861         if (err) {
 862                 netdev_err(dev, "Failed to set proto admin");
 863                 return err;
 864         }
 865
 866         err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
 867         if (err) {
 868                 netdev_err(dev, "Failed to get oper status");
 869                 return err;
 870         }
 871         if (!is_up)
 872                 return 0;
 873
 874         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
 875         if (err) {
 876                 netdev_err(dev, "Failed to set admin status");
 877                 return err;
 878         }
 879
 880         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
 881         if (err) {
 882                 netdev_err(dev, "Failed to set admin status");
 883                 return err;
 884         }
 885
 886         return 0;
 887 }
 888
 889 static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
 890         .get_drvinfo            = mlxsw_sx_port_get_drvinfo,
 891         .get_link               = ethtool_op_get_link,
 892         .get_strings            = mlxsw_sx_port_get_strings,
 893         .get_ethtool_stats      = mlxsw_sx_port_get_stats,
 894         .get_sset_count         = mlxsw_sx_port_get_sset_count,
 895         .get_link_ksettings     = mlxsw_sx_port_get_link_ksettings,
 896         .set_link_ksettings     = mlxsw_sx_port_set_link_ksettings,
 897 };
 898
 899 static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
 900 {
 901         char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
 902         int err;
 903
 904         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
 905         if (err)
 906                 return err;
 907         mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
 908         return 0;
 909 }
 910
 911 static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
 912 {
 913         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 914         struct net_device *dev = mlxsw_sx_port->dev;
 915         char ppad_pl[MLXSW_REG_PPAD_LEN];
 916         int err;
 917
 918         mlxsw_reg_ppad_pack(ppad_pl, false, 0);
 919         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
 920         if (err)
 921                 return err;
 922         mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
 923         /* The last byte value in base mac address is guaranteed
 924          * to be such it does not overflow when adding local_port
 925          * value.
 926          */
 927         dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
 928         return 0;
 929 }
 930
 931 static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
 932                                        u16 vid, enum mlxsw_reg_spms_state state)
 933 {
 934         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 935         char *spms_pl;
 936         int err;
 937
 938         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
 939         if (!spms_pl)
 940                 return -ENOMEM;
 941         mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port);
 942         mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
 943         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
 944         kfree(spms_pl);
 945         return err;
 946 }
 947
 948 static int mlxsw_sx_port_ib_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
 949                                       u16 speed, u16 width)
 950 {
 951         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 952         char ptys_pl[MLXSW_REG_PTYS_LEN];
 953
 954         mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sx_port->local_port, speed,
 955                                width);
 956         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 957 }
 958
 959 static int
 960 mlxsw_sx_port_speed_by_width_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 width)
 961 {
 962         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 963         u32 upper_speed = MLXSW_SX_PORT_BASE_SPEED * width;
 964         char ptys_pl[MLXSW_REG_PTYS_LEN];
 965         u32 eth_proto_admin;
 966
 967         eth_proto_admin = mlxsw_sx_to_ptys_upper_speed(upper_speed);
 968         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
 969                                 eth_proto_admin, true);
 970         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 971 }
 972
 973 static int
 974 mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
 975                                     enum mlxsw_reg_spmlr_learn_mode mode)
 976 {
 977         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 978         char spmlr_pl[MLXSW_REG_SPMLR_LEN];
 979
 980         mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
 981         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
 982 }
 983
 984 static int __mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
 985                                       u8 module, u8 width)
 986 {
 987         struct mlxsw_sx_port *mlxsw_sx_port;
 988         struct net_device *dev;
 989         int err;
 990
 991         dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
 992         if (!dev)
 993                 return -ENOMEM;
 994         SET_NETDEV_DEV(dev, mlxsw_sx->bus_info->dev);
 995         dev_net_set(dev, mlxsw_core_net(mlxsw_sx->core));
 996         mlxsw_sx_port = netdev_priv(dev);
 997         mlxsw_sx_port->dev = dev;
 998         mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
 999         mlxsw_sx_port->local_port = local_port;
1000         mlxsw_sx_port->mapping.module = module;
1001
1002         mlxsw_sx_port->pcpu_stats =
1003                 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
1004         if (!mlxsw_sx_port->pcpu_stats) {
1005                 err = -ENOMEM;
1006                 goto err_alloc_stats;
1007         }
1008
1009         dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
1010         dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
1011
1012         err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
1013         if (err) {
1014                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
1015                         mlxsw_sx_port->local_port);
1016                 goto err_dev_addr_get;
1017         }
1018
1019         netif_carrier_off(dev);
1020
1021         dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1022                          NETIF_F_VLAN_CHALLENGED;
1023
1024         dev->min_mtu = 0;
1025         dev->max_mtu = ETH_MAX_MTU;
1026
1027         /* Each packet needs to have a Tx header (metadata) on top all other
1028          * headers.
1029          */
1030         dev->needed_headroom = MLXSW_TXHDR_LEN;
1031
1032         err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1033         if (err) {
1034                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1035                         mlxsw_sx_port->local_port);
1036                 goto err_port_system_port_mapping_set;
1037         }
1038
1039         err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1040         if (err) {
1041                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1042                         mlxsw_sx_port->local_port);
1043                 goto err_port_swid_set;
1044         }
1045
1046         err = mlxsw_sx_port_speed_by_width_set(mlxsw_sx_port, width);
1047         if (err) {
1048                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1049                         mlxsw_sx_port->local_port);
1050                 goto err_port_speed_set;
1051         }
1052
1053         err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, ETH_DATA_LEN);
1054         if (err) {
1055                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1056                         mlxsw_sx_port->local_port);
1057                 goto err_port_mtu_set;
1058         }
1059
1060         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1061         if (err)
1062                 goto err_port_admin_status_set;
1063
1064         err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1065                                           MLXSW_PORT_DEFAULT_VID,
1066                                           MLXSW_REG_SPMS_STATE_FORWARDING);
1067         if (err) {
1068                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1069                         mlxsw_sx_port->local_port);
1070                 goto err_port_stp_state_set;
1071         }
1072
1073         err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1074                                                   MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1075         if (err) {
1076                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1077                         mlxsw_sx_port->local_port);
1078                 goto err_port_mac_learning_mode_set;
1079         }
1080
1081         err = register_netdev(dev);
1082         if (err) {
1083                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1084                         mlxsw_sx_port->local_port);
1085                 goto err_register_netdev;
1086         }
1087
1088         mlxsw_core_port_eth_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1089                                 mlxsw_sx_port, dev);
1090         mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1091         return 0;
1092
1093 err_register_netdev:
1094 err_port_mac_learning_mode_set:
1095 err_port_stp_state_set:
1096 err_port_admin_status_set:
1097 err_port_mtu_set:
1098 err_port_speed_set:
1099         mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1100 err_port_swid_set:
1101 err_port_system_port_mapping_set:
1102 err_dev_addr_get:
1103         free_percpu(mlxsw_sx_port->pcpu_stats);
1104 err_alloc_stats:
1105         free_netdev(dev);
1106         return err;
1107 }
1108
1109 static int mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1110                                     u8 module, u8 width)
1111 {
1112         int err;
1113
1114         err = mlxsw_core_port_init(mlxsw_sx->core, local_port,
1115                                    module + 1, false, 0,
1116                                    mlxsw_sx->hw_id, sizeof(mlxsw_sx->hw_id));
1117         if (err) {
1118                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to init core port\n",
1119                         local_port);
1120                 return err;
1121         }
1122         err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module, width);
1123         if (err)
1124                 goto err_port_create;
1125
1126         return 0;
1127
1128 err_port_create:
1129         mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1130         return err;
1131 }
1132
1133 static void __mlxsw_sx_port_eth_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1134 {
1135         struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1136
1137         mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1138         unregister_netdev(mlxsw_sx_port->dev); /* This calls ndo_stop */
1139         mlxsw_sx->ports[local_port] = NULL;
1140         mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1141         free_percpu(mlxsw_sx_port->pcpu_stats);
1142         free_netdev(mlxsw_sx_port->dev);
1143 }
1144
1145 static bool mlxsw_sx_port_created(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1146 {
1147         return mlxsw_sx->ports[local_port] != NULL;
1148 }
1149
1150 static int __mlxsw_sx_port_ib_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1151                                      u8 module, u8 width)
1152 {
1153         struct mlxsw_sx_port *mlxsw_sx_port;
1154         int err;
1155
1156         mlxsw_sx_port = kzalloc(sizeof(*mlxsw_sx_port), GFP_KERNEL);
1157         if (!mlxsw_sx_port)
1158                 return -ENOMEM;
1159         mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
1160         mlxsw_sx_port->local_port = local_port;
1161         mlxsw_sx_port->mapping.module = module;
1162
1163         err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1164         if (err) {
1165                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1166                         mlxsw_sx_port->local_port);
1167                 goto err_port_system_port_mapping_set;
1168         }
1169
1170         /* Adding port to Infiniband swid (1) */
1171         err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 1);
1172         if (err) {
1173                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1174                         mlxsw_sx_port->local_port);
1175                 goto err_port_swid_set;
1176         }
1177
1178         /* Expose the IB port number as it's front panel name */
1179         err = mlxsw_sx_port_ib_port_set(mlxsw_sx_port, module + 1);
1180         if (err) {
1181                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set IB port\n",
1182                         mlxsw_sx_port->local_port);
1183                 goto err_port_ib_set;
1184         }
1185
1186         /* Supports all speeds from SDR to FDR (bitmask) and support bus width
1187          * of 1x, 2x and 4x (3 bits bitmask)
1188          */
1189         err = mlxsw_sx_port_ib_speed_set(mlxsw_sx_port,
1190                                          MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
1191                                          BIT(3) - 1);
1192         if (err) {
1193                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1194                         mlxsw_sx_port->local_port);
1195                 goto err_port_speed_set;
1196         }
1197
1198         /* Change to the maximum MTU the device supports, the SMA will take
1199          * care of the active MTU
1200          */
1201         err = mlxsw_sx_port_mtu_ib_set(mlxsw_sx_port, MLXSW_IB_DEFAULT_MTU);
1202         if (err) {
1203                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1204                         mlxsw_sx_port->local_port);
1205                 goto err_port_mtu_set;
1206         }
1207
1208         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
1209         if (err) {
1210                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
1211                         mlxsw_sx_port->local_port);
1212                 goto err_port_admin_set;
1213         }
1214
1215         mlxsw_core_port_ib_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1216                                mlxsw_sx_port);
1217         mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1218         return 0;
1219
1220 err_port_admin_set:
1221 err_port_mtu_set:
1222 err_port_speed_set:
1223 err_port_ib_set:
1224         mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1225 err_port_swid_set:
1226 err_port_system_port_mapping_set:
1227         kfree(mlxsw_sx_port);
1228         return err;
1229 }
1230
1231 static void __mlxsw_sx_port_ib_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1232 {
1233         struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1234
1235         mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1236         mlxsw_sx->ports[local_port] = NULL;
1237         mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1238         mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1239         kfree(mlxsw_sx_port);
1240 }
1241
1242 static void __mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1243 {
1244         enum devlink_port_type port_type =
1245                 mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1246
1247         if (port_type == DEVLINK_PORT_TYPE_ETH)
1248                 __mlxsw_sx_port_eth_remove(mlxsw_sx, local_port);
1249         else if (port_type == DEVLINK_PORT_TYPE_IB)
1250                 __mlxsw_sx_port_ib_remove(mlxsw_sx, local_port);
1251 }
1252
1253 static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1254 {
1255         __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1256         mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1257 }
1258
1259 static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1260 {
1261         int i;
1262
1263         for (i = 1; i < mlxsw_core_max_ports(mlxsw_sx->core); i++)
1264                 if (mlxsw_sx_port_created(mlxsw_sx, i))
1265                         mlxsw_sx_port_remove(mlxsw_sx, i);
1266         kfree(mlxsw_sx->ports);
1267 }
1268
1269 static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1270 {
1271         unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sx->core);
1272         size_t alloc_size;
1273         u8 module, width;
1274         int i;
1275         int err;
1276
1277         alloc_size = sizeof(struct mlxsw_sx_port *) * max_ports;
1278         mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1279         if (!mlxsw_sx->ports)
1280                 return -ENOMEM;
1281
1282         for (i = 1; i < max_ports; i++) {
1283                 err = mlxsw_sx_port_module_info_get(mlxsw_sx, i, &module,
1284                                                     &width);
1285                 if (err)
1286                         goto err_port_module_info_get;
1287                 if (!width)
1288                         continue;
1289                 err = mlxsw_sx_port_eth_create(mlxsw_sx, i, module, width);
1290                 if (err)
1291                         goto err_port_create;
1292         }
1293         return 0;
1294
1295 err_port_create:
1296 err_port_module_info_get:
1297         for (i--; i >= 1; i--)
1298                 if (mlxsw_sx_port_created(mlxsw_sx, i))
1299                         mlxsw_sx_port_remove(mlxsw_sx, i);
1300         kfree(mlxsw_sx->ports);
1301         return err;
1302 }
1303
1304 static void mlxsw_sx_pude_eth_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1305                                          enum mlxsw_reg_pude_oper_status status)
1306 {
1307         if (status == MLXSW_PORT_OPER_STATUS_UP) {
1308                 netdev_info(mlxsw_sx_port->dev, "link up\n");
1309                 netif_carrier_on(mlxsw_sx_port->dev);
1310         } else {
1311                 netdev_info(mlxsw_sx_port->dev, "link down\n");
1312                 netif_carrier_off(mlxsw_sx_port->dev);
1313         }
1314 }
1315
1316 static void mlxsw_sx_pude_ib_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1317                                         enum mlxsw_reg_pude_oper_status status)
1318 {
1319         if (status == MLXSW_PORT_OPER_STATUS_UP)
1320                 pr_info("ib link for port %d - up\n",
1321                         mlxsw_sx_port->mapping.module + 1);
1322         else
1323                 pr_info("ib link for port %d - down\n",
1324                         mlxsw_sx_port->mapping.module + 1);
1325 }
1326
1327 static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1328                                      char *pude_pl, void *priv)
1329 {
1330         struct mlxsw_sx *mlxsw_sx = priv;
1331         struct mlxsw_sx_port *mlxsw_sx_port;
1332         enum mlxsw_reg_pude_oper_status status;
1333         enum devlink_port_type port_type;
1334         u8 local_port;
1335
1336         local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1337         mlxsw_sx_port = mlxsw_sx->ports[local_port];
1338         if (!mlxsw_sx_port) {
1339                 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1340                          local_port);
1341                 return;
1342         }
1343
1344         status = mlxsw_reg_pude_oper_status_get(pude_pl);
1345         port_type = mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1346         if (port_type == DEVLINK_PORT_TYPE_ETH)
1347                 mlxsw_sx_pude_eth_event_func(mlxsw_sx_port, status);
1348         else if (port_type == DEVLINK_PORT_TYPE_IB)
1349                 mlxsw_sx_pude_ib_event_func(mlxsw_sx_port, status);
1350 }
1351
1352 static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1353                                       void *priv)
1354 {
1355         struct mlxsw_sx *mlxsw_sx = priv;
1356         struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1357         struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1358
1359         if (unlikely(!mlxsw_sx_port)) {
1360                 dev_warn_ratelimited(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1361                                      local_port);
1362                 return;
1363         }
1364
1365         skb->dev = mlxsw_sx_port->dev;
1366
1367         pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1368         u64_stats_update_begin(&pcpu_stats->syncp);
1369         pcpu_stats->rx_packets++;
1370         pcpu_stats->rx_bytes += skb->len;
1371         u64_stats_update_end(&pcpu_stats->syncp);
1372
1373         skb->protocol = eth_type_trans(skb, skb->dev);
1374         netif_receive_skb(skb);
1375 }
1376
1377 static int mlxsw_sx_port_type_set(struct mlxsw_core *mlxsw_core, u8 local_port,
1378                                   enum devlink_port_type new_type)
1379 {
1380         struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1381         u8 module, width;
1382         int err;
1383
1384         if (new_type == DEVLINK_PORT_TYPE_AUTO)
1385                 return -EOPNOTSUPP;
1386
1387         __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1388         err = mlxsw_sx_port_module_info_get(mlxsw_sx, local_port, &module,
1389                                             &width);
1390         if (err)
1391                 goto err_port_module_info_get;
1392
1393         if (new_type == DEVLINK_PORT_TYPE_ETH)
1394                 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module,
1395                                                  width);
1396         else if (new_type == DEVLINK_PORT_TYPE_IB)
1397                 err = __mlxsw_sx_port_ib_create(mlxsw_sx, local_port, module,
1398                                                 width);
1399
1400 err_port_module_info_get:
1401         return err;
1402 }
1403
1404 #define MLXSW_SX_RXL(_trap_id) \
1405         MLXSW_RXL(mlxsw_sx_rx_listener_func, _trap_id, TRAP_TO_CPU,     \
1406                   false, SX2_RX, FORWARD)
1407
1408 static const struct mlxsw_listener mlxsw_sx_listener[] = {
1409         MLXSW_EVENTL(mlxsw_sx_pude_event_func, PUDE, EMAD),
1410         MLXSW_SX_RXL(FDB_MC),
1411         MLXSW_SX_RXL(STP),
1412         MLXSW_SX_RXL(LACP),
1413         MLXSW_SX_RXL(EAPOL),
1414         MLXSW_SX_RXL(LLDP),
1415         MLXSW_SX_RXL(MMRP),
1416         MLXSW_SX_RXL(MVRP),
1417         MLXSW_SX_RXL(RPVST),
1418         MLXSW_SX_RXL(DHCP),
1419         MLXSW_SX_RXL(IGMP_QUERY),
1420         MLXSW_SX_RXL(IGMP_V1_REPORT),
1421         MLXSW_SX_RXL(IGMP_V2_REPORT),
1422         MLXSW_SX_RXL(IGMP_V2_LEAVE),
1423         MLXSW_SX_RXL(IGMP_V3_REPORT),
1424 };
1425
1426 static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1427 {
1428         char htgt_pl[MLXSW_REG_HTGT_LEN];
1429         int i;
1430         int err;
1431
1432         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
1433                             MLXSW_REG_HTGT_INVALID_POLICER,
1434                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1435                             MLXSW_REG_HTGT_DEFAULT_TC);
1436         mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1437                                           MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX);
1438
1439         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1440         if (err)
1441                 return err;
1442
1443         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
1444                             MLXSW_REG_HTGT_INVALID_POLICER,
1445                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1446                             MLXSW_REG_HTGT_DEFAULT_TC);
1447         mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1448                                         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL);
1449
1450         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1451         if (err)
1452                 return err;
1453
1454         for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1455                 err = mlxsw_core_trap_register(mlxsw_sx->core,
1456                                                &mlxsw_sx_listener[i],
1457                                                mlxsw_sx);
1458                 if (err)
1459                         goto err_listener_register;
1460
1461         }
1462         return 0;
1463
1464 err_listener_register:
1465         for (i--; i >= 0; i--) {
1466                 mlxsw_core_trap_unregister(mlxsw_sx->core,
1467                                            &mlxsw_sx_listener[i],
1468                                            mlxsw_sx);
1469         }
1470         return err;
1471 }
1472
1473 static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1474 {
1475         int i;
1476
1477         for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1478                 mlxsw_core_trap_unregister(mlxsw_sx->core,
1479                                            &mlxsw_sx_listener[i],
1480                                            mlxsw_sx);
1481         }
1482 }
1483
1484 static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1485 {
1486         char sfgc_pl[MLXSW_REG_SFGC_LEN];
1487         char sgcr_pl[MLXSW_REG_SGCR_LEN];
1488         char *sftr_pl;
1489         int err;
1490
1491         /* Configure a flooding table, which includes only CPU port. */
1492         sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1493         if (!sftr_pl)
1494                 return -ENOMEM;
1495         mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0,
1496                             MLXSW_PORT_CPU_PORT, true);
1497         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1498         kfree(sftr_pl);
1499         if (err)
1500                 return err;
1501
1502         /* Flood different packet types using the flooding table. */
1503         mlxsw_reg_sfgc_pack(sfgc_pl,
1504                             MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1505                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1506                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1507                             0);
1508         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1509         if (err)
1510                 return err;
1511
1512         mlxsw_reg_sfgc_pack(sfgc_pl,
1513                             MLXSW_REG_SFGC_TYPE_BROADCAST,
1514                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1515                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1516                             0);
1517         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1518         if (err)
1519                 return err;
1520
1521         mlxsw_reg_sfgc_pack(sfgc_pl,
1522                             MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1523                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1524                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1525                             0);
1526         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1527         if (err)
1528                 return err;
1529
1530         mlxsw_reg_sfgc_pack(sfgc_pl,
1531                             MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1532                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1533                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1534                             0);
1535         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1536         if (err)
1537                 return err;
1538
1539         mlxsw_reg_sfgc_pack(sfgc_pl,
1540                             MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1541                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1542                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1543                             0);
1544         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1545         if (err)
1546                 return err;
1547
1548         mlxsw_reg_sgcr_pack(sgcr_pl, true);
1549         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1550 }
1551
1552 static int mlxsw_sx_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
1553 {
1554         char htgt_pl[MLXSW_REG_HTGT_LEN];
1555
1556         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
1557                             MLXSW_REG_HTGT_INVALID_POLICER,
1558                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1559                             MLXSW_REG_HTGT_DEFAULT_TC);
1560         mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
1561         mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1562                                         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD);
1563         return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
1564 }
1565
1566 static int mlxsw_sx_init(struct mlxsw_core *mlxsw_core,
1567                          const struct mlxsw_bus_info *mlxsw_bus_info,
1568                          struct netlink_ext_ack *extack)
1569 {
1570         struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1571         int err;
1572
1573         mlxsw_sx->core = mlxsw_core;
1574         mlxsw_sx->bus_info = mlxsw_bus_info;
1575
1576         err = mlxsw_sx_hw_id_get(mlxsw_sx);
1577         if (err) {
1578                 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1579                 return err;
1580         }
1581
1582         err = mlxsw_sx_ports_create(mlxsw_sx);
1583         if (err) {
1584                 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1585                 return err;
1586         }
1587
1588         err = mlxsw_sx_traps_init(mlxsw_sx);
1589         if (err) {
1590                 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps\n");
1591                 goto err_listener_register;
1592         }
1593
1594         err = mlxsw_sx_flood_init(mlxsw_sx);
1595         if (err) {
1596                 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1597                 goto err_flood_init;
1598         }
1599
1600         return 0;
1601
1602 err_flood_init:
1603         mlxsw_sx_traps_fini(mlxsw_sx);
1604 err_listener_register:
1605         mlxsw_sx_ports_remove(mlxsw_sx);
1606         return err;
1607 }
1608
1609 static void mlxsw_sx_fini(struct mlxsw_core *mlxsw_core)
1610 {
1611         struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1612
1613         mlxsw_sx_traps_fini(mlxsw_sx);
1614         mlxsw_sx_ports_remove(mlxsw_sx);
1615 }
1616
1617 static const struct mlxsw_config_profile mlxsw_sx_config_profile = {
1618         .used_max_vepa_channels         = 1,
1619         .max_vepa_channels              = 0,
1620         .used_max_mid                   = 1,
1621         .max_mid                        = 7000,
1622         .used_max_pgt                   = 1,
1623         .max_pgt                        = 0,
1624         .used_max_system_port           = 1,
1625         .max_system_port                = 48000,
1626         .used_max_vlan_groups           = 1,
1627         .max_vlan_groups                = 127,
1628         .used_max_regions               = 1,
1629         .max_regions                    = 400,
1630         .used_flood_tables              = 1,
1631         .max_flood_tables               = 2,
1632         .max_vid_flood_tables           = 1,
1633         .used_flood_mode                = 1,
1634         .flood_mode                     = 3,
1635         .used_max_ib_mc                 = 1,
1636         .max_ib_mc                      = 6,
1637         .used_max_pkey                  = 1,
1638         .max_pkey                       = 0,
1639         .swid_config                    = {
1640                 {
1641                         .used_type      = 1,
1642                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
1643                 },
1644                 {
1645                         .used_type      = 1,
1646                         .type           = MLXSW_PORT_SWID_TYPE_IB,
1647                 }
1648         },
1649 };
1650
1651 static struct mlxsw_driver mlxsw_sx_driver = {
1652         .kind                   = mlxsw_sx_driver_name,
1653         .priv_size              = sizeof(struct mlxsw_sx),
1654         .init                   = mlxsw_sx_init,
1655         .fini                   = mlxsw_sx_fini,
1656         .basic_trap_groups_set  = mlxsw_sx_basic_trap_groups_set,
1657         .txhdr_construct        = mlxsw_sx_txhdr_construct,
1658         .txhdr_len              = MLXSW_TXHDR_LEN,
1659         .profile                = &mlxsw_sx_config_profile,
1660         .port_type_set          = mlxsw_sx_port_type_set,
1661 };
1662
1663 static const struct pci_device_id mlxsw_sx_pci_id_table[] = {
1664         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
1665         {0, },
1666 };
1667
1668 static struct pci_driver mlxsw_sx_pci_driver = {
1669         .name = mlxsw_sx_driver_name,
1670         .id_table = mlxsw_sx_pci_id_table,
1671 };
1672
1673 static int __init mlxsw_sx_module_init(void)
1674 {
1675         int err;
1676
1677         err = mlxsw_core_driver_register(&mlxsw_sx_driver);
1678         if (err)
1679                 return err;
1680
1681         err = mlxsw_pci_driver_register(&mlxsw_sx_pci_driver);
1682         if (err)
1683                 goto err_pci_driver_register;
1684
1685         return 0;
1686
1687 err_pci_driver_register:
1688         mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1689         return err;
1690 }
1691
1692 static void __exit mlxsw_sx_module_exit(void)
1693 {
1694         mlxsw_pci_driver_unregister(&mlxsw_sx_pci_driver);
1695         mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1696 }
1697
1698 module_init(mlxsw_sx_module_init);
1699 module_exit(mlxsw_sx_module_exit);
1700
1701 MODULE_LICENSE("Dual BSD/GPL");
1702 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1703 MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1704 MODULE_DEVICE_TABLE(pci, mlxsw_sx_pci_id_table);