1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2018 Mellanox Technologies. All rights reserved */
4 #include <linux/netdevice.h>
5 #include <linux/netlink.h>
6 #include <linux/random.h>
11 #include "spectrum_nve.h"
13 /* Eth (18B) | IPv6 (40B) | UDP (8B) | VxLAN (8B) | Eth (14B) | IPv6 (40B)
15 * In the worst case - where we have a VLAN tag on the outer Ethernet
16 * header and IPv6 in overlay and underlay - we need to parse 128 bytes
18 #define MLXSW_SP_NVE_VXLAN_PARSING_DEPTH 128
19 #define MLXSW_SP_NVE_DEFAULT_PARSING_DEPTH 96
21 #define MLXSW_SP_NVE_VXLAN_SUPPORTED_FLAGS (VXLAN_F_UDP_ZERO_CSUM_TX | \
24 static bool mlxsw_sp_nve_vxlan_can_offload(const struct mlxsw_sp_nve *nve,
25 const struct net_device *dev,
26 struct netlink_ext_ack *extack)
28 struct vxlan_dev *vxlan = netdev_priv(dev);
29 struct vxlan_config *cfg = &vxlan->cfg;
31 if (cfg->saddr.sa.sa_family != AF_INET) {
32 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Only IPv4 underlay is supported");
36 if (vxlan_addr_multicast(&cfg->remote_ip)) {
37 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Multicast destination IP is not supported");
41 if (vxlan_addr_any(&cfg->saddr)) {
42 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Source address must be specified");
46 if (cfg->remote_ifindex) {
47 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Local interface is not supported");
51 if (cfg->port_min || cfg->port_max) {
52 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Only default UDP source port range is supported");
57 NL_SET_ERR_MSG_MOD(extack, "VxLAN: TOS must be configured to inherit");
61 if (cfg->flags & VXLAN_F_TTL_INHERIT) {
62 NL_SET_ERR_MSG_MOD(extack, "VxLAN: TTL must not be configured to inherit");
66 if (!(cfg->flags & VXLAN_F_UDP_ZERO_CSUM_TX)) {
67 NL_SET_ERR_MSG_MOD(extack, "VxLAN: UDP checksum is not supported");
71 if (cfg->flags & ~MLXSW_SP_NVE_VXLAN_SUPPORTED_FLAGS) {
72 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Unsupported flag");
77 NL_SET_ERR_MSG_MOD(extack, "VxLAN: TTL must not be configured to 0");
81 if (cfg->label != 0) {
82 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Flow label must be configured to 0");
89 static void mlxsw_sp_nve_vxlan_config(const struct mlxsw_sp_nve *nve,
90 const struct net_device *dev,
91 struct mlxsw_sp_nve_config *config)
93 struct vxlan_dev *vxlan = netdev_priv(dev);
94 struct vxlan_config *cfg = &vxlan->cfg;
96 config->type = MLXSW_SP_NVE_TYPE_VXLAN;
97 config->ttl = cfg->ttl;
98 config->flowlabel = cfg->label;
99 config->learning_en = cfg->flags & VXLAN_F_LEARN ? 1 : 0;
100 config->ul_tb_id = RT_TABLE_MAIN;
101 config->ul_proto = MLXSW_SP_L3_PROTO_IPV4;
102 config->ul_sip.addr4 = cfg->saddr.sin.sin_addr.s_addr;
103 config->udp_dport = cfg->dst_port;
106 static int __mlxsw_sp_nve_parsing_set(struct mlxsw_sp *mlxsw_sp,
107 unsigned int parsing_depth,
110 char mprs_pl[MLXSW_REG_MPRS_LEN];
112 mlxsw_reg_mprs_pack(mprs_pl, parsing_depth, be16_to_cpu(udp_dport));
113 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
116 static int mlxsw_sp_nve_parsing_set(struct mlxsw_sp *mlxsw_sp,
119 int parsing_depth = mlxsw_sp->nve->inc_parsing_depth_refs ?
120 MLXSW_SP_NVE_VXLAN_PARSING_DEPTH :
121 MLXSW_SP_NVE_DEFAULT_PARSING_DEPTH;
123 return __mlxsw_sp_nve_parsing_set(mlxsw_sp, parsing_depth, udp_dport);
127 __mlxsw_sp_nve_inc_parsing_depth_get(struct mlxsw_sp *mlxsw_sp,
132 mlxsw_sp->nve->inc_parsing_depth_refs++;
134 err = mlxsw_sp_nve_parsing_set(mlxsw_sp, udp_dport);
136 goto err_nve_parsing_set;
140 mlxsw_sp->nve->inc_parsing_depth_refs--;
145 __mlxsw_sp_nve_inc_parsing_depth_put(struct mlxsw_sp *mlxsw_sp,
148 mlxsw_sp->nve->inc_parsing_depth_refs--;
149 mlxsw_sp_nve_parsing_set(mlxsw_sp, udp_dport);
152 int mlxsw_sp_nve_inc_parsing_depth_get(struct mlxsw_sp *mlxsw_sp)
154 __be16 udp_dport = mlxsw_sp->nve->config.udp_dport;
156 return __mlxsw_sp_nve_inc_parsing_depth_get(mlxsw_sp, udp_dport);
159 void mlxsw_sp_nve_inc_parsing_depth_put(struct mlxsw_sp *mlxsw_sp)
161 __be16 udp_dport = mlxsw_sp->nve->config.udp_dport;
163 __mlxsw_sp_nve_inc_parsing_depth_put(mlxsw_sp, udp_dport);
167 mlxsw_sp_nve_vxlan_config_prepare(char *tngcr_pl,
168 const struct mlxsw_sp_nve_config *config)
172 mlxsw_reg_tngcr_pack(tngcr_pl, MLXSW_REG_TNGCR_TYPE_VXLAN, true,
174 /* VxLAN driver's default UDP source port range is 32768 (0x8000)
175 * to 60999 (0xee47). Set the upper 8 bits of the UDP source port
176 * to a random number between 0x80 and 0xee
178 get_random_bytes(&udp_sport, sizeof(udp_sport));
179 udp_sport = (udp_sport % (0xee - 0x80 + 1)) + 0x80;
180 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(tngcr_pl, udp_sport);
181 mlxsw_reg_tngcr_usipv4_set(tngcr_pl, be32_to_cpu(config->ul_sip.addr4));
185 mlxsw_sp1_nve_vxlan_config_set(struct mlxsw_sp *mlxsw_sp,
186 const struct mlxsw_sp_nve_config *config)
188 char tngcr_pl[MLXSW_REG_TNGCR_LEN];
192 err = mlxsw_sp_router_tb_id_vr_id(mlxsw_sp, config->ul_tb_id,
197 mlxsw_sp_nve_vxlan_config_prepare(tngcr_pl, config);
198 mlxsw_reg_tngcr_learn_enable_set(tngcr_pl, config->learning_en);
199 mlxsw_reg_tngcr_underlay_virtual_router_set(tngcr_pl, ul_vr_id);
201 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tngcr), tngcr_pl);
204 static void mlxsw_sp1_nve_vxlan_config_clear(struct mlxsw_sp *mlxsw_sp)
206 char tngcr_pl[MLXSW_REG_TNGCR_LEN];
208 mlxsw_reg_tngcr_pack(tngcr_pl, MLXSW_REG_TNGCR_TYPE_VXLAN, false, 0);
210 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tngcr), tngcr_pl);
213 static int mlxsw_sp1_nve_vxlan_rtdp_set(struct mlxsw_sp *mlxsw_sp,
214 unsigned int tunnel_index)
216 char rtdp_pl[MLXSW_REG_RTDP_LEN];
218 mlxsw_reg_rtdp_pack(rtdp_pl, MLXSW_REG_RTDP_TYPE_NVE, tunnel_index);
220 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rtdp), rtdp_pl);
223 static int mlxsw_sp1_nve_vxlan_init(struct mlxsw_sp_nve *nve,
224 const struct mlxsw_sp_nve_config *config)
226 struct mlxsw_sp *mlxsw_sp = nve->mlxsw_sp;
229 err = __mlxsw_sp_nve_inc_parsing_depth_get(mlxsw_sp, config->udp_dport);
233 err = mlxsw_sp1_nve_vxlan_config_set(mlxsw_sp, config);
237 err = mlxsw_sp1_nve_vxlan_rtdp_set(mlxsw_sp, nve->tunnel_index);
241 err = mlxsw_sp_router_nve_promote_decap(mlxsw_sp, config->ul_tb_id,
246 goto err_promote_decap;
252 mlxsw_sp1_nve_vxlan_config_clear(mlxsw_sp);
254 __mlxsw_sp_nve_inc_parsing_depth_put(mlxsw_sp, 0);
258 static void mlxsw_sp1_nve_vxlan_fini(struct mlxsw_sp_nve *nve)
260 struct mlxsw_sp_nve_config *config = &nve->config;
261 struct mlxsw_sp *mlxsw_sp = nve->mlxsw_sp;
263 mlxsw_sp_router_nve_demote_decap(mlxsw_sp, config->ul_tb_id,
264 config->ul_proto, &config->ul_sip);
265 mlxsw_sp1_nve_vxlan_config_clear(mlxsw_sp);
266 __mlxsw_sp_nve_inc_parsing_depth_put(mlxsw_sp, 0);
270 mlxsw_sp_nve_vxlan_fdb_replay(const struct net_device *nve_dev, __be32 vni,
271 struct netlink_ext_ack *extack)
273 if (WARN_ON(!netif_is_vxlan(nve_dev)))
275 return vxlan_fdb_replay(nve_dev, vni, &mlxsw_sp_switchdev_notifier,
280 mlxsw_sp_nve_vxlan_clear_offload(const struct net_device *nve_dev, __be32 vni)
282 if (WARN_ON(!netif_is_vxlan(nve_dev)))
284 vxlan_fdb_clear_offload(nve_dev, vni);
287 const struct mlxsw_sp_nve_ops mlxsw_sp1_nve_vxlan_ops = {
288 .type = MLXSW_SP_NVE_TYPE_VXLAN,
289 .can_offload = mlxsw_sp_nve_vxlan_can_offload,
290 .nve_config = mlxsw_sp_nve_vxlan_config,
291 .init = mlxsw_sp1_nve_vxlan_init,
292 .fini = mlxsw_sp1_nve_vxlan_fini,
293 .fdb_replay = mlxsw_sp_nve_vxlan_fdb_replay,
294 .fdb_clear_offload = mlxsw_sp_nve_vxlan_clear_offload,
297 static bool mlxsw_sp2_nve_vxlan_learning_set(struct mlxsw_sp *mlxsw_sp,
300 char tnpc_pl[MLXSW_REG_TNPC_LEN];
302 mlxsw_reg_tnpc_pack(tnpc_pl, MLXSW_REG_TUNNEL_PORT_NVE,
304 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tnpc), tnpc_pl);
308 mlxsw_sp2_nve_vxlan_config_set(struct mlxsw_sp *mlxsw_sp,
309 const struct mlxsw_sp_nve_config *config)
311 char tngcr_pl[MLXSW_REG_TNGCR_LEN];
315 err = mlxsw_sp_router_ul_rif_get(mlxsw_sp, config->ul_tb_id,
319 mlxsw_sp->nve->ul_rif_index = ul_rif_index;
321 err = mlxsw_sp2_nve_vxlan_learning_set(mlxsw_sp, config->learning_en);
323 goto err_vxlan_learning_set;
325 mlxsw_sp_nve_vxlan_config_prepare(tngcr_pl, config);
326 mlxsw_reg_tngcr_underlay_rif_set(tngcr_pl, ul_rif_index);
328 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tngcr), tngcr_pl);
330 goto err_tngcr_write;
335 mlxsw_sp2_nve_vxlan_learning_set(mlxsw_sp, false);
336 err_vxlan_learning_set:
337 mlxsw_sp_router_ul_rif_put(mlxsw_sp, ul_rif_index);
341 static void mlxsw_sp2_nve_vxlan_config_clear(struct mlxsw_sp *mlxsw_sp)
343 char tngcr_pl[MLXSW_REG_TNGCR_LEN];
345 mlxsw_reg_tngcr_pack(tngcr_pl, MLXSW_REG_TNGCR_TYPE_VXLAN, false, 0);
346 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tngcr), tngcr_pl);
347 mlxsw_sp2_nve_vxlan_learning_set(mlxsw_sp, false);
348 mlxsw_sp_router_ul_rif_put(mlxsw_sp, mlxsw_sp->nve->ul_rif_index);
351 static int mlxsw_sp2_nve_vxlan_rtdp_set(struct mlxsw_sp *mlxsw_sp,
352 unsigned int tunnel_index,
355 char rtdp_pl[MLXSW_REG_RTDP_LEN];
357 mlxsw_reg_rtdp_pack(rtdp_pl, MLXSW_REG_RTDP_TYPE_NVE, tunnel_index);
358 mlxsw_reg_rtdp_egress_router_interface_set(rtdp_pl, ul_rif_index);
360 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rtdp), rtdp_pl);
363 static int mlxsw_sp2_nve_vxlan_init(struct mlxsw_sp_nve *nve,
364 const struct mlxsw_sp_nve_config *config)
366 struct mlxsw_sp *mlxsw_sp = nve->mlxsw_sp;
369 err = __mlxsw_sp_nve_inc_parsing_depth_get(mlxsw_sp, config->udp_dport);
373 err = mlxsw_sp2_nve_vxlan_config_set(mlxsw_sp, config);
377 err = mlxsw_sp2_nve_vxlan_rtdp_set(mlxsw_sp, nve->tunnel_index,
382 err = mlxsw_sp_router_nve_promote_decap(mlxsw_sp, config->ul_tb_id,
387 goto err_promote_decap;
393 mlxsw_sp2_nve_vxlan_config_clear(mlxsw_sp);
395 __mlxsw_sp_nve_inc_parsing_depth_put(mlxsw_sp, 0);
399 static void mlxsw_sp2_nve_vxlan_fini(struct mlxsw_sp_nve *nve)
401 struct mlxsw_sp_nve_config *config = &nve->config;
402 struct mlxsw_sp *mlxsw_sp = nve->mlxsw_sp;
404 mlxsw_sp_router_nve_demote_decap(mlxsw_sp, config->ul_tb_id,
405 config->ul_proto, &config->ul_sip);
406 mlxsw_sp2_nve_vxlan_config_clear(mlxsw_sp);
407 __mlxsw_sp_nve_inc_parsing_depth_put(mlxsw_sp, 0);
410 const struct mlxsw_sp_nve_ops mlxsw_sp2_nve_vxlan_ops = {
411 .type = MLXSW_SP_NVE_TYPE_VXLAN,
412 .can_offload = mlxsw_sp_nve_vxlan_can_offload,
413 .nve_config = mlxsw_sp_nve_vxlan_config,
414 .init = mlxsw_sp2_nve_vxlan_init,
415 .fini = mlxsw_sp2_nve_vxlan_fini,
416 .fdb_replay = mlxsw_sp_nve_vxlan_fdb_replay,
417 .fdb_clear_offload = mlxsw_sp_nve_vxlan_clear_offload,