drivers/net/ethernet/mellanox/mlxsw/spectrum_ethtool.c

   1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
   2 /* Copyright (c) 2020 Mellanox Technologies. All rights reserved */
   3
   4 #include "reg.h"
   5 #include "core.h"
   6 #include "spectrum.h"
   7 #include "core_env.h"
   8
   9 static const char mlxsw_sp_driver_version[] = "1.0";
  10
  11 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
  12                                       struct ethtool_drvinfo *drvinfo)
  13 {
  14         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  15         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  16
  17         strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
  18                 sizeof(drvinfo->driver));
  19         strlcpy(drvinfo->version, mlxsw_sp_driver_version,
  20                 sizeof(drvinfo->version));
  21         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
  22                  "%d.%d.%d",
  23                  mlxsw_sp->bus_info->fw_rev.major,
  24                  mlxsw_sp->bus_info->fw_rev.minor,
  25                  mlxsw_sp->bus_info->fw_rev.subminor);
  26         strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
  27                 sizeof(drvinfo->bus_info));
  28 }
  29
  30 struct mlxsw_sp_ethtool_link_ext_state_opcode_mapping {
  31         u32 status_opcode;
  32         enum ethtool_link_ext_state link_ext_state;
  33         u8 link_ext_substate;
  34 };
  35
  36 static const struct mlxsw_sp_ethtool_link_ext_state_opcode_mapping
  37 mlxsw_sp_link_ext_state_opcode_map[] = {
  38         {2, ETHTOOL_LINK_EXT_STATE_AUTONEG,
  39                 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED},
  40         {3, ETHTOOL_LINK_EXT_STATE_AUTONEG,
  41                 ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED},
  42         {4, ETHTOOL_LINK_EXT_STATE_AUTONEG,
  43                 ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED},
  44         {36, ETHTOOL_LINK_EXT_STATE_AUTONEG,
  45                 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE},
  46         {38, ETHTOOL_LINK_EXT_STATE_AUTONEG,
  47                 ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE},
  48         {39, ETHTOOL_LINK_EXT_STATE_AUTONEG,
  49                 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD},
  50
  51         {5, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
  52                 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED},
  53         {6, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
  54                 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT},
  55         {7, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
  56                 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY},
  57         {8, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 0},
  58         {14, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
  59                 ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT},
  60
  61         {9, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
  62                 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK},
  63         {10, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
  64                 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK},
  65         {11, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
  66                 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS},
  67         {12, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
  68                 ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED},
  69         {13, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
  70                 ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED},
  71
  72         {15, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 0},
  73         {17, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
  74                 ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS},
  75         {42, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
  76                 ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE},
  77
  78         {1024, ETHTOOL_LINK_EXT_STATE_NO_CABLE, 0},
  79
  80         {16, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
  81                 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
  82         {20, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
  83                 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
  84         {29, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
  85                 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
  86         {1025, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
  87                 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
  88         {1029, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
  89                 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
  90         {1031, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 0},
  91
  92         {1027, ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 0},
  93
  94         {23, ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, 0},
  95
  96         {1032, ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 0},
  97
  98         {1030, ETHTOOL_LINK_EXT_STATE_OVERHEAT, 0},
  99
 100         {1042, ETHTOOL_LINK_EXT_STATE_MODULE,
 101          ETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY},
 102 };
 103
 104 static void
 105 mlxsw_sp_port_set_link_ext_state(struct mlxsw_sp_ethtool_link_ext_state_opcode_mapping
 106                                  link_ext_state_mapping,
 107                                  struct ethtool_link_ext_state_info *link_ext_state_info)
 108 {
 109         switch (link_ext_state_mapping.link_ext_state) {
 110         case ETHTOOL_LINK_EXT_STATE_AUTONEG:
 111                 link_ext_state_info->autoneg =
 112                         link_ext_state_mapping.link_ext_substate;
 113                 break;
 114         case ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE:
 115                 link_ext_state_info->link_training =
 116                         link_ext_state_mapping.link_ext_substate;
 117                 break;
 118         case ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH:
 119                 link_ext_state_info->link_logical_mismatch =
 120                         link_ext_state_mapping.link_ext_substate;
 121                 break;
 122         case ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY:
 123                 link_ext_state_info->bad_signal_integrity =
 124                         link_ext_state_mapping.link_ext_substate;
 125                 break;
 126         case ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE:
 127                 link_ext_state_info->cable_issue =
 128                         link_ext_state_mapping.link_ext_substate;
 129                 break;
 130         case ETHTOOL_LINK_EXT_STATE_MODULE:
 131                 link_ext_state_info->module =
 132                         link_ext_state_mapping.link_ext_substate;
 133                 break;
 134         default:
 135                 break;
 136         }
 137
 138         link_ext_state_info->link_ext_state = link_ext_state_mapping.link_ext_state;
 139 }
 140
 141 static int
 142 mlxsw_sp_port_get_link_ext_state(struct net_device *dev,
 143                                  struct ethtool_link_ext_state_info *link_ext_state_info)
 144 {
 145         struct mlxsw_sp_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping;
 146         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 147         char pddr_pl[MLXSW_REG_PDDR_LEN];
 148         int opcode, err, i;
 149         u32 status_opcode;
 150
 151         if (netif_carrier_ok(dev))
 152                 return -ENODATA;
 153
 154         mlxsw_reg_pddr_pack(pddr_pl, mlxsw_sp_port->local_port,
 155                             MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO);
 156
 157         opcode = MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR;
 158         mlxsw_reg_pddr_trblsh_group_opcode_set(pddr_pl, opcode);
 159
 160         err = mlxsw_reg_query(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pddr),
 161                               pddr_pl);
 162         if (err)
 163                 return err;
 164
 165         status_opcode = mlxsw_reg_pddr_trblsh_status_opcode_get(pddr_pl);
 166         if (!status_opcode)
 167                 return -ENODATA;
 168
 169         for (i = 0; i < ARRAY_SIZE(mlxsw_sp_link_ext_state_opcode_map); i++) {
 170                 link_ext_state_mapping = mlxsw_sp_link_ext_state_opcode_map[i];
 171                 if (link_ext_state_mapping.status_opcode == status_opcode) {
 172                         mlxsw_sp_port_set_link_ext_state(link_ext_state_mapping,
 173                                                          link_ext_state_info);
 174                         return 0;
 175                 }
 176         }
 177
 178         return -ENODATA;
 179 }
 180
 181 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
 182                                          struct ethtool_pauseparam *pause)
 183 {
 184         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 185
 186         pause->rx_pause = mlxsw_sp_port->link.rx_pause;
 187         pause->tx_pause = mlxsw_sp_port->link.tx_pause;
 188 }
 189
 190 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
 191                                    struct ethtool_pauseparam *pause)
 192 {
 193         char pfcc_pl[MLXSW_REG_PFCC_LEN];
 194
 195         mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
 196         mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
 197         mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
 198
 199         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
 200                                pfcc_pl);
 201 }
 202
 203 /* Maximum delay buffer needed in case of PAUSE frames. Similar to PFC delay, but is
 204  * measured in bytes. Assumes 100m cable and does not take into account MTU.
 205  */
 206 #define MLXSW_SP_PAUSE_DELAY_BYTES 19476
 207
 208 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
 209                                         struct ethtool_pauseparam *pause)
 210 {
 211         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 212         bool pause_en = pause->tx_pause || pause->rx_pause;
 213         struct mlxsw_sp_hdroom orig_hdroom;
 214         struct mlxsw_sp_hdroom hdroom;
 215         int prio;
 216         int err;
 217
 218         if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
 219                 netdev_err(dev, "PFC already enabled on port\n");
 220                 return -EINVAL;
 221         }
 222
 223         if (pause->autoneg) {
 224                 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
 225                 return -EINVAL;
 226         }
 227
 228         orig_hdroom = *mlxsw_sp_port->hdroom;
 229
 230         hdroom = orig_hdroom;
 231         if (pause_en)
 232                 hdroom.delay_bytes = MLXSW_SP_PAUSE_DELAY_BYTES;
 233         else
 234                 hdroom.delay_bytes = 0;
 235
 236         for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++)
 237                 hdroom.prios.prio[prio].lossy = !pause_en;
 238
 239         mlxsw_sp_hdroom_bufs_reset_lossiness(&hdroom);
 240         mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
 241
 242         err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
 243         if (err) {
 244                 netdev_err(dev, "Failed to configure port's headroom\n");
 245                 return err;
 246         }
 247
 248         err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
 249         if (err) {
 250                 netdev_err(dev, "Failed to set PAUSE parameters\n");
 251                 goto err_port_pause_configure;
 252         }
 253
 254         mlxsw_sp_port->link.rx_pause = pause->rx_pause;
 255         mlxsw_sp_port->link.tx_pause = pause->tx_pause;
 256
 257         return 0;
 258
 259 err_port_pause_configure:
 260         mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom);
 261         return err;
 262 }
 263
 264 struct mlxsw_sp_port_hw_stats {
 265         char str[ETH_GSTRING_LEN];
 266         u64 (*getter)(const char *payload);
 267         bool cells_bytes;
 268 };
 269
 270 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
 271         {
 272                 .str = "a_frames_transmitted_ok",
 273                 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
 274         },
 275         {
 276                 .str = "a_frames_received_ok",
 277                 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
 278         },
 279         {
 280                 .str = "a_frame_check_sequence_errors",
 281                 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
 282         },
 283         {
 284                 .str = "a_alignment_errors",
 285                 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
 286         },
 287         {
 288                 .str = "a_octets_transmitted_ok",
 289                 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
 290         },
 291         {
 292                 .str = "a_octets_received_ok",
 293                 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
 294         },
 295         {
 296                 .str = "a_multicast_frames_xmitted_ok",
 297                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
 298         },
 299         {
 300                 .str = "a_broadcast_frames_xmitted_ok",
 301                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
 302         },
 303         {
 304                 .str = "a_multicast_frames_received_ok",
 305                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
 306         },
 307         {
 308                 .str = "a_broadcast_frames_received_ok",
 309                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
 310         },
 311         {
 312                 .str = "a_in_range_length_errors",
 313                 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
 314         },
 315         {
 316                 .str = "a_out_of_range_length_field",
 317                 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
 318         },
 319         {
 320                 .str = "a_frame_too_long_errors",
 321                 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
 322         },
 323         {
 324                 .str = "a_symbol_error_during_carrier",
 325                 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
 326         },
 327         {
 328                 .str = "a_mac_control_frames_transmitted",
 329                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
 330         },
 331         {
 332                 .str = "a_mac_control_frames_received",
 333                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
 334         },
 335         {
 336                 .str = "a_unsupported_opcodes_received",
 337                 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
 338         },
 339         {
 340                 .str = "a_pause_mac_ctrl_frames_received",
 341                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
 342         },
 343         {
 344                 .str = "a_pause_mac_ctrl_frames_xmitted",
 345                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
 346         },
 347 };
 348
 349 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
 350
 351 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2863_stats[] = {
 352         {
 353                 .str = "if_in_discards",
 354                 .getter = mlxsw_reg_ppcnt_if_in_discards_get,
 355         },
 356         {
 357                 .str = "if_out_discards",
 358                 .getter = mlxsw_reg_ppcnt_if_out_discards_get,
 359         },
 360         {
 361                 .str = "if_out_errors",
 362                 .getter = mlxsw_reg_ppcnt_if_out_errors_get,
 363         },
 364 };
 365
 366 #define MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN \
 367         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2863_stats)
 368
 369 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
 370         {
 371                 .str = "ether_stats_undersize_pkts",
 372                 .getter = mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get,
 373         },
 374         {
 375                 .str = "ether_stats_oversize_pkts",
 376                 .getter = mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get,
 377         },
 378         {
 379                 .str = "ether_stats_fragments",
 380                 .getter = mlxsw_reg_ppcnt_ether_stats_fragments_get,
 381         },
 382         {
 383                 .str = "ether_pkts64octets",
 384                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
 385         },
 386         {
 387                 .str = "ether_pkts65to127octets",
 388                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
 389         },
 390         {
 391                 .str = "ether_pkts128to255octets",
 392                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
 393         },
 394         {
 395                 .str = "ether_pkts256to511octets",
 396                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
 397         },
 398         {
 399                 .str = "ether_pkts512to1023octets",
 400                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
 401         },
 402         {
 403                 .str = "ether_pkts1024to1518octets",
 404                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
 405         },
 406         {
 407                 .str = "ether_pkts1519to2047octets",
 408                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
 409         },
 410         {
 411                 .str = "ether_pkts2048to4095octets",
 412                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
 413         },
 414         {
 415                 .str = "ether_pkts4096to8191octets",
 416                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
 417         },
 418         {
 419                 .str = "ether_pkts8192to10239octets",
 420                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
 421         },
 422 };
 423
 424 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
 425         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
 426
 427 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_3635_stats[] = {
 428         {
 429                 .str = "dot3stats_fcs_errors",
 430                 .getter = mlxsw_reg_ppcnt_dot3stats_fcs_errors_get,
 431         },
 432         {
 433                 .str = "dot3stats_symbol_errors",
 434                 .getter = mlxsw_reg_ppcnt_dot3stats_symbol_errors_get,
 435         },
 436         {
 437                 .str = "dot3control_in_unknown_opcodes",
 438                 .getter = mlxsw_reg_ppcnt_dot3control_in_unknown_opcodes_get,
 439         },
 440         {
 441                 .str = "dot3in_pause_frames",
 442                 .getter = mlxsw_reg_ppcnt_dot3in_pause_frames_get,
 443         },
 444 };
 445
 446 #define MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN \
 447         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_3635_stats)
 448
 449 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_ext_stats[] = {
 450         {
 451                 .str = "ecn_marked",
 452                 .getter = mlxsw_reg_ppcnt_ecn_marked_get,
 453         },
 454 };
 455
 456 #define MLXSW_SP_PORT_HW_EXT_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_ext_stats)
 457
 458 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_discard_stats[] = {
 459         {
 460                 .str = "discard_ingress_general",
 461                 .getter = mlxsw_reg_ppcnt_ingress_general_get,
 462         },
 463         {
 464                 .str = "discard_ingress_policy_engine",
 465                 .getter = mlxsw_reg_ppcnt_ingress_policy_engine_get,
 466         },
 467         {
 468                 .str = "discard_ingress_vlan_membership",
 469                 .getter = mlxsw_reg_ppcnt_ingress_vlan_membership_get,
 470         },
 471         {
 472                 .str = "discard_ingress_tag_frame_type",
 473                 .getter = mlxsw_reg_ppcnt_ingress_tag_frame_type_get,
 474         },
 475         {
 476                 .str = "discard_egress_vlan_membership",
 477                 .getter = mlxsw_reg_ppcnt_egress_vlan_membership_get,
 478         },
 479         {
 480                 .str = "discard_loopback_filter",
 481                 .getter = mlxsw_reg_ppcnt_loopback_filter_get,
 482         },
 483         {
 484                 .str = "discard_egress_general",
 485                 .getter = mlxsw_reg_ppcnt_egress_general_get,
 486         },
 487         {
 488                 .str = "discard_egress_hoq",
 489                 .getter = mlxsw_reg_ppcnt_egress_hoq_get,
 490         },
 491         {
 492                 .str = "discard_egress_policy_engine",
 493                 .getter = mlxsw_reg_ppcnt_egress_policy_engine_get,
 494         },
 495         {
 496                 .str = "discard_ingress_tx_link_down",
 497                 .getter = mlxsw_reg_ppcnt_ingress_tx_link_down_get,
 498         },
 499         {
 500                 .str = "discard_egress_stp_filter",
 501                 .getter = mlxsw_reg_ppcnt_egress_stp_filter_get,
 502         },
 503         {
 504                 .str = "discard_egress_sll",
 505                 .getter = mlxsw_reg_ppcnt_egress_sll_get,
 506         },
 507 };
 508
 509 #define MLXSW_SP_PORT_HW_DISCARD_STATS_LEN \
 510         ARRAY_SIZE(mlxsw_sp_port_hw_discard_stats)
 511
 512 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
 513         {
 514                 .str = "rx_octets_prio",
 515                 .getter = mlxsw_reg_ppcnt_rx_octets_get,
 516         },
 517         {
 518                 .str = "rx_frames_prio",
 519                 .getter = mlxsw_reg_ppcnt_rx_frames_get,
 520         },
 521         {
 522                 .str = "tx_octets_prio",
 523                 .getter = mlxsw_reg_ppcnt_tx_octets_get,
 524         },
 525         {
 526                 .str = "tx_frames_prio",
 527                 .getter = mlxsw_reg_ppcnt_tx_frames_get,
 528         },
 529         {
 530                 .str = "rx_pause_prio",
 531                 .getter = mlxsw_reg_ppcnt_rx_pause_get,
 532         },
 533         {
 534                 .str = "rx_pause_duration_prio",
 535                 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
 536         },
 537         {
 538                 .str = "tx_pause_prio",
 539                 .getter = mlxsw_reg_ppcnt_tx_pause_get,
 540         },
 541         {
 542                 .str = "tx_pause_duration_prio",
 543                 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
 544         },
 545 };
 546
 547 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
 548
 549 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
 550         {
 551                 .str = "tc_transmit_queue_tc",
 552                 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
 553                 .cells_bytes = true,
 554         },
 555         {
 556                 .str = "tc_no_buffer_discard_uc_tc",
 557                 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
 558         },
 559 };
 560
 561 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
 562
 563 struct mlxsw_sp_port_stats {
 564         char str[ETH_GSTRING_LEN];
 565         u64 (*getter)(struct mlxsw_sp_port *mlxsw_sp_port);
 566 };
 567
 568 static u64
 569 mlxsw_sp_port_get_transceiver_overheat_stats(struct mlxsw_sp_port *mlxsw_sp_port)
 570 {
 571         struct mlxsw_sp_port_mapping port_mapping = mlxsw_sp_port->mapping;
 572         struct mlxsw_core *mlxsw_core = mlxsw_sp_port->mlxsw_sp->core;
 573         u64 stats;
 574         int err;
 575
 576         err = mlxsw_env_module_overheat_counter_get(mlxsw_core,
 577                                                     port_mapping.module,
 578                                                     &stats);
 579         if (err)
 580                 return mlxsw_sp_port->module_overheat_initial_val;
 581
 582         return stats - mlxsw_sp_port->module_overheat_initial_val;
 583 }
 584
 585 static struct mlxsw_sp_port_stats mlxsw_sp_port_transceiver_stats[] = {
 586         {
 587                 .str = "transceiver_overheat",
 588                 .getter = mlxsw_sp_port_get_transceiver_overheat_stats,
 589         },
 590 };
 591
 592 #define MLXSW_SP_PORT_HW_TRANSCEIVER_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_transceiver_stats)
 593
 594 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
 595                                          MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN + \
 596                                          MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
 597                                          MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN + \
 598                                          MLXSW_SP_PORT_HW_EXT_STATS_LEN + \
 599                                          MLXSW_SP_PORT_HW_DISCARD_STATS_LEN + \
 600                                          (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
 601                                           IEEE_8021QAZ_MAX_TCS) + \
 602                                          (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
 603                                           TC_MAX_QUEUE) + \
 604                                           MLXSW_SP_PORT_HW_TRANSCEIVER_STATS_LEN)
 605
 606 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
 607 {
 608         int i;
 609
 610         for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
 611                 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
 612                          mlxsw_sp_port_hw_prio_stats[i].str, prio);
 613                 *p += ETH_GSTRING_LEN;
 614         }
 615 }
 616
 617 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
 618 {
 619         int i;
 620
 621         for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
 622                 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
 623                          mlxsw_sp_port_hw_tc_stats[i].str, tc);
 624                 *p += ETH_GSTRING_LEN;
 625         }
 626 }
 627
 628 static void mlxsw_sp_port_get_strings(struct net_device *dev,
 629                                       u32 stringset, u8 *data)
 630 {
 631         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 632         u8 *p = data;
 633         int i;
 634
 635         switch (stringset) {
 636         case ETH_SS_STATS:
 637                 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
 638                         memcpy(p, mlxsw_sp_port_hw_stats[i].str,
 639                                ETH_GSTRING_LEN);
 640                         p += ETH_GSTRING_LEN;
 641                 }
 642
 643                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; i++) {
 644                         memcpy(p, mlxsw_sp_port_hw_rfc_2863_stats[i].str,
 645                                ETH_GSTRING_LEN);
 646                         p += ETH_GSTRING_LEN;
 647                 }
 648
 649                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
 650                         memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
 651                                ETH_GSTRING_LEN);
 652                         p += ETH_GSTRING_LEN;
 653                 }
 654
 655                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; i++) {
 656                         memcpy(p, mlxsw_sp_port_hw_rfc_3635_stats[i].str,
 657                                ETH_GSTRING_LEN);
 658                         p += ETH_GSTRING_LEN;
 659                 }
 660
 661                 for (i = 0; i < MLXSW_SP_PORT_HW_EXT_STATS_LEN; i++) {
 662                         memcpy(p, mlxsw_sp_port_hw_ext_stats[i].str,
 663                                ETH_GSTRING_LEN);
 664                         p += ETH_GSTRING_LEN;
 665                 }
 666
 667                 for (i = 0; i < MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; i++) {
 668                         memcpy(p, mlxsw_sp_port_hw_discard_stats[i].str,
 669                                ETH_GSTRING_LEN);
 670                         p += ETH_GSTRING_LEN;
 671                 }
 672
 673                 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
 674                         mlxsw_sp_port_get_prio_strings(&p, i);
 675
 676                 for (i = 0; i < TC_MAX_QUEUE; i++)
 677                         mlxsw_sp_port_get_tc_strings(&p, i);
 678
 679                 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_strings(&p);
 680
 681                 for (i = 0; i < MLXSW_SP_PORT_HW_TRANSCEIVER_STATS_LEN; i++) {
 682                         memcpy(p, mlxsw_sp_port_transceiver_stats[i].str,
 683                                ETH_GSTRING_LEN);
 684                         p += ETH_GSTRING_LEN;
 685                 }
 686                 break;
 687         }
 688 }
 689
 690 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
 691                                      enum ethtool_phys_id_state state)
 692 {
 693         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 694         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 695         char mlcr_pl[MLXSW_REG_MLCR_LEN];
 696         bool active;
 697
 698         switch (state) {
 699         case ETHTOOL_ID_ACTIVE:
 700                 active = true;
 701                 break;
 702         case ETHTOOL_ID_INACTIVE:
 703                 active = false;
 704                 break;
 705         default:
 706                 return -EOPNOTSUPP;
 707         }
 708
 709         mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
 710         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
 711 }
 712
 713 static int
 714 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
 715                                int *p_len, enum mlxsw_reg_ppcnt_grp grp)
 716 {
 717         switch (grp) {
 718         case MLXSW_REG_PPCNT_IEEE_8023_CNT:
 719                 *p_hw_stats = mlxsw_sp_port_hw_stats;
 720                 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
 721                 break;
 722         case MLXSW_REG_PPCNT_RFC_2863_CNT:
 723                 *p_hw_stats = mlxsw_sp_port_hw_rfc_2863_stats;
 724                 *p_len = MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
 725                 break;
 726         case MLXSW_REG_PPCNT_RFC_2819_CNT:
 727                 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
 728                 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
 729                 break;
 730         case MLXSW_REG_PPCNT_RFC_3635_CNT:
 731                 *p_hw_stats = mlxsw_sp_port_hw_rfc_3635_stats;
 732                 *p_len = MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
 733                 break;
 734         case MLXSW_REG_PPCNT_EXT_CNT:
 735                 *p_hw_stats = mlxsw_sp_port_hw_ext_stats;
 736                 *p_len = MLXSW_SP_PORT_HW_EXT_STATS_LEN;
 737                 break;
 738         case MLXSW_REG_PPCNT_DISCARD_CNT:
 739                 *p_hw_stats = mlxsw_sp_port_hw_discard_stats;
 740                 *p_len = MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
 741                 break;
 742         case MLXSW_REG_PPCNT_PRIO_CNT:
 743                 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
 744                 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
 745                 break;
 746         case MLXSW_REG_PPCNT_TC_CNT:
 747                 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
 748                 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
 749                 break;
 750         default:
 751                 WARN_ON(1);
 752                 return -EOPNOTSUPP;
 753         }
 754         return 0;
 755 }
 756
 757 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
 758                                       enum mlxsw_reg_ppcnt_grp grp, int prio,
 759                                       u64 *data, int data_index)
 760 {
 761         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 762         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 763         struct mlxsw_sp_port_hw_stats *hw_stats;
 764         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
 765         int i, len;
 766         int err;
 767
 768         err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
 769         if (err)
 770                 return;
 771         mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
 772         for (i = 0; i < len; i++) {
 773                 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
 774                 if (!hw_stats[i].cells_bytes)
 775                         continue;
 776                 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
 777                                                             data[data_index + i]);
 778         }
 779 }
 780
 781 static void __mlxsw_sp_port_get_env_stats(struct net_device *dev, u64 *data, int data_index,
 782                                           struct mlxsw_sp_port_stats *port_stats,
 783                                           int len)
 784 {
 785         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 786         int i;
 787
 788         for (i = 0; i < len; i++)
 789                 data[data_index + i] = port_stats[i].getter(mlxsw_sp_port);
 790 }
 791
 792 static void mlxsw_sp_port_get_stats(struct net_device *dev,
 793                                     struct ethtool_stats *stats, u64 *data)
 794 {
 795         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 796         int i, data_index = 0;
 797
 798         /* IEEE 802.3 Counters */
 799         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
 800                                   data, data_index);
 801         data_index = MLXSW_SP_PORT_HW_STATS_LEN;
 802
 803         /* RFC 2863 Counters */
 804         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2863_CNT, 0,
 805                                   data, data_index);
 806         data_index += MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
 807
 808         /* RFC 2819 Counters */
 809         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
 810                                   data, data_index);
 811         data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
 812
 813         /* RFC 3635 Counters */
 814         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_3635_CNT, 0,
 815                                   data, data_index);
 816         data_index += MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
 817
 818         /* Extended Counters */
 819         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
 820                                   data, data_index);
 821         data_index += MLXSW_SP_PORT_HW_EXT_STATS_LEN;
 822
 823         /* Discard Counters */
 824         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_DISCARD_CNT, 0,
 825                                   data, data_index);
 826         data_index += MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
 827
 828         /* Per-Priority Counters */
 829         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
 830                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
 831                                           data, data_index);
 832                 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
 833         }
 834
 835         /* Per-TC Counters */
 836         for (i = 0; i < TC_MAX_QUEUE; i++) {
 837                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
 838                                           data, data_index);
 839                 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
 840         }
 841
 842         /* PTP counters */
 843         mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats(mlxsw_sp_port,
 844                                                     data, data_index);
 845         data_index += mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
 846
 847         /* Transceiver counters */
 848         __mlxsw_sp_port_get_env_stats(dev, data, data_index, mlxsw_sp_port_transceiver_stats,
 849                                       MLXSW_SP_PORT_HW_TRANSCEIVER_STATS_LEN);
 850         data_index += MLXSW_SP_PORT_HW_TRANSCEIVER_STATS_LEN;
 851 }
 852
 853 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
 854 {
 855         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 856
 857         switch (sset) {
 858         case ETH_SS_STATS:
 859                 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN +
 860                         mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
 861         default:
 862                 return -EOPNOTSUPP;
 863         }
 864 }
 865
 866 static void
 867 mlxsw_sp_port_get_link_supported(struct mlxsw_sp *mlxsw_sp, u32 eth_proto_cap,
 868                                  struct ethtool_link_ksettings *cmd)
 869 {
 870         const struct mlxsw_sp_port_type_speed_ops *ops;
 871
 872         ops = mlxsw_sp->port_type_speed_ops;
 873
 874         ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
 875         ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
 876         ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
 877
 878         ops->from_ptys_supported_port(mlxsw_sp, eth_proto_cap, cmd);
 879         ops->from_ptys_link(mlxsw_sp, eth_proto_cap,
 880                             cmd->link_modes.supported);
 881 }
 882
 883 static void
 884 mlxsw_sp_port_get_link_advertise(struct mlxsw_sp *mlxsw_sp,
 885                                  u32 eth_proto_admin, bool autoneg,
 886                                  struct ethtool_link_ksettings *cmd)
 887 {
 888         const struct mlxsw_sp_port_type_speed_ops *ops;
 889
 890         ops = mlxsw_sp->port_type_speed_ops;
 891
 892         if (!autoneg)
 893                 return;
 894
 895         ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
 896         ops->from_ptys_link(mlxsw_sp, eth_proto_admin,
 897                             cmd->link_modes.advertising);
 898 }
 899
 900 static u8
 901 mlxsw_sp_port_connector_port(enum mlxsw_reg_ptys_connector_type connector_type)
 902 {
 903         switch (connector_type) {
 904         case MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR:
 905                 return PORT_OTHER;
 906         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE:
 907                 return PORT_NONE;
 908         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP:
 909                 return PORT_TP;
 910         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI:
 911                 return PORT_AUI;
 912         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC:
 913                 return PORT_BNC;
 914         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII:
 915                 return PORT_MII;
 916         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE:
 917                 return PORT_FIBRE;
 918         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA:
 919                 return PORT_DA;
 920         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER:
 921                 return PORT_OTHER;
 922         default:
 923                 WARN_ON_ONCE(1);
 924                 return PORT_OTHER;
 925         }
 926 }
 927
 928 static int mlxsw_sp_port_ptys_query(struct mlxsw_sp_port *mlxsw_sp_port,
 929                                     u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
 930                                     u32 *p_eth_proto_oper, u8 *p_connector_type)
 931 {
 932         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 933         const struct mlxsw_sp_port_type_speed_ops *ops;
 934         char ptys_pl[MLXSW_REG_PTYS_LEN];
 935         int err;
 936
 937         ops = mlxsw_sp->port_type_speed_ops;
 938
 939         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 0, false);
 940         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
 941         if (err)
 942                 return err;
 943
 944         ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, p_eth_proto_cap, p_eth_proto_admin,
 945                                  p_eth_proto_oper);
 946         if (p_connector_type)
 947                 *p_connector_type = mlxsw_reg_ptys_connector_type_get(ptys_pl);
 948         return 0;
 949 }
 950
 951 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
 952                                             struct ethtool_link_ksettings *cmd)
 953 {
 954         u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
 955         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 956         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 957         const struct mlxsw_sp_port_type_speed_ops *ops;
 958         u8 connector_type;
 959         bool autoneg;
 960         int err;
 961
 962         err = mlxsw_sp_port_ptys_query(mlxsw_sp_port, &eth_proto_cap, &eth_proto_admin,
 963                                        &eth_proto_oper, &connector_type);
 964         if (err)
 965                 return err;
 966
 967         ops = mlxsw_sp->port_type_speed_ops;
 968         autoneg = mlxsw_sp_port->link.autoneg;
 969
 970         mlxsw_sp_port_get_link_supported(mlxsw_sp, eth_proto_cap, cmd);
 971
 972         mlxsw_sp_port_get_link_advertise(mlxsw_sp, eth_proto_admin, autoneg, cmd);
 973
 974         cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
 975         cmd->base.port = mlxsw_sp_port_connector_port(connector_type);
 976         ops->from_ptys_link_mode(mlxsw_sp, netif_carrier_ok(dev),
 977                                  eth_proto_oper, cmd);
 978
 979         return 0;
 980 }
 981
 982 static int
 983 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
 984                                  const struct ethtool_link_ksettings *cmd)
 985 {
 986         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 987         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 988         const struct mlxsw_sp_port_type_speed_ops *ops;
 989         char ptys_pl[MLXSW_REG_PTYS_LEN];
 990         u32 eth_proto_cap, eth_proto_new;
 991         bool autoneg;
 992         int err;
 993
 994         ops = mlxsw_sp->port_type_speed_ops;
 995
 996         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
 997                                0, false);
 998         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
 999         if (err)
1000                 return err;
1001         ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, &eth_proto_cap, NULL, NULL);
1002
1003         autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
1004         eth_proto_new = autoneg ?
1005                 ops->to_ptys_advert_link(mlxsw_sp, cmd) :
1006                 ops->to_ptys_speed_lanes(mlxsw_sp, mlxsw_sp_port->mapping.width,
1007                                          cmd);
1008
1009         eth_proto_new = eth_proto_new & eth_proto_cap;
1010         if (!eth_proto_new) {
1011                 netdev_err(dev, "No supported speed or lanes requested\n");
1012                 return -EINVAL;
1013         }
1014
1015         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1016                                eth_proto_new, autoneg);
1017         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1018         if (err)
1019                 return err;
1020
1021         mlxsw_sp_port->link.autoneg = autoneg;
1022
1023         if (!netif_running(dev))
1024                 return 0;
1025
1026         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1027         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1028
1029         return 0;
1030 }
1031
1032 static int mlxsw_sp_get_module_info(struct net_device *netdev,
1033                                     struct ethtool_modinfo *modinfo)
1034 {
1035         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
1036         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1037
1038         return mlxsw_env_get_module_info(mlxsw_sp->core,
1039                                          mlxsw_sp_port->mapping.module,
1040                                          modinfo);
1041 }
1042
1043 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
1044                                       struct ethtool_eeprom *ee, u8 *data)
1045 {
1046         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
1047         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1048
1049         return mlxsw_env_get_module_eeprom(netdev, mlxsw_sp->core,
1050                                            mlxsw_sp_port->mapping.module, ee,
1051                                            data);
1052 }
1053
1054 static int
1055 mlxsw_sp_get_module_eeprom_by_page(struct net_device *dev,
1056                                    const struct ethtool_module_eeprom *page,
1057                                    struct netlink_ext_ack *extack)
1058 {
1059         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1060         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1061         u8 module = mlxsw_sp_port->mapping.module;
1062
1063         return mlxsw_env_get_module_eeprom_by_page(mlxsw_sp->core, module, page,
1064                                                    extack);
1065 }
1066
1067 static int
1068 mlxsw_sp_get_ts_info(struct net_device *netdev, struct ethtool_ts_info *info)
1069 {
1070         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
1071         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1072
1073         return mlxsw_sp->ptp_ops->get_ts_info(mlxsw_sp, info);
1074 }
1075
1076 static void
1077 mlxsw_sp_get_eth_phy_stats(struct net_device *dev,
1078                            struct ethtool_eth_phy_stats *phy_stats)
1079 {
1080         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1081
1082         if (mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1083                                         0, ppcnt_pl))
1084                 return;
1085
1086         phy_stats->SymbolErrorDuringCarrier =
1087                 mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get(ppcnt_pl);
1088 }
1089
1090 static void
1091 mlxsw_sp_get_eth_mac_stats(struct net_device *dev,
1092                            struct ethtool_eth_mac_stats *mac_stats)
1093 {
1094         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1095
1096         if (mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1097                                         0, ppcnt_pl))
1098                 return;
1099
1100         mac_stats->FramesTransmittedOK =
1101                 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1102         mac_stats->FramesReceivedOK =
1103                 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1104         mac_stats->FrameCheckSequenceErrors =
1105                 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1106         mac_stats->AlignmentErrors =
1107                 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1108         mac_stats->OctetsTransmittedOK =
1109                 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1110         mac_stats->OctetsReceivedOK =
1111                 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1112         mac_stats->MulticastFramesXmittedOK =
1113                 mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get(ppcnt_pl);
1114         mac_stats->BroadcastFramesXmittedOK =
1115                 mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get(ppcnt_pl);
1116         mac_stats->MulticastFramesReceivedOK =
1117                 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1118         mac_stats->BroadcastFramesReceivedOK =
1119                 mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get(ppcnt_pl);
1120         mac_stats->InRangeLengthErrors =
1121                 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl);
1122         mac_stats->OutOfRangeLengthField =
1123                 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl);
1124         mac_stats->FrameTooLongErrors =
1125                 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl);
1126 }
1127
1128 static void
1129 mlxsw_sp_get_eth_ctrl_stats(struct net_device *dev,
1130                             struct ethtool_eth_ctrl_stats *ctrl_stats)
1131 {
1132         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1133
1134         if (mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1135                                         0, ppcnt_pl))
1136                 return;
1137
1138         ctrl_stats->MACControlFramesTransmitted =
1139                 mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get(ppcnt_pl);
1140         ctrl_stats->MACControlFramesReceived =
1141                 mlxsw_reg_ppcnt_a_mac_control_frames_received_get(ppcnt_pl);
1142         ctrl_stats->UnsupportedOpcodesReceived =
1143                 mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get(ppcnt_pl);
1144 }
1145
1146 static const struct ethtool_rmon_hist_range mlxsw_rmon_ranges[] = {
1147         {    0,    64 },
1148         {   65,   127 },
1149         {  128,   255 },
1150         {  256,   511 },
1151         {  512,  1023 },
1152         { 1024,  1518 },
1153         { 1519,  2047 },
1154         { 2048,  4095 },
1155         { 4096,  8191 },
1156         { 8192, 10239 },
1157         {}
1158 };
1159
1160 static void
1161 mlxsw_sp_get_rmon_stats(struct net_device *dev,
1162                         struct ethtool_rmon_stats *rmon,
1163                         const struct ethtool_rmon_hist_range **ranges)
1164 {
1165         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1166
1167         if (mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_RFC_2819_CNT,
1168                                         0, ppcnt_pl))
1169                 return;
1170
1171         rmon->undersize_pkts =
1172                 mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get(ppcnt_pl);
1173         rmon->oversize_pkts =
1174                 mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get(ppcnt_pl);
1175         rmon->fragments =
1176                 mlxsw_reg_ppcnt_ether_stats_fragments_get(ppcnt_pl);
1177
1178         rmon->hist[0] = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get(ppcnt_pl);
1179         rmon->hist[1] =
1180                 mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get(ppcnt_pl);
1181         rmon->hist[2] =
1182                 mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get(ppcnt_pl);
1183         rmon->hist[3] =
1184                 mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get(ppcnt_pl);
1185         rmon->hist[4] =
1186                 mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get(ppcnt_pl);
1187         rmon->hist[5] =
1188                 mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get(ppcnt_pl);
1189         rmon->hist[6] =
1190                 mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get(ppcnt_pl);
1191         rmon->hist[7] =
1192                 mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get(ppcnt_pl);
1193         rmon->hist[8] =
1194                 mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get(ppcnt_pl);
1195         rmon->hist[9] =
1196                 mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get(ppcnt_pl);
1197
1198         *ranges = mlxsw_rmon_ranges;
1199 }
1200
1201 static int mlxsw_sp_reset(struct net_device *dev, u32 *flags)
1202 {
1203         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1204         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1205         u8 module = mlxsw_sp_port->mapping.module;
1206
1207         return mlxsw_env_reset_module(dev, mlxsw_sp->core, module, flags);
1208 }
1209
1210 static int
1211 mlxsw_sp_get_module_power_mode(struct net_device *dev,
1212                                struct ethtool_module_power_mode_params *params,
1213                                struct netlink_ext_ack *extack)
1214 {
1215         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1216         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1217         u8 module = mlxsw_sp_port->mapping.module;
1218
1219         return mlxsw_env_get_module_power_mode(mlxsw_sp->core, module, params,
1220                                                extack);
1221 }
1222
1223 static int
1224 mlxsw_sp_set_module_power_mode(struct net_device *dev,
1225                                const struct ethtool_module_power_mode_params *params,
1226                                struct netlink_ext_ack *extack)
1227 {
1228         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1229         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1230         u8 module = mlxsw_sp_port->mapping.module;
1231
1232         return mlxsw_env_set_module_power_mode(mlxsw_sp->core, module,
1233                                                params->policy, extack);
1234 }
1235
1236 const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1237         .cap_link_lanes_supported       = true,
1238         .get_drvinfo                    = mlxsw_sp_port_get_drvinfo,
1239         .get_link                       = ethtool_op_get_link,
1240         .get_link_ext_state             = mlxsw_sp_port_get_link_ext_state,
1241         .get_pauseparam                 = mlxsw_sp_port_get_pauseparam,
1242         .set_pauseparam                 = mlxsw_sp_port_set_pauseparam,
1243         .get_strings                    = mlxsw_sp_port_get_strings,
1244         .set_phys_id                    = mlxsw_sp_port_set_phys_id,
1245         .get_ethtool_stats              = mlxsw_sp_port_get_stats,
1246         .get_sset_count                 = mlxsw_sp_port_get_sset_count,
1247         .get_link_ksettings             = mlxsw_sp_port_get_link_ksettings,
1248         .set_link_ksettings             = mlxsw_sp_port_set_link_ksettings,
1249         .get_module_info                = mlxsw_sp_get_module_info,
1250         .get_module_eeprom              = mlxsw_sp_get_module_eeprom,
1251         .get_module_eeprom_by_page      = mlxsw_sp_get_module_eeprom_by_page,
1252         .get_ts_info                    = mlxsw_sp_get_ts_info,
1253         .get_eth_phy_stats              = mlxsw_sp_get_eth_phy_stats,
1254         .get_eth_mac_stats              = mlxsw_sp_get_eth_mac_stats,
1255         .get_eth_ctrl_stats             = mlxsw_sp_get_eth_ctrl_stats,
1256         .get_rmon_stats                 = mlxsw_sp_get_rmon_stats,
1257         .reset                          = mlxsw_sp_reset,
1258         .get_module_power_mode          = mlxsw_sp_get_module_power_mode,
1259         .set_module_power_mode          = mlxsw_sp_set_module_power_mode,
1260 };
1261
1262 struct mlxsw_sp1_port_link_mode {
1263         enum ethtool_link_mode_bit_indices mask_ethtool;
1264         u32 mask;
1265         u32 speed;
1266 };
1267
1268 static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = {
1269         {
1270                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1271                                   MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1272                 .mask_ethtool   = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1273                 .speed          = SPEED_1000,
1274         },
1275         {
1276                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1277                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1278                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
1279                 .speed          = SPEED_10000,
1280         },
1281         {
1282                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1283                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1284                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1285                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1286                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1287                 .speed          = SPEED_10000,
1288         },
1289         {
1290                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1291                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1292                 .speed          = SPEED_40000,
1293         },
1294         {
1295                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1296                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1297                 .speed          = SPEED_40000,
1298         },
1299         {
1300                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1301                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1302                 .speed          = SPEED_40000,
1303         },
1304         {
1305                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1306                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1307                 .speed          = SPEED_40000,
1308         },
1309         {
1310                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
1311                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1312                 .speed          = SPEED_25000,
1313         },
1314         {
1315                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
1316                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1317                 .speed          = SPEED_25000,
1318         },
1319         {
1320                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1321                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1322                 .speed          = SPEED_25000,
1323         },
1324         {
1325                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
1326                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1327                 .speed          = SPEED_50000,
1328         },
1329         {
1330                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1331                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1332                 .speed          = SPEED_50000,
1333         },
1334         {
1335                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
1336                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1337                 .speed          = SPEED_50000,
1338         },
1339         {
1340                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
1341                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1342                 .speed          = SPEED_100000,
1343         },
1344         {
1345                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
1346                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1347                 .speed          = SPEED_100000,
1348         },
1349         {
1350                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
1351                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1352                 .speed          = SPEED_100000,
1353         },
1354         {
1355                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1356                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
1357                 .speed          = SPEED_100000,
1358         },
1359 };
1360
1361 #define MLXSW_SP1_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp1_port_link_mode)
1362
1363 static void
1364 mlxsw_sp1_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
1365                                    u32 ptys_eth_proto,
1366                                    struct ethtool_link_ksettings *cmd)
1367 {
1368         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1369                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1370                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1371                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1372                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1373                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1374                 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
1375
1376         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1377                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1378                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1379                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1380                               MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1381                 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
1382 }
1383
1384 static void
1385 mlxsw_sp1_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
1386                          unsigned long *mode)
1387 {
1388         int i;
1389
1390         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1391                 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
1392                         __set_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
1393                                   mode);
1394         }
1395 }
1396
1397 static u32
1398 mlxsw_sp1_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
1399 {
1400         int i;
1401
1402         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1403                 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
1404                         return mlxsw_sp1_port_link_mode[i].speed;
1405         }
1406
1407         return SPEED_UNKNOWN;
1408 }
1409
1410 static void
1411 mlxsw_sp1_from_ptys_link_mode(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
1412                               u32 ptys_eth_proto,
1413                               struct ethtool_link_ksettings *cmd)
1414 {
1415         struct mlxsw_sp1_port_link_mode link;
1416         int i;
1417
1418         cmd->base.speed = SPEED_UNKNOWN;
1419         cmd->base.duplex = DUPLEX_UNKNOWN;
1420         cmd->lanes = 0;
1421
1422         if (!carrier_ok)
1423                 return;
1424
1425         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1426                 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask) {
1427                         link = mlxsw_sp1_port_link_mode[i];
1428                         ethtool_params_from_link_mode(cmd,
1429                                                       link.mask_ethtool);
1430                 }
1431         }
1432 }
1433
1434 static int mlxsw_sp1_ptys_max_speed(struct mlxsw_sp_port *mlxsw_sp_port, u32 *p_max_speed)
1435 {
1436         u32 eth_proto_cap;
1437         u32 max_speed = 0;
1438         int err;
1439         int i;
1440
1441         err = mlxsw_sp_port_ptys_query(mlxsw_sp_port, &eth_proto_cap, NULL, NULL, NULL);
1442         if (err)
1443                 return err;
1444
1445         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1446                 if ((eth_proto_cap & mlxsw_sp1_port_link_mode[i].mask) &&
1447                     mlxsw_sp1_port_link_mode[i].speed > max_speed)
1448                         max_speed = mlxsw_sp1_port_link_mode[i].speed;
1449         }
1450
1451         *p_max_speed = max_speed;
1452         return 0;
1453 }
1454
1455 static u32
1456 mlxsw_sp1_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp,
1457                               const struct ethtool_link_ksettings *cmd)
1458 {
1459         u32 ptys_proto = 0;
1460         int i;
1461
1462         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1463                 if (test_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
1464                              cmd->link_modes.advertising))
1465                         ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
1466         }
1467         return ptys_proto;
1468 }
1469
1470 static u32 mlxsw_sp1_to_ptys_speed_lanes(struct mlxsw_sp *mlxsw_sp, u8 width,
1471                                          const struct ethtool_link_ksettings *cmd)
1472 {
1473         u32 ptys_proto = 0;
1474         int i;
1475
1476         if (cmd->lanes > width)
1477                 return ptys_proto;
1478
1479         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1480                 if (cmd->base.speed == mlxsw_sp1_port_link_mode[i].speed)
1481                         ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
1482         }
1483         return ptys_proto;
1484 }
1485
1486 static void
1487 mlxsw_sp1_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
1488                             u16 local_port, u32 proto_admin, bool autoneg)
1489 {
1490         mlxsw_reg_ptys_eth_pack(payload, local_port, proto_admin, autoneg);
1491 }
1492
1493 static void
1494 mlxsw_sp1_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
1495                               u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
1496                               u32 *p_eth_proto_oper)
1497 {
1498         mlxsw_reg_ptys_eth_unpack(payload, p_eth_proto_cap, p_eth_proto_admin,
1499                                   p_eth_proto_oper);
1500 }
1501
1502 static u32 mlxsw_sp1_ptys_proto_cap_masked_get(u32 eth_proto_cap)
1503 {
1504         u32 ptys_proto_cap_masked = 0;
1505         int i;
1506
1507         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1508                 if (mlxsw_sp1_port_link_mode[i].mask & eth_proto_cap)
1509                         ptys_proto_cap_masked |=
1510                                 mlxsw_sp1_port_link_mode[i].mask;
1511         }
1512
1513         return ptys_proto_cap_masked;
1514 }
1515
1516 const struct mlxsw_sp_port_type_speed_ops mlxsw_sp1_port_type_speed_ops = {
1517         .from_ptys_supported_port       = mlxsw_sp1_from_ptys_supported_port,
1518         .from_ptys_link                 = mlxsw_sp1_from_ptys_link,
1519         .from_ptys_speed                = mlxsw_sp1_from_ptys_speed,
1520         .from_ptys_link_mode            = mlxsw_sp1_from_ptys_link_mode,
1521         .ptys_max_speed                 = mlxsw_sp1_ptys_max_speed,
1522         .to_ptys_advert_link            = mlxsw_sp1_to_ptys_advert_link,
1523         .to_ptys_speed_lanes            = mlxsw_sp1_to_ptys_speed_lanes,
1524         .reg_ptys_eth_pack              = mlxsw_sp1_reg_ptys_eth_pack,
1525         .reg_ptys_eth_unpack            = mlxsw_sp1_reg_ptys_eth_unpack,
1526         .ptys_proto_cap_masked_get      = mlxsw_sp1_ptys_proto_cap_masked_get,
1527 };
1528
1529 static const enum ethtool_link_mode_bit_indices
1530 mlxsw_sp2_mask_ethtool_sgmii_100m[] = {
1531         ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1532 };
1533
1534 #define MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN \
1535         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_sgmii_100m)
1536
1537 static const enum ethtool_link_mode_bit_indices
1538 mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] = {
1539         ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1540         ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1541 };
1542
1543 #define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \
1544         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii)
1545
1546 static const enum ethtool_link_mode_bit_indices
1547 mlxsw_sp2_mask_ethtool_5gbase_r[] = {
1548         ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
1549 };
1550
1551 #define MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN \
1552         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_5gbase_r)
1553
1554 static const enum ethtool_link_mode_bit_indices
1555 mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g[] = {
1556         ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1557         ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1558         ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
1559         ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
1560         ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1561         ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
1562         ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
1563 };
1564
1565 #define MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN \
1566         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g)
1567
1568 static const enum ethtool_link_mode_bit_indices
1569 mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g[] = {
1570         ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1571         ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1572         ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1573         ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1574 };
1575
1576 #define MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN \
1577         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g)
1578
1579 static const enum ethtool_link_mode_bit_indices
1580 mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr[] = {
1581         ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1582         ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1583         ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1584 };
1585
1586 #define MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN \
1587         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr)
1588
1589 static const enum ethtool_link_mode_bit_indices
1590 mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2[] = {
1591         ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1592         ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1593         ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1594 };
1595
1596 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN \
1597         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2)
1598
1599 static const enum ethtool_link_mode_bit_indices
1600 mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr[] = {
1601         ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
1602         ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
1603         ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
1604         ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
1605         ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
1606 };
1607
1608 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN \
1609         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr)
1610
1611 static const enum ethtool_link_mode_bit_indices
1612 mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4[] = {
1613         ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1614         ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1615         ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1616         ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
1617 };
1618
1619 #define MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN \
1620         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4)
1621
1622 static const enum ethtool_link_mode_bit_indices
1623 mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2[] = {
1624         ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
1625         ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
1626         ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
1627         ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
1628         ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
1629 };
1630
1631 #define MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN \
1632         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2)
1633
1634 static const enum ethtool_link_mode_bit_indices
1635 mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = {
1636         ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
1637         ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
1638         ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
1639         ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
1640         ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
1641 };
1642
1643 #define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \
1644         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4)
1645
1646 static const enum ethtool_link_mode_bit_indices
1647 mlxsw_sp2_mask_ethtool_400gaui_8[] = {
1648         ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
1649         ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
1650         ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
1651         ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
1652         ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,
1653 };
1654
1655 #define MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN \
1656         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_400gaui_8)
1657
1658 #define MLXSW_SP_PORT_MASK_WIDTH_1X     BIT(0)
1659 #define MLXSW_SP_PORT_MASK_WIDTH_2X     BIT(1)
1660 #define MLXSW_SP_PORT_MASK_WIDTH_4X     BIT(2)
1661 #define MLXSW_SP_PORT_MASK_WIDTH_8X     BIT(3)
1662
1663 static u8 mlxsw_sp_port_mask_width_get(u8 width)
1664 {
1665         switch (width) {
1666         case 1:
1667                 return MLXSW_SP_PORT_MASK_WIDTH_1X;
1668         case 2:
1669                 return MLXSW_SP_PORT_MASK_WIDTH_2X;
1670         case 4:
1671                 return MLXSW_SP_PORT_MASK_WIDTH_4X;
1672         case 8:
1673                 return MLXSW_SP_PORT_MASK_WIDTH_8X;
1674         default:
1675                 WARN_ON_ONCE(1);
1676                 return 0;
1677         }
1678 }
1679
1680 struct mlxsw_sp2_port_link_mode {
1681         const enum ethtool_link_mode_bit_indices *mask_ethtool;
1682         int m_ethtool_len;
1683         u32 mask;
1684         u32 speed;
1685         u32 width;
1686         u8 mask_sup_width;
1687 };
1688
1689 static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
1690         {
1691                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M,
1692                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_sgmii_100m,
1693                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN,
1694                 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
1695                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
1696                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
1697                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
1698                 .speed          = SPEED_100,
1699                 .width          = 1,
1700         },
1701         {
1702                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII,
1703                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_1000base_x_sgmii,
1704                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN,
1705                 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
1706                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
1707                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
1708                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
1709                 .speed          = SPEED_1000,
1710                 .width          = 1,
1711         },
1712         {
1713                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R,
1714                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_5gbase_r,
1715                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN,
1716                 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
1717                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
1718                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
1719                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
1720                 .speed          = SPEED_5000,
1721                 .width          = 1,
1722         },
1723         {
1724                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G,
1725                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g,
1726                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN,
1727                 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
1728                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
1729                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
1730                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
1731                 .speed          = SPEED_10000,
1732                 .width          = 1,
1733         },
1734         {
1735                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G,
1736                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g,
1737                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN,
1738                 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_4X |
1739                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
1740                 .speed          = SPEED_40000,
1741                 .width          = 4,
1742         },
1743         {
1744                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR,
1745                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr,
1746                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN,
1747                 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
1748                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
1749                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
1750                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
1751                 .speed          = SPEED_25000,
1752                 .width          = 1,
1753         },
1754         {
1755                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
1756                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2,
1757                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN,
1758                 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_2X |
1759                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
1760                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
1761                 .speed          = SPEED_50000,
1762                 .width          = 2,
1763         },
1764         {
1765                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR,
1766                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr,
1767                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN,
1768                 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X,
1769                 .speed          = SPEED_50000,
1770                 .width          = 1,
1771         },
1772         {
1773                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4,
1774                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4,
1775                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN,
1776                 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_4X |
1777                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
1778                 .speed          = SPEED_100000,
1779                 .width          = 4,
1780         },
1781         {
1782                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2,
1783                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2,
1784                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN,
1785                 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_2X,
1786                 .speed          = SPEED_100000,
1787                 .width          = 2,
1788         },
1789         {
1790                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4,
1791                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4,
1792                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN,
1793                 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_4X |
1794                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
1795                 .speed          = SPEED_200000,
1796                 .width          = 4,
1797         },
1798         {
1799                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8,
1800                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_400gaui_8,
1801                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN,
1802                 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_8X,
1803                 .speed          = SPEED_400000,
1804                 .width          = 8,
1805         },
1806 };
1807
1808 #define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)
1809
1810 static void
1811 mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
1812                                    u32 ptys_eth_proto,
1813                                    struct ethtool_link_ksettings *cmd)
1814 {
1815         ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
1816         ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
1817 }
1818
1819 static void
1820 mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
1821                           unsigned long *mode)
1822 {
1823         int i;
1824
1825         for (i = 0; i < link_mode->m_ethtool_len; i++)
1826                 __set_bit(link_mode->mask_ethtool[i], mode);
1827 }
1828
1829 static void
1830 mlxsw_sp2_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
1831                          unsigned long *mode)
1832 {
1833         int i;
1834
1835         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
1836                 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask)
1837                         mlxsw_sp2_set_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
1838                                                   mode);
1839         }
1840 }
1841
1842 static u32
1843 mlxsw_sp2_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
1844 {
1845         int i;
1846
1847         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
1848                 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask)
1849                         return mlxsw_sp2_port_link_mode[i].speed;
1850         }
1851
1852         return SPEED_UNKNOWN;
1853 }
1854
1855 static void
1856 mlxsw_sp2_from_ptys_link_mode(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
1857                               u32 ptys_eth_proto,
1858                               struct ethtool_link_ksettings *cmd)
1859 {
1860         struct mlxsw_sp2_port_link_mode link;
1861         int i;
1862
1863         cmd->base.speed = SPEED_UNKNOWN;
1864         cmd->base.duplex = DUPLEX_UNKNOWN;
1865         cmd->lanes = 0;
1866
1867         if (!carrier_ok)
1868                 return;
1869
1870         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
1871                 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) {
1872                         link = mlxsw_sp2_port_link_mode[i];
1873                         ethtool_params_from_link_mode(cmd,
1874                                                       link.mask_ethtool[1]);
1875                 }
1876         }
1877 }
1878
1879 static int mlxsw_sp2_ptys_max_speed(struct mlxsw_sp_port *mlxsw_sp_port, u32 *p_max_speed)
1880 {
1881         u32 eth_proto_cap;
1882         u32 max_speed = 0;
1883         int err;
1884         int i;
1885
1886         err = mlxsw_sp_port_ptys_query(mlxsw_sp_port, &eth_proto_cap, NULL, NULL, NULL);
1887         if (err)
1888                 return err;
1889
1890         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
1891                 if ((eth_proto_cap & mlxsw_sp2_port_link_mode[i].mask) &&
1892                     mlxsw_sp2_port_link_mode[i].speed > max_speed)
1893                         max_speed = mlxsw_sp2_port_link_mode[i].speed;
1894         }
1895
1896         *p_max_speed = max_speed;
1897         return 0;
1898 }
1899
1900 static bool
1901 mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
1902                            const unsigned long *mode)
1903 {
1904         int cnt = 0;
1905         int i;
1906
1907         for (i = 0; i < link_mode->m_ethtool_len; i++) {
1908                 if (test_bit(link_mode->mask_ethtool[i], mode))
1909                         cnt++;
1910         }
1911
1912         return cnt == link_mode->m_ethtool_len;
1913 }
1914
1915 static u32
1916 mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp,
1917                               const struct ethtool_link_ksettings *cmd)
1918 {
1919         u32 ptys_proto = 0;
1920         int i;
1921
1922         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
1923                 if (mlxsw_sp2_test_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
1924                                                cmd->link_modes.advertising))
1925                         ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
1926         }
1927         return ptys_proto;
1928 }
1929
1930 static u32 mlxsw_sp2_to_ptys_speed_lanes(struct mlxsw_sp *mlxsw_sp, u8 width,
1931                                          const struct ethtool_link_ksettings *cmd)
1932 {
1933         u8 mask_width = mlxsw_sp_port_mask_width_get(width);
1934         struct mlxsw_sp2_port_link_mode link_mode;
1935         u32 ptys_proto = 0;
1936         int i;
1937
1938         if (cmd->lanes > width)
1939                 return ptys_proto;
1940
1941         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
1942                 if (cmd->base.speed == mlxsw_sp2_port_link_mode[i].speed) {
1943                         link_mode = mlxsw_sp2_port_link_mode[i];
1944
1945                         if (!cmd->lanes) {
1946                                 /* If number of lanes was not set by user space,
1947                                  * choose the link mode that supports the width
1948                                  * of the port.
1949                                  */
1950                                 if (mask_width & link_mode.mask_sup_width)
1951                                         ptys_proto |= link_mode.mask;
1952                         } else if (cmd->lanes == link_mode.width) {
1953                                 /* Else if the number of lanes was set, choose
1954                                  * the link mode that its actual width equals to
1955                                  * it.
1956                                  */
1957                                 ptys_proto |= link_mode.mask;
1958                         }
1959                 }
1960         }
1961         return ptys_proto;
1962 }
1963
1964 static void
1965 mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
1966                             u16 local_port, u32 proto_admin,
1967                             bool autoneg)
1968 {
1969         mlxsw_reg_ptys_ext_eth_pack(payload, local_port, proto_admin, autoneg);
1970 }
1971
1972 static void
1973 mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
1974                               u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
1975                               u32 *p_eth_proto_oper)
1976 {
1977         mlxsw_reg_ptys_ext_eth_unpack(payload, p_eth_proto_cap,
1978                                       p_eth_proto_admin, p_eth_proto_oper);
1979 }
1980
1981 static u32 mlxsw_sp2_ptys_proto_cap_masked_get(u32 eth_proto_cap)
1982 {
1983         u32 ptys_proto_cap_masked = 0;
1984         int i;
1985
1986         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
1987                 if (mlxsw_sp2_port_link_mode[i].mask & eth_proto_cap)
1988                         ptys_proto_cap_masked |=
1989                                 mlxsw_sp2_port_link_mode[i].mask;
1990         }
1991
1992         return ptys_proto_cap_masked;
1993 }
1994
1995 const struct mlxsw_sp_port_type_speed_ops mlxsw_sp2_port_type_speed_ops = {
1996         .from_ptys_supported_port       = mlxsw_sp2_from_ptys_supported_port,
1997         .from_ptys_link                 = mlxsw_sp2_from_ptys_link,
1998         .from_ptys_speed                = mlxsw_sp2_from_ptys_speed,
1999         .from_ptys_link_mode            = mlxsw_sp2_from_ptys_link_mode,
2000         .ptys_max_speed                 = mlxsw_sp2_ptys_max_speed,
2001         .to_ptys_advert_link            = mlxsw_sp2_to_ptys_advert_link,
2002         .to_ptys_speed_lanes            = mlxsw_sp2_to_ptys_speed_lanes,
2003         .reg_ptys_eth_pack              = mlxsw_sp2_reg_ptys_eth_pack,
2004         .reg_ptys_eth_unpack            = mlxsw_sp2_reg_ptys_eth_unpack,
2005         .ptys_proto_cap_masked_get      = mlxsw_sp2_ptys_proto_cap_masked_get,
2006 };