1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/ethtool.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/if_bridge.h>
16 #include <linux/workqueue.h>
17 #include <linux/jiffies.h>
18 #include <linux/bitops.h>
19 #include <linux/list.h>
20 #include <linux/notifier.h>
21 #include <linux/dcbnl.h>
22 #include <linux/inetdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/jhash.h>
25 #include <linux/log2.h>
26 #include <net/switchdev.h>
27 #include <net/pkt_cls.h>
28 #include <net/tc_act/tc_mirred.h>
29 #include <net/netevent.h>
30 #include <net/tc_act/tc_sample.h>
31 #include <net/addrconf.h>
41 #include "spectrum_cnt.h"
42 #include "spectrum_dpipe.h"
43 #include "spectrum_acl_flex_actions.h"
44 #include "spectrum_span.h"
45 #include "spectrum_ptp.h"
46 #include "spectrum_trap.h"
47 #include "../mlxfw/mlxfw.h"
49 #define MLXSW_SP1_FWREV_MAJOR 13
50 #define MLXSW_SP1_FWREV_MINOR 2000
51 #define MLXSW_SP1_FWREV_SUBMINOR 2714
52 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
54 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
55 .major = MLXSW_SP1_FWREV_MAJOR,
56 .minor = MLXSW_SP1_FWREV_MINOR,
57 .subminor = MLXSW_SP1_FWREV_SUBMINOR,
58 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
61 #define MLXSW_SP1_FW_FILENAME \
62 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
63 "." __stringify(MLXSW_SP1_FWREV_MINOR) \
64 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
66 #define MLXSW_SP2_FWREV_MAJOR 29
67 #define MLXSW_SP2_FWREV_MINOR 2000
68 #define MLXSW_SP2_FWREV_SUBMINOR 2714
70 static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = {
71 .major = MLXSW_SP2_FWREV_MAJOR,
72 .minor = MLXSW_SP2_FWREV_MINOR,
73 .subminor = MLXSW_SP2_FWREV_SUBMINOR,
76 #define MLXSW_SP2_FW_FILENAME \
77 "mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \
78 "." __stringify(MLXSW_SP2_FWREV_MINOR) \
79 "." __stringify(MLXSW_SP2_FWREV_SUBMINOR) ".mfa2"
81 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
82 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
83 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3";
84 static const char mlxsw_sp_driver_version[] = "1.0";
86 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
87 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
89 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
90 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
97 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
100 * Packet control type.
101 * 0 - Ethernet control (e.g. EMADs, LACP)
104 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
107 * Packet protocol type. Must be set to 1 (Ethernet).
109 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
111 /* tx_hdr_rx_is_router
112 * Packet is sent from the router. Valid for data packets only.
114 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
117 * Indicates if the 'fid' field is valid and should be used for
118 * forwarding lookup. Valid for data packets only.
120 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
123 * Switch partition ID. Must be set to 0.
125 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
127 /* tx_hdr_control_tclass
128 * Indicates if the packet should use the control TClass and not one
129 * of the data TClasses.
131 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
134 * Egress TClass to be used on the egress device on the egress port.
136 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
139 * Destination local port for unicast packets.
140 * Destination multicast ID for multicast packets.
142 * Control packets are directed to a specific egress port, while data
143 * packets are transmitted through the CPU port (0) into the switch partition,
144 * where forwarding rules are applied.
146 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
149 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
150 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
151 * Valid for data packets only.
153 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
157 * 6 - Control packets
159 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
161 struct mlxsw_sp_mlxfw_dev {
162 struct mlxfw_dev mlxfw_dev;
163 struct mlxsw_sp *mlxsw_sp;
166 struct mlxsw_sp_ptp_ops {
167 struct mlxsw_sp_ptp_clock *
168 (*clock_init)(struct mlxsw_sp *mlxsw_sp, struct device *dev);
169 void (*clock_fini)(struct mlxsw_sp_ptp_clock *clock);
171 struct mlxsw_sp_ptp_state *(*init)(struct mlxsw_sp *mlxsw_sp);
172 void (*fini)(struct mlxsw_sp_ptp_state *ptp_state);
174 /* Notify a driver that a packet that might be PTP was received. Driver
175 * is responsible for freeing the passed-in SKB.
177 void (*receive)(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
180 /* Notify a driver that a timestamped packet was transmitted. Driver
181 * is responsible for freeing the passed-in SKB.
183 void (*transmitted)(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
186 int (*hwtstamp_get)(struct mlxsw_sp_port *mlxsw_sp_port,
187 struct hwtstamp_config *config);
188 int (*hwtstamp_set)(struct mlxsw_sp_port *mlxsw_sp_port,
189 struct hwtstamp_config *config);
190 void (*shaper_work)(struct work_struct *work);
191 int (*get_ts_info)(struct mlxsw_sp *mlxsw_sp,
192 struct ethtool_ts_info *info);
193 int (*get_stats_count)(void);
194 void (*get_stats_strings)(u8 **p);
195 void (*get_stats)(struct mlxsw_sp_port *mlxsw_sp_port,
196 u64 *data, int data_index);
199 struct mlxsw_sp_span_ops {
200 u32 (*buffsize_get)(int mtu, u32 speed);
203 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
204 u16 component_index, u32 *p_max_size,
205 u8 *p_align_bits, u16 *p_max_write_size)
207 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
208 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
209 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
210 char mcqi_pl[MLXSW_REG_MCQI_LEN];
213 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
214 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
217 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
220 *p_align_bits = max_t(u8, *p_align_bits, 2);
221 *p_max_write_size = min_t(u16, *p_max_write_size,
222 MLXSW_REG_MCDA_MAX_DATA_LEN);
226 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
228 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
229 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
230 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
231 char mcc_pl[MLXSW_REG_MCC_LEN];
235 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
236 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
240 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
241 if (control_state != MLXFW_FSM_STATE_IDLE)
244 mlxsw_reg_mcc_pack(mcc_pl,
245 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
247 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
250 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
251 u32 fwhandle, u16 component_index,
254 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
255 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
256 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
257 char mcc_pl[MLXSW_REG_MCC_LEN];
259 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
260 component_index, fwhandle, component_size);
261 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
264 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
265 u32 fwhandle, u8 *data, u16 size,
268 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
269 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
270 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
271 char mcda_pl[MLXSW_REG_MCDA_LEN];
273 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
274 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
277 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
278 u32 fwhandle, u16 component_index)
280 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
281 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
283 char mcc_pl[MLXSW_REG_MCC_LEN];
285 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
286 component_index, fwhandle, 0);
287 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
290 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
292 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
293 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
294 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
295 char mcc_pl[MLXSW_REG_MCC_LEN];
297 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
299 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
302 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
303 enum mlxfw_fsm_state *fsm_state,
304 enum mlxfw_fsm_state_err *fsm_state_err)
306 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
307 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
308 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
309 char mcc_pl[MLXSW_REG_MCC_LEN];
314 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
315 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
319 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
320 *fsm_state = control_state;
321 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
322 MLXFW_FSM_STATE_ERR_MAX);
326 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
328 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
329 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
330 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
331 char mcc_pl[MLXSW_REG_MCC_LEN];
333 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
335 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
338 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
340 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
341 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
342 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
343 char mcc_pl[MLXSW_REG_MCC_LEN];
345 mlxsw_reg_mcc_pack(mcc_pl,
346 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
348 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
351 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
352 .component_query = mlxsw_sp_component_query,
353 .fsm_lock = mlxsw_sp_fsm_lock,
354 .fsm_component_update = mlxsw_sp_fsm_component_update,
355 .fsm_block_download = mlxsw_sp_fsm_block_download,
356 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
357 .fsm_activate = mlxsw_sp_fsm_activate,
358 .fsm_query_state = mlxsw_sp_fsm_query_state,
359 .fsm_cancel = mlxsw_sp_fsm_cancel,
360 .fsm_release = mlxsw_sp_fsm_release,
363 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
364 const struct firmware *firmware,
365 struct netlink_ext_ack *extack)
367 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
369 .ops = &mlxsw_sp_mlxfw_dev_ops,
370 .psid = mlxsw_sp->bus_info->psid,
371 .psid_size = strlen(mlxsw_sp->bus_info->psid),
372 .devlink = priv_to_devlink(mlxsw_sp->core),
378 mlxsw_core_fw_flash_start(mlxsw_sp->core);
379 err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev,
381 mlxsw_core_fw_flash_end(mlxsw_sp->core);
386 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
388 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
389 const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
390 const char *fw_filename = mlxsw_sp->fw_filename;
391 union devlink_param_value value;
392 const struct firmware *firmware;
395 /* Don't check if driver does not require it */
396 if (!req_rev || !fw_filename)
399 /* Don't check if devlink 'fw_load_policy' param is 'flash' */
400 err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_sp->core),
401 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
405 if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)
408 /* Validate driver & FW are compatible */
409 if (rev->major != req_rev->major) {
410 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
411 rev->major, req_rev->major);
414 if (mlxsw_core_fw_rev_minor_subminor_validate(rev, req_rev))
417 dev_err(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver (required >= %d.%d.%d)\n",
418 rev->major, rev->minor, rev->subminor, req_rev->major,
419 req_rev->minor, req_rev->subminor);
420 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
423 err = request_firmware_direct(&firmware, fw_filename,
424 mlxsw_sp->bus_info->dev);
426 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
431 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware, NULL);
432 release_firmware(firmware);
434 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
436 /* On FW flash success, tell the caller FW reset is needed
437 * if current FW supports it.
439 if (rev->minor >= req_rev->can_reset_minor)
440 return err ? err : -EAGAIN;
445 static int mlxsw_sp_flash_update(struct mlxsw_core *mlxsw_core,
446 const char *file_name, const char *component,
447 struct netlink_ext_ack *extack)
449 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
450 const struct firmware *firmware;
456 err = request_firmware_direct(&firmware, file_name,
457 mlxsw_sp->bus_info->dev);
460 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware, extack);
461 release_firmware(firmware);
466 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
467 unsigned int counter_index, u64 *packets,
470 char mgpc_pl[MLXSW_REG_MGPC_LEN];
473 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
474 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
475 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
479 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
481 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
485 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
486 unsigned int counter_index)
488 char mgpc_pl[MLXSW_REG_MGPC_LEN];
490 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
491 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
492 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
495 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
496 unsigned int *p_counter_index)
500 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
504 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
506 goto err_counter_clear;
510 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
515 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
516 unsigned int counter_index)
518 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
522 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
523 const struct mlxsw_tx_info *tx_info)
525 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
527 memset(txhdr, 0, MLXSW_TXHDR_LEN);
529 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
530 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
531 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
532 mlxsw_tx_hdr_swid_set(txhdr, 0);
533 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
534 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
535 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
538 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
541 case BR_STATE_FORWARDING:
542 return MLXSW_REG_SPMS_STATE_FORWARDING;
543 case BR_STATE_LEARNING:
544 return MLXSW_REG_SPMS_STATE_LEARNING;
545 case BR_STATE_LISTENING: /* fall-through */
546 case BR_STATE_DISABLED: /* fall-through */
547 case BR_STATE_BLOCKING:
548 return MLXSW_REG_SPMS_STATE_DISCARDING;
554 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
557 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
558 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
562 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
565 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
566 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
568 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
573 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
575 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
578 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
581 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
585 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
586 bool enable, u32 rate)
588 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
589 char mpsc_pl[MLXSW_REG_MPSC_LEN];
591 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
592 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
595 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
598 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
599 char paos_pl[MLXSW_REG_PAOS_LEN];
601 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
602 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
603 MLXSW_PORT_ADMIN_STATUS_DOWN);
604 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
607 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
610 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
611 char ppad_pl[MLXSW_REG_PPAD_LEN];
613 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
614 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
615 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
618 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
620 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
621 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
623 ether_addr_copy(addr, mlxsw_sp->base_mac);
624 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
625 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
628 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
630 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
631 char pmtu_pl[MLXSW_REG_PMTU_LEN];
635 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
636 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
637 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
640 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
645 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
646 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
649 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
651 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
652 char pspa_pl[MLXSW_REG_PSPA_LEN];
654 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
655 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
658 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
660 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
661 char svpe_pl[MLXSW_REG_SVPE_LEN];
663 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
664 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
667 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
670 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
674 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
677 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
679 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
684 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
687 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
688 char spvid_pl[MLXSW_REG_SPVID_LEN];
690 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
691 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
694 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
697 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
698 char spaft_pl[MLXSW_REG_SPAFT_LEN];
700 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
701 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
704 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
709 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
713 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
716 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
718 goto err_port_allow_untagged_set;
721 mlxsw_sp_port->pvid = vid;
724 err_port_allow_untagged_set:
725 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
730 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
732 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
733 char sspr_pl[MLXSW_REG_SSPR_LEN];
735 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
736 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
740 mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u8 local_port,
741 struct mlxsw_sp_port_mapping *port_mapping)
743 char pmlp_pl[MLXSW_REG_PMLP_LEN];
750 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
751 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
754 module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
755 width = mlxsw_reg_pmlp_width_get(pmlp_pl);
756 separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl);
758 if (width && !is_power_of_2(width)) {
759 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n",
764 for (i = 0; i < width; i++) {
765 if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) {
766 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n",
771 mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) !=
772 mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) {
773 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n",
777 if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i) {
778 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n",
784 port_mapping->module = module;
785 port_mapping->width = width;
786 port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
790 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port)
792 struct mlxsw_sp_port_mapping *port_mapping = &mlxsw_sp_port->mapping;
793 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
794 char pmlp_pl[MLXSW_REG_PMLP_LEN];
797 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
798 mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width);
799 for (i = 0; i < port_mapping->width; i++) {
800 mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module);
801 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */
804 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
807 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
809 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
810 char pmlp_pl[MLXSW_REG_PMLP_LEN];
812 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
813 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
814 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
817 static int mlxsw_sp_port_open(struct net_device *dev)
819 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
822 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
825 netif_start_queue(dev);
829 static int mlxsw_sp_port_stop(struct net_device *dev)
831 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
833 netif_stop_queue(dev);
834 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
837 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
838 struct net_device *dev)
840 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
841 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
842 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
843 const struct mlxsw_tx_info tx_info = {
844 .local_port = mlxsw_sp_port->local_port,
850 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
851 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
852 dev_kfree_skb_any(skb);
856 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
858 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
859 return NETDEV_TX_BUSY;
861 if (eth_skb_pad(skb)) {
862 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
866 mlxsw_sp_txhdr_construct(skb, &tx_info);
867 /* TX header is consumed by HW on the way so we shouldn't count its
868 * bytes as being sent.
870 len = skb->len - MLXSW_TXHDR_LEN;
872 /* Due to a race we might fail here because of a full queue. In that
873 * unlikely case we simply drop the packet.
875 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
878 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
879 u64_stats_update_begin(&pcpu_stats->syncp);
880 pcpu_stats->tx_packets++;
881 pcpu_stats->tx_bytes += len;
882 u64_stats_update_end(&pcpu_stats->syncp);
884 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
885 dev_kfree_skb_any(skb);
890 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
894 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
896 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
897 struct sockaddr *addr = p;
900 if (!is_valid_ether_addr(addr->sa_data))
901 return -EADDRNOTAVAIL;
903 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
906 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
910 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
913 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
916 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
918 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
921 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
923 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
927 /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
928 * Assumes 100m cable and maximum MTU.
930 #define MLXSW_SP_PAUSE_DELAY 58752
932 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
933 u16 delay, bool pfc, bool pause)
936 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
938 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
943 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
947 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
949 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
953 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
954 u8 *prio_tc, bool pause_en,
955 struct ieee_pfc *my_pfc)
957 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
958 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
959 u16 delay = !!my_pfc ? my_pfc->delay : 0;
960 char pbmc_pl[MLXSW_REG_PBMC_LEN];
961 u32 taken_headroom_cells = 0;
962 u32 max_headroom_cells;
965 max_headroom_cells = mlxsw_sp_sb_max_headroom_cells(mlxsw_sp);
967 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
968 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
972 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
973 bool configure = false;
980 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
981 if (prio_tc[j] == i) {
982 pfc = pfc_en & BIT(j);
991 lossy = !(pfc || pause_en);
992 thres_cells = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
993 delay_cells = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay,
995 total_cells = thres_cells + delay_cells;
997 taken_headroom_cells += total_cells;
998 if (taken_headroom_cells > max_headroom_cells)
1001 mlxsw_sp_pg_buf_pack(pbmc_pl, i, total_cells,
1002 thres_cells, lossy);
1005 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1008 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
1009 int mtu, bool pause_en)
1011 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1012 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
1013 struct ieee_pfc *my_pfc;
1016 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
1017 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
1019 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
1023 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1025 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1026 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1029 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
1032 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1034 goto err_span_port_mtu_update;
1035 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1037 goto err_port_mtu_set;
1042 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1043 err_span_port_mtu_update:
1044 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1049 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1050 struct rtnl_link_stats64 *stats)
1052 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1053 struct mlxsw_sp_port_pcpu_stats *p;
1054 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1059 for_each_possible_cpu(i) {
1060 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1062 start = u64_stats_fetch_begin_irq(&p->syncp);
1063 rx_packets = p->rx_packets;
1064 rx_bytes = p->rx_bytes;
1065 tx_packets = p->tx_packets;
1066 tx_bytes = p->tx_bytes;
1067 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1069 stats->rx_packets += rx_packets;
1070 stats->rx_bytes += rx_bytes;
1071 stats->tx_packets += tx_packets;
1072 stats->tx_bytes += tx_bytes;
1073 /* tx_dropped is u32, updated without syncp protection. */
1074 tx_dropped += p->tx_dropped;
1076 stats->tx_dropped = tx_dropped;
1080 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
1083 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1090 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1094 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1095 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1101 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1102 int prio, char *ppcnt_pl)
1104 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1105 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1107 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1108 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1111 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1112 struct rtnl_link_stats64 *stats)
1114 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1117 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1123 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1125 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1127 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1129 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1131 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1133 stats->rx_crc_errors =
1134 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1135 stats->rx_frame_errors =
1136 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1138 stats->rx_length_errors = (
1139 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1140 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1141 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1143 stats->rx_errors = (stats->rx_crc_errors +
1144 stats->rx_frame_errors + stats->rx_length_errors);
1151 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1152 struct mlxsw_sp_port_xstats *xstats)
1154 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1157 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1160 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1162 for (i = 0; i < TC_MAX_QUEUE; i++) {
1163 err = mlxsw_sp_port_get_stats_raw(dev,
1164 MLXSW_REG_PPCNT_TC_CONG_TC,
1167 xstats->wred_drop[i] =
1168 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1170 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1175 xstats->backlog[i] =
1176 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1177 xstats->tail_drop[i] =
1178 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1181 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1182 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1187 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1188 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1192 static void update_stats_cache(struct work_struct *work)
1194 struct mlxsw_sp_port *mlxsw_sp_port =
1195 container_of(work, struct mlxsw_sp_port,
1196 periodic_hw_stats.update_dw.work);
1198 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1199 /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as
1200 * necessary when port goes down.
1204 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1205 &mlxsw_sp_port->periodic_hw_stats.stats);
1206 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1207 &mlxsw_sp_port->periodic_hw_stats.xstats);
1210 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1211 MLXSW_HW_STATS_UPDATE_TIME);
1214 /* Return the stats from a cache that is updated periodically,
1215 * as this function might get called in an atomic context.
1218 mlxsw_sp_port_get_stats64(struct net_device *dev,
1219 struct rtnl_link_stats64 *stats)
1221 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1223 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1226 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1227 u16 vid_begin, u16 vid_end,
1228 bool is_member, bool untagged)
1230 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1234 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1238 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1239 vid_end, is_member, untagged);
1240 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1245 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1246 u16 vid_end, bool is_member, bool untagged)
1251 for (vid = vid_begin; vid <= vid_end;
1252 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1253 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1256 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1257 is_member, untagged);
1265 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
1268 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1270 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1271 &mlxsw_sp_port->vlans_list, list) {
1272 if (!flush_default &&
1273 mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
1275 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1280 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1282 if (mlxsw_sp_port_vlan->bridge_port)
1283 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1284 else if (mlxsw_sp_port_vlan->fid)
1285 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1288 struct mlxsw_sp_port_vlan *
1289 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1291 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1292 bool untagged = vid == MLXSW_SP_DEFAULT_VID;
1295 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1296 if (mlxsw_sp_port_vlan)
1297 return ERR_PTR(-EEXIST);
1299 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1301 return ERR_PTR(err);
1303 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1304 if (!mlxsw_sp_port_vlan) {
1306 goto err_port_vlan_alloc;
1309 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1310 mlxsw_sp_port_vlan->vid = vid;
1311 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1313 return mlxsw_sp_port_vlan;
1315 err_port_vlan_alloc:
1316 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1317 return ERR_PTR(err);
1320 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1322 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1323 u16 vid = mlxsw_sp_port_vlan->vid;
1325 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
1326 list_del(&mlxsw_sp_port_vlan->list);
1327 kfree(mlxsw_sp_port_vlan);
1328 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1331 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1332 __be16 __always_unused proto, u16 vid)
1334 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1336 /* VLAN 0 is added to HW filter when device goes up, but it is
1337 * reserved in our case, so simply return.
1342 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
1345 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1346 __be16 __always_unused proto, u16 vid)
1348 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1349 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1351 /* VLAN 0 is removed from HW filter when device goes down, but
1352 * it is reserved in our case, so simply return.
1357 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1358 if (!mlxsw_sp_port_vlan)
1360 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1365 static struct mlxsw_sp_port_mall_tc_entry *
1366 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1367 unsigned long cookie) {
1368 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1370 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1371 if (mall_tc_entry->cookie == cookie)
1372 return mall_tc_entry;
1378 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1379 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1380 const struct flow_action_entry *act,
1383 enum mlxsw_sp_span_type span_type;
1386 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1390 mirror->ingress = ingress;
1391 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1392 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, act->dev, span_type,
1393 true, &mirror->span_id);
1397 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1398 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1400 enum mlxsw_sp_span_type span_type;
1402 span_type = mirror->ingress ?
1403 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1404 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1409 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1410 struct tc_cls_matchall_offload *cls,
1411 const struct flow_action_entry *act,
1416 if (!mlxsw_sp_port->sample)
1418 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1419 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1422 if (act->sample.rate > MLXSW_REG_MPSC_RATE_MAX) {
1423 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1427 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1428 act->sample.psample_group);
1429 mlxsw_sp_port->sample->truncate = act->sample.truncate;
1430 mlxsw_sp_port->sample->trunc_size = act->sample.trunc_size;
1431 mlxsw_sp_port->sample->rate = act->sample.rate;
1433 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, act->sample.rate);
1435 goto err_port_sample_set;
1438 err_port_sample_set:
1439 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1444 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1446 if (!mlxsw_sp_port->sample)
1449 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1450 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1453 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1454 struct tc_cls_matchall_offload *f,
1457 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1458 __be16 protocol = f->common.protocol;
1459 struct flow_action_entry *act;
1462 if (!flow_offload_has_one_action(&f->rule->action)) {
1463 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1467 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1470 mall_tc_entry->cookie = f->cookie;
1472 act = &f->rule->action.entries[0];
1474 if (act->id == FLOW_ACTION_MIRRED && protocol == htons(ETH_P_ALL)) {
1475 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1477 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1478 mirror = &mall_tc_entry->mirror;
1479 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1482 } else if (act->id == FLOW_ACTION_SAMPLE &&
1483 protocol == htons(ETH_P_ALL)) {
1484 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1485 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1492 goto err_add_action;
1494 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1498 kfree(mall_tc_entry);
1502 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1503 struct tc_cls_matchall_offload *f)
1505 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1507 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1509 if (!mall_tc_entry) {
1510 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1513 list_del(&mall_tc_entry->list);
1515 switch (mall_tc_entry->type) {
1516 case MLXSW_SP_PORT_MALL_MIRROR:
1517 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1518 &mall_tc_entry->mirror);
1520 case MLXSW_SP_PORT_MALL_SAMPLE:
1521 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1527 kfree(mall_tc_entry);
1530 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1531 struct tc_cls_matchall_offload *f,
1534 switch (f->command) {
1535 case TC_CLSMATCHALL_REPLACE:
1536 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1538 case TC_CLSMATCHALL_DESTROY:
1539 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1547 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1548 struct flow_cls_offload *f)
1550 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1552 switch (f->command) {
1553 case FLOW_CLS_REPLACE:
1554 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1555 case FLOW_CLS_DESTROY:
1556 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1558 case FLOW_CLS_STATS:
1559 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1560 case FLOW_CLS_TMPLT_CREATE:
1561 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1562 case FLOW_CLS_TMPLT_DESTROY:
1563 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1570 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1572 void *cb_priv, bool ingress)
1574 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1577 case TC_SETUP_CLSMATCHALL:
1578 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1582 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1584 case TC_SETUP_CLSFLOWER:
1591 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1595 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1599 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1603 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1607 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1608 void *type_data, void *cb_priv)
1610 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1613 case TC_SETUP_CLSMATCHALL:
1615 case TC_SETUP_CLSFLOWER:
1616 if (mlxsw_sp_acl_block_disabled(acl_block))
1619 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1625 static void mlxsw_sp_tc_block_flower_release(void *cb_priv)
1627 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1629 mlxsw_sp_acl_block_destroy(acl_block);
1632 static LIST_HEAD(mlxsw_sp_block_cb_list);
1635 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1636 struct flow_block_offload *f, bool ingress)
1638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1639 struct mlxsw_sp_acl_block *acl_block;
1640 struct flow_block_cb *block_cb;
1641 bool register_block = false;
1644 block_cb = flow_block_cb_lookup(f->block,
1645 mlxsw_sp_setup_tc_block_cb_flower,
1648 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, f->net);
1651 block_cb = flow_block_cb_alloc(mlxsw_sp_setup_tc_block_cb_flower,
1652 mlxsw_sp, acl_block,
1653 mlxsw_sp_tc_block_flower_release);
1654 if (IS_ERR(block_cb)) {
1655 mlxsw_sp_acl_block_destroy(acl_block);
1656 err = PTR_ERR(block_cb);
1657 goto err_cb_register;
1659 register_block = true;
1661 acl_block = flow_block_cb_priv(block_cb);
1663 flow_block_cb_incref(block_cb);
1664 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1665 mlxsw_sp_port, ingress, f->extack);
1667 goto err_block_bind;
1670 mlxsw_sp_port->ing_acl_block = acl_block;
1672 mlxsw_sp_port->eg_acl_block = acl_block;
1674 if (register_block) {
1675 flow_block_cb_add(block_cb, f);
1676 list_add_tail(&block_cb->driver_list, &mlxsw_sp_block_cb_list);
1682 if (!flow_block_cb_decref(block_cb))
1683 flow_block_cb_free(block_cb);
1689 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1690 struct flow_block_offload *f, bool ingress)
1692 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1693 struct mlxsw_sp_acl_block *acl_block;
1694 struct flow_block_cb *block_cb;
1697 block_cb = flow_block_cb_lookup(f->block,
1698 mlxsw_sp_setup_tc_block_cb_flower,
1704 mlxsw_sp_port->ing_acl_block = NULL;
1706 mlxsw_sp_port->eg_acl_block = NULL;
1708 acl_block = flow_block_cb_priv(block_cb);
1709 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1710 mlxsw_sp_port, ingress);
1711 if (!err && !flow_block_cb_decref(block_cb)) {
1712 flow_block_cb_remove(block_cb, f);
1713 list_del(&block_cb->driver_list);
1717 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1718 struct flow_block_offload *f)
1720 struct flow_block_cb *block_cb;
1721 flow_setup_cb_t *cb;
1725 if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1726 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1728 } else if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1729 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1735 f->driver_block_list = &mlxsw_sp_block_cb_list;
1737 switch (f->command) {
1738 case FLOW_BLOCK_BIND:
1739 if (flow_block_cb_is_busy(cb, mlxsw_sp_port,
1740 &mlxsw_sp_block_cb_list))
1743 block_cb = flow_block_cb_alloc(cb, mlxsw_sp_port,
1744 mlxsw_sp_port, NULL);
1745 if (IS_ERR(block_cb))
1746 return PTR_ERR(block_cb);
1747 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, f,
1750 flow_block_cb_free(block_cb);
1753 flow_block_cb_add(block_cb, f);
1754 list_add_tail(&block_cb->driver_list, &mlxsw_sp_block_cb_list);
1756 case FLOW_BLOCK_UNBIND:
1757 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1759 block_cb = flow_block_cb_lookup(f->block, cb, mlxsw_sp_port);
1763 flow_block_cb_remove(block_cb, f);
1764 list_del(&block_cb->driver_list);
1771 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1774 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1777 case TC_SETUP_BLOCK:
1778 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1779 case TC_SETUP_QDISC_RED:
1780 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1781 case TC_SETUP_QDISC_PRIO:
1782 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1783 case TC_SETUP_QDISC_ETS:
1784 return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data);
1785 case TC_SETUP_QDISC_TBF:
1786 return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data);
1787 case TC_SETUP_QDISC_FIFO:
1788 return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data);
1795 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1797 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1800 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1801 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1802 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1803 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1806 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1807 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1809 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1810 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1815 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable)
1817 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1818 char pplr_pl[MLXSW_REG_PPLR_LEN];
1821 if (netif_running(dev))
1822 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1824 mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable);
1825 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
1828 if (netif_running(dev))
1829 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1834 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1836 static int mlxsw_sp_handle_feature(struct net_device *dev,
1837 netdev_features_t wanted_features,
1838 netdev_features_t feature,
1839 mlxsw_sp_feature_handler feature_handler)
1841 netdev_features_t changes = wanted_features ^ dev->features;
1842 bool enable = !!(wanted_features & feature);
1845 if (!(changes & feature))
1848 err = feature_handler(dev, enable);
1850 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1851 enable ? "Enable" : "Disable", &feature, err);
1856 dev->features |= feature;
1858 dev->features &= ~feature;
1862 static int mlxsw_sp_set_features(struct net_device *dev,
1863 netdev_features_t features)
1865 netdev_features_t oper_features = dev->features;
1868 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1869 mlxsw_sp_feature_hw_tc);
1870 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK,
1871 mlxsw_sp_feature_loopback);
1874 dev->features = oper_features;
1881 static struct devlink_port *
1882 mlxsw_sp_port_get_devlink_port(struct net_device *dev)
1884 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1885 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1887 return mlxsw_core_port_devlink_port_get(mlxsw_sp->core,
1888 mlxsw_sp_port->local_port);
1891 static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
1894 struct hwtstamp_config config;
1897 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1900 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
1905 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1911 static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
1914 struct hwtstamp_config config;
1917 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
1922 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1928 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port)
1930 struct hwtstamp_config config = {0};
1932 mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config);
1936 mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1938 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1942 return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr);
1944 return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr);
1950 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1951 .ndo_open = mlxsw_sp_port_open,
1952 .ndo_stop = mlxsw_sp_port_stop,
1953 .ndo_start_xmit = mlxsw_sp_port_xmit,
1954 .ndo_setup_tc = mlxsw_sp_setup_tc,
1955 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
1956 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1957 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1958 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
1959 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1960 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
1961 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1962 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1963 .ndo_set_features = mlxsw_sp_set_features,
1964 .ndo_get_devlink_port = mlxsw_sp_port_get_devlink_port,
1965 .ndo_do_ioctl = mlxsw_sp_port_ioctl,
1968 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1969 struct ethtool_drvinfo *drvinfo)
1971 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1972 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1974 strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1975 sizeof(drvinfo->driver));
1976 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1977 sizeof(drvinfo->version));
1978 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1980 mlxsw_sp->bus_info->fw_rev.major,
1981 mlxsw_sp->bus_info->fw_rev.minor,
1982 mlxsw_sp->bus_info->fw_rev.subminor);
1983 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1984 sizeof(drvinfo->bus_info));
1987 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1988 struct ethtool_pauseparam *pause)
1990 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1992 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1993 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1996 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1997 struct ethtool_pauseparam *pause)
1999 char pfcc_pl[MLXSW_REG_PFCC_LEN];
2001 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
2002 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
2003 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
2005 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
2009 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
2010 struct ethtool_pauseparam *pause)
2012 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2013 bool pause_en = pause->tx_pause || pause->rx_pause;
2016 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
2017 netdev_err(dev, "PFC already enabled on port\n");
2021 if (pause->autoneg) {
2022 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
2026 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2028 netdev_err(dev, "Failed to configure port's headroom\n");
2032 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
2034 netdev_err(dev, "Failed to set PAUSE parameters\n");
2035 goto err_port_pause_configure;
2038 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
2039 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
2043 err_port_pause_configure:
2044 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
2045 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2049 struct mlxsw_sp_port_hw_stats {
2050 char str[ETH_GSTRING_LEN];
2051 u64 (*getter)(const char *payload);
2055 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
2057 .str = "a_frames_transmitted_ok",
2058 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
2061 .str = "a_frames_received_ok",
2062 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
2065 .str = "a_frame_check_sequence_errors",
2066 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2069 .str = "a_alignment_errors",
2070 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2073 .str = "a_octets_transmitted_ok",
2074 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2077 .str = "a_octets_received_ok",
2078 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2081 .str = "a_multicast_frames_xmitted_ok",
2082 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2085 .str = "a_broadcast_frames_xmitted_ok",
2086 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2089 .str = "a_multicast_frames_received_ok",
2090 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2093 .str = "a_broadcast_frames_received_ok",
2094 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2097 .str = "a_in_range_length_errors",
2098 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2101 .str = "a_out_of_range_length_field",
2102 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2105 .str = "a_frame_too_long_errors",
2106 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2109 .str = "a_symbol_error_during_carrier",
2110 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2113 .str = "a_mac_control_frames_transmitted",
2114 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2117 .str = "a_mac_control_frames_received",
2118 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2121 .str = "a_unsupported_opcodes_received",
2122 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2125 .str = "a_pause_mac_ctrl_frames_received",
2126 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2129 .str = "a_pause_mac_ctrl_frames_xmitted",
2130 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2134 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2136 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2863_stats[] = {
2138 .str = "if_in_discards",
2139 .getter = mlxsw_reg_ppcnt_if_in_discards_get,
2142 .str = "if_out_discards",
2143 .getter = mlxsw_reg_ppcnt_if_out_discards_get,
2146 .str = "if_out_errors",
2147 .getter = mlxsw_reg_ppcnt_if_out_errors_get,
2151 #define MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN \
2152 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2863_stats)
2154 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
2156 .str = "ether_stats_undersize_pkts",
2157 .getter = mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get,
2160 .str = "ether_stats_oversize_pkts",
2161 .getter = mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get,
2164 .str = "ether_stats_fragments",
2165 .getter = mlxsw_reg_ppcnt_ether_stats_fragments_get,
2168 .str = "ether_pkts64octets",
2169 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
2172 .str = "ether_pkts65to127octets",
2173 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
2176 .str = "ether_pkts128to255octets",
2177 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
2180 .str = "ether_pkts256to511octets",
2181 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
2184 .str = "ether_pkts512to1023octets",
2185 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
2188 .str = "ether_pkts1024to1518octets",
2189 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
2192 .str = "ether_pkts1519to2047octets",
2193 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
2196 .str = "ether_pkts2048to4095octets",
2197 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
2200 .str = "ether_pkts4096to8191octets",
2201 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
2204 .str = "ether_pkts8192to10239octets",
2205 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
2209 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
2210 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
2212 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_3635_stats[] = {
2214 .str = "dot3stats_fcs_errors",
2215 .getter = mlxsw_reg_ppcnt_dot3stats_fcs_errors_get,
2218 .str = "dot3stats_symbol_errors",
2219 .getter = mlxsw_reg_ppcnt_dot3stats_symbol_errors_get,
2222 .str = "dot3control_in_unknown_opcodes",
2223 .getter = mlxsw_reg_ppcnt_dot3control_in_unknown_opcodes_get,
2226 .str = "dot3in_pause_frames",
2227 .getter = mlxsw_reg_ppcnt_dot3in_pause_frames_get,
2231 #define MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN \
2232 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_3635_stats)
2234 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_ext_stats[] = {
2236 .str = "ecn_marked",
2237 .getter = mlxsw_reg_ppcnt_ecn_marked_get,
2241 #define MLXSW_SP_PORT_HW_EXT_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_ext_stats)
2243 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_discard_stats[] = {
2245 .str = "discard_ingress_general",
2246 .getter = mlxsw_reg_ppcnt_ingress_general_get,
2249 .str = "discard_ingress_policy_engine",
2250 .getter = mlxsw_reg_ppcnt_ingress_policy_engine_get,
2253 .str = "discard_ingress_vlan_membership",
2254 .getter = mlxsw_reg_ppcnt_ingress_vlan_membership_get,
2257 .str = "discard_ingress_tag_frame_type",
2258 .getter = mlxsw_reg_ppcnt_ingress_tag_frame_type_get,
2261 .str = "discard_egress_vlan_membership",
2262 .getter = mlxsw_reg_ppcnt_egress_vlan_membership_get,
2265 .str = "discard_loopback_filter",
2266 .getter = mlxsw_reg_ppcnt_loopback_filter_get,
2269 .str = "discard_egress_general",
2270 .getter = mlxsw_reg_ppcnt_egress_general_get,
2273 .str = "discard_egress_hoq",
2274 .getter = mlxsw_reg_ppcnt_egress_hoq_get,
2277 .str = "discard_egress_policy_engine",
2278 .getter = mlxsw_reg_ppcnt_egress_policy_engine_get,
2281 .str = "discard_ingress_tx_link_down",
2282 .getter = mlxsw_reg_ppcnt_ingress_tx_link_down_get,
2285 .str = "discard_egress_stp_filter",
2286 .getter = mlxsw_reg_ppcnt_egress_stp_filter_get,
2289 .str = "discard_egress_sll",
2290 .getter = mlxsw_reg_ppcnt_egress_sll_get,
2294 #define MLXSW_SP_PORT_HW_DISCARD_STATS_LEN \
2295 ARRAY_SIZE(mlxsw_sp_port_hw_discard_stats)
2297 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2299 .str = "rx_octets_prio",
2300 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2303 .str = "rx_frames_prio",
2304 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2307 .str = "tx_octets_prio",
2308 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2311 .str = "tx_frames_prio",
2312 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2315 .str = "rx_pause_prio",
2316 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2319 .str = "rx_pause_duration_prio",
2320 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2323 .str = "tx_pause_prio",
2324 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2327 .str = "tx_pause_duration_prio",
2328 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2332 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2334 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2336 .str = "tc_transmit_queue_tc",
2337 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2338 .cells_bytes = true,
2341 .str = "tc_no_buffer_discard_uc_tc",
2342 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2346 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2348 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
2349 MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN + \
2350 MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
2351 MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN + \
2352 MLXSW_SP_PORT_HW_EXT_STATS_LEN + \
2353 MLXSW_SP_PORT_HW_DISCARD_STATS_LEN + \
2354 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
2355 IEEE_8021QAZ_MAX_TCS) + \
2356 (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
2359 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2363 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2364 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2365 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2366 *p += ETH_GSTRING_LEN;
2370 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2374 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2375 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2376 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2377 *p += ETH_GSTRING_LEN;
2381 static void mlxsw_sp_port_get_strings(struct net_device *dev,
2382 u32 stringset, u8 *data)
2384 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2388 switch (stringset) {
2390 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2391 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2393 p += ETH_GSTRING_LEN;
2396 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; i++) {
2397 memcpy(p, mlxsw_sp_port_hw_rfc_2863_stats[i].str,
2399 p += ETH_GSTRING_LEN;
2402 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2403 memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2405 p += ETH_GSTRING_LEN;
2408 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; i++) {
2409 memcpy(p, mlxsw_sp_port_hw_rfc_3635_stats[i].str,
2411 p += ETH_GSTRING_LEN;
2414 for (i = 0; i < MLXSW_SP_PORT_HW_EXT_STATS_LEN; i++) {
2415 memcpy(p, mlxsw_sp_port_hw_ext_stats[i].str,
2417 p += ETH_GSTRING_LEN;
2420 for (i = 0; i < MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; i++) {
2421 memcpy(p, mlxsw_sp_port_hw_discard_stats[i].str,
2423 p += ETH_GSTRING_LEN;
2426 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2427 mlxsw_sp_port_get_prio_strings(&p, i);
2429 for (i = 0; i < TC_MAX_QUEUE; i++)
2430 mlxsw_sp_port_get_tc_strings(&p, i);
2432 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_strings(&p);
2437 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2438 enum ethtool_phys_id_state state)
2440 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2441 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2442 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2446 case ETHTOOL_ID_ACTIVE:
2449 case ETHTOOL_ID_INACTIVE:
2456 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2457 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2461 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2462 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2465 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2466 *p_hw_stats = mlxsw_sp_port_hw_stats;
2467 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2469 case MLXSW_REG_PPCNT_RFC_2863_CNT:
2470 *p_hw_stats = mlxsw_sp_port_hw_rfc_2863_stats;
2471 *p_len = MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2473 case MLXSW_REG_PPCNT_RFC_2819_CNT:
2474 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2475 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2477 case MLXSW_REG_PPCNT_RFC_3635_CNT:
2478 *p_hw_stats = mlxsw_sp_port_hw_rfc_3635_stats;
2479 *p_len = MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2481 case MLXSW_REG_PPCNT_EXT_CNT:
2482 *p_hw_stats = mlxsw_sp_port_hw_ext_stats;
2483 *p_len = MLXSW_SP_PORT_HW_EXT_STATS_LEN;
2485 case MLXSW_REG_PPCNT_DISCARD_CNT:
2486 *p_hw_stats = mlxsw_sp_port_hw_discard_stats;
2487 *p_len = MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2489 case MLXSW_REG_PPCNT_PRIO_CNT:
2490 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2491 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2493 case MLXSW_REG_PPCNT_TC_CNT:
2494 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2495 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2504 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2505 enum mlxsw_reg_ppcnt_grp grp, int prio,
2506 u64 *data, int data_index)
2508 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2509 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2510 struct mlxsw_sp_port_hw_stats *hw_stats;
2511 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2515 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2518 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2519 for (i = 0; i < len; i++) {
2520 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2521 if (!hw_stats[i].cells_bytes)
2523 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2524 data[data_index + i]);
2528 static void mlxsw_sp_port_get_stats(struct net_device *dev,
2529 struct ethtool_stats *stats, u64 *data)
2531 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2532 int i, data_index = 0;
2534 /* IEEE 802.3 Counters */
2535 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2537 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2539 /* RFC 2863 Counters */
2540 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2863_CNT, 0,
2542 data_index += MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2544 /* RFC 2819 Counters */
2545 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2547 data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2549 /* RFC 3635 Counters */
2550 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_3635_CNT, 0,
2552 data_index += MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2554 /* Extended Counters */
2555 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
2557 data_index += MLXSW_SP_PORT_HW_EXT_STATS_LEN;
2559 /* Discard Counters */
2560 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_DISCARD_CNT, 0,
2562 data_index += MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2564 /* Per-Priority Counters */
2565 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2566 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2568 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2571 /* Per-TC Counters */
2572 for (i = 0; i < TC_MAX_QUEUE; i++) {
2573 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2575 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2579 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats(mlxsw_sp_port,
2581 data_index += mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
2584 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2586 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2590 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN +
2591 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
2597 struct mlxsw_sp1_port_link_mode {
2598 enum ethtool_link_mode_bit_indices mask_ethtool;
2603 static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = {
2605 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2606 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2610 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2611 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2612 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2613 .speed = SPEED_1000,
2616 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2617 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2618 .speed = SPEED_10000,
2621 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2622 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2623 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2624 .speed = SPEED_10000,
2627 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2628 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2629 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2630 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2631 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2632 .speed = SPEED_10000,
2635 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2636 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2637 .speed = SPEED_20000,
2640 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2641 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2642 .speed = SPEED_40000,
2645 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2646 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2647 .speed = SPEED_40000,
2650 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2651 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2652 .speed = SPEED_40000,
2655 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2656 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2657 .speed = SPEED_40000,
2660 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2661 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2662 .speed = SPEED_25000,
2665 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2666 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2667 .speed = SPEED_25000,
2670 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2671 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2672 .speed = SPEED_25000,
2675 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2676 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2677 .speed = SPEED_50000,
2680 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2681 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2682 .speed = SPEED_50000,
2685 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2686 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2687 .speed = SPEED_50000,
2690 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2691 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2692 .speed = SPEED_100000,
2695 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2696 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2697 .speed = SPEED_100000,
2700 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2701 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2702 .speed = SPEED_100000,
2705 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2706 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2707 .speed = SPEED_100000,
2711 #define MLXSW_SP1_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp1_port_link_mode)
2714 mlxsw_sp1_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
2716 struct ethtool_link_ksettings *cmd)
2718 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2719 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2720 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2721 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2722 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2723 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2724 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2726 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2727 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2728 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2729 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2730 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2731 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2735 mlxsw_sp1_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
2736 u8 width, unsigned long *mode)
2740 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2741 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
2742 __set_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
2748 mlxsw_sp1_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
2752 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2753 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
2754 return mlxsw_sp1_port_link_mode[i].speed;
2757 return SPEED_UNKNOWN;
2761 mlxsw_sp1_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
2763 struct ethtool_link_ksettings *cmd)
2765 cmd->base.speed = SPEED_UNKNOWN;
2766 cmd->base.duplex = DUPLEX_UNKNOWN;
2771 cmd->base.speed = mlxsw_sp1_from_ptys_speed(mlxsw_sp, ptys_eth_proto);
2772 if (cmd->base.speed != SPEED_UNKNOWN)
2773 cmd->base.duplex = DUPLEX_FULL;
2777 mlxsw_sp1_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, u8 width,
2778 const struct ethtool_link_ksettings *cmd)
2783 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2784 if (test_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
2785 cmd->link_modes.advertising))
2786 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2791 static u32 mlxsw_sp1_to_ptys_speed(struct mlxsw_sp *mlxsw_sp, u8 width,
2797 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2798 if (speed == mlxsw_sp1_port_link_mode[i].speed)
2799 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2805 mlxsw_sp1_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
2806 u8 local_port, u32 proto_admin, bool autoneg)
2808 mlxsw_reg_ptys_eth_pack(payload, local_port, proto_admin, autoneg);
2812 mlxsw_sp1_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
2813 u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
2814 u32 *p_eth_proto_oper)
2816 mlxsw_reg_ptys_eth_unpack(payload, p_eth_proto_cap, p_eth_proto_admin,
2820 static const struct mlxsw_sp_port_type_speed_ops
2821 mlxsw_sp1_port_type_speed_ops = {
2822 .from_ptys_supported_port = mlxsw_sp1_from_ptys_supported_port,
2823 .from_ptys_link = mlxsw_sp1_from_ptys_link,
2824 .from_ptys_speed = mlxsw_sp1_from_ptys_speed,
2825 .from_ptys_speed_duplex = mlxsw_sp1_from_ptys_speed_duplex,
2826 .to_ptys_advert_link = mlxsw_sp1_to_ptys_advert_link,
2827 .to_ptys_speed = mlxsw_sp1_to_ptys_speed,
2828 .reg_ptys_eth_pack = mlxsw_sp1_reg_ptys_eth_pack,
2829 .reg_ptys_eth_unpack = mlxsw_sp1_reg_ptys_eth_unpack,
2832 static const enum ethtool_link_mode_bit_indices
2833 mlxsw_sp2_mask_ethtool_sgmii_100m[] = {
2834 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2837 #define MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN \
2838 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_sgmii_100m)
2840 static const enum ethtool_link_mode_bit_indices
2841 mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] = {
2842 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2843 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2846 #define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \
2847 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii)
2849 static const enum ethtool_link_mode_bit_indices
2850 mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii[] = {
2851 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
2854 #define MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN \
2855 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii)
2857 static const enum ethtool_link_mode_bit_indices
2858 mlxsw_sp2_mask_ethtool_5gbase_r[] = {
2859 ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
2862 #define MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN \
2863 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_5gbase_r)
2865 static const enum ethtool_link_mode_bit_indices
2866 mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g[] = {
2867 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2868 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2869 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
2870 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
2871 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
2872 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
2873 ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
2876 #define MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN \
2877 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g)
2879 static const enum ethtool_link_mode_bit_indices
2880 mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g[] = {
2881 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2882 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2883 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2884 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2887 #define MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN \
2888 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g)
2890 static const enum ethtool_link_mode_bit_indices
2891 mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr[] = {
2892 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2893 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2894 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2897 #define MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN \
2898 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr)
2900 static const enum ethtool_link_mode_bit_indices
2901 mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2[] = {
2902 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2903 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2904 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2907 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN \
2908 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2)
2910 static const enum ethtool_link_mode_bit_indices
2911 mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr[] = {
2912 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
2913 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
2914 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
2915 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
2916 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
2919 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN \
2920 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr)
2922 static const enum ethtool_link_mode_bit_indices
2923 mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4[] = {
2924 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2925 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2926 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2927 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2930 #define MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN \
2931 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4)
2933 static const enum ethtool_link_mode_bit_indices
2934 mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2[] = {
2935 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
2936 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
2937 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
2938 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
2939 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
2942 #define MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN \
2943 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2)
2945 static const enum ethtool_link_mode_bit_indices
2946 mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = {
2947 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
2948 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
2949 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
2950 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
2951 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
2954 #define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \
2955 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4)
2957 static const enum ethtool_link_mode_bit_indices
2958 mlxsw_sp2_mask_ethtool_400gaui_8[] = {
2959 ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
2960 ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
2961 ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
2962 ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
2963 ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,
2966 #define MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN \
2967 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_400gaui_8)
2969 #define MLXSW_SP_PORT_MASK_WIDTH_1X BIT(0)
2970 #define MLXSW_SP_PORT_MASK_WIDTH_2X BIT(1)
2971 #define MLXSW_SP_PORT_MASK_WIDTH_4X BIT(2)
2972 #define MLXSW_SP_PORT_MASK_WIDTH_8X BIT(3)
2974 static u8 mlxsw_sp_port_mask_width_get(u8 width)
2978 return MLXSW_SP_PORT_MASK_WIDTH_1X;
2980 return MLXSW_SP_PORT_MASK_WIDTH_2X;
2982 return MLXSW_SP_PORT_MASK_WIDTH_4X;
2984 return MLXSW_SP_PORT_MASK_WIDTH_8X;
2991 struct mlxsw_sp2_port_link_mode {
2992 const enum ethtool_link_mode_bit_indices *mask_ethtool;
2999 static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
3001 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M,
3002 .mask_ethtool = mlxsw_sp2_mask_ethtool_sgmii_100m,
3003 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN,
3004 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
3005 MLXSW_SP_PORT_MASK_WIDTH_2X |
3006 MLXSW_SP_PORT_MASK_WIDTH_4X |
3007 MLXSW_SP_PORT_MASK_WIDTH_8X,
3011 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII,
3012 .mask_ethtool = mlxsw_sp2_mask_ethtool_1000base_x_sgmii,
3013 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN,
3014 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
3015 MLXSW_SP_PORT_MASK_WIDTH_2X |
3016 MLXSW_SP_PORT_MASK_WIDTH_4X |
3017 MLXSW_SP_PORT_MASK_WIDTH_8X,
3018 .speed = SPEED_1000,
3021 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII,
3022 .mask_ethtool = mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii,
3023 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN,
3024 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
3025 MLXSW_SP_PORT_MASK_WIDTH_2X |
3026 MLXSW_SP_PORT_MASK_WIDTH_4X |
3027 MLXSW_SP_PORT_MASK_WIDTH_8X,
3028 .speed = SPEED_2500,
3031 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R,
3032 .mask_ethtool = mlxsw_sp2_mask_ethtool_5gbase_r,
3033 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN,
3034 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
3035 MLXSW_SP_PORT_MASK_WIDTH_2X |
3036 MLXSW_SP_PORT_MASK_WIDTH_4X |
3037 MLXSW_SP_PORT_MASK_WIDTH_8X,
3038 .speed = SPEED_5000,
3041 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G,
3042 .mask_ethtool = mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g,
3043 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN,
3044 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
3045 MLXSW_SP_PORT_MASK_WIDTH_2X |
3046 MLXSW_SP_PORT_MASK_WIDTH_4X |
3047 MLXSW_SP_PORT_MASK_WIDTH_8X,
3048 .speed = SPEED_10000,
3051 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G,
3052 .mask_ethtool = mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g,
3053 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN,
3054 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_4X |
3055 MLXSW_SP_PORT_MASK_WIDTH_8X,
3056 .speed = SPEED_40000,
3059 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR,
3060 .mask_ethtool = mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr,
3061 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN,
3062 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
3063 MLXSW_SP_PORT_MASK_WIDTH_2X |
3064 MLXSW_SP_PORT_MASK_WIDTH_4X |
3065 MLXSW_SP_PORT_MASK_WIDTH_8X,
3066 .speed = SPEED_25000,
3069 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
3070 .mask_ethtool = mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2,
3071 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN,
3072 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_2X |
3073 MLXSW_SP_PORT_MASK_WIDTH_4X |
3074 MLXSW_SP_PORT_MASK_WIDTH_8X,
3075 .speed = SPEED_50000,
3078 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR,
3079 .mask_ethtool = mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr,
3080 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN,
3081 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X,
3082 .speed = SPEED_50000,
3085 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4,
3086 .mask_ethtool = mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4,
3087 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN,
3088 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_4X |
3089 MLXSW_SP_PORT_MASK_WIDTH_8X,
3090 .speed = SPEED_100000,
3093 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2,
3094 .mask_ethtool = mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2,
3095 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN,
3096 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_2X,
3097 .speed = SPEED_100000,
3100 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4,
3101 .mask_ethtool = mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4,
3102 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN,
3103 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_4X |
3104 MLXSW_SP_PORT_MASK_WIDTH_8X,
3105 .speed = SPEED_200000,
3108 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8,
3109 .mask_ethtool = mlxsw_sp2_mask_ethtool_400gaui_8,
3110 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN,
3111 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_8X,
3112 .speed = SPEED_400000,
3116 #define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)
3119 mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
3121 struct ethtool_link_ksettings *cmd)
3123 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
3124 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
3128 mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
3129 unsigned long *mode)
3133 for (i = 0; i < link_mode->m_ethtool_len; i++)
3134 __set_bit(link_mode->mask_ethtool[i], mode);
3138 mlxsw_sp2_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
3139 u8 width, unsigned long *mode)
3141 u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3144 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3145 if ((ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) &&
3146 (mask_width & mlxsw_sp2_port_link_mode[i].mask_width))
3147 mlxsw_sp2_set_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
3153 mlxsw_sp2_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
3157 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3158 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask)
3159 return mlxsw_sp2_port_link_mode[i].speed;
3162 return SPEED_UNKNOWN;
3166 mlxsw_sp2_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
3168 struct ethtool_link_ksettings *cmd)
3170 cmd->base.speed = SPEED_UNKNOWN;
3171 cmd->base.duplex = DUPLEX_UNKNOWN;
3176 cmd->base.speed = mlxsw_sp2_from_ptys_speed(mlxsw_sp, ptys_eth_proto);
3177 if (cmd->base.speed != SPEED_UNKNOWN)
3178 cmd->base.duplex = DUPLEX_FULL;
3182 mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
3183 const unsigned long *mode)
3188 for (i = 0; i < link_mode->m_ethtool_len; i++) {
3189 if (test_bit(link_mode->mask_ethtool[i], mode))
3193 return cnt == link_mode->m_ethtool_len;
3197 mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, u8 width,
3198 const struct ethtool_link_ksettings *cmd)
3200 u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3204 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3205 if ((mask_width & mlxsw_sp2_port_link_mode[i].mask_width) &&
3206 mlxsw_sp2_test_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
3207 cmd->link_modes.advertising))
3208 ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3213 static u32 mlxsw_sp2_to_ptys_speed(struct mlxsw_sp *mlxsw_sp,
3214 u8 width, u32 speed)
3216 u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3220 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3221 if ((speed == mlxsw_sp2_port_link_mode[i].speed) &&
3222 (mask_width & mlxsw_sp2_port_link_mode[i].mask_width))
3223 ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3229 mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
3230 u8 local_port, u32 proto_admin,
3233 mlxsw_reg_ptys_ext_eth_pack(payload, local_port, proto_admin, autoneg);
3237 mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
3238 u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
3239 u32 *p_eth_proto_oper)
3241 mlxsw_reg_ptys_ext_eth_unpack(payload, p_eth_proto_cap,
3242 p_eth_proto_admin, p_eth_proto_oper);
3245 static const struct mlxsw_sp_port_type_speed_ops
3246 mlxsw_sp2_port_type_speed_ops = {
3247 .from_ptys_supported_port = mlxsw_sp2_from_ptys_supported_port,
3248 .from_ptys_link = mlxsw_sp2_from_ptys_link,
3249 .from_ptys_speed = mlxsw_sp2_from_ptys_speed,
3250 .from_ptys_speed_duplex = mlxsw_sp2_from_ptys_speed_duplex,
3251 .to_ptys_advert_link = mlxsw_sp2_to_ptys_advert_link,
3252 .to_ptys_speed = mlxsw_sp2_to_ptys_speed,
3253 .reg_ptys_eth_pack = mlxsw_sp2_reg_ptys_eth_pack,
3254 .reg_ptys_eth_unpack = mlxsw_sp2_reg_ptys_eth_unpack,
3258 mlxsw_sp_port_get_link_supported(struct mlxsw_sp *mlxsw_sp, u32 eth_proto_cap,
3259 u8 width, struct ethtool_link_ksettings *cmd)
3261 const struct mlxsw_sp_port_type_speed_ops *ops;
3263 ops = mlxsw_sp->port_type_speed_ops;
3265 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
3266 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
3267 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
3269 ops->from_ptys_supported_port(mlxsw_sp, eth_proto_cap, cmd);
3270 ops->from_ptys_link(mlxsw_sp, eth_proto_cap, width,
3271 cmd->link_modes.supported);
3275 mlxsw_sp_port_get_link_advertise(struct mlxsw_sp *mlxsw_sp,
3276 u32 eth_proto_admin, bool autoneg, u8 width,
3277 struct ethtool_link_ksettings *cmd)
3279 const struct mlxsw_sp_port_type_speed_ops *ops;
3281 ops = mlxsw_sp->port_type_speed_ops;
3286 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
3287 ops->from_ptys_link(mlxsw_sp, eth_proto_admin, width,
3288 cmd->link_modes.advertising);
3292 mlxsw_sp_port_connector_port(enum mlxsw_reg_ptys_connector_type connector_type)
3294 switch (connector_type) {
3295 case MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR:
3297 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE:
3299 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP:
3301 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI:
3303 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC:
3305 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII:
3307 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE:
3309 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA:
3311 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER:
3319 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
3320 struct ethtool_link_ksettings *cmd)
3322 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
3323 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3324 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3325 const struct mlxsw_sp_port_type_speed_ops *ops;
3326 char ptys_pl[MLXSW_REG_PTYS_LEN];
3331 ops = mlxsw_sp->port_type_speed_ops;
3333 autoneg = mlxsw_sp_port->link.autoneg;
3334 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3336 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3339 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap,
3340 ð_proto_admin, ð_proto_oper);
3342 mlxsw_sp_port_get_link_supported(mlxsw_sp, eth_proto_cap,
3343 mlxsw_sp_port->mapping.width, cmd);
3345 mlxsw_sp_port_get_link_advertise(mlxsw_sp, eth_proto_admin, autoneg,
3346 mlxsw_sp_port->mapping.width, cmd);
3348 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3349 connector_type = mlxsw_reg_ptys_connector_type_get(ptys_pl);
3350 cmd->base.port = mlxsw_sp_port_connector_port(connector_type);
3351 ops->from_ptys_speed_duplex(mlxsw_sp, netif_carrier_ok(dev),
3352 eth_proto_oper, cmd);
3358 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
3359 const struct ethtool_link_ksettings *cmd)
3361 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3362 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3363 const struct mlxsw_sp_port_type_speed_ops *ops;
3364 char ptys_pl[MLXSW_REG_PTYS_LEN];
3365 u32 eth_proto_cap, eth_proto_new;
3369 ops = mlxsw_sp->port_type_speed_ops;
3371 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3373 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3376 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap, NULL, NULL);
3378 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
3379 eth_proto_new = autoneg ?
3380 ops->to_ptys_advert_link(mlxsw_sp, mlxsw_sp_port->mapping.width,
3382 ops->to_ptys_speed(mlxsw_sp, mlxsw_sp_port->mapping.width,
3385 eth_proto_new = eth_proto_new & eth_proto_cap;
3386 if (!eth_proto_new) {
3387 netdev_err(dev, "No supported speed requested\n");
3391 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3392 eth_proto_new, autoneg);
3393 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3397 mlxsw_sp_port->link.autoneg = autoneg;
3399 if (!netif_running(dev))
3402 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3403 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
3408 static int mlxsw_sp_get_module_info(struct net_device *netdev,
3409 struct ethtool_modinfo *modinfo)
3411 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3412 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3415 err = mlxsw_env_get_module_info(mlxsw_sp->core,
3416 mlxsw_sp_port->mapping.module,
3422 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
3423 struct ethtool_eeprom *ee,
3426 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3427 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3430 err = mlxsw_env_get_module_eeprom(netdev, mlxsw_sp->core,
3431 mlxsw_sp_port->mapping.module, ee,
3438 mlxsw_sp_get_ts_info(struct net_device *netdev, struct ethtool_ts_info *info)
3440 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3441 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3443 return mlxsw_sp->ptp_ops->get_ts_info(mlxsw_sp, info);
3446 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
3447 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
3448 .get_link = ethtool_op_get_link,
3449 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
3450 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
3451 .get_strings = mlxsw_sp_port_get_strings,
3452 .set_phys_id = mlxsw_sp_port_set_phys_id,
3453 .get_ethtool_stats = mlxsw_sp_port_get_stats,
3454 .get_sset_count = mlxsw_sp_port_get_sset_count,
3455 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
3456 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
3457 .get_module_info = mlxsw_sp_get_module_info,
3458 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
3459 .get_ts_info = mlxsw_sp_get_ts_info,
3463 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port)
3465 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3466 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
3467 const struct mlxsw_sp_port_type_speed_ops *ops;
3468 char ptys_pl[MLXSW_REG_PTYS_LEN];
3471 ops = mlxsw_sp->port_type_speed_ops;
3473 /* Set advertised speeds to supported speeds. */
3474 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3476 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3480 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap,
3481 ð_proto_admin, ð_proto_oper);
3482 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3483 eth_proto_cap, mlxsw_sp_port->link.autoneg);
3484 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3487 int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed)
3489 const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops;
3490 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3491 char ptys_pl[MLXSW_REG_PTYS_LEN];
3495 port_type_speed_ops = mlxsw_sp->port_type_speed_ops;
3496 port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl,
3497 mlxsw_sp_port->local_port, 0,
3499 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3502 port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL,
3504 *speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper);
3508 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
3509 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
3510 bool dwrr, u8 dwrr_weight)
3512 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3513 char qeec_pl[MLXSW_REG_QEEC_LEN];
3515 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3517 mlxsw_reg_qeec_de_set(qeec_pl, true);
3518 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
3519 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
3520 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3523 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
3524 enum mlxsw_reg_qeec_hr hr, u8 index,
3525 u8 next_index, u32 maxrate, u8 burst_size)
3527 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3528 char qeec_pl[MLXSW_REG_QEEC_LEN];
3530 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3532 mlxsw_reg_qeec_mase_set(qeec_pl, true);
3533 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
3534 mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size);
3535 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3538 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
3539 enum mlxsw_reg_qeec_hr hr, u8 index,
3540 u8 next_index, u32 minrate)
3542 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3543 char qeec_pl[MLXSW_REG_QEEC_LEN];
3545 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3547 mlxsw_reg_qeec_mise_set(qeec_pl, true);
3548 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
3550 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3553 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
3554 u8 switch_prio, u8 tclass)
3556 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3557 char qtct_pl[MLXSW_REG_QTCT_LEN];
3559 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
3561 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
3564 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
3568 /* Setup the elements hierarcy, so that each TC is linked to
3569 * one subgroup, which are all member in the same group.
3571 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3572 MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0);
3575 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3576 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3577 MLXSW_REG_QEEC_HR_SUBGROUP, i,
3582 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3583 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3584 MLXSW_REG_QEEC_HR_TC, i, i,
3589 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3590 MLXSW_REG_QEEC_HR_TC,
3597 /* Make sure the max shaper is disabled in all hierarchies that support
3598 * it. Note that this disables ptps (PTP shaper), but that is intended
3599 * for the initial configuration.
3601 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3602 MLXSW_REG_QEEC_HR_PORT, 0, 0,
3603 MLXSW_REG_QEEC_MAS_DIS, 0);
3606 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3607 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3608 MLXSW_REG_QEEC_HR_SUBGROUP,
3610 MLXSW_REG_QEEC_MAS_DIS, 0);
3614 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3615 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3616 MLXSW_REG_QEEC_HR_TC,
3618 MLXSW_REG_QEEC_MAS_DIS, 0);
3622 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3623 MLXSW_REG_QEEC_HR_TC,
3625 MLXSW_REG_QEEC_MAS_DIS, 0);
3630 /* Configure the min shaper for multicast TCs. */
3631 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3632 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
3633 MLXSW_REG_QEEC_HR_TC,
3635 MLXSW_REG_QEEC_MIS_MIN);
3640 /* Map all priorities to traffic class 0. */
3641 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3642 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
3650 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
3653 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3654 char qtctm_pl[MLXSW_REG_QTCTM_LEN];
3656 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
3657 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
3660 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3661 u8 split_base_local_port,
3662 struct mlxsw_sp_port_mapping *port_mapping)
3664 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
3665 bool split = !!split_base_local_port;
3666 struct mlxsw_sp_port *mlxsw_sp_port;
3667 struct net_device *dev;
3670 err = mlxsw_core_port_init(mlxsw_sp->core, local_port,
3671 port_mapping->module + 1, split,
3672 port_mapping->lane / port_mapping->width,
3674 sizeof(mlxsw_sp->base_mac));
3676 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
3681 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
3684 goto err_alloc_etherdev;
3686 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
3687 dev_net_set(dev, mlxsw_sp_net(mlxsw_sp));
3688 mlxsw_sp_port = netdev_priv(dev);
3689 mlxsw_sp_port->dev = dev;
3690 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3691 mlxsw_sp_port->local_port = local_port;
3692 mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
3693 mlxsw_sp_port->split = split;
3694 mlxsw_sp_port->split_base_local_port = split_base_local_port;
3695 mlxsw_sp_port->mapping = *port_mapping;
3696 mlxsw_sp_port->link.autoneg = 1;
3697 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
3698 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
3700 mlxsw_sp_port->pcpu_stats =
3701 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
3702 if (!mlxsw_sp_port->pcpu_stats) {
3704 goto err_alloc_stats;
3707 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
3709 if (!mlxsw_sp_port->sample) {
3711 goto err_alloc_sample;
3714 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
3715 &update_stats_cache);
3717 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
3718 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3720 err = mlxsw_sp_port_module_map(mlxsw_sp_port);
3722 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3723 mlxsw_sp_port->local_port);
3724 goto err_port_module_map;
3727 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3729 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3730 mlxsw_sp_port->local_port);
3731 goto err_port_swid_set;
3734 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3736 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3737 mlxsw_sp_port->local_port);
3738 goto err_dev_addr_init;
3741 netif_carrier_off(dev);
3743 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
3744 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3745 dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK;
3748 dev->max_mtu = ETH_MAX_MTU;
3750 /* Each packet needs to have a Tx header (metadata) on top all other
3753 dev->needed_headroom = MLXSW_TXHDR_LEN;
3755 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3757 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3758 mlxsw_sp_port->local_port);
3759 goto err_port_system_port_mapping_set;
3762 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port);
3764 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3765 mlxsw_sp_port->local_port);
3766 goto err_port_speed_by_width_set;
3769 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3771 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3772 mlxsw_sp_port->local_port);
3773 goto err_port_mtu_set;
3776 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3778 goto err_port_admin_status_set;
3780 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3782 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3783 mlxsw_sp_port->local_port);
3784 goto err_port_buffers_init;
3787 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3789 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3790 mlxsw_sp_port->local_port);
3791 goto err_port_ets_init;
3794 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
3796 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
3797 mlxsw_sp_port->local_port);
3798 goto err_port_tc_mc_mode;
3801 /* ETS and buffers must be initialized before DCB. */
3802 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3804 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3805 mlxsw_sp_port->local_port);
3806 goto err_port_dcb_init;
3809 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
3811 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
3812 mlxsw_sp_port->local_port);
3813 goto err_port_fids_init;
3816 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3818 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3819 mlxsw_sp_port->local_port);
3820 goto err_port_qdiscs_init;
3823 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false,
3826 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
3827 mlxsw_sp_port->local_port);
3828 goto err_port_vlan_clear;
3831 err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
3833 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
3834 mlxsw_sp_port->local_port);
3835 goto err_port_nve_init;
3838 err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
3840 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
3841 mlxsw_sp_port->local_port);
3842 goto err_port_pvid_set;
3845 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
3846 MLXSW_SP_DEFAULT_VID);
3847 if (IS_ERR(mlxsw_sp_port_vlan)) {
3848 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
3849 mlxsw_sp_port->local_port);
3850 err = PTR_ERR(mlxsw_sp_port_vlan);
3851 goto err_port_vlan_create;
3853 mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
3855 INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw,
3856 mlxsw_sp->ptp_ops->shaper_work);
3857 INIT_DELAYED_WORK(&mlxsw_sp_port->span.speed_update_dw,
3858 mlxsw_sp_span_speed_update_work);
3860 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
3861 err = register_netdev(dev);
3863 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3864 mlxsw_sp_port->local_port);
3865 goto err_register_netdev;
3868 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3869 mlxsw_sp_port, dev);
3870 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
3873 err_register_netdev:
3874 mlxsw_sp->ports[local_port] = NULL;
3875 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
3876 err_port_vlan_create:
3878 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3880 err_port_vlan_clear:
3881 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3882 err_port_qdiscs_init:
3883 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3885 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3887 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3888 err_port_tc_mc_mode:
3890 err_port_buffers_init:
3891 err_port_admin_status_set:
3893 err_port_speed_by_width_set:
3894 err_port_system_port_mapping_set:
3896 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3898 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3899 err_port_module_map:
3900 kfree(mlxsw_sp_port->sample);
3902 free_percpu(mlxsw_sp_port->pcpu_stats);
3906 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3910 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3912 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3914 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
3915 cancel_delayed_work_sync(&mlxsw_sp_port->span.speed_update_dw);
3916 cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw);
3917 mlxsw_sp_port_ptp_clear(mlxsw_sp_port);
3918 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
3919 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
3920 mlxsw_sp->ports[local_port] = NULL;
3921 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
3922 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3923 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3924 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3925 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3926 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3927 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3928 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3929 kfree(mlxsw_sp_port->sample);
3930 free_percpu(mlxsw_sp_port->pcpu_stats);
3931 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
3932 free_netdev(mlxsw_sp_port->dev);
3933 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3936 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
3938 struct mlxsw_sp_port *mlxsw_sp_port;
3941 mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL);
3945 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3946 mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT;
3948 err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
3951 sizeof(mlxsw_sp->base_mac));
3953 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
3954 goto err_core_cpu_port_init;
3957 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
3960 err_core_cpu_port_init:
3961 kfree(mlxsw_sp_port);
3965 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
3967 struct mlxsw_sp_port *mlxsw_sp_port =
3968 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
3970 mlxsw_core_cpu_port_fini(mlxsw_sp->core);
3971 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
3972 kfree(mlxsw_sp_port);
3975 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3977 return mlxsw_sp->ports[local_port] != NULL;
3980 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3984 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3985 if (mlxsw_sp_port_created(mlxsw_sp, i))
3986 mlxsw_sp_port_remove(mlxsw_sp, i);
3987 mlxsw_sp_cpu_port_remove(mlxsw_sp);
3988 kfree(mlxsw_sp->ports);
3991 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3993 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3994 struct mlxsw_sp_port_mapping *port_mapping;
3999 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
4000 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
4001 if (!mlxsw_sp->ports)
4004 err = mlxsw_sp_cpu_port_create(mlxsw_sp);
4006 goto err_cpu_port_create;
4008 for (i = 1; i < max_ports; i++) {
4009 port_mapping = mlxsw_sp->port_mapping[i];
4012 err = mlxsw_sp_port_create(mlxsw_sp, i, 0, port_mapping);
4014 goto err_port_create;
4019 for (i--; i >= 1; i--)
4020 if (mlxsw_sp_port_created(mlxsw_sp, i))
4021 mlxsw_sp_port_remove(mlxsw_sp, i);
4022 mlxsw_sp_cpu_port_remove(mlxsw_sp);
4023 err_cpu_port_create:
4024 kfree(mlxsw_sp->ports);
4028 static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp)
4030 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
4031 struct mlxsw_sp_port_mapping port_mapping;
4035 mlxsw_sp->port_mapping = kcalloc(max_ports,
4036 sizeof(struct mlxsw_sp_port_mapping *),
4038 if (!mlxsw_sp->port_mapping)
4041 for (i = 1; i < max_ports; i++) {
4042 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &port_mapping);
4044 goto err_port_module_info_get;
4045 if (!port_mapping.width)
4048 mlxsw_sp->port_mapping[i] = kmemdup(&port_mapping,
4049 sizeof(port_mapping),
4051 if (!mlxsw_sp->port_mapping[i]) {
4053 goto err_port_module_info_dup;
4058 err_port_module_info_get:
4059 err_port_module_info_dup:
4060 for (i--; i >= 1; i--)
4061 kfree(mlxsw_sp->port_mapping[i]);
4062 kfree(mlxsw_sp->port_mapping);
4066 static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp)
4070 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
4071 kfree(mlxsw_sp->port_mapping[i]);
4072 kfree(mlxsw_sp->port_mapping);
4075 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port, unsigned int max_width)
4077 u8 offset = (local_port - 1) % max_width;
4079 return local_port - offset;
4083 mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
4084 struct mlxsw_sp_port_mapping *port_mapping,
4085 unsigned int count, u8 offset)
4087 struct mlxsw_sp_port_mapping split_port_mapping;
4090 split_port_mapping = *port_mapping;
4091 split_port_mapping.width /= count;
4092 for (i = 0; i < count; i++) {
4093 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i * offset,
4094 base_port, &split_port_mapping);
4096 goto err_port_create;
4097 split_port_mapping.lane += split_port_mapping.width;
4103 for (i--; i >= 0; i--)
4104 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4105 mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4109 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
4111 unsigned int count, u8 offset)
4113 struct mlxsw_sp_port_mapping *port_mapping;
4116 /* Go over original unsplit ports in the gap and recreate them. */
4117 for (i = 0; i < count * offset; i++) {
4118 port_mapping = mlxsw_sp->port_mapping[base_port + i];
4121 mlxsw_sp_port_create(mlxsw_sp, base_port + i, 0, port_mapping);
4125 static int mlxsw_sp_local_ports_offset(struct mlxsw_core *mlxsw_core,
4127 unsigned int max_width)
4129 enum mlxsw_res_id local_ports_in_x_res_id;
4130 int split_width = max_width / count;
4132 if (split_width == 1)
4133 local_ports_in_x_res_id = MLXSW_RES_ID_LOCAL_PORTS_IN_1X;
4134 else if (split_width == 2)
4135 local_ports_in_x_res_id = MLXSW_RES_ID_LOCAL_PORTS_IN_2X;
4136 else if (split_width == 4)
4137 local_ports_in_x_res_id = MLXSW_RES_ID_LOCAL_PORTS_IN_4X;
4141 if (!mlxsw_core_res_valid(mlxsw_core, local_ports_in_x_res_id))
4143 return mlxsw_core_res_get(mlxsw_core, local_ports_in_x_res_id);
4146 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
4148 struct netlink_ext_ack *extack)
4150 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4151 struct mlxsw_sp_port_mapping port_mapping;
4152 struct mlxsw_sp_port *mlxsw_sp_port;
4159 mlxsw_sp_port = mlxsw_sp->ports[local_port];
4160 if (!mlxsw_sp_port) {
4161 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
4163 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
4167 /* Split ports cannot be split. */
4168 if (mlxsw_sp_port->split) {
4169 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
4170 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
4174 max_width = mlxsw_core_module_max_width(mlxsw_core,
4175 mlxsw_sp_port->mapping.module);
4176 if (max_width < 0) {
4177 netdev_err(mlxsw_sp_port->dev, "Cannot get max width of port module\n");
4178 NL_SET_ERR_MSG_MOD(extack, "Cannot get max width of port module");
4182 /* Split port with non-max and 1 module width cannot be split. */
4183 if (mlxsw_sp_port->mapping.width != max_width || max_width == 1) {
4184 netdev_err(mlxsw_sp_port->dev, "Port cannot be split\n");
4185 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split");
4189 if (count == 1 || !is_power_of_2(count) || count > max_width) {
4190 netdev_err(mlxsw_sp_port->dev, "Invalid split count\n");
4191 NL_SET_ERR_MSG_MOD(extack, "Invalid split count");
4195 offset = mlxsw_sp_local_ports_offset(mlxsw_core, count, max_width);
4197 netdev_err(mlxsw_sp_port->dev, "Cannot obtain local port offset\n");
4198 NL_SET_ERR_MSG_MOD(extack, "Cannot obtain local port offset");
4202 /* Only in case max split is being done, the local port and
4203 * base port may differ.
4205 base_port = count == max_width ?
4206 mlxsw_sp_cluster_base_port_get(local_port, max_width) :
4209 for (i = 0; i < count * offset; i++) {
4210 /* Expect base port to exist and also the one in the middle in
4211 * case of maximal split count.
4213 if (i == 0 || (count == max_width && i == count / 2))
4216 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) {
4217 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
4218 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
4223 port_mapping = mlxsw_sp_port->mapping;
4225 for (i = 0; i < count; i++)
4226 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4227 mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4229 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, &port_mapping,
4232 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
4233 goto err_port_split_create;
4238 err_port_split_create:
4239 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count, offset);
4243 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
4244 struct netlink_ext_ack *extack)
4246 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4247 struct mlxsw_sp_port *mlxsw_sp_port;
4254 mlxsw_sp_port = mlxsw_sp->ports[local_port];
4255 if (!mlxsw_sp_port) {
4256 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
4258 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
4262 if (!mlxsw_sp_port->split) {
4263 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
4264 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
4268 max_width = mlxsw_core_module_max_width(mlxsw_core,
4269 mlxsw_sp_port->mapping.module);
4270 if (max_width < 0) {
4271 netdev_err(mlxsw_sp_port->dev, "Cannot get max width of port module\n");
4272 NL_SET_ERR_MSG_MOD(extack, "Cannot get max width of port module");
4276 count = max_width / mlxsw_sp_port->mapping.width;
4278 offset = mlxsw_sp_local_ports_offset(mlxsw_core, count, max_width);
4279 if (WARN_ON(offset < 0)) {
4280 netdev_err(mlxsw_sp_port->dev, "Cannot obtain local port offset\n");
4281 NL_SET_ERR_MSG_MOD(extack, "Cannot obtain local port offset");
4285 base_port = mlxsw_sp_port->split_base_local_port;
4287 for (i = 0; i < count; i++)
4288 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4289 mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4291 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count, offset);
4297 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port)
4301 for (i = 0; i < TC_MAX_QUEUE; i++)
4302 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0;
4305 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
4306 char *pude_pl, void *priv)
4308 struct mlxsw_sp *mlxsw_sp = priv;
4309 struct mlxsw_sp_port *mlxsw_sp_port;
4310 enum mlxsw_reg_pude_oper_status status;
4313 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
4314 mlxsw_sp_port = mlxsw_sp->ports[local_port];
4318 status = mlxsw_reg_pude_oper_status_get(pude_pl);
4319 if (status == MLXSW_PORT_OPER_STATUS_UP) {
4320 netdev_info(mlxsw_sp_port->dev, "link up\n");
4321 netif_carrier_on(mlxsw_sp_port->dev);
4322 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0);
4323 mlxsw_core_schedule_dw(&mlxsw_sp_port->span.speed_update_dw, 0);
4325 netdev_info(mlxsw_sp_port->dev, "link down\n");
4326 netif_carrier_off(mlxsw_sp_port->dev);
4327 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port);
4331 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
4332 char *mtpptr_pl, bool ingress)
4338 local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl);
4339 num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl);
4340 for (i = 0; i < num_rec; i++) {
4346 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type,
4347 &domain_number, &sequence_id,
4349 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
4350 message_type, domain_number,
4351 sequence_id, timestamp);
4355 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg,
4356 char *mtpptr_pl, void *priv)
4358 struct mlxsw_sp *mlxsw_sp = priv;
4360 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
4363 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg,
4364 char *mtpptr_pl, void *priv)
4366 struct mlxsw_sp *mlxsw_sp = priv;
4368 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
4371 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
4372 u8 local_port, void *priv)
4374 struct mlxsw_sp *mlxsw_sp = priv;
4375 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
4376 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
4378 if (unlikely(!mlxsw_sp_port)) {
4379 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
4384 skb->dev = mlxsw_sp_port->dev;
4386 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
4387 u64_stats_update_begin(&pcpu_stats->syncp);
4388 pcpu_stats->rx_packets++;
4389 pcpu_stats->rx_bytes += skb->len;
4390 u64_stats_update_end(&pcpu_stats->syncp);
4392 skb->protocol = eth_type_trans(skb, skb->dev);
4393 netif_receive_skb(skb);
4396 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
4399 skb->offload_fwd_mark = 1;
4400 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
4403 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
4404 u8 local_port, void *priv)
4406 skb->offload_l3_fwd_mark = 1;
4407 skb->offload_fwd_mark = 1;
4408 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
4411 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
4414 struct mlxsw_sp *mlxsw_sp = priv;
4415 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
4416 struct psample_group *psample_group;
4419 if (unlikely(!mlxsw_sp_port)) {
4420 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
4424 if (unlikely(!mlxsw_sp_port->sample)) {
4425 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
4430 size = mlxsw_sp_port->sample->truncate ?
4431 mlxsw_sp_port->sample->trunc_size : skb->len;
4434 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
4437 psample_sample_packet(psample_group, skb, size,
4438 mlxsw_sp_port->dev->ifindex, 0,
4439 mlxsw_sp_port->sample->rate);
4446 static void mlxsw_sp_rx_listener_ptp(struct sk_buff *skb, u8 local_port,
4449 struct mlxsw_sp *mlxsw_sp = priv;
4451 mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
4454 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
4455 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
4456 _is_ctrl, SP_##_trap_group, DISCARD)
4458 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
4459 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
4460 _is_ctrl, SP_##_trap_group, DISCARD)
4462 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
4463 MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \
4464 _is_ctrl, SP_##_trap_group, DISCARD)
4466 #define MLXSW_SP_EVENTL(_func, _trap_id) \
4467 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
4469 static const struct mlxsw_listener mlxsw_sp_listener[] = {
4471 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
4473 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
4474 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
4475 MLXSW_RXL(mlxsw_sp_rx_listener_ptp, LLDP, TRAP_TO_CPU,
4476 false, SP_LLDP, DISCARD),
4477 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
4478 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
4479 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
4480 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
4481 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
4482 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
4483 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
4484 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
4485 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
4486 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
4488 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
4490 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
4492 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
4495 MLXSW_SP_RXL_L3_MARK(LBERROR, MIRROR_TO_CPU, LBERROR, false),
4496 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
4497 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
4499 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
4500 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
4501 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
4502 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
4504 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
4505 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
4506 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
4507 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
4508 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
4509 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
4510 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
4512 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
4514 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
4516 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
4518 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
4519 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
4521 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
4522 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
4523 MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, VRRP, false),
4524 MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, VRRP, false),
4525 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD,
4527 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD,
4529 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD,
4531 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD,
4533 /* PKT Sample trap */
4534 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
4535 false, SP_IP2ME, DISCARD),
4537 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
4538 /* Multicast Router Traps */
4539 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
4540 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
4541 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
4542 MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
4544 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false),
4545 MLXSW_SP_RXL_NO_MARK(NVE_DECAP_ARP, TRAP_TO_CPU, ARP, false),
4547 MLXSW_RXL(mlxsw_sp_rx_listener_ptp, PTP0, TRAP_TO_CPU,
4548 false, SP_PTP0, DISCARD),
4549 MLXSW_SP_RXL_NO_MARK(PTP1, TRAP_TO_CPU, PTP1, false),
4552 static const struct mlxsw_listener mlxsw_sp1_listener[] = {
4554 MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0),
4555 MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0),
4558 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
4560 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4561 char qpcr_pl[MLXSW_REG_QPCR_LEN];
4562 enum mlxsw_reg_qpcr_ir_units ir_units;
4563 int max_cpu_policers;
4569 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
4572 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
4574 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
4575 for (i = 0; i < max_cpu_policers; i++) {
4578 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
4579 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
4580 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
4581 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
4582 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
4583 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
4584 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
4588 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
4589 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
4593 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
4594 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
4595 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
4596 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
4597 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
4598 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
4599 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
4600 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
4604 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
4608 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:
4612 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:
4616 case MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP:
4624 __set_bit(i, mlxsw_sp->trap->policers_usage);
4625 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
4627 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
4635 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
4637 char htgt_pl[MLXSW_REG_HTGT_LEN];
4638 enum mlxsw_reg_htgt_trap_group i;
4639 int max_cpu_policers;
4640 int max_trap_groups;
4645 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
4648 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
4649 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
4651 for (i = 0; i < max_trap_groups; i++) {
4654 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
4655 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
4656 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
4657 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
4658 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
4659 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:
4660 case MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP:
4664 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
4665 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
4669 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
4670 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
4671 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
4675 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
4676 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
4677 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
4678 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:
4682 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
4683 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
4684 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
4685 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
4686 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
4690 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
4691 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
4692 tc = MLXSW_REG_HTGT_DEFAULT_TC;
4693 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
4699 if (max_cpu_policers <= policer_id &&
4700 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
4703 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
4704 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
4712 static int mlxsw_sp_traps_register(struct mlxsw_sp *mlxsw_sp,
4713 const struct mlxsw_listener listeners[],
4714 size_t listeners_count)
4719 for (i = 0; i < listeners_count; i++) {
4720 err = mlxsw_core_trap_register(mlxsw_sp->core,
4724 goto err_listener_register;
4729 err_listener_register:
4730 for (i--; i >= 0; i--) {
4731 mlxsw_core_trap_unregister(mlxsw_sp->core,
4738 static void mlxsw_sp_traps_unregister(struct mlxsw_sp *mlxsw_sp,
4739 const struct mlxsw_listener listeners[],
4740 size_t listeners_count)
4744 for (i = 0; i < listeners_count; i++) {
4745 mlxsw_core_trap_unregister(mlxsw_sp->core,
4751 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
4753 struct mlxsw_sp_trap *trap;
4757 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS))
4759 max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS);
4760 trap = kzalloc(struct_size(trap, policers_usage,
4761 BITS_TO_LONGS(max_policers)), GFP_KERNEL);
4764 trap->max_policers = max_policers;
4765 mlxsw_sp->trap = trap;
4767 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
4769 goto err_cpu_policers_set;
4771 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
4773 goto err_trap_groups_set;
4775 err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp_listener,
4776 ARRAY_SIZE(mlxsw_sp_listener));
4778 goto err_traps_register;
4780 err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp->listeners,
4781 mlxsw_sp->listeners_count);
4783 goto err_extra_traps_init;
4787 err_extra_traps_init:
4788 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
4789 ARRAY_SIZE(mlxsw_sp_listener));
4791 err_trap_groups_set:
4792 err_cpu_policers_set:
4797 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
4799 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp->listeners,
4800 mlxsw_sp->listeners_count);
4801 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
4802 ARRAY_SIZE(mlxsw_sp_listener));
4803 kfree(mlxsw_sp->trap);
4806 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe
4808 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
4810 char slcr_pl[MLXSW_REG_SLCR_LEN];
4814 seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
4815 MLXSW_SP_LAG_SEED_INIT);
4816 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
4817 MLXSW_REG_SLCR_LAG_HASH_DMAC |
4818 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
4819 MLXSW_REG_SLCR_LAG_HASH_VLANID |
4820 MLXSW_REG_SLCR_LAG_HASH_SIP |
4821 MLXSW_REG_SLCR_LAG_HASH_DIP |
4822 MLXSW_REG_SLCR_LAG_HASH_SPORT |
4823 MLXSW_REG_SLCR_LAG_HASH_DPORT |
4824 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
4825 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
4829 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
4830 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
4833 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
4834 sizeof(struct mlxsw_sp_upper),
4836 if (!mlxsw_sp->lags)
4842 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
4844 kfree(mlxsw_sp->lags);
4847 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
4849 char htgt_pl[MLXSW_REG_HTGT_LEN];
4851 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
4852 MLXSW_REG_HTGT_INVALID_POLICER,
4853 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
4854 MLXSW_REG_HTGT_DEFAULT_TC);
4855 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
4858 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = {
4859 .clock_init = mlxsw_sp1_ptp_clock_init,
4860 .clock_fini = mlxsw_sp1_ptp_clock_fini,
4861 .init = mlxsw_sp1_ptp_init,
4862 .fini = mlxsw_sp1_ptp_fini,
4863 .receive = mlxsw_sp1_ptp_receive,
4864 .transmitted = mlxsw_sp1_ptp_transmitted,
4865 .hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get,
4866 .hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set,
4867 .shaper_work = mlxsw_sp1_ptp_shaper_work,
4868 .get_ts_info = mlxsw_sp1_ptp_get_ts_info,
4869 .get_stats_count = mlxsw_sp1_get_stats_count,
4870 .get_stats_strings = mlxsw_sp1_get_stats_strings,
4871 .get_stats = mlxsw_sp1_get_stats,
4874 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = {
4875 .clock_init = mlxsw_sp2_ptp_clock_init,
4876 .clock_fini = mlxsw_sp2_ptp_clock_fini,
4877 .init = mlxsw_sp2_ptp_init,
4878 .fini = mlxsw_sp2_ptp_fini,
4879 .receive = mlxsw_sp2_ptp_receive,
4880 .transmitted = mlxsw_sp2_ptp_transmitted,
4881 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get,
4882 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set,
4883 .shaper_work = mlxsw_sp2_ptp_shaper_work,
4884 .get_ts_info = mlxsw_sp2_ptp_get_ts_info,
4885 .get_stats_count = mlxsw_sp2_get_stats_count,
4886 .get_stats_strings = mlxsw_sp2_get_stats_strings,
4887 .get_stats = mlxsw_sp2_get_stats,
4890 static u32 mlxsw_sp1_span_buffsize_get(int mtu, u32 speed)
4895 static const struct mlxsw_sp_span_ops mlxsw_sp1_span_ops = {
4896 .buffsize_get = mlxsw_sp1_span_buffsize_get,
4899 #define MLXSW_SP2_SPAN_EG_MIRROR_BUFFER_FACTOR 38
4900 #define MLXSW_SP3_SPAN_EG_MIRROR_BUFFER_FACTOR 50
4902 static u32 __mlxsw_sp_span_buffsize_get(int mtu, u32 speed, u32 buffer_factor)
4904 return 3 * mtu + buffer_factor * speed / 1000;
4907 static u32 mlxsw_sp2_span_buffsize_get(int mtu, u32 speed)
4909 int factor = MLXSW_SP2_SPAN_EG_MIRROR_BUFFER_FACTOR;
4911 return __mlxsw_sp_span_buffsize_get(mtu, speed, factor);
4914 static const struct mlxsw_sp_span_ops mlxsw_sp2_span_ops = {
4915 .buffsize_get = mlxsw_sp2_span_buffsize_get,
4918 static u32 mlxsw_sp3_span_buffsize_get(int mtu, u32 speed)
4920 int factor = MLXSW_SP3_SPAN_EG_MIRROR_BUFFER_FACTOR;
4922 return __mlxsw_sp_span_buffsize_get(mtu, speed, factor);
4925 static const struct mlxsw_sp_span_ops mlxsw_sp3_span_ops = {
4926 .buffsize_get = mlxsw_sp3_span_buffsize_get,
4929 u32 mlxsw_sp_span_buffsize_get(struct mlxsw_sp *mlxsw_sp, int mtu, u32 speed)
4931 u32 buffsize = mlxsw_sp->span_ops->buffsize_get(speed, mtu);
4933 return mlxsw_sp_bytes_cells(mlxsw_sp, buffsize) + 1;
4936 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4937 unsigned long event, void *ptr);
4939 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
4940 const struct mlxsw_bus_info *mlxsw_bus_info,
4941 struct netlink_ext_ack *extack)
4943 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4946 mlxsw_sp->core = mlxsw_core;
4947 mlxsw_sp->bus_info = mlxsw_bus_info;
4949 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
4953 mlxsw_core_emad_string_tlv_enable(mlxsw_core);
4955 err = mlxsw_sp_base_mac_get(mlxsw_sp);
4957 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
4961 err = mlxsw_sp_kvdl_init(mlxsw_sp);
4963 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
4967 err = mlxsw_sp_fids_init(mlxsw_sp);
4969 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
4973 err = mlxsw_sp_traps_init(mlxsw_sp);
4975 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
4976 goto err_traps_init;
4979 err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
4981 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
4982 goto err_devlink_traps_init;
4985 err = mlxsw_sp_buffers_init(mlxsw_sp);
4987 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
4988 goto err_buffers_init;
4991 err = mlxsw_sp_lag_init(mlxsw_sp);
4993 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
4997 /* Initialize SPAN before router and switchdev, so that those components
4998 * can call mlxsw_sp_span_respin().
5000 err = mlxsw_sp_span_init(mlxsw_sp);
5002 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
5006 err = mlxsw_sp_switchdev_init(mlxsw_sp);
5008 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
5009 goto err_switchdev_init;
5012 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
5014 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
5015 goto err_counter_pool_init;
5018 err = mlxsw_sp_afa_init(mlxsw_sp);
5020 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
5024 err = mlxsw_sp_nve_init(mlxsw_sp);
5026 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
5030 err = mlxsw_sp_acl_init(mlxsw_sp);
5032 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
5036 err = mlxsw_sp_router_init(mlxsw_sp, extack);
5038 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
5039 goto err_router_init;
5042 if (mlxsw_sp->bus_info->read_frc_capable) {
5043 /* NULL is a valid return value from clock_init */
5045 mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
5046 mlxsw_sp->bus_info->dev);
5047 if (IS_ERR(mlxsw_sp->clock)) {
5048 err = PTR_ERR(mlxsw_sp->clock);
5049 dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
5050 goto err_ptp_clock_init;
5054 if (mlxsw_sp->clock) {
5055 /* NULL is a valid return value from ptp_ops->init */
5056 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
5057 if (IS_ERR(mlxsw_sp->ptp_state)) {
5058 err = PTR_ERR(mlxsw_sp->ptp_state);
5059 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
5064 /* Initialize netdevice notifier after router and SPAN is initialized,
5065 * so that the event handler can use router structures and call SPAN
5068 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
5069 err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
5070 &mlxsw_sp->netdevice_nb);
5072 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
5073 goto err_netdev_notifier;
5076 err = mlxsw_sp_dpipe_init(mlxsw_sp);
5078 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
5079 goto err_dpipe_init;
5082 err = mlxsw_sp_port_module_info_init(mlxsw_sp);
5084 dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n");
5085 goto err_port_module_info_init;
5088 err = mlxsw_sp_ports_create(mlxsw_sp);
5090 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
5091 goto err_ports_create;
5097 mlxsw_sp_port_module_info_fini(mlxsw_sp);
5098 err_port_module_info_init:
5099 mlxsw_sp_dpipe_fini(mlxsw_sp);
5101 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
5102 &mlxsw_sp->netdevice_nb);
5103 err_netdev_notifier:
5104 if (mlxsw_sp->clock)
5105 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
5107 if (mlxsw_sp->clock)
5108 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
5110 mlxsw_sp_router_fini(mlxsw_sp);
5112 mlxsw_sp_acl_fini(mlxsw_sp);
5114 mlxsw_sp_nve_fini(mlxsw_sp);
5116 mlxsw_sp_afa_fini(mlxsw_sp);
5118 mlxsw_sp_counter_pool_fini(mlxsw_sp);
5119 err_counter_pool_init:
5120 mlxsw_sp_switchdev_fini(mlxsw_sp);
5122 mlxsw_sp_span_fini(mlxsw_sp);
5124 mlxsw_sp_lag_fini(mlxsw_sp);
5126 mlxsw_sp_buffers_fini(mlxsw_sp);
5128 mlxsw_sp_devlink_traps_fini(mlxsw_sp);
5129 err_devlink_traps_init:
5130 mlxsw_sp_traps_fini(mlxsw_sp);
5132 mlxsw_sp_fids_fini(mlxsw_sp);
5134 mlxsw_sp_kvdl_fini(mlxsw_sp);
5138 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
5139 const struct mlxsw_bus_info *mlxsw_bus_info,
5140 struct netlink_ext_ack *extack)
5142 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5144 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
5145 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
5146 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
5147 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
5148 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
5149 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
5150 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
5151 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
5152 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
5153 mlxsw_sp->rif_ops_arr = mlxsw_sp1_rif_ops_arr;
5154 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
5155 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
5156 mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
5157 mlxsw_sp->span_ops = &mlxsw_sp1_span_ops;
5158 mlxsw_sp->listeners = mlxsw_sp1_listener;
5159 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
5160 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1;
5162 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
5165 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
5166 const struct mlxsw_bus_info *mlxsw_bus_info,
5167 struct netlink_ext_ack *extack)
5169 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5171 mlxsw_sp->req_rev = &mlxsw_sp2_fw_rev;
5172 mlxsw_sp->fw_filename = MLXSW_SP2_FW_FILENAME;
5173 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
5174 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
5175 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
5176 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
5177 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
5178 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
5179 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
5180 mlxsw_sp->rif_ops_arr = mlxsw_sp2_rif_ops_arr;
5181 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
5182 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
5183 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
5184 mlxsw_sp->span_ops = &mlxsw_sp2_span_ops;
5185 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2;
5187 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
5190 static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core,
5191 const struct mlxsw_bus_info *mlxsw_bus_info,
5192 struct netlink_ext_ack *extack)
5194 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5196 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
5197 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
5198 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
5199 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
5200 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
5201 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
5202 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
5203 mlxsw_sp->rif_ops_arr = mlxsw_sp2_rif_ops_arr;
5204 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
5205 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
5206 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
5207 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
5208 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3;
5210 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
5213 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
5215 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5217 mlxsw_sp_ports_remove(mlxsw_sp);
5218 mlxsw_sp_port_module_info_fini(mlxsw_sp);
5219 mlxsw_sp_dpipe_fini(mlxsw_sp);
5220 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
5221 &mlxsw_sp->netdevice_nb);
5222 if (mlxsw_sp->clock) {
5223 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
5224 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
5226 mlxsw_sp_router_fini(mlxsw_sp);
5227 mlxsw_sp_acl_fini(mlxsw_sp);
5228 mlxsw_sp_nve_fini(mlxsw_sp);
5229 mlxsw_sp_afa_fini(mlxsw_sp);
5230 mlxsw_sp_counter_pool_fini(mlxsw_sp);
5231 mlxsw_sp_switchdev_fini(mlxsw_sp);
5232 mlxsw_sp_span_fini(mlxsw_sp);
5233 mlxsw_sp_lag_fini(mlxsw_sp);
5234 mlxsw_sp_buffers_fini(mlxsw_sp);
5235 mlxsw_sp_devlink_traps_fini(mlxsw_sp);
5236 mlxsw_sp_traps_fini(mlxsw_sp);
5237 mlxsw_sp_fids_fini(mlxsw_sp);
5238 mlxsw_sp_kvdl_fini(mlxsw_sp);
5241 /* Per-FID flood tables are used for both "true" 802.1D FIDs and emulated
5244 #define MLXSW_SP_FID_FLOOD_TABLE_SIZE (MLXSW_SP_FID_8021D_MAX + \
5247 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
5249 .max_mid = MLXSW_SP_MID_MAX,
5250 .used_flood_tables = 1,
5251 .used_flood_mode = 1,
5253 .max_fid_flood_tables = 3,
5254 .fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
5255 .used_max_ib_mc = 1,
5259 .used_kvd_sizes = 1,
5260 .kvd_hash_single_parts = 59,
5261 .kvd_hash_double_parts = 41,
5262 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
5266 .type = MLXSW_PORT_SWID_TYPE_ETH,
5271 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
5273 .max_mid = MLXSW_SP_MID_MAX,
5274 .used_flood_tables = 1,
5275 .used_flood_mode = 1,
5277 .max_fid_flood_tables = 3,
5278 .fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
5279 .used_max_ib_mc = 1,
5286 .type = MLXSW_PORT_SWID_TYPE_ETH,
5292 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
5293 struct devlink_resource_size_params *kvd_size_params,
5294 struct devlink_resource_size_params *linear_size_params,
5295 struct devlink_resource_size_params *hash_double_size_params,
5296 struct devlink_resource_size_params *hash_single_size_params)
5298 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
5299 KVD_SINGLE_MIN_SIZE);
5300 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
5301 KVD_DOUBLE_MIN_SIZE);
5302 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5303 u32 linear_size_min = 0;
5305 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
5306 MLXSW_SP_KVD_GRANULARITY,
5307 DEVLINK_RESOURCE_UNIT_ENTRY);
5308 devlink_resource_size_params_init(linear_size_params, linear_size_min,
5309 kvd_size - single_size_min -
5311 MLXSW_SP_KVD_GRANULARITY,
5312 DEVLINK_RESOURCE_UNIT_ENTRY);
5313 devlink_resource_size_params_init(hash_double_size_params,
5315 kvd_size - single_size_min -
5317 MLXSW_SP_KVD_GRANULARITY,
5318 DEVLINK_RESOURCE_UNIT_ENTRY);
5319 devlink_resource_size_params_init(hash_single_size_params,
5321 kvd_size - double_size_min -
5323 MLXSW_SP_KVD_GRANULARITY,
5324 DEVLINK_RESOURCE_UNIT_ENTRY);
5327 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
5329 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5330 struct devlink_resource_size_params hash_single_size_params;
5331 struct devlink_resource_size_params hash_double_size_params;
5332 struct devlink_resource_size_params linear_size_params;
5333 struct devlink_resource_size_params kvd_size_params;
5334 u32 kvd_size, single_size, double_size, linear_size;
5335 const struct mlxsw_config_profile *profile;
5338 profile = &mlxsw_sp1_config_profile;
5339 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
5342 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
5343 &linear_size_params,
5344 &hash_double_size_params,
5345 &hash_single_size_params);
5347 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5348 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
5349 kvd_size, MLXSW_SP_RESOURCE_KVD,
5350 DEVLINK_RESOURCE_ID_PARENT_TOP,
5355 linear_size = profile->kvd_linear_size;
5356 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
5358 MLXSW_SP_RESOURCE_KVD_LINEAR,
5359 MLXSW_SP_RESOURCE_KVD,
5360 &linear_size_params);
5364 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
5368 double_size = kvd_size - linear_size;
5369 double_size *= profile->kvd_hash_double_parts;
5370 double_size /= profile->kvd_hash_double_parts +
5371 profile->kvd_hash_single_parts;
5372 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
5373 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
5375 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
5376 MLXSW_SP_RESOURCE_KVD,
5377 &hash_double_size_params);
5381 single_size = kvd_size - double_size - linear_size;
5382 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
5384 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
5385 MLXSW_SP_RESOURCE_KVD,
5386 &hash_single_size_params);
5393 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core)
5395 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5396 struct devlink_resource_size_params kvd_size_params;
5399 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
5402 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5403 devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size,
5404 MLXSW_SP_KVD_GRANULARITY,
5405 DEVLINK_RESOURCE_UNIT_ENTRY);
5407 return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
5408 kvd_size, MLXSW_SP_RESOURCE_KVD,
5409 DEVLINK_RESOURCE_ID_PARENT_TOP,
5413 static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core)
5415 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5416 struct devlink_resource_size_params span_size_params;
5419 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN))
5422 max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN);
5423 devlink_resource_size_params_init(&span_size_params, max_span, max_span,
5424 1, DEVLINK_RESOURCE_UNIT_ENTRY);
5426 return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN,
5427 max_span, MLXSW_SP_RESOURCE_SPAN,
5428 DEVLINK_RESOURCE_ID_PARENT_TOP,
5432 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
5436 err = mlxsw_sp1_resources_kvd_register(mlxsw_core);
5440 err = mlxsw_sp_resources_span_register(mlxsw_core);
5442 goto err_resources_span_register;
5444 err = mlxsw_sp_counter_resources_register(mlxsw_core);
5446 goto err_resources_counter_register;
5450 err_resources_counter_register:
5451 err_resources_span_register:
5452 devlink_resources_unregister(priv_to_devlink(mlxsw_core), NULL);
5456 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
5460 err = mlxsw_sp2_resources_kvd_register(mlxsw_core);
5464 err = mlxsw_sp_resources_span_register(mlxsw_core);
5466 goto err_resources_span_register;
5468 err = mlxsw_sp_counter_resources_register(mlxsw_core);
5470 goto err_resources_counter_register;
5474 err_resources_counter_register:
5475 err_resources_span_register:
5476 devlink_resources_unregister(priv_to_devlink(mlxsw_core), NULL);
5480 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
5481 const struct mlxsw_config_profile *profile,
5482 u64 *p_single_size, u64 *p_double_size,
5485 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5489 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
5490 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
5493 /* The hash part is what left of the kvd without the
5494 * linear part. It is split to the single size and
5495 * double size by the parts ratio from the profile.
5496 * Both sizes must be a multiplications of the
5497 * granularity from the profile. In case the user
5498 * provided the sizes they are obtained via devlink.
5500 err = devlink_resource_size_get(devlink,
5501 MLXSW_SP_RESOURCE_KVD_LINEAR,
5504 *p_linear_size = profile->kvd_linear_size;
5506 err = devlink_resource_size_get(devlink,
5507 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
5510 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
5512 double_size *= profile->kvd_hash_double_parts;
5513 double_size /= profile->kvd_hash_double_parts +
5514 profile->kvd_hash_single_parts;
5515 *p_double_size = rounddown(double_size,
5516 MLXSW_SP_KVD_GRANULARITY);
5519 err = devlink_resource_size_get(devlink,
5520 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
5523 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
5524 *p_double_size - *p_linear_size;
5526 /* Check results are legal. */
5527 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
5528 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
5529 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
5536 mlxsw_sp_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id,
5537 union devlink_param_value val,
5538 struct netlink_ext_ack *extack)
5540 if ((val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER) &&
5541 (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)) {
5542 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'");
5549 static const struct devlink_param mlxsw_sp_devlink_params[] = {
5550 DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY,
5551 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
5553 mlxsw_sp_devlink_param_fw_load_policy_validate),
5556 static int mlxsw_sp_params_register(struct mlxsw_core *mlxsw_core)
5558 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5559 union devlink_param_value value;
5562 err = devlink_params_register(devlink, mlxsw_sp_devlink_params,
5563 ARRAY_SIZE(mlxsw_sp_devlink_params));
5567 value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER;
5568 devlink_param_driverinit_value_set(devlink,
5569 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
5574 static void mlxsw_sp_params_unregister(struct mlxsw_core *mlxsw_core)
5576 devlink_params_unregister(priv_to_devlink(mlxsw_core),
5577 mlxsw_sp_devlink_params,
5578 ARRAY_SIZE(mlxsw_sp_devlink_params));
5582 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id,
5583 struct devlink_param_gset_ctx *ctx)
5585 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
5586 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5588 ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp);
5593 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id,
5594 struct devlink_param_gset_ctx *ctx)
5596 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
5597 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5599 return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32);
5602 static const struct devlink_param mlxsw_sp2_devlink_params[] = {
5603 DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
5604 "acl_region_rehash_interval",
5605 DEVLINK_PARAM_TYPE_U32,
5606 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
5607 mlxsw_sp_params_acl_region_rehash_intrvl_get,
5608 mlxsw_sp_params_acl_region_rehash_intrvl_set,
5612 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core)
5614 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5615 union devlink_param_value value;
5618 err = mlxsw_sp_params_register(mlxsw_core);
5622 err = devlink_params_register(devlink, mlxsw_sp2_devlink_params,
5623 ARRAY_SIZE(mlxsw_sp2_devlink_params));
5625 goto err_devlink_params_register;
5628 devlink_param_driverinit_value_set(devlink,
5629 MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
5633 err_devlink_params_register:
5634 mlxsw_sp_params_unregister(mlxsw_core);
5638 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core)
5640 devlink_params_unregister(priv_to_devlink(mlxsw_core),
5641 mlxsw_sp2_devlink_params,
5642 ARRAY_SIZE(mlxsw_sp2_devlink_params));
5643 mlxsw_sp_params_unregister(mlxsw_core);
5646 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core,
5647 struct sk_buff *skb, u8 local_port)
5649 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5651 skb_pull(skb, MLXSW_TXHDR_LEN);
5652 mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
5655 static struct mlxsw_driver mlxsw_sp1_driver = {
5656 .kind = mlxsw_sp1_driver_name,
5657 .priv_size = sizeof(struct mlxsw_sp),
5658 .init = mlxsw_sp1_init,
5659 .fini = mlxsw_sp_fini,
5660 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
5661 .port_split = mlxsw_sp_port_split,
5662 .port_unsplit = mlxsw_sp_port_unsplit,
5663 .sb_pool_get = mlxsw_sp_sb_pool_get,
5664 .sb_pool_set = mlxsw_sp_sb_pool_set,
5665 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
5666 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
5667 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
5668 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
5669 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
5670 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
5671 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
5672 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
5673 .flash_update = mlxsw_sp_flash_update,
5674 .trap_init = mlxsw_sp_trap_init,
5675 .trap_fini = mlxsw_sp_trap_fini,
5676 .trap_action_set = mlxsw_sp_trap_action_set,
5677 .trap_group_init = mlxsw_sp_trap_group_init,
5678 .txhdr_construct = mlxsw_sp_txhdr_construct,
5679 .resources_register = mlxsw_sp1_resources_register,
5680 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
5681 .params_register = mlxsw_sp_params_register,
5682 .params_unregister = mlxsw_sp_params_unregister,
5683 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
5684 .txhdr_len = MLXSW_TXHDR_LEN,
5685 .profile = &mlxsw_sp1_config_profile,
5686 .res_query_enabled = true,
5689 static struct mlxsw_driver mlxsw_sp2_driver = {
5690 .kind = mlxsw_sp2_driver_name,
5691 .priv_size = sizeof(struct mlxsw_sp),
5692 .init = mlxsw_sp2_init,
5693 .fini = mlxsw_sp_fini,
5694 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
5695 .port_split = mlxsw_sp_port_split,
5696 .port_unsplit = mlxsw_sp_port_unsplit,
5697 .sb_pool_get = mlxsw_sp_sb_pool_get,
5698 .sb_pool_set = mlxsw_sp_sb_pool_set,
5699 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
5700 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
5701 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
5702 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
5703 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
5704 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
5705 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
5706 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
5707 .flash_update = mlxsw_sp_flash_update,
5708 .trap_init = mlxsw_sp_trap_init,
5709 .trap_fini = mlxsw_sp_trap_fini,
5710 .trap_action_set = mlxsw_sp_trap_action_set,
5711 .trap_group_init = mlxsw_sp_trap_group_init,
5712 .txhdr_construct = mlxsw_sp_txhdr_construct,
5713 .resources_register = mlxsw_sp2_resources_register,
5714 .params_register = mlxsw_sp2_params_register,
5715 .params_unregister = mlxsw_sp2_params_unregister,
5716 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
5717 .txhdr_len = MLXSW_TXHDR_LEN,
5718 .profile = &mlxsw_sp2_config_profile,
5719 .res_query_enabled = true,
5722 static struct mlxsw_driver mlxsw_sp3_driver = {
5723 .kind = mlxsw_sp3_driver_name,
5724 .priv_size = sizeof(struct mlxsw_sp),
5725 .init = mlxsw_sp3_init,
5726 .fini = mlxsw_sp_fini,
5727 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
5728 .port_split = mlxsw_sp_port_split,
5729 .port_unsplit = mlxsw_sp_port_unsplit,
5730 .sb_pool_get = mlxsw_sp_sb_pool_get,
5731 .sb_pool_set = mlxsw_sp_sb_pool_set,
5732 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
5733 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
5734 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
5735 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
5736 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
5737 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
5738 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
5739 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
5740 .flash_update = mlxsw_sp_flash_update,
5741 .trap_init = mlxsw_sp_trap_init,
5742 .trap_fini = mlxsw_sp_trap_fini,
5743 .trap_action_set = mlxsw_sp_trap_action_set,
5744 .trap_group_init = mlxsw_sp_trap_group_init,
5745 .txhdr_construct = mlxsw_sp_txhdr_construct,
5746 .resources_register = mlxsw_sp2_resources_register,
5747 .params_register = mlxsw_sp2_params_register,
5748 .params_unregister = mlxsw_sp2_params_unregister,
5749 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
5750 .txhdr_len = MLXSW_TXHDR_LEN,
5751 .profile = &mlxsw_sp2_config_profile,
5752 .res_query_enabled = true,
5755 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
5757 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
5760 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
5762 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
5765 if (mlxsw_sp_port_dev_check(lower_dev)) {
5766 *p_mlxsw_sp_port = netdev_priv(lower_dev);
5773 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
5775 struct mlxsw_sp_port *mlxsw_sp_port;
5777 if (mlxsw_sp_port_dev_check(dev))
5778 return netdev_priv(dev);
5780 mlxsw_sp_port = NULL;
5781 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
5783 return mlxsw_sp_port;
5786 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
5788 struct mlxsw_sp_port *mlxsw_sp_port;
5790 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
5791 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
5794 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
5796 struct mlxsw_sp_port *mlxsw_sp_port;
5798 if (mlxsw_sp_port_dev_check(dev))
5799 return netdev_priv(dev);
5801 mlxsw_sp_port = NULL;
5802 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
5805 return mlxsw_sp_port;
5808 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
5810 struct mlxsw_sp_port *mlxsw_sp_port;
5813 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
5815 dev_hold(mlxsw_sp_port->dev);
5817 return mlxsw_sp_port;
5820 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
5822 dev_put(mlxsw_sp_port->dev);
5826 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
5827 struct net_device *lag_dev)
5829 struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
5830 struct net_device *upper_dev;
5831 struct list_head *iter;
5833 if (netif_is_bridge_port(lag_dev))
5834 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
5836 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
5837 if (!netif_is_bridge_port(upper_dev))
5839 br_dev = netdev_master_upper_dev_get(upper_dev);
5840 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
5844 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
5846 char sldr_pl[MLXSW_REG_SLDR_LEN];
5848 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
5849 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5852 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
5854 char sldr_pl[MLXSW_REG_SLDR_LEN];
5856 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
5857 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5860 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
5861 u16 lag_id, u8 port_index)
5863 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5864 char slcor_pl[MLXSW_REG_SLCOR_LEN];
5866 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
5867 lag_id, port_index);
5868 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5871 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
5874 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5875 char slcor_pl[MLXSW_REG_SLCOR_LEN];
5877 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
5879 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5882 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
5885 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5886 char slcor_pl[MLXSW_REG_SLCOR_LEN];
5888 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
5890 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5893 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
5896 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5897 char slcor_pl[MLXSW_REG_SLCOR_LEN];
5899 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
5901 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5904 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
5905 struct net_device *lag_dev,
5908 struct mlxsw_sp_upper *lag;
5909 int free_lag_id = -1;
5913 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
5914 for (i = 0; i < max_lag; i++) {
5915 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
5916 if (lag->ref_count) {
5917 if (lag->dev == lag_dev) {
5921 } else if (free_lag_id < 0) {
5925 if (free_lag_id < 0)
5927 *p_lag_id = free_lag_id;
5932 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
5933 struct net_device *lag_dev,
5934 struct netdev_lag_upper_info *lag_upper_info,
5935 struct netlink_ext_ack *extack)
5939 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
5940 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
5943 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
5944 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
5950 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
5951 u16 lag_id, u8 *p_port_index)
5953 u64 max_lag_members;
5956 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
5958 for (i = 0; i < max_lag_members; i++) {
5959 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
5967 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
5968 struct net_device *lag_dev)
5970 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5971 struct mlxsw_sp_upper *lag;
5976 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
5979 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
5980 if (!lag->ref_count) {
5981 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
5987 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
5990 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
5992 goto err_col_port_add;
5994 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
5995 mlxsw_sp_port->local_port);
5996 mlxsw_sp_port->lag_id = lag_id;
5997 mlxsw_sp_port->lagged = 1;
6000 /* Port is no longer usable as a router interface */
6001 if (mlxsw_sp_port->default_vlan->fid)
6002 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
6007 if (!lag->ref_count)
6008 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
6012 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
6013 struct net_device *lag_dev)
6015 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
6016 u16 lag_id = mlxsw_sp_port->lag_id;
6017 struct mlxsw_sp_upper *lag;
6019 if (!mlxsw_sp_port->lagged)
6021 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
6022 WARN_ON(lag->ref_count == 0);
6024 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
6026 /* Any VLANs configured on the port are no longer valid */
6027 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
6028 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
6029 /* Make the LAG and its directly linked uppers leave bridges they
6032 mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
6034 if (lag->ref_count == 1)
6035 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
6037 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
6038 mlxsw_sp_port->local_port);
6039 mlxsw_sp_port->lagged = 0;
6042 /* Make sure untagged frames are allowed to ingress */
6043 mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
6046 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
6049 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
6050 char sldr_pl[MLXSW_REG_SLDR_LEN];
6052 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
6053 mlxsw_sp_port->local_port);
6054 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
6057 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
6060 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
6061 char sldr_pl[MLXSW_REG_SLDR_LEN];
6063 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
6064 mlxsw_sp_port->local_port);
6065 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
6069 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
6073 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
6074 mlxsw_sp_port->lag_id);
6078 err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
6080 goto err_dist_port_add;
6085 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
6090 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
6094 err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
6095 mlxsw_sp_port->lag_id);
6099 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
6100 mlxsw_sp_port->lag_id);
6102 goto err_col_port_disable;
6106 err_col_port_disable:
6107 mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
6111 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
6112 struct netdev_lag_lower_state_info *info)
6114 if (info->tx_enabled)
6115 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
6117 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
6120 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
6123 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
6124 enum mlxsw_reg_spms_state spms_state;
6129 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
6130 MLXSW_REG_SPMS_STATE_DISCARDING;
6132 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
6135 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
6137 for (vid = 0; vid < VLAN_N_VID; vid++)
6138 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
6140 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
6145 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
6150 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
6153 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
6155 goto err_port_stp_set;
6156 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
6159 goto err_port_vlan_set;
6161 for (; vid <= VLAN_N_VID - 1; vid++) {
6162 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
6165 goto err_vid_learning_set;
6170 err_vid_learning_set:
6171 for (vid--; vid >= 1; vid--)
6172 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
6174 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
6176 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
6180 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
6184 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
6185 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
6188 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
6190 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
6191 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
6194 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
6196 unsigned int num_vxlans = 0;
6197 struct net_device *dev;
6198 struct list_head *iter;
6200 netdev_for_each_lower_dev(br_dev, dev, iter) {
6201 if (netif_is_vxlan(dev))
6205 return num_vxlans > 1;
6208 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
6210 DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
6211 struct net_device *dev;
6212 struct list_head *iter;
6214 netdev_for_each_lower_dev(br_dev, dev, iter) {
6218 if (!netif_is_vxlan(dev))
6221 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
6225 if (test_and_set_bit(pvid, vlans))
6232 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
6233 struct netlink_ext_ack *extack)
6235 if (br_multicast_enabled(br_dev)) {
6236 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
6240 if (!br_vlan_enabled(br_dev) &&
6241 mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
6242 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
6246 if (br_vlan_enabled(br_dev) &&
6247 !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
6248 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
6255 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
6256 struct net_device *dev,
6257 unsigned long event, void *ptr)
6259 struct netdev_notifier_changeupper_info *info;
6260 struct mlxsw_sp_port *mlxsw_sp_port;
6261 struct netlink_ext_ack *extack;
6262 struct net_device *upper_dev;
6263 struct mlxsw_sp *mlxsw_sp;
6266 mlxsw_sp_port = netdev_priv(dev);
6267 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
6269 extack = netdev_notifier_info_to_extack(&info->info);
6272 case NETDEV_PRECHANGEUPPER:
6273 upper_dev = info->upper_dev;
6274 if (!is_vlan_dev(upper_dev) &&
6275 !netif_is_lag_master(upper_dev) &&
6276 !netif_is_bridge_master(upper_dev) &&
6277 !netif_is_ovs_master(upper_dev) &&
6278 !netif_is_macvlan(upper_dev)) {
6279 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6284 if (netif_is_bridge_master(upper_dev) &&
6285 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
6286 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
6287 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6289 if (netdev_has_any_upper_dev(upper_dev) &&
6290 (!netif_is_bridge_master(upper_dev) ||
6291 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
6293 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
6296 if (netif_is_lag_master(upper_dev) &&
6297 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
6298 info->upper_info, extack))
6300 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
6301 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
6304 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
6305 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
6306 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
6309 if (netif_is_macvlan(upper_dev) &&
6310 !mlxsw_sp_rif_exists(mlxsw_sp, lower_dev)) {
6311 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6314 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
6315 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
6318 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
6319 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
6323 case NETDEV_CHANGEUPPER:
6324 upper_dev = info->upper_dev;
6325 if (netif_is_bridge_master(upper_dev)) {
6327 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
6332 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
6335 } else if (netif_is_lag_master(upper_dev)) {
6336 if (info->linking) {
6337 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
6340 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
6341 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
6344 } else if (netif_is_ovs_master(upper_dev)) {
6346 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
6348 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
6349 } else if (netif_is_macvlan(upper_dev)) {
6351 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6352 } else if (is_vlan_dev(upper_dev)) {
6353 struct net_device *br_dev;
6355 if (!netif_is_bridge_port(upper_dev))
6359 br_dev = netdev_master_upper_dev_get(upper_dev);
6360 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
6369 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
6370 unsigned long event, void *ptr)
6372 struct netdev_notifier_changelowerstate_info *info;
6373 struct mlxsw_sp_port *mlxsw_sp_port;
6376 mlxsw_sp_port = netdev_priv(dev);
6380 case NETDEV_CHANGELOWERSTATE:
6381 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
6382 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
6383 info->lower_state_info);
6385 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
6393 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
6394 struct net_device *port_dev,
6395 unsigned long event, void *ptr)
6398 case NETDEV_PRECHANGEUPPER:
6399 case NETDEV_CHANGEUPPER:
6400 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
6402 case NETDEV_CHANGELOWERSTATE:
6403 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
6410 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
6411 unsigned long event, void *ptr)
6413 struct net_device *dev;
6414 struct list_head *iter;
6417 netdev_for_each_lower_dev(lag_dev, dev, iter) {
6418 if (mlxsw_sp_port_dev_check(dev)) {
6419 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
6429 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
6430 struct net_device *dev,
6431 unsigned long event, void *ptr,
6434 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
6435 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
6436 struct netdev_notifier_changeupper_info *info = ptr;
6437 struct netlink_ext_ack *extack;
6438 struct net_device *upper_dev;
6441 extack = netdev_notifier_info_to_extack(&info->info);
6444 case NETDEV_PRECHANGEUPPER:
6445 upper_dev = info->upper_dev;
6446 if (!netif_is_bridge_master(upper_dev) &&
6447 !netif_is_macvlan(upper_dev)) {
6448 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6453 if (netif_is_bridge_master(upper_dev) &&
6454 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
6455 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
6456 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6458 if (netdev_has_any_upper_dev(upper_dev) &&
6459 (!netif_is_bridge_master(upper_dev) ||
6460 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
6462 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
6465 if (netif_is_macvlan(upper_dev) &&
6466 !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) {
6467 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6471 case NETDEV_CHANGEUPPER:
6472 upper_dev = info->upper_dev;
6473 if (netif_is_bridge_master(upper_dev)) {
6475 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
6480 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
6483 } else if (netif_is_macvlan(upper_dev)) {
6485 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6496 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
6497 struct net_device *lag_dev,
6498 unsigned long event,
6501 struct net_device *dev;
6502 struct list_head *iter;
6505 netdev_for_each_lower_dev(lag_dev, dev, iter) {
6506 if (mlxsw_sp_port_dev_check(dev)) {
6507 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
6518 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev,
6519 struct net_device *br_dev,
6520 unsigned long event, void *ptr,
6523 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
6524 struct netdev_notifier_changeupper_info *info = ptr;
6525 struct netlink_ext_ack *extack;
6526 struct net_device *upper_dev;
6531 extack = netdev_notifier_info_to_extack(&info->info);
6534 case NETDEV_PRECHANGEUPPER:
6535 upper_dev = info->upper_dev;
6536 if (!netif_is_macvlan(upper_dev)) {
6537 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6542 if (netif_is_macvlan(upper_dev) &&
6543 !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) {
6544 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6548 case NETDEV_CHANGEUPPER:
6549 upper_dev = info->upper_dev;
6552 if (netif_is_macvlan(upper_dev))
6553 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6560 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
6561 unsigned long event, void *ptr)
6563 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
6564 u16 vid = vlan_dev_vlan_id(vlan_dev);
6566 if (mlxsw_sp_port_dev_check(real_dev))
6567 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
6569 else if (netif_is_lag_master(real_dev))
6570 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
6573 else if (netif_is_bridge_master(real_dev))
6574 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev,
6580 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
6581 unsigned long event, void *ptr)
6583 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
6584 struct netdev_notifier_changeupper_info *info = ptr;
6585 struct netlink_ext_ack *extack;
6586 struct net_device *upper_dev;
6591 extack = netdev_notifier_info_to_extack(&info->info);
6594 case NETDEV_PRECHANGEUPPER:
6595 upper_dev = info->upper_dev;
6596 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
6597 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6602 if (netif_is_macvlan(upper_dev) &&
6603 !mlxsw_sp_rif_exists(mlxsw_sp, br_dev)) {
6604 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6608 case NETDEV_CHANGEUPPER:
6609 upper_dev = info->upper_dev;
6612 if (is_vlan_dev(upper_dev))
6613 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
6614 if (netif_is_macvlan(upper_dev))
6615 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6622 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
6623 unsigned long event, void *ptr)
6625 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
6626 struct netdev_notifier_changeupper_info *info = ptr;
6627 struct netlink_ext_ack *extack;
6629 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
6632 extack = netdev_notifier_info_to_extack(&info->info);
6634 /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
6635 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6640 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
6642 struct netdev_notifier_changeupper_info *info = ptr;
6644 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
6646 return netif_is_l3_master(info->upper_dev);
6649 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
6650 struct net_device *dev,
6651 unsigned long event, void *ptr)
6653 struct netdev_notifier_changeupper_info *cu_info;
6654 struct netdev_notifier_info *info = ptr;
6655 struct netlink_ext_ack *extack;
6656 struct net_device *upper_dev;
6658 extack = netdev_notifier_info_to_extack(info);
6661 case NETDEV_CHANGEUPPER:
6662 cu_info = container_of(info,
6663 struct netdev_notifier_changeupper_info,
6665 upper_dev = cu_info->upper_dev;
6666 if (!netif_is_bridge_master(upper_dev))
6668 if (!mlxsw_sp_lower_get(upper_dev))
6670 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6672 if (cu_info->linking) {
6673 if (!netif_running(dev))
6675 /* When the bridge is VLAN-aware, the VNI of the VxLAN
6676 * device needs to be mapped to a VLAN, but at this
6677 * point no VLANs are configured on the VxLAN device
6679 if (br_vlan_enabled(upper_dev))
6681 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
6684 /* VLANs were already flushed, which triggered the
6687 if (br_vlan_enabled(upper_dev))
6689 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
6693 upper_dev = netdev_master_upper_dev_get(dev);
6696 if (!netif_is_bridge_master(upper_dev))
6698 if (!mlxsw_sp_lower_get(upper_dev))
6700 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
6703 upper_dev = netdev_master_upper_dev_get(dev);
6706 if (!netif_is_bridge_master(upper_dev))
6708 if (!mlxsw_sp_lower_get(upper_dev))
6710 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
6717 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
6718 unsigned long event, void *ptr)
6720 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6721 struct mlxsw_sp_span_entry *span_entry;
6722 struct mlxsw_sp *mlxsw_sp;
6725 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
6726 if (event == NETDEV_UNREGISTER) {
6727 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
6729 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
6731 mlxsw_sp_span_respin(mlxsw_sp);
6733 if (netif_is_vxlan(dev))
6734 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
6735 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
6736 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
6738 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
6739 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
6741 else if (event == NETDEV_PRE_CHANGEADDR ||
6742 event == NETDEV_CHANGEADDR ||
6743 event == NETDEV_CHANGEMTU)
6744 err = mlxsw_sp_netdevice_router_port_event(dev, event, ptr);
6745 else if (mlxsw_sp_is_vrf_event(event, ptr))
6746 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
6747 else if (mlxsw_sp_port_dev_check(dev))
6748 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
6749 else if (netif_is_lag_master(dev))
6750 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
6751 else if (is_vlan_dev(dev))
6752 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
6753 else if (netif_is_bridge_master(dev))
6754 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
6755 else if (netif_is_macvlan(dev))
6756 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
6758 return notifier_from_errno(err);
6761 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
6762 .notifier_call = mlxsw_sp_inetaddr_valid_event,
6765 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
6766 .notifier_call = mlxsw_sp_inet6addr_valid_event,
6769 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
6770 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
6774 static struct pci_driver mlxsw_sp1_pci_driver = {
6775 .name = mlxsw_sp1_driver_name,
6776 .id_table = mlxsw_sp1_pci_id_table,
6779 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
6780 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
6784 static struct pci_driver mlxsw_sp2_pci_driver = {
6785 .name = mlxsw_sp2_driver_name,
6786 .id_table = mlxsw_sp2_pci_id_table,
6789 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = {
6790 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0},
6794 static struct pci_driver mlxsw_sp3_pci_driver = {
6795 .name = mlxsw_sp3_driver_name,
6796 .id_table = mlxsw_sp3_pci_id_table,
6799 static int __init mlxsw_sp_module_init(void)
6803 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6804 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6806 err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
6808 goto err_sp1_core_driver_register;
6810 err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
6812 goto err_sp2_core_driver_register;
6814 err = mlxsw_core_driver_register(&mlxsw_sp3_driver);
6816 goto err_sp3_core_driver_register;
6818 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
6820 goto err_sp1_pci_driver_register;
6822 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
6824 goto err_sp2_pci_driver_register;
6826 err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver);
6828 goto err_sp3_pci_driver_register;
6832 err_sp3_pci_driver_register:
6833 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
6834 err_sp2_pci_driver_register:
6835 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
6836 err_sp1_pci_driver_register:
6837 mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
6838 err_sp3_core_driver_register:
6839 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
6840 err_sp2_core_driver_register:
6841 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
6842 err_sp1_core_driver_register:
6843 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6844 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6848 static void __exit mlxsw_sp_module_exit(void)
6850 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
6851 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
6852 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
6853 mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
6854 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
6855 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
6856 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6857 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6860 module_init(mlxsw_sp_module_init);
6861 module_exit(mlxsw_sp_module_exit);
6863 MODULE_LICENSE("Dual BSD/GPL");
6864 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
6865 MODULE_DESCRIPTION("Mellanox Spectrum driver");
6866 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
6867 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
6868 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table);
6869 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);
6870 MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME);