1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
4 #ifndef _MLXSW_PCI_HW_H
5 #define _MLXSW_PCI_HW_H
7 #include <linux/bitops.h>
11 #define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */
12 #define MLXSW_PCI_PAGE_SIZE 4096
14 #define MLXSW_PCI_CIR_BASE 0x71000
15 #define MLXSW_PCI_CIR_IN_PARAM_HI MLXSW_PCI_CIR_BASE
16 #define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04)
17 #define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08)
18 #define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C)
19 #define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10)
20 #define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14)
21 #define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18)
22 #define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23)
23 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22)
24 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 12
25 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT 24
26 #define MLXSW_PCI_CIR_TIMEOUT_MSECS 1000
28 #define MLXSW_PCI_SW_RESET 0xF0010
29 #define MLXSW_PCI_SW_RESET_RST_BIT BIT(0)
30 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 13000
31 #define MLXSW_PCI_SW_RESET_WAIT_MSECS 100
32 #define MLXSW_PCI_FW_READY 0xA1844
33 #define MLXSW_PCI_FW_READY_MASK 0xFFFF
34 #define MLXSW_PCI_FW_READY_MAGIC 0x5E
36 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000
37 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200
38 #define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400
39 #define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600
40 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800
41 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00
43 #define MLXSW_PCI_DOORBELL(offset, type_offset, num) \
44 ((offset) + (type_offset) + (num) * 4)
46 #define MLXSW_PCI_CQS_MAX 96
47 #define MLXSW_PCI_EQS_COUNT 2
48 #define MLXSW_PCI_EQ_ASYNC_NUM 0
49 #define MLXSW_PCI_EQ_COMP_NUM 1
51 #define MLXSW_PCI_AQ_PAGES 8
52 #define MLXSW_PCI_AQ_SIZE (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
53 #define MLXSW_PCI_WQE_SIZE 32 /* 32 bytes per element */
54 #define MLXSW_PCI_CQE01_SIZE 16 /* 16 bytes per element */
55 #define MLXSW_PCI_CQE2_SIZE 32 /* 32 bytes per element */
56 #define MLXSW_PCI_CQE_SIZE_MAX MLXSW_PCI_CQE2_SIZE
57 #define MLXSW_PCI_EQE_SIZE 16 /* 16 bytes per element */
58 #define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
59 #define MLXSW_PCI_CQE01_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE)
60 #define MLXSW_PCI_CQE2_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE)
61 #define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
62 #define MLXSW_PCI_EQE_UPDATE_COUNT 0x80
64 #define MLXSW_PCI_WQE_SG_ENTRIES 3
65 #define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA
68 * If set it indicates that a completion should be reported upon
69 * execution of this descriptor.
71 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
74 * Local Processing, set if packet should be processed by the local
76 * For Ethernet EMAD (Direct Route and non Direct Route) -
77 * must be set if packet destination is local device
78 * For InfiniBand CTL - must be set if packet destination is local device
79 * Otherwise it must be clear
80 * Local Process packets must not exceed the size of 2K (including payload
83 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
88 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
91 * Size of i-th scatter/gather entry, 0 if entry is unused.
93 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
96 * Physical address of i-th scatter/gather entry.
97 * Gather Entries must be 2Byte aligned.
99 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
101 enum mlxsw_pci_cqe_v {
107 #define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2) \
108 static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \
112 case MLXSW_PCI_CQE_V0: \
113 return mlxsw_pci_cqe##v0##_##name##_get(cqe); \
114 case MLXSW_PCI_CQE_V1: \
115 return mlxsw_pci_cqe##v1##_##name##_get(cqe); \
116 case MLXSW_PCI_CQE_V2: \
117 return mlxsw_pci_cqe##v2##_##name##_get(cqe); \
120 static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v, \
121 char *cqe, u32 val) \
125 case MLXSW_PCI_CQE_V0: \
126 mlxsw_pci_cqe##v0##_##name##_set(cqe, val); \
128 case MLXSW_PCI_CQE_V1: \
129 mlxsw_pci_cqe##v1##_##name##_set(cqe, val); \
131 case MLXSW_PCI_CQE_V2: \
132 mlxsw_pci_cqe##v2##_##name##_set(cqe, val); \
138 * Packet arrives from a port which is a LAG
140 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
141 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
142 mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);
144 /* pci_cqe_system_port/lag_id
145 * When lag=0: System port on which the packet was received
147 * bits [15:4] LAG ID on which the packet was received
148 * bits [3:0] sub_port on which the packet was received
150 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
151 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
152 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
153 mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
154 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
155 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
156 mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);
158 /* pci_cqe_wqe_counter
159 * WQE count of the WQEs completed on the associated dqn
161 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
163 /* pci_cqe_byte_count
164 * Byte count of received packets including additional two
165 * Reserved Bytes that are append to the end of the frame.
166 * Reserved for Send CQE.
168 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
171 * Trap ID that captured the packet.
173 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);
176 * Length include CRC. Indicates the length field includes
179 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
180 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
181 mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);
186 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
187 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
188 mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);
194 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
195 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
196 mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);
199 * Descriptor Queue (DQ) Number.
201 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
202 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
203 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
208 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
209 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
210 mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2);
212 /* pci_eqe_event_type
215 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
216 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00
217 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A
219 /* pci_eqe_event_sub_type
222 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
225 * Completion Queue that triggered this EQE.
227 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
232 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
235 * Command completion event - token
237 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
239 /* pci_eqe_cmd_status
240 * Command completion event - status
242 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
244 /* pci_eqe_cmd_out_param_h
245 * Command completion event - output parameter - higher part
247 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
249 /* pci_eqe_cmd_out_param_l
250 * Command completion event - output parameter - lower part
252 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);