drivers/net/ethernet/mellanox/mlxsw/pci.c

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/pci.c
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/export.h>
  38 #include <linux/err.h>
  39 #include <linux/device.h>
  40 #include <linux/pci.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/wait.h>
  43 #include <linux/types.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/log2.h>
  47 #include <linux/string.h>
  48
  49 #include "pci_hw.h"
  50 #include "pci.h"
  51 #include "core.h"
  52 #include "cmd.h"
  53 #include "port.h"
  54 #include "resources.h"
  55
  56 static const char mlxsw_pci_driver_name[] = "mlxsw_pci";
  57
  58 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
  59         iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  60 #define mlxsw_pci_read32(mlxsw_pci, reg) \
  61         ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  62
  63 enum mlxsw_pci_queue_type {
  64         MLXSW_PCI_QUEUE_TYPE_SDQ,
  65         MLXSW_PCI_QUEUE_TYPE_RDQ,
  66         MLXSW_PCI_QUEUE_TYPE_CQ,
  67         MLXSW_PCI_QUEUE_TYPE_EQ,
  68 };
  69
  70 #define MLXSW_PCI_QUEUE_TYPE_COUNT      4
  71
  72 static const u16 mlxsw_pci_doorbell_type_offset[] = {
  73         MLXSW_PCI_DOORBELL_SDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
  74         MLXSW_PCI_DOORBELL_RDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
  75         MLXSW_PCI_DOORBELL_CQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
  76         MLXSW_PCI_DOORBELL_EQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
  77 };
  78
  79 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = {
  80         0, /* unused */
  81         0, /* unused */
  82         MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
  83         MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
  84 };
  85
  86 struct mlxsw_pci_mem_item {
  87         char *buf;
  88         dma_addr_t mapaddr;
  89         size_t size;
  90 };
  91
  92 struct mlxsw_pci_queue_elem_info {
  93         char *elem; /* pointer to actual dma mapped element mem chunk */
  94         union {
  95                 struct {
  96                         struct sk_buff *skb;
  97                 } sdq;
  98                 struct {
  99                         struct sk_buff *skb;
 100                 } rdq;
 101         } u;
 102 };
 103
 104 struct mlxsw_pci_queue {
 105         spinlock_t lock; /* for queue accesses */
 106         struct mlxsw_pci_mem_item mem_item;
 107         struct mlxsw_pci_queue_elem_info *elem_info;
 108         u16 producer_counter;
 109         u16 consumer_counter;
 110         u16 count; /* number of elements in queue */
 111         u8 num; /* queue number */
 112         u8 elem_size; /* size of one element */
 113         enum mlxsw_pci_queue_type type;
 114         struct tasklet_struct tasklet; /* queue processing tasklet */
 115         struct mlxsw_pci *pci;
 116         union {
 117                 struct {
 118                         u32 comp_sdq_count;
 119                         u32 comp_rdq_count;
 120                         enum mlxsw_pci_cqe_v v;
 121                 } cq;
 122                 struct {
 123                         u32 ev_cmd_count;
 124                         u32 ev_comp_count;
 125                         u32 ev_other_count;
 126                 } eq;
 127         } u;
 128 };
 129
 130 struct mlxsw_pci_queue_type_group {
 131         struct mlxsw_pci_queue *q;
 132         u8 count; /* number of queues in group */
 133 };
 134
 135 struct mlxsw_pci {
 136         struct pci_dev *pdev;
 137         u8 __iomem *hw_addr;
 138         struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
 139         u32 doorbell_offset;
 140         struct mlxsw_core *core;
 141         struct {
 142                 struct mlxsw_pci_mem_item *items;
 143                 unsigned int count;
 144         } fw_area;
 145         struct {
 146                 struct mlxsw_pci_mem_item out_mbox;
 147                 struct mlxsw_pci_mem_item in_mbox;
 148                 struct mutex lock; /* Lock access to command registers */
 149                 bool nopoll;
 150                 wait_queue_head_t wait;
 151                 bool wait_done;
 152                 struct {
 153                         u8 status;
 154                         u64 out_param;
 155                 } comp;
 156         } cmd;
 157         struct mlxsw_bus_info bus_info;
 158         const struct pci_device_id *id;
 159         enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */
 160         u8 num_sdq_cqs; /* Number of CQs used for SDQs */
 161 };
 162
 163 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
 164 {
 165         tasklet_schedule(&q->tasklet);
 166 }
 167
 168 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q,
 169                                         size_t elem_size, int elem_index)
 170 {
 171         return q->mem_item.buf + (elem_size * elem_index);
 172 }
 173
 174 static struct mlxsw_pci_queue_elem_info *
 175 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index)
 176 {
 177         return &q->elem_info[elem_index];
 178 }
 179
 180 static struct mlxsw_pci_queue_elem_info *
 181 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q)
 182 {
 183         int index = q->producer_counter & (q->count - 1);
 184
 185         if ((u16) (q->producer_counter - q->consumer_counter) == q->count)
 186                 return NULL;
 187         return mlxsw_pci_queue_elem_info_get(q, index);
 188 }
 189
 190 static struct mlxsw_pci_queue_elem_info *
 191 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q)
 192 {
 193         int index = q->consumer_counter & (q->count - 1);
 194
 195         return mlxsw_pci_queue_elem_info_get(q, index);
 196 }
 197
 198 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index)
 199 {
 200         return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem;
 201 }
 202
 203 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit)
 204 {
 205         return owner_bit != !!(q->consumer_counter & q->count);
 206 }
 207
 208 static struct mlxsw_pci_queue_type_group *
 209 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci,
 210                                enum mlxsw_pci_queue_type q_type)
 211 {
 212         return &mlxsw_pci->queues[q_type];
 213 }
 214
 215 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci,
 216                                   enum mlxsw_pci_queue_type q_type)
 217 {
 218         struct mlxsw_pci_queue_type_group *queue_group;
 219
 220         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type);
 221         return queue_group->count;
 222 }
 223
 224 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci)
 225 {
 226         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ);
 227 }
 228
 229 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci)
 230 {
 231         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ);
 232 }
 233
 234 static struct mlxsw_pci_queue *
 235 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci,
 236                       enum mlxsw_pci_queue_type q_type, u8 q_num)
 237 {
 238         return &mlxsw_pci->queues[q_type].q[q_num];
 239 }
 240
 241 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci,
 242                                                  u8 q_num)
 243 {
 244         return __mlxsw_pci_queue_get(mlxsw_pci,
 245                                      MLXSW_PCI_QUEUE_TYPE_SDQ, q_num);
 246 }
 247
 248 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci,
 249                                                  u8 q_num)
 250 {
 251         return __mlxsw_pci_queue_get(mlxsw_pci,
 252                                      MLXSW_PCI_QUEUE_TYPE_RDQ, q_num);
 253 }
 254
 255 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci,
 256                                                 u8 q_num)
 257 {
 258         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num);
 259 }
 260
 261 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci,
 262                                                 u8 q_num)
 263 {
 264         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num);
 265 }
 266
 267 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci,
 268                                            struct mlxsw_pci_queue *q,
 269                                            u16 val)
 270 {
 271         mlxsw_pci_write32(mlxsw_pci,
 272                           DOORBELL(mlxsw_pci->doorbell_offset,
 273                                    mlxsw_pci_doorbell_type_offset[q->type],
 274                                    q->num), val);
 275 }
 276
 277 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci,
 278                                                struct mlxsw_pci_queue *q,
 279                                                u16 val)
 280 {
 281         mlxsw_pci_write32(mlxsw_pci,
 282                           DOORBELL(mlxsw_pci->doorbell_offset,
 283                                    mlxsw_pci_doorbell_arm_type_offset[q->type],
 284                                    q->num), val);
 285 }
 286
 287 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci,
 288                                                    struct mlxsw_pci_queue *q)
 289 {
 290         wmb(); /* ensure all writes are done before we ring a bell */
 291         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter);
 292 }
 293
 294 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 295                                                    struct mlxsw_pci_queue *q)
 296 {
 297         wmb(); /* ensure all writes are done before we ring a bell */
 298         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q,
 299                                        q->consumer_counter + q->count);
 300 }
 301
 302 static void
 303 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 304                                            struct mlxsw_pci_queue *q)
 305 {
 306         wmb(); /* ensure all writes are done before we ring a bell */
 307         __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter);
 308 }
 309
 310 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q,
 311                                              int page_index)
 312 {
 313         return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index;
 314 }
 315
 316 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 317                               struct mlxsw_pci_queue *q)
 318 {
 319         int i;
 320         int err;
 321
 322         q->producer_counter = 0;
 323         q->consumer_counter = 0;
 324
 325         /* Set CQ of same number of this SDQ. */
 326         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);
 327         mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 3);
 328         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 329         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 330                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 331
 332                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 333         }
 334
 335         err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
 336         if (err)
 337                 return err;
 338         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 339         return 0;
 340 }
 341
 342 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci,
 343                                struct mlxsw_pci_queue *q)
 344 {
 345         mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num);
 346 }
 347
 348 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe,
 349                                   int index, char *frag_data, size_t frag_len,
 350                                   int direction)
 351 {
 352         struct pci_dev *pdev = mlxsw_pci->pdev;
 353         dma_addr_t mapaddr;
 354
 355         mapaddr = pci_map_single(pdev, frag_data, frag_len, direction);
 356         if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) {
 357                 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n");
 358                 return -EIO;
 359         }
 360         mlxsw_pci_wqe_address_set(wqe, index, mapaddr);
 361         mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len);
 362         return 0;
 363 }
 364
 365 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe,
 366                                      int index, int direction)
 367 {
 368         struct pci_dev *pdev = mlxsw_pci->pdev;
 369         size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index);
 370         dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index);
 371
 372         if (!frag_len)
 373                 return;
 374         pci_unmap_single(pdev, mapaddr, frag_len, direction);
 375 }
 376
 377 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci,
 378                                    struct mlxsw_pci_queue_elem_info *elem_info)
 379 {
 380         size_t buf_len = MLXSW_PORT_MAX_MTU;
 381         char *wqe = elem_info->elem;
 382         struct sk_buff *skb;
 383         int err;
 384
 385         elem_info->u.rdq.skb = NULL;
 386         skb = netdev_alloc_skb_ip_align(NULL, buf_len);
 387         if (!skb)
 388                 return -ENOMEM;
 389
 390         /* Assume that wqe was previously zeroed. */
 391
 392         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
 393                                      buf_len, DMA_FROM_DEVICE);
 394         if (err)
 395                 goto err_frag_map;
 396
 397         elem_info->u.rdq.skb = skb;
 398         return 0;
 399
 400 err_frag_map:
 401         dev_kfree_skb_any(skb);
 402         return err;
 403 }
 404
 405 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci,
 406                                    struct mlxsw_pci_queue_elem_info *elem_info)
 407 {
 408         struct sk_buff *skb;
 409         char *wqe;
 410
 411         skb = elem_info->u.rdq.skb;
 412         wqe = elem_info->elem;
 413
 414         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 415         dev_kfree_skb_any(skb);
 416 }
 417
 418 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 419                               struct mlxsw_pci_queue *q)
 420 {
 421         struct mlxsw_pci_queue_elem_info *elem_info;
 422         u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci);
 423         int i;
 424         int err;
 425
 426         q->producer_counter = 0;
 427         q->consumer_counter = 0;
 428
 429         /* Set CQ of same number of this RDQ with base
 430          * above SDQ count as the lower ones are assigned to SDQs.
 431          */
 432         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);
 433         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 434         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 435                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 436
 437                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 438         }
 439
 440         err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
 441         if (err)
 442                 return err;
 443
 444         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 445
 446         for (i = 0; i < q->count; i++) {
 447                 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
 448                 BUG_ON(!elem_info);
 449                 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 450                 if (err)
 451                         goto rollback;
 452                 /* Everything is set up, ring doorbell to pass elem to HW */
 453                 q->producer_counter++;
 454                 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 455         }
 456
 457         return 0;
 458
 459 rollback:
 460         for (i--; i >= 0; i--) {
 461                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 462                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 463         }
 464         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 465
 466         return err;
 467 }
 468
 469 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
 470                                struct mlxsw_pci_queue *q)
 471 {
 472         struct mlxsw_pci_queue_elem_info *elem_info;
 473         int i;
 474
 475         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 476         for (i = 0; i < q->count; i++) {
 477                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 478                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 479         }
 480 }
 481
 482 static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci,
 483                                   struct mlxsw_pci_queue *q)
 484 {
 485         q->u.cq.v = mlxsw_pci->max_cqe_ver;
 486
 487         /* For SDQ it is pointless to use CQEv2, so use CQEv1 instead */
 488         if (q->u.cq.v == MLXSW_PCI_CQE_V2 &&
 489             q->num < mlxsw_pci->num_sdq_cqs)
 490                 q->u.cq.v = MLXSW_PCI_CQE_V1;
 491 }
 492
 493 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 494                              struct mlxsw_pci_queue *q)
 495 {
 496         int i;
 497         int err;
 498
 499         q->consumer_counter = 0;
 500
 501         for (i = 0; i < q->count; i++) {
 502                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 503
 504                 mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1);
 505         }
 506
 507         if (q->u.cq.v == MLXSW_PCI_CQE_V1)
 508                 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
 509                                 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1);
 510         else if (q->u.cq.v == MLXSW_PCI_CQE_V2)
 511                 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
 512                                 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2);
 513
 514         mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
 515         mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
 516         mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
 517         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 518                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 519
 520                 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
 521         }
 522         err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
 523         if (err)
 524                 return err;
 525         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 526         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 527         return 0;
 528 }
 529
 530 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
 531                               struct mlxsw_pci_queue *q)
 532 {
 533         mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
 534 }
 535
 536 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
 537                                      struct mlxsw_pci_queue *q,
 538                                      u16 consumer_counter_limit,
 539                                      char *cqe)
 540 {
 541         struct pci_dev *pdev = mlxsw_pci->pdev;
 542         struct mlxsw_pci_queue_elem_info *elem_info;
 543         char *wqe;
 544         struct sk_buff *skb;
 545         int i;
 546
 547         spin_lock(&q->lock);
 548         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 549         skb = elem_info->u.sdq.skb;
 550         wqe = elem_info->elem;
 551         for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
 552                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
 553         dev_kfree_skb_any(skb);
 554         elem_info->u.sdq.skb = NULL;
 555
 556         if (q->consumer_counter++ != consumer_counter_limit)
 557                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n");
 558         spin_unlock(&q->lock);
 559 }
 560
 561 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci,
 562                                      struct mlxsw_pci_queue *q,
 563                                      u16 consumer_counter_limit,
 564                                      enum mlxsw_pci_cqe_v cqe_v, char *cqe)
 565 {
 566         struct pci_dev *pdev = mlxsw_pci->pdev;
 567         struct mlxsw_pci_queue_elem_info *elem_info;
 568         char *wqe;
 569         struct sk_buff *skb;
 570         struct mlxsw_rx_info rx_info;
 571         u16 byte_count;
 572         int err;
 573
 574         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 575         skb = elem_info->u.sdq.skb;
 576         if (!skb)
 577                 return;
 578         wqe = elem_info->elem;
 579         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 580
 581         if (q->consumer_counter++ != consumer_counter_limit)
 582                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n");
 583
 584         if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) {
 585                 rx_info.is_lag = true;
 586                 rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe);
 587                 rx_info.lag_port_index =
 588                         mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe);
 589         } else {
 590                 rx_info.is_lag = false;
 591                 rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe);
 592         }
 593
 594         rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe);
 595
 596         byte_count = mlxsw_pci_cqe_byte_count_get(cqe);
 597         if (mlxsw_pci_cqe_crc_get(cqe_v, cqe))
 598                 byte_count -= ETH_FCS_LEN;
 599         skb_put(skb, byte_count);
 600         mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info);
 601
 602         memset(wqe, 0, q->elem_size);
 603         err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 604         if (err)
 605                 dev_dbg_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n");
 606         /* Everything is set up, ring doorbell to pass elem to HW */
 607         q->producer_counter++;
 608         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 609         return;
 610 }
 611
 612 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q)
 613 {
 614         struct mlxsw_pci_queue_elem_info *elem_info;
 615         char *elem;
 616         bool owner_bit;
 617
 618         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 619         elem = elem_info->elem;
 620         owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem);
 621         if (mlxsw_pci_elem_hw_owned(q, owner_bit))
 622                 return NULL;
 623         q->consumer_counter++;
 624         rmb(); /* make sure we read owned bit before the rest of elem */
 625         return elem;
 626 }
 627
 628 static void mlxsw_pci_cq_tasklet(unsigned long data)
 629 {
 630         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 631         struct mlxsw_pci *mlxsw_pci = q->pci;
 632         char *cqe;
 633         int items = 0;
 634         int credits = q->count >> 1;
 635
 636         while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) {
 637                 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe);
 638                 u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe);
 639                 u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe);
 640
 641                 if (sendq) {
 642                         struct mlxsw_pci_queue *sdq;
 643
 644                         sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn);
 645                         mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq,
 646                                                  wqe_counter, cqe);
 647                         q->u.cq.comp_sdq_count++;
 648                 } else {
 649                         struct mlxsw_pci_queue *rdq;
 650
 651                         rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn);
 652                         mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq,
 653                                                  wqe_counter, q->u.cq.v, cqe);
 654                         q->u.cq.comp_rdq_count++;
 655                 }
 656                 if (++items == credits)
 657                         break;
 658         }
 659         if (items) {
 660                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 661                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 662         }
 663 }
 664
 665 static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q)
 666 {
 667         return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT :
 668                                                MLXSW_PCI_CQE01_COUNT;
 669 }
 670
 671 static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q)
 672 {
 673         return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE :
 674                                                MLXSW_PCI_CQE01_SIZE;
 675 }
 676
 677 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 678                              struct mlxsw_pci_queue *q)
 679 {
 680         int i;
 681         int err;
 682
 683         q->consumer_counter = 0;
 684
 685         for (i = 0; i < q->count; i++) {
 686                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 687
 688                 mlxsw_pci_eqe_owner_set(elem, 1);
 689         }
 690
 691         mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */
 692         mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */
 693         mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
 694         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 695                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 696
 697                 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
 698         }
 699         err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
 700         if (err)
 701                 return err;
 702         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 703         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 704         return 0;
 705 }
 706
 707 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci,
 708                               struct mlxsw_pci_queue *q)
 709 {
 710         mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num);
 711 }
 712
 713 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe)
 714 {
 715         mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe);
 716         mlxsw_pci->cmd.comp.out_param =
 717                 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 |
 718                 mlxsw_pci_eqe_cmd_out_param_l_get(eqe);
 719         mlxsw_pci->cmd.wait_done = true;
 720         wake_up(&mlxsw_pci->cmd.wait);
 721 }
 722
 723 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q)
 724 {
 725         struct mlxsw_pci_queue_elem_info *elem_info;
 726         char *elem;
 727         bool owner_bit;
 728
 729         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 730         elem = elem_info->elem;
 731         owner_bit = mlxsw_pci_eqe_owner_get(elem);
 732         if (mlxsw_pci_elem_hw_owned(q, owner_bit))
 733                 return NULL;
 734         q->consumer_counter++;
 735         rmb(); /* make sure we read owned bit before the rest of elem */
 736         return elem;
 737 }
 738
 739 static void mlxsw_pci_eq_tasklet(unsigned long data)
 740 {
 741         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 742         struct mlxsw_pci *mlxsw_pci = q->pci;
 743         u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci);
 744         unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)];
 745         char *eqe;
 746         u8 cqn;
 747         bool cq_handle = false;
 748         int items = 0;
 749         int credits = q->count >> 1;
 750
 751         memset(&active_cqns, 0, sizeof(active_cqns));
 752
 753         while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) {
 754                 u8 event_type = mlxsw_pci_eqe_event_type_get(eqe);
 755
 756                 switch (event_type) {
 757                 case MLXSW_PCI_EQE_EVENT_TYPE_CMD:
 758                         mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe);
 759                         q->u.eq.ev_cmd_count++;
 760                         break;
 761                 case MLXSW_PCI_EQE_EVENT_TYPE_COMP:
 762                         cqn = mlxsw_pci_eqe_cqn_get(eqe);
 763                         set_bit(cqn, active_cqns);
 764                         cq_handle = true;
 765                         q->u.eq.ev_comp_count++;
 766                         break;
 767                 default:
 768                         q->u.eq.ev_other_count++;
 769                 }
 770                 if (++items == credits)
 771                         break;
 772         }
 773         if (items) {
 774                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 775                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 776         }
 777
 778         if (!cq_handle)
 779                 return;
 780         for_each_set_bit(cqn, active_cqns, cq_count) {
 781                 q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
 782                 mlxsw_pci_queue_tasklet_schedule(q);
 783         }
 784 }
 785
 786 struct mlxsw_pci_queue_ops {
 787         const char *name;
 788         enum mlxsw_pci_queue_type type;
 789         void (*pre_init)(struct mlxsw_pci *mlxsw_pci,
 790                          struct mlxsw_pci_queue *q);
 791         int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
 792                     struct mlxsw_pci_queue *q);
 793         void (*fini)(struct mlxsw_pci *mlxsw_pci,
 794                      struct mlxsw_pci_queue *q);
 795         void (*tasklet)(unsigned long data);
 796         u16 (*elem_count_f)(const struct mlxsw_pci_queue *q);
 797         u8 (*elem_size_f)(const struct mlxsw_pci_queue *q);
 798         u16 elem_count;
 799         u8 elem_size;
 800 };
 801
 802 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = {
 803         .type           = MLXSW_PCI_QUEUE_TYPE_SDQ,
 804         .init           = mlxsw_pci_sdq_init,
 805         .fini           = mlxsw_pci_sdq_fini,
 806         .elem_count     = MLXSW_PCI_WQE_COUNT,
 807         .elem_size      = MLXSW_PCI_WQE_SIZE,
 808 };
 809
 810 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
 811         .type           = MLXSW_PCI_QUEUE_TYPE_RDQ,
 812         .init           = mlxsw_pci_rdq_init,
 813         .fini           = mlxsw_pci_rdq_fini,
 814         .elem_count     = MLXSW_PCI_WQE_COUNT,
 815         .elem_size      = MLXSW_PCI_WQE_SIZE
 816 };
 817
 818 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
 819         .type           = MLXSW_PCI_QUEUE_TYPE_CQ,
 820         .pre_init       = mlxsw_pci_cq_pre_init,
 821         .init           = mlxsw_pci_cq_init,
 822         .fini           = mlxsw_pci_cq_fini,
 823         .tasklet        = mlxsw_pci_cq_tasklet,
 824         .elem_count_f   = mlxsw_pci_cq_elem_count,
 825         .elem_size_f    = mlxsw_pci_cq_elem_size
 826 };
 827
 828 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
 829         .type           = MLXSW_PCI_QUEUE_TYPE_EQ,
 830         .init           = mlxsw_pci_eq_init,
 831         .fini           = mlxsw_pci_eq_fini,
 832         .tasklet        = mlxsw_pci_eq_tasklet,
 833         .elem_count     = MLXSW_PCI_EQE_COUNT,
 834         .elem_size      = MLXSW_PCI_EQE_SIZE
 835 };
 836
 837 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 838                                 const struct mlxsw_pci_queue_ops *q_ops,
 839                                 struct mlxsw_pci_queue *q, u8 q_num)
 840 {
 841         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 842         int i;
 843         int err;
 844
 845         q->num = q_num;
 846         if (q_ops->pre_init)
 847                 q_ops->pre_init(mlxsw_pci, q);
 848
 849         spin_lock_init(&q->lock);
 850         q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) :
 851                                          q_ops->elem_count;
 852         q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) :
 853                                             q_ops->elem_size;
 854         q->type = q_ops->type;
 855         q->pci = mlxsw_pci;
 856
 857         if (q_ops->tasklet)
 858                 tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q);
 859
 860         mem_item->size = MLXSW_PCI_AQ_SIZE;
 861         mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
 862                                              mem_item->size,
 863                                              &mem_item->mapaddr);
 864         if (!mem_item->buf)
 865                 return -ENOMEM;
 866         memset(mem_item->buf, 0, mem_item->size);
 867
 868         q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL);
 869         if (!q->elem_info) {
 870                 err = -ENOMEM;
 871                 goto err_elem_info_alloc;
 872         }
 873
 874         /* Initialize dma mapped elements info elem_info for
 875          * future easy access.
 876          */
 877         for (i = 0; i < q->count; i++) {
 878                 struct mlxsw_pci_queue_elem_info *elem_info;
 879
 880                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 881                 elem_info->elem =
 882                         __mlxsw_pci_queue_elem_get(q, q->elem_size, i);
 883         }
 884
 885         mlxsw_cmd_mbox_zero(mbox);
 886         err = q_ops->init(mlxsw_pci, mbox, q);
 887         if (err)
 888                 goto err_q_ops_init;
 889         return 0;
 890
 891 err_q_ops_init:
 892         kfree(q->elem_info);
 893 err_elem_info_alloc:
 894         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 895                             mem_item->buf, mem_item->mapaddr);
 896         return err;
 897 }
 898
 899 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci,
 900                                  const struct mlxsw_pci_queue_ops *q_ops,
 901                                  struct mlxsw_pci_queue *q)
 902 {
 903         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 904
 905         q_ops->fini(mlxsw_pci, q);
 906         kfree(q->elem_info);
 907         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 908                             mem_item->buf, mem_item->mapaddr);
 909 }
 910
 911 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 912                                       const struct mlxsw_pci_queue_ops *q_ops,
 913                                       u8 num_qs)
 914 {
 915         struct mlxsw_pci_queue_type_group *queue_group;
 916         int i;
 917         int err;
 918
 919         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
 920         queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL);
 921         if (!queue_group->q)
 922                 return -ENOMEM;
 923
 924         for (i = 0; i < num_qs; i++) {
 925                 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
 926                                            &queue_group->q[i], i);
 927                 if (err)
 928                         goto err_queue_init;
 929         }
 930         queue_group->count = num_qs;
 931
 932         return 0;
 933
 934 err_queue_init:
 935         for (i--; i >= 0; i--)
 936                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
 937         kfree(queue_group->q);
 938         return err;
 939 }
 940
 941 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci,
 942                                        const struct mlxsw_pci_queue_ops *q_ops)
 943 {
 944         struct mlxsw_pci_queue_type_group *queue_group;
 945         int i;
 946
 947         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
 948         for (i = 0; i < queue_group->count; i++)
 949                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
 950         kfree(queue_group->q);
 951 }
 952
 953 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
 954 {
 955         struct pci_dev *pdev = mlxsw_pci->pdev;
 956         u8 num_sdqs;
 957         u8 sdq_log2sz;
 958         u8 num_rdqs;
 959         u8 rdq_log2sz;
 960         u8 num_cqs;
 961         u8 cq_log2sz;
 962         u8 cqv2_log2sz;
 963         u8 num_eqs;
 964         u8 eq_log2sz;
 965         int err;
 966
 967         mlxsw_cmd_mbox_zero(mbox);
 968         err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
 969         if (err)
 970                 return err;
 971
 972         num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
 973         sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
 974         num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
 975         rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
 976         num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
 977         cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
 978         cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox);
 979         num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
 980         eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
 981
 982         if (num_sdqs + num_rdqs > num_cqs ||
 983             num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) {
 984                 dev_err(&pdev->dev, "Unsupported number of queues\n");
 985                 return -EINVAL;
 986         }
 987
 988         if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
 989             (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
 990             (1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) ||
 991             (mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 &&
 992              (1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) ||
 993             (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
 994                 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
 995                 return -EINVAL;
 996         }
 997
 998         mlxsw_pci->num_sdq_cqs = num_sdqs;
 999
1000         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
1001                                          num_eqs);
1002         if (err) {
1003                 dev_err(&pdev->dev, "Failed to initialize event queues\n");
1004                 return err;
1005         }
1006
1007         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
1008                                          num_cqs);
1009         if (err) {
1010                 dev_err(&pdev->dev, "Failed to initialize completion queues\n");
1011                 goto err_cqs_init;
1012         }
1013
1014         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
1015                                          num_sdqs);
1016         if (err) {
1017                 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n");
1018                 goto err_sdqs_init;
1019         }
1020
1021         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
1022                                          num_rdqs);
1023         if (err) {
1024                 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n");
1025                 goto err_rdqs_init;
1026         }
1027
1028         /* We have to poll in command interface until queues are initialized */
1029         mlxsw_pci->cmd.nopoll = true;
1030         return 0;
1031
1032 err_rdqs_init:
1033         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1034 err_sdqs_init:
1035         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1036 err_cqs_init:
1037         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1038         return err;
1039 }
1040
1041 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci)
1042 {
1043         mlxsw_pci->cmd.nopoll = false;
1044         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
1045         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1046         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1047         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1048 }
1049
1050 static void
1051 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
1052                                      char *mbox, int index,
1053                                      const struct mlxsw_swid_config *swid)
1054 {
1055         u8 mask = 0;
1056
1057         if (swid->used_type) {
1058                 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1059                         mbox, index, swid->type);
1060                 mask |= 1;
1061         }
1062         if (swid->used_properties) {
1063                 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1064                         mbox, index, swid->properties);
1065                 mask |= 2;
1066         }
1067         mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1068 }
1069
1070 static int mlxsw_pci_resources_query(struct mlxsw_pci *mlxsw_pci, char *mbox,
1071                                      struct mlxsw_res *res)
1072 {
1073         int index, i;
1074         u64 data;
1075         u16 id;
1076         int err;
1077
1078         if (!res)
1079                 return 0;
1080
1081         mlxsw_cmd_mbox_zero(mbox);
1082
1083         for (index = 0; index < MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES;
1084              index++) {
1085                 err = mlxsw_cmd_query_resources(mlxsw_pci->core, mbox, index);
1086                 if (err)
1087                         return err;
1088
1089                 for (i = 0; i < MLXSW_CMD_QUERY_RESOURCES_PER_QUERY; i++) {
1090                         id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i);
1091                         data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i);
1092
1093                         if (id == MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID)
1094                                 return 0;
1095
1096                         mlxsw_res_parse(res, id, data);
1097                 }
1098         }
1099
1100         /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get
1101          * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW.
1102          */
1103         return -EIO;
1104 }
1105
1106 static int
1107 mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci,
1108                                 const struct mlxsw_config_profile *profile,
1109                                 struct mlxsw_res *res)
1110 {
1111         u64 single_size, double_size, linear_size;
1112         int err;
1113
1114         err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile,
1115                                        &single_size, &double_size,
1116                                        &linear_size);
1117         if (err)
1118                 return err;
1119
1120         MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size);
1121         MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size);
1122         MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size);
1123
1124         return 0;
1125 }
1126
1127 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1128                                     const struct mlxsw_config_profile *profile,
1129                                     struct mlxsw_res *res)
1130 {
1131         int i;
1132         int err;
1133
1134         mlxsw_cmd_mbox_zero(mbox);
1135
1136         if (profile->used_max_vepa_channels) {
1137                 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1138                         mbox, 1);
1139                 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1140                         mbox, profile->max_vepa_channels);
1141         }
1142         if (profile->used_max_mid) {
1143                 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1144                         mbox, 1);
1145                 mlxsw_cmd_mbox_config_profile_max_mid_set(
1146                         mbox, profile->max_mid);
1147         }
1148         if (profile->used_max_pgt) {
1149                 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1150                         mbox, 1);
1151                 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1152                         mbox, profile->max_pgt);
1153         }
1154         if (profile->used_max_system_port) {
1155                 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1156                         mbox, 1);
1157                 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1158                         mbox, profile->max_system_port);
1159         }
1160         if (profile->used_max_vlan_groups) {
1161                 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1162                         mbox, 1);
1163                 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1164                         mbox, profile->max_vlan_groups);
1165         }
1166         if (profile->used_max_regions) {
1167                 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1168                         mbox, 1);
1169                 mlxsw_cmd_mbox_config_profile_max_regions_set(
1170                         mbox, profile->max_regions);
1171         }
1172         if (profile->used_flood_tables) {
1173                 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1174                         mbox, 1);
1175                 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1176                         mbox, profile->max_flood_tables);
1177                 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1178                         mbox, profile->max_vid_flood_tables);
1179                 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1180                         mbox, profile->max_fid_offset_flood_tables);
1181                 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1182                         mbox, profile->fid_offset_flood_table_size);
1183                 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1184                         mbox, profile->max_fid_flood_tables);
1185                 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1186                         mbox, profile->fid_flood_table_size);
1187         }
1188         if (profile->used_flood_mode) {
1189                 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1190                         mbox, 1);
1191                 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1192                         mbox, profile->flood_mode);
1193         }
1194         if (profile->used_max_ib_mc) {
1195                 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1196                         mbox, 1);
1197                 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1198                         mbox, profile->max_ib_mc);
1199         }
1200         if (profile->used_max_pkey) {
1201                 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1202                         mbox, 1);
1203                 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1204                         mbox, profile->max_pkey);
1205         }
1206         if (profile->used_ar_sec) {
1207                 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1208                         mbox, 1);
1209                 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1210                         mbox, profile->ar_sec);
1211         }
1212         if (profile->used_adaptive_routing_group_cap) {
1213                 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1214                         mbox, 1);
1215                 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1216                         mbox, profile->adaptive_routing_group_cap);
1217         }
1218         if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) {
1219                 err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res);
1220                 if (err)
1221                         return err;
1222
1223                 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1);
1224                 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox,
1225                                         MLXSW_RES_GET(res, KVD_LINEAR_SIZE));
1226                 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox,
1227                                                                            1);
1228                 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox,
1229                                         MLXSW_RES_GET(res, KVD_SINGLE_SIZE));
1230                 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set(
1231                                                                 mbox, 1);
1232                 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox,
1233                                         MLXSW_RES_GET(res, KVD_DOUBLE_SIZE));
1234         }
1235
1236         for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)
1237                 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1238                                                      &profile->swid_config[i]);
1239
1240         if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) {
1241                 mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1);
1242                 mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1);
1243         }
1244
1245         return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1246 }
1247
1248 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1249 {
1250         struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info;
1251         int err;
1252
1253         mlxsw_cmd_mbox_zero(mbox);
1254         err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1255         if (err)
1256                 return err;
1257         mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1258         mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1259         return 0;
1260 }
1261
1262 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1263                                   u16 num_pages)
1264 {
1265         struct mlxsw_pci_mem_item *mem_item;
1266         int nent = 0;
1267         int i;
1268         int err;
1269
1270         mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item),
1271                                            GFP_KERNEL);
1272         if (!mlxsw_pci->fw_area.items)
1273                 return -ENOMEM;
1274         mlxsw_pci->fw_area.count = num_pages;
1275
1276         mlxsw_cmd_mbox_zero(mbox);
1277         for (i = 0; i < num_pages; i++) {
1278                 mem_item = &mlxsw_pci->fw_area.items[i];
1279
1280                 mem_item->size = MLXSW_PCI_PAGE_SIZE;
1281                 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
1282                                                      mem_item->size,
1283                                                      &mem_item->mapaddr);
1284                 if (!mem_item->buf) {
1285                         err = -ENOMEM;
1286                         goto err_alloc;
1287                 }
1288                 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);
1289                 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */
1290                 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) {
1291                         err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1292                         if (err)
1293                                 goto err_cmd_map_fa;
1294                         nent = 0;
1295                         mlxsw_cmd_mbox_zero(mbox);
1296                 }
1297         }
1298
1299         if (nent) {
1300                 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1301                 if (err)
1302                         goto err_cmd_map_fa;
1303         }
1304
1305         return 0;
1306
1307 err_cmd_map_fa:
1308 err_alloc:
1309         for (i--; i >= 0; i--) {
1310                 mem_item = &mlxsw_pci->fw_area.items[i];
1311
1312                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1313                                     mem_item->buf, mem_item->mapaddr);
1314         }
1315         kfree(mlxsw_pci->fw_area.items);
1316         return err;
1317 }
1318
1319 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci)
1320 {
1321         struct mlxsw_pci_mem_item *mem_item;
1322         int i;
1323
1324         mlxsw_cmd_unmap_fa(mlxsw_pci->core);
1325
1326         for (i = 0; i < mlxsw_pci->fw_area.count; i++) {
1327                 mem_item = &mlxsw_pci->fw_area.items[i];
1328
1329                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1330                                     mem_item->buf, mem_item->mapaddr);
1331         }
1332         kfree(mlxsw_pci->fw_area.items);
1333 }
1334
1335 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id)
1336 {
1337         struct mlxsw_pci *mlxsw_pci = dev_id;
1338         struct mlxsw_pci_queue *q;
1339         int i;
1340
1341         for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) {
1342                 q = mlxsw_pci_eq_get(mlxsw_pci, i);
1343                 mlxsw_pci_queue_tasklet_schedule(q);
1344         }
1345         return IRQ_HANDLED;
1346 }
1347
1348 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci,
1349                                 struct mlxsw_pci_mem_item *mbox)
1350 {
1351         struct pci_dev *pdev = mlxsw_pci->pdev;
1352         int err = 0;
1353
1354         mbox->size = MLXSW_CMD_MBOX_SIZE;
1355         mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE,
1356                                          &mbox->mapaddr);
1357         if (!mbox->buf) {
1358                 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n");
1359                 err = -ENOMEM;
1360         }
1361
1362         return err;
1363 }
1364
1365 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci,
1366                                 struct mlxsw_pci_mem_item *mbox)
1367 {
1368         struct pci_dev *pdev = mlxsw_pci->pdev;
1369
1370         pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf,
1371                             mbox->mapaddr);
1372 }
1373
1374 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci,
1375                               const struct pci_device_id *id)
1376 {
1377         unsigned long end;
1378         char mrsr_pl[MLXSW_REG_MRSR_LEN];
1379         int err;
1380
1381         mlxsw_reg_mrsr_pack(mrsr_pl);
1382         err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl);
1383         if (err)
1384                 return err;
1385         if (id->device == PCI_DEVICE_ID_MELLANOX_SWITCHX2) {
1386                 msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1387                 return 0;
1388         }
1389
1390         /* We must wait for the HW to become responsive once again. */
1391         msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS);
1392
1393         end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1394         do {
1395                 u32 val = mlxsw_pci_read32(mlxsw_pci, FW_READY);
1396
1397                 if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC)
1398                         break;
1399                 cond_resched();
1400         } while (time_before(jiffies, end));
1401         return 0;
1402 }
1403
1404 static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1405 {
1406         int err;
1407
1408         err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX);
1409         if (err < 0)
1410                 dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n");
1411         return err;
1412 }
1413
1414 static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1415 {
1416         pci_free_irq_vectors(mlxsw_pci->pdev);
1417 }
1418
1419 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
1420                           const struct mlxsw_config_profile *profile,
1421                           struct mlxsw_res *res)
1422 {
1423         struct mlxsw_pci *mlxsw_pci = bus_priv;
1424         struct pci_dev *pdev = mlxsw_pci->pdev;
1425         char *mbox;
1426         u16 num_pages;
1427         int err;
1428
1429         mutex_init(&mlxsw_pci->cmd.lock);
1430         init_waitqueue_head(&mlxsw_pci->cmd.wait);
1431
1432         mlxsw_pci->core = mlxsw_core;
1433
1434         mbox = mlxsw_cmd_mbox_alloc();
1435         if (!mbox)
1436                 return -ENOMEM;
1437
1438         err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1439         if (err)
1440                 goto mbox_put;
1441
1442         err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1443         if (err)
1444                 goto err_out_mbox_alloc;
1445
1446         err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id);
1447         if (err)
1448                 goto err_sw_reset;
1449
1450         err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci);
1451         if (err < 0) {
1452                 dev_err(&pdev->dev, "MSI-X init failed\n");
1453                 goto err_alloc_irq;
1454         }
1455
1456         err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1457         if (err)
1458                 goto err_query_fw;
1459
1460         mlxsw_pci->bus_info.fw_rev.major =
1461                 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1462         mlxsw_pci->bus_info.fw_rev.minor =
1463                 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1464         mlxsw_pci->bus_info.fw_rev.subminor =
1465                 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1466
1467         if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1468                 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n");
1469                 err = -EINVAL;
1470                 goto err_iface_rev;
1471         }
1472         if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1473                 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n");
1474                 err = -EINVAL;
1475                 goto err_doorbell_page_bar;
1476         }
1477
1478         mlxsw_pci->doorbell_offset =
1479                 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1480
1481         num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1482         err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1483         if (err)
1484                 goto err_fw_area_init;
1485
1486         err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1487         if (err)
1488                 goto err_boardinfo;
1489
1490         err = mlxsw_pci_resources_query(mlxsw_pci, mbox, res);
1491         if (err)
1492                 goto err_query_resources;
1493
1494         if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) &&
1495             MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2))
1496                 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2;
1497         else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) &&
1498                  MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1))
1499                 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1;
1500         else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) &&
1501                   MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) ||
1502                  !MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) {
1503                 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0;
1504         } else {
1505                 dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n");
1506                 goto err_cqe_v_check;
1507         }
1508
1509         err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res);
1510         if (err)
1511                 goto err_config_profile;
1512
1513         err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1514         if (err)
1515                 goto err_aqs_init;
1516
1517         err = request_irq(pci_irq_vector(pdev, 0),
1518                           mlxsw_pci_eq_irq_handler, 0,
1519                           mlxsw_pci->bus_info.device_kind, mlxsw_pci);
1520         if (err) {
1521                 dev_err(&pdev->dev, "IRQ request failed\n");
1522                 goto err_request_eq_irq;
1523         }
1524
1525         goto mbox_put;
1526
1527 err_request_eq_irq:
1528         mlxsw_pci_aqs_fini(mlxsw_pci);
1529 err_aqs_init:
1530 err_config_profile:
1531 err_cqe_v_check:
1532 err_query_resources:
1533 err_boardinfo:
1534         mlxsw_pci_fw_area_fini(mlxsw_pci);
1535 err_fw_area_init:
1536 err_doorbell_page_bar:
1537 err_iface_rev:
1538 err_query_fw:
1539         mlxsw_pci_free_irq_vectors(mlxsw_pci);
1540 err_alloc_irq:
1541 err_sw_reset:
1542         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1543 err_out_mbox_alloc:
1544         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1545 mbox_put:
1546         mlxsw_cmd_mbox_free(mbox);
1547         return err;
1548 }
1549
1550 static void mlxsw_pci_fini(void *bus_priv)
1551 {
1552         struct mlxsw_pci *mlxsw_pci = bus_priv;
1553
1554         free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci);
1555         mlxsw_pci_aqs_fini(mlxsw_pci);
1556         mlxsw_pci_fw_area_fini(mlxsw_pci);
1557         mlxsw_pci_free_irq_vectors(mlxsw_pci);
1558         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1559         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1560 }
1561
1562 static struct mlxsw_pci_queue *
1563 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci,
1564                    const struct mlxsw_tx_info *tx_info)
1565 {
1566         u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci);
1567
1568         return mlxsw_pci_sdq_get(mlxsw_pci, sdqn);
1569 }
1570
1571 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv,
1572                                         const struct mlxsw_tx_info *tx_info)
1573 {
1574         struct mlxsw_pci *mlxsw_pci = bus_priv;
1575         struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1576
1577         return !mlxsw_pci_queue_elem_info_producer_get(q);
1578 }
1579
1580 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
1581                                   const struct mlxsw_tx_info *tx_info)
1582 {
1583         struct mlxsw_pci *mlxsw_pci = bus_priv;
1584         struct mlxsw_pci_queue *q;
1585         struct mlxsw_pci_queue_elem_info *elem_info;
1586         char *wqe;
1587         int i;
1588         int err;
1589
1590         if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) {
1591                 err = skb_linearize(skb);
1592                 if (err)
1593                         return err;
1594         }
1595
1596         q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1597         spin_lock_bh(&q->lock);
1598         elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
1599         if (!elem_info) {
1600                 /* queue is full */
1601                 err = -EAGAIN;
1602                 goto unlock;
1603         }
1604         elem_info->u.sdq.skb = skb;
1605
1606         wqe = elem_info->elem;
1607         mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */
1608         mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad);
1609         mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET);
1610
1611         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
1612                                      skb_headlen(skb), DMA_TO_DEVICE);
1613         if (err)
1614                 goto unlock;
1615
1616         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1617                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1618
1619                 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1,
1620                                              skb_frag_address(frag),
1621                                              skb_frag_size(frag),
1622                                              DMA_TO_DEVICE);
1623                 if (err)
1624                         goto unmap_frags;
1625         }
1626
1627         /* Set unused sq entries byte count to zero. */
1628         for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
1629                 mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
1630
1631         /* Everything is set up, ring producer doorbell to get HW going */
1632         q->producer_counter++;
1633         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
1634
1635         goto unlock;
1636
1637 unmap_frags:
1638         for (; i >= 0; i--)
1639                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
1640 unlock:
1641         spin_unlock_bh(&q->lock);
1642         return err;
1643 }
1644
1645 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
1646                               u32 in_mod, bool out_mbox_direct,
1647                               char *in_mbox, size_t in_mbox_size,
1648                               char *out_mbox, size_t out_mbox_size,
1649                               u8 *p_status)
1650 {
1651         struct mlxsw_pci *mlxsw_pci = bus_priv;
1652         dma_addr_t in_mapaddr = 0, out_mapaddr = 0;
1653         bool evreq = mlxsw_pci->cmd.nopoll;
1654         unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS);
1655         bool *p_wait_done = &mlxsw_pci->cmd.wait_done;
1656         int err;
1657
1658         *p_status = MLXSW_CMD_STATUS_OK;
1659
1660         err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock);
1661         if (err)
1662                 return err;
1663
1664         if (in_mbox) {
1665                 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size);
1666                 in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr;
1667         }
1668         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr));
1669         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr));
1670
1671         if (out_mbox)
1672                 out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr;
1673         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr));
1674         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr));
1675
1676         mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod);
1677         mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0);
1678
1679         *p_wait_done = false;
1680
1681         wmb(); /* all needs to be written before we write control register */
1682         mlxsw_pci_write32(mlxsw_pci, CIR_CTRL,
1683                           MLXSW_PCI_CIR_CTRL_GO_BIT |
1684                           (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) |
1685                           (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) |
1686                           opcode);
1687
1688         if (!evreq) {
1689                 unsigned long end;
1690
1691                 end = jiffies + timeout;
1692                 do {
1693                         u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL);
1694
1695                         if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) {
1696                                 *p_wait_done = true;
1697                                 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT;
1698                                 break;
1699                         }
1700                         cond_resched();
1701                 } while (time_before(jiffies, end));
1702         } else {
1703                 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout);
1704                 *p_status = mlxsw_pci->cmd.comp.status;
1705         }
1706
1707         err = 0;
1708         if (*p_wait_done) {
1709                 if (*p_status)
1710                         err = -EIO;
1711         } else {
1712                 err = -ETIMEDOUT;
1713         }
1714
1715         if (!err && out_mbox && out_mbox_direct) {
1716                 /* Some commands don't use output param as address to mailbox
1717                  * but they store output directly into registers. In that case,
1718                  * copy registers into mbox buffer.
1719                  */
1720                 __be32 tmp;
1721
1722                 if (!evreq) {
1723                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1724                                                            CIR_OUT_PARAM_HI));
1725                         memcpy(out_mbox, &tmp, sizeof(tmp));
1726                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1727                                                            CIR_OUT_PARAM_LO));
1728                         memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp));
1729                 }
1730         } else if (!err && out_mbox) {
1731                 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size);
1732         }
1733
1734         mutex_unlock(&mlxsw_pci->cmd.lock);
1735
1736         return err;
1737 }
1738
1739 static const struct mlxsw_bus mlxsw_pci_bus = {
1740         .kind                   = "pci",
1741         .init                   = mlxsw_pci_init,
1742         .fini                   = mlxsw_pci_fini,
1743         .skb_transmit_busy      = mlxsw_pci_skb_transmit_busy,
1744         .skb_transmit           = mlxsw_pci_skb_transmit,
1745         .cmd_exec               = mlxsw_pci_cmd_exec,
1746         .features               = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET,
1747 };
1748
1749 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1750 {
1751         const char *driver_name = pdev->driver->name;
1752         struct mlxsw_pci *mlxsw_pci;
1753         int err;
1754
1755         mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL);
1756         if (!mlxsw_pci)
1757                 return -ENOMEM;
1758
1759         err = pci_enable_device(pdev);
1760         if (err) {
1761                 dev_err(&pdev->dev, "pci_enable_device failed\n");
1762                 goto err_pci_enable_device;
1763         }
1764
1765         err = pci_request_regions(pdev, driver_name);
1766         if (err) {
1767                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1768                 goto err_pci_request_regions;
1769         }
1770
1771         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1772         if (!err) {
1773                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1774                 if (err) {
1775                         dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n");
1776                         goto err_pci_set_dma_mask;
1777                 }
1778         } else {
1779                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1780                 if (err) {
1781                         dev_err(&pdev->dev, "pci_set_dma_mask failed\n");
1782                         goto err_pci_set_dma_mask;
1783                 }
1784         }
1785
1786         if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) {
1787                 dev_err(&pdev->dev, "invalid PCI region size\n");
1788                 err = -EINVAL;
1789                 goto err_pci_resource_len_check;
1790         }
1791
1792         mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0),
1793                                      pci_resource_len(pdev, 0));
1794         if (!mlxsw_pci->hw_addr) {
1795                 dev_err(&pdev->dev, "ioremap failed\n");
1796                 err = -EIO;
1797                 goto err_ioremap;
1798         }
1799         pci_set_master(pdev);
1800
1801         mlxsw_pci->pdev = pdev;
1802         pci_set_drvdata(pdev, mlxsw_pci);
1803
1804         mlxsw_pci->bus_info.device_kind = driver_name;
1805         mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
1806         mlxsw_pci->bus_info.dev = &pdev->dev;
1807         mlxsw_pci->id = id;
1808
1809         err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,
1810                                              &mlxsw_pci_bus, mlxsw_pci, false,
1811                                              NULL);
1812         if (err) {
1813                 dev_err(&pdev->dev, "cannot register bus device\n");
1814                 goto err_bus_device_register;
1815         }
1816
1817         return 0;
1818
1819 err_bus_device_register:
1820         iounmap(mlxsw_pci->hw_addr);
1821 err_ioremap:
1822 err_pci_resource_len_check:
1823 err_pci_set_dma_mask:
1824         pci_release_regions(pdev);
1825 err_pci_request_regions:
1826         pci_disable_device(pdev);
1827 err_pci_enable_device:
1828         kfree(mlxsw_pci);
1829         return err;
1830 }
1831
1832 static void mlxsw_pci_remove(struct pci_dev *pdev)
1833 {
1834         struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);
1835
1836         mlxsw_core_bus_device_unregister(mlxsw_pci->core, false);
1837         iounmap(mlxsw_pci->hw_addr);
1838         pci_release_regions(mlxsw_pci->pdev);
1839         pci_disable_device(mlxsw_pci->pdev);
1840         kfree(mlxsw_pci);
1841 }
1842
1843 int mlxsw_pci_driver_register(struct pci_driver *pci_driver)
1844 {
1845         pci_driver->probe = mlxsw_pci_probe;
1846         pci_driver->remove = mlxsw_pci_remove;
1847         return pci_register_driver(pci_driver);
1848 }
1849 EXPORT_SYMBOL(mlxsw_pci_driver_register);
1850
1851 void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver)
1852 {
1853         pci_unregister_driver(pci_driver);
1854 }
1855 EXPORT_SYMBOL(mlxsw_pci_driver_unregister);
1856
1857 static int __init mlxsw_pci_module_init(void)
1858 {
1859         return 0;
1860 }
1861
1862 static void __exit mlxsw_pci_module_exit(void)
1863 {
1864 }
1865
1866 module_init(mlxsw_pci_module_init);
1867 module_exit(mlxsw_pci_module_exit);
1868
1869 MODULE_LICENSE("Dual BSD/GPL");
1870 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1871 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");