drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
   2
   3 /* Gigabit Ethernet driver for Mellanox BlueField SoC
   4  *
   5  * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
   6  */
   7
   8 #include <linux/acpi.h>
   9 #include <linux/device.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/etherdevice.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/module.h>
  15 #include <linux/phy.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/skbuff.h>
  18
  19 #include "mlxbf_gige.h"
  20 #include "mlxbf_gige_regs.h"
  21
  22 #define DRV_NAME    "mlxbf_gige"
  23
  24 /* Allocate SKB whose payload pointer aligns with the Bluefield
  25  * hardware DMA limitation, i.e. DMA operation can't cross
  26  * a 4KB boundary.  A maximum packet size of 2KB is assumed in the
  27  * alignment formula.  The alignment logic overallocates an SKB,
  28  * and then adjusts the headroom so that the SKB data pointer is
  29  * naturally aligned to a 2KB boundary.
  30  */
  31 struct sk_buff *mlxbf_gige_alloc_skb(struct mlxbf_gige *priv,
  32                                      unsigned int map_len,
  33                                      dma_addr_t *buf_dma,
  34                                      enum dma_data_direction dir)
  35 {
  36         struct sk_buff *skb;
  37         u64 addr, offset;
  38
  39         /* Overallocate the SKB so that any headroom adjustment (to
  40          * provide 2KB natural alignment) does not exceed payload area
  41          */
  42         skb = netdev_alloc_skb(priv->netdev, MLXBF_GIGE_DEFAULT_BUF_SZ * 2);
  43         if (!skb)
  44                 return NULL;
  45
  46         /* Adjust the headroom so that skb->data is naturally aligned to
  47          * a 2KB boundary, which is the maximum packet size supported.
  48          */
  49         addr = (long)skb->data;
  50         offset = (addr + MLXBF_GIGE_DEFAULT_BUF_SZ - 1) &
  51                 ~(MLXBF_GIGE_DEFAULT_BUF_SZ - 1);
  52         offset -= addr;
  53         if (offset)
  54                 skb_reserve(skb, offset);
  55
  56         /* Return streaming DMA mapping to caller */
  57         *buf_dma = dma_map_single(priv->dev, skb->data, map_len, dir);
  58         if (dma_mapping_error(priv->dev, *buf_dma)) {
  59                 dev_kfree_skb(skb);
  60                 *buf_dma = (dma_addr_t)0;
  61                 return NULL;
  62         }
  63
  64         return skb;
  65 }
  66
  67 static void mlxbf_gige_initial_mac(struct mlxbf_gige *priv)
  68 {
  69         u8 mac[ETH_ALEN];
  70         u64 local_mac;
  71
  72         memset(mac, 0, ETH_ALEN);
  73         mlxbf_gige_get_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX,
  74                                      &local_mac);
  75         u64_to_ether_addr(local_mac, mac);
  76
  77         if (is_valid_ether_addr(mac)) {
  78                 ether_addr_copy(priv->netdev->dev_addr, mac);
  79         } else {
  80                 /* Provide a random MAC if for some reason the device has
  81                  * not been configured with a valid MAC address already.
  82                  */
  83                 eth_hw_addr_random(priv->netdev);
  84         }
  85
  86         local_mac = ether_addr_to_u64(priv->netdev->dev_addr);
  87         mlxbf_gige_set_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX,
  88                                      local_mac);
  89 }
  90
  91 static void mlxbf_gige_cache_stats(struct mlxbf_gige *priv)
  92 {
  93         struct mlxbf_gige_stats *p;
  94
  95         /* Cache stats that will be cleared by clean port operation */
  96         p = &priv->stats;
  97         p->rx_din_dropped_pkts += readq(priv->base +
  98                                         MLXBF_GIGE_RX_DIN_DROP_COUNTER);
  99         p->rx_filter_passed_pkts += readq(priv->base +
 100                                           MLXBF_GIGE_RX_PASS_COUNTER_ALL);
 101         p->rx_filter_discard_pkts += readq(priv->base +
 102                                            MLXBF_GIGE_RX_DISC_COUNTER_ALL);
 103 }
 104
 105 static int mlxbf_gige_clean_port(struct mlxbf_gige *priv)
 106 {
 107         u64 control;
 108         u64 temp;
 109         int err;
 110
 111         /* Set the CLEAN_PORT_EN bit to trigger SW reset */
 112         control = readq(priv->base + MLXBF_GIGE_CONTROL);
 113         control |= MLXBF_GIGE_CONTROL_CLEAN_PORT_EN;
 114         writeq(control, priv->base + MLXBF_GIGE_CONTROL);
 115
 116         /* Ensure completion of "clean port" write before polling status */
 117         mb();
 118
 119         err = readq_poll_timeout_atomic(priv->base + MLXBF_GIGE_STATUS, temp,
 120                                         (temp & MLXBF_GIGE_STATUS_READY),
 121                                         100, 100000);
 122
 123         /* Clear the CLEAN_PORT_EN bit at end of this loop */
 124         control = readq(priv->base + MLXBF_GIGE_CONTROL);
 125         control &= ~MLXBF_GIGE_CONTROL_CLEAN_PORT_EN;
 126         writeq(control, priv->base + MLXBF_GIGE_CONTROL);
 127
 128         return err;
 129 }
 130
 131 static int mlxbf_gige_open(struct net_device *netdev)
 132 {
 133         struct mlxbf_gige *priv = netdev_priv(netdev);
 134         struct phy_device *phydev = netdev->phydev;
 135         u64 int_en;
 136         int err;
 137
 138         err = mlxbf_gige_request_irqs(priv);
 139         if (err)
 140                 return err;
 141         mlxbf_gige_cache_stats(priv);
 142         err = mlxbf_gige_clean_port(priv);
 143         if (err)
 144                 goto free_irqs;
 145         err = mlxbf_gige_rx_init(priv);
 146         if (err)
 147                 goto free_irqs;
 148         err = mlxbf_gige_tx_init(priv);
 149         if (err)
 150                 goto rx_deinit;
 151
 152         phy_start(phydev);
 153
 154         netif_napi_add(netdev, &priv->napi, mlxbf_gige_poll, NAPI_POLL_WEIGHT);
 155         napi_enable(&priv->napi);
 156         netif_start_queue(netdev);
 157
 158         /* Set bits in INT_EN that we care about */
 159         int_en = MLXBF_GIGE_INT_EN_HW_ACCESS_ERROR |
 160                  MLXBF_GIGE_INT_EN_TX_CHECKSUM_INPUTS |
 161                  MLXBF_GIGE_INT_EN_TX_SMALL_FRAME_SIZE |
 162                  MLXBF_GIGE_INT_EN_TX_PI_CI_EXCEED_WQ_SIZE |
 163                  MLXBF_GIGE_INT_EN_SW_CONFIG_ERROR |
 164                  MLXBF_GIGE_INT_EN_SW_ACCESS_ERROR |
 165                  MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET;
 166
 167         /* Ensure completion of all initialization before enabling interrupts */
 168         mb();
 169
 170         writeq(int_en, priv->base + MLXBF_GIGE_INT_EN);
 171
 172         return 0;
 173
 174 rx_deinit:
 175         mlxbf_gige_rx_deinit(priv);
 176
 177 free_irqs:
 178         mlxbf_gige_free_irqs(priv);
 179         return err;
 180 }
 181
 182 static int mlxbf_gige_stop(struct net_device *netdev)
 183 {
 184         struct mlxbf_gige *priv = netdev_priv(netdev);
 185
 186         writeq(0, priv->base + MLXBF_GIGE_INT_EN);
 187         netif_stop_queue(netdev);
 188         napi_disable(&priv->napi);
 189         netif_napi_del(&priv->napi);
 190         mlxbf_gige_free_irqs(priv);
 191
 192         phy_stop(netdev->phydev);
 193
 194         mlxbf_gige_rx_deinit(priv);
 195         mlxbf_gige_tx_deinit(priv);
 196         mlxbf_gige_cache_stats(priv);
 197         mlxbf_gige_clean_port(priv);
 198
 199         return 0;
 200 }
 201
 202 static int mlxbf_gige_eth_ioctl(struct net_device *netdev,
 203                                struct ifreq *ifr, int cmd)
 204 {
 205         if (!(netif_running(netdev)))
 206                 return -EINVAL;
 207
 208         return phy_mii_ioctl(netdev->phydev, ifr, cmd);
 209 }
 210
 211 static void mlxbf_gige_set_rx_mode(struct net_device *netdev)
 212 {
 213         struct mlxbf_gige *priv = netdev_priv(netdev);
 214         bool new_promisc_enabled;
 215
 216         new_promisc_enabled = netdev->flags & IFF_PROMISC;
 217
 218         /* Only write to the hardware registers if the new setting
 219          * of promiscuous mode is different from the current one.
 220          */
 221         if (new_promisc_enabled != priv->promisc_enabled) {
 222                 priv->promisc_enabled = new_promisc_enabled;
 223
 224                 if (new_promisc_enabled)
 225                         mlxbf_gige_enable_promisc(priv);
 226                 else
 227                         mlxbf_gige_disable_promisc(priv);
 228         }
 229 }
 230
 231 static void mlxbf_gige_get_stats64(struct net_device *netdev,
 232                                    struct rtnl_link_stats64 *stats)
 233 {
 234         struct mlxbf_gige *priv = netdev_priv(netdev);
 235
 236         netdev_stats_to_stats64(stats, &netdev->stats);
 237
 238         stats->rx_length_errors = priv->stats.rx_truncate_errors;
 239         stats->rx_fifo_errors = priv->stats.rx_din_dropped_pkts +
 240                                 readq(priv->base + MLXBF_GIGE_RX_DIN_DROP_COUNTER);
 241         stats->rx_crc_errors = priv->stats.rx_mac_errors;
 242         stats->rx_errors = stats->rx_length_errors +
 243                            stats->rx_fifo_errors +
 244                            stats->rx_crc_errors;
 245
 246         stats->tx_fifo_errors = priv->stats.tx_fifo_full;
 247         stats->tx_errors = stats->tx_fifo_errors;
 248 }
 249
 250 static const struct net_device_ops mlxbf_gige_netdev_ops = {
 251         .ndo_open               = mlxbf_gige_open,
 252         .ndo_stop               = mlxbf_gige_stop,
 253         .ndo_start_xmit         = mlxbf_gige_start_xmit,
 254         .ndo_set_mac_address    = eth_mac_addr,
 255         .ndo_validate_addr      = eth_validate_addr,
 256         .ndo_eth_ioctl          = mlxbf_gige_eth_ioctl,
 257         .ndo_set_rx_mode        = mlxbf_gige_set_rx_mode,
 258         .ndo_get_stats64        = mlxbf_gige_get_stats64,
 259 };
 260
 261 static void mlxbf_gige_adjust_link(struct net_device *netdev)
 262 {
 263         struct phy_device *phydev = netdev->phydev;
 264
 265         phy_print_status(phydev);
 266 }
 267
 268 static int mlxbf_gige_probe(struct platform_device *pdev)
 269 {
 270         struct phy_device *phydev;
 271         struct net_device *netdev;
 272         struct mlxbf_gige *priv;
 273         void __iomem *llu_base;
 274         void __iomem *plu_base;
 275         void __iomem *base;
 276         u64 control;
 277         int addr;
 278         int err;
 279
 280         base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MAC);
 281         if (IS_ERR(base))
 282                 return PTR_ERR(base);
 283
 284         llu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_LLU);
 285         if (IS_ERR(llu_base))
 286                 return PTR_ERR(llu_base);
 287
 288         plu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_PLU);
 289         if (IS_ERR(plu_base))
 290                 return PTR_ERR(plu_base);
 291
 292         /* Perform general init of GigE block */
 293         control = readq(base + MLXBF_GIGE_CONTROL);
 294         control |= MLXBF_GIGE_CONTROL_PORT_EN;
 295         writeq(control, base + MLXBF_GIGE_CONTROL);
 296
 297         netdev = devm_alloc_etherdev(&pdev->dev, sizeof(*priv));
 298         if (!netdev)
 299                 return -ENOMEM;
 300
 301         SET_NETDEV_DEV(netdev, &pdev->dev);
 302         netdev->netdev_ops = &mlxbf_gige_netdev_ops;
 303         netdev->ethtool_ops = &mlxbf_gige_ethtool_ops;
 304         priv = netdev_priv(netdev);
 305         priv->netdev = netdev;
 306
 307         platform_set_drvdata(pdev, priv);
 308         priv->dev = &pdev->dev;
 309         priv->pdev = pdev;
 310
 311         spin_lock_init(&priv->lock);
 312         spin_lock_init(&priv->gpio_lock);
 313
 314         /* Attach MDIO device */
 315         err = mlxbf_gige_mdio_probe(pdev, priv);
 316         if (err)
 317                 return err;
 318
 319         err = mlxbf_gige_gpio_init(pdev, priv);
 320         if (err) {
 321                 dev_err(&pdev->dev, "PHY IRQ initialization failed\n");
 322                 mlxbf_gige_mdio_remove(priv);
 323                 return -ENODEV;
 324         }
 325
 326         priv->base = base;
 327         priv->llu_base = llu_base;
 328         priv->plu_base = plu_base;
 329
 330         priv->rx_q_entries = MLXBF_GIGE_DEFAULT_RXQ_SZ;
 331         priv->tx_q_entries = MLXBF_GIGE_DEFAULT_TXQ_SZ;
 332
 333         /* Write initial MAC address to hardware */
 334         mlxbf_gige_initial_mac(priv);
 335
 336         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 337         if (err) {
 338                 dev_err(&pdev->dev, "DMA configuration failed: 0x%x\n", err);
 339                 goto out;
 340         }
 341
 342         priv->error_irq = platform_get_irq(pdev, MLXBF_GIGE_ERROR_INTR_IDX);
 343         priv->rx_irq = platform_get_irq(pdev, MLXBF_GIGE_RECEIVE_PKT_INTR_IDX);
 344         priv->llu_plu_irq = platform_get_irq(pdev, MLXBF_GIGE_LLU_PLU_INTR_IDX);
 345
 346         phydev = phy_find_first(priv->mdiobus);
 347         if (!phydev) {
 348                 err = -ENODEV;
 349                 goto out;
 350         }
 351
 352         addr = phydev->mdio.addr;
 353         priv->mdiobus->irq[addr] = priv->phy_irq;
 354         phydev->irq = priv->phy_irq;
 355
 356         err = phy_connect_direct(netdev, phydev,
 357                                  mlxbf_gige_adjust_link,
 358                                  PHY_INTERFACE_MODE_GMII);
 359         if (err) {
 360                 dev_err(&pdev->dev, "Could not attach to PHY\n");
 361                 goto out;
 362         }
 363
 364         /* MAC only supports 1000T full duplex mode */
 365         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
 366         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT);
 367         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
 368         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
 369         phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
 370
 371         /* Only symmetric pause with flow control enabled is supported so no
 372          * need to negotiate pause.
 373          */
 374         linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising);
 375         linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising);
 376
 377         /* Display information about attached PHY device */
 378         phy_attached_info(phydev);
 379
 380         err = register_netdev(netdev);
 381         if (err) {
 382                 dev_err(&pdev->dev, "Failed to register netdev\n");
 383                 phy_disconnect(phydev);
 384                 goto out;
 385         }
 386
 387         return 0;
 388
 389 out:
 390         mlxbf_gige_gpio_free(priv);
 391         mlxbf_gige_mdio_remove(priv);
 392         return err;
 393 }
 394
 395 static int mlxbf_gige_remove(struct platform_device *pdev)
 396 {
 397         struct mlxbf_gige *priv = platform_get_drvdata(pdev);
 398
 399         unregister_netdev(priv->netdev);
 400         phy_disconnect(priv->netdev->phydev);
 401         mlxbf_gige_gpio_free(priv);
 402         mlxbf_gige_mdio_remove(priv);
 403         platform_set_drvdata(pdev, NULL);
 404
 405         return 0;
 406 }
 407
 408 static void mlxbf_gige_shutdown(struct platform_device *pdev)
 409 {
 410         struct mlxbf_gige *priv = platform_get_drvdata(pdev);
 411
 412         writeq(0, priv->base + MLXBF_GIGE_INT_EN);
 413         mlxbf_gige_clean_port(priv);
 414 }
 415
 416 static const struct acpi_device_id __maybe_unused mlxbf_gige_acpi_match[] = {
 417         { "MLNXBF17", 0 },
 418         {},
 419 };
 420 MODULE_DEVICE_TABLE(acpi, mlxbf_gige_acpi_match);
 421
 422 static struct platform_driver mlxbf_gige_driver = {
 423         .probe = mlxbf_gige_probe,
 424         .remove = mlxbf_gige_remove,
 425         .shutdown = mlxbf_gige_shutdown,
 426         .driver = {
 427                 .name = DRV_NAME,
 428                 .acpi_match_table = ACPI_PTR(mlxbf_gige_acpi_match),
 429         },
 430 };
 431
 432 module_platform_driver(mlxbf_gige_driver);
 433
 434 MODULE_DESCRIPTION("Mellanox BlueField SoC Gigabit Ethernet Driver");
 435 MODULE_AUTHOR("David Thompson <davthompson@nvidia.com>");
 436 MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
 437 MODULE_LICENSE("Dual BSD/GPL");