1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2019, Mellanox Technologies */
7 #include <linux/mlx5/driver.h>
8 #include <linux/refcount.h>
12 #include "mlx5_ifc_dr.h"
15 #define DR_RULE_MAX_STES 17
16 #define DR_ACTION_MAX_STES 5
17 #define WIRE_PORT 0xFFFF
18 #define DR_STE_SVLAN 0x1
19 #define DR_STE_CVLAN 0x2
21 #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg)
22 #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg)
23 #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg)
25 enum mlx5dr_icm_chunk_size {
27 DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */
52 enum mlx5dr_icm_type {
54 DR_ICM_TYPE_MODIFY_ACTION,
57 static inline enum mlx5dr_icm_chunk_size
58 mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk)
61 if (chunk < DR_CHUNK_SIZE_MAX)
64 return DR_CHUNK_SIZE_MAX;
69 DR_STE_SIZE_CTRL = 32,
71 DR_STE_SIZE_MASK = 16,
75 DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK,
79 DR_MODIFY_ACTION_SIZE = 8,
82 enum mlx5dr_matcher_criteria {
83 DR_MATCHER_CRITERIA_EMPTY = 0,
84 DR_MATCHER_CRITERIA_OUTER = 1 << 0,
85 DR_MATCHER_CRITERIA_MISC = 1 << 1,
86 DR_MATCHER_CRITERIA_INNER = 1 << 2,
87 DR_MATCHER_CRITERIA_MISC2 = 1 << 3,
88 DR_MATCHER_CRITERIA_MISC3 = 1 << 4,
89 DR_MATCHER_CRITERIA_MAX = 1 << 5,
92 enum mlx5dr_action_type {
93 DR_ACTION_TYP_TNL_L2_TO_L2,
94 DR_ACTION_TYP_L2_TO_TNL_L2,
95 DR_ACTION_TYP_TNL_L3_TO_L2,
96 DR_ACTION_TYP_L2_TO_TNL_L3,
102 DR_ACTION_TYP_MODIFY_HDR,
104 DR_ACTION_TYP_POP_VLAN,
105 DR_ACTION_TYP_PUSH_VLAN,
115 struct mlx5dr_icm_pool;
116 struct mlx5dr_icm_chunk;
117 struct mlx5dr_icm_bucket;
118 struct mlx5dr_ste_htbl;
119 struct mlx5dr_match_param;
120 struct mlx5dr_cmd_caps;
121 struct mlx5dr_matcher_rx_tx;
125 /* refcount: indicates the num of rules that using this ste */
128 /* attached to the miss_list head at each htbl entry */
129 struct list_head miss_list_node;
131 /* each rule member that uses this ste attached here */
132 struct list_head rule_list;
134 /* this ste is member of htbl */
135 struct mlx5dr_ste_htbl *htbl;
137 struct mlx5dr_ste_htbl *next_htbl;
139 /* this ste is part of a rule, located in ste's chain */
140 u8 ste_chain_location;
143 struct mlx5dr_ste_htbl_ctrl {
144 /* total number of valid entries belonging to this hash table. This
145 * includes the non collision and collision entries
147 unsigned int num_of_valid_entries;
149 /* total number of collisions entries attached to this table */
150 unsigned int num_of_collisions;
151 unsigned int increase_threshold;
155 struct mlx5dr_ste_htbl {
159 struct mlx5dr_icm_chunk *chunk;
160 struct mlx5dr_ste *ste_arr;
163 struct list_head *miss_list;
165 enum mlx5dr_icm_chunk_size chunk_size;
166 struct mlx5dr_ste *pointing_ste;
168 struct mlx5dr_ste_htbl_ctrl ctrl;
171 struct mlx5dr_ste_send_info {
172 struct mlx5dr_ste *ste;
173 struct list_head send_list;
176 u8 data_cont[DR_STE_SIZE];
180 void mlx5dr_send_fill_and_append_ste_send_info(struct mlx5dr_ste *ste, u16 size,
181 u16 offset, u8 *data,
182 struct mlx5dr_ste_send_info *ste_info,
183 struct list_head *send_list,
186 struct mlx5dr_ste_build {
190 struct mlx5dr_domain *dmn;
191 struct mlx5dr_cmd_caps *caps;
194 u8 bit_mask[DR_STE_SIZE_MASK];
195 int (*ste_build_tag_func)(struct mlx5dr_match_param *spec,
196 struct mlx5dr_ste_build *sb,
200 struct mlx5dr_ste_htbl *
201 mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool,
202 enum mlx5dr_icm_chunk_size chunk_size,
203 u8 lu_type, u16 byte_mask);
205 int mlx5dr_ste_htbl_free(struct mlx5dr_ste_htbl *htbl);
207 static inline void mlx5dr_htbl_put(struct mlx5dr_ste_htbl *htbl)
211 mlx5dr_ste_htbl_free(htbl);
214 static inline void mlx5dr_htbl_get(struct mlx5dr_ste_htbl *htbl)
220 u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl);
221 void mlx5dr_ste_init(u8 *hw_ste_p, u8 lu_type, u8 entry_type, u16 gvmi);
222 void mlx5dr_ste_always_hit_htbl(struct mlx5dr_ste *ste,
223 struct mlx5dr_ste_htbl *next_htbl);
224 void mlx5dr_ste_set_miss_addr(u8 *hw_ste, u64 miss_addr);
225 u64 mlx5dr_ste_get_miss_addr(u8 *hw_ste);
226 void mlx5dr_ste_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi);
227 void mlx5dr_ste_set_hit_addr(u8 *hw_ste, u64 icm_addr, u32 ht_size);
228 void mlx5dr_ste_always_miss_addr(struct mlx5dr_ste *ste, u64 miss_addr);
229 void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask);
230 bool mlx5dr_ste_is_last_in_rule(struct mlx5dr_matcher_rx_tx *nic_matcher,
232 void mlx5dr_ste_rx_set_flow_tag(u8 *hw_ste_p, u32 flow_tag);
233 void mlx5dr_ste_set_counter_id(u8 *hw_ste_p, u32 ctr_id);
234 void mlx5dr_ste_set_tx_encap(void *hw_ste_p, u32 reformat_id,
235 int size, bool encap_l3);
236 void mlx5dr_ste_set_rx_decap(u8 *hw_ste_p);
237 void mlx5dr_ste_set_rx_decap_l3(u8 *hw_ste_p, bool vlan);
238 void mlx5dr_ste_set_rx_pop_vlan(u8 *hw_ste_p);
239 void mlx5dr_ste_set_tx_push_vlan(u8 *hw_ste_p, u32 vlan_tpid_pcp_dei_vid,
241 void mlx5dr_ste_set_entry_type(u8 *hw_ste_p, u8 entry_type);
242 u8 mlx5dr_ste_get_entry_type(u8 *hw_ste_p);
243 void mlx5dr_ste_set_rewrite_actions(u8 *hw_ste_p, u16 num_of_actions,
245 void mlx5dr_ste_set_go_back_bit(u8 *hw_ste_p);
246 u64 mlx5dr_ste_get_icm_addr(struct mlx5dr_ste *ste);
247 u64 mlx5dr_ste_get_mr_addr(struct mlx5dr_ste *ste);
248 struct list_head *mlx5dr_ste_get_miss_list(struct mlx5dr_ste *ste);
250 void mlx5dr_ste_free(struct mlx5dr_ste *ste,
251 struct mlx5dr_matcher *matcher,
252 struct mlx5dr_matcher_rx_tx *nic_matcher);
253 static inline void mlx5dr_ste_put(struct mlx5dr_ste *ste,
254 struct mlx5dr_matcher *matcher,
255 struct mlx5dr_matcher_rx_tx *nic_matcher)
259 mlx5dr_ste_free(ste, matcher, nic_matcher);
262 /* initial as 0, increased only when ste appears in a new rule */
263 static inline void mlx5dr_ste_get(struct mlx5dr_ste *ste)
268 static inline bool mlx5dr_ste_is_not_used(struct mlx5dr_ste *ste)
270 return !ste->refcount;
273 void mlx5dr_ste_set_hit_addr_by_next_htbl(u8 *hw_ste,
274 struct mlx5dr_ste_htbl *next_htbl);
275 bool mlx5dr_ste_equal_tag(void *src, void *dst);
276 int mlx5dr_ste_create_next_htbl(struct mlx5dr_matcher *matcher,
277 struct mlx5dr_matcher_rx_tx *nic_matcher,
278 struct mlx5dr_ste *ste,
280 enum mlx5dr_icm_chunk_size log_table_size);
282 /* STE build functions */
283 int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn,
285 struct mlx5dr_match_param *mask,
286 struct mlx5dr_match_param *value);
287 int mlx5dr_ste_build_ste_arr(struct mlx5dr_matcher *matcher,
288 struct mlx5dr_matcher_rx_tx *nic_matcher,
289 struct mlx5dr_match_param *value,
291 int mlx5dr_ste_build_eth_l2_src_des(struct mlx5dr_ste_build *builder,
292 struct mlx5dr_match_param *mask,
293 bool inner, bool rx);
294 void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_build *sb,
295 struct mlx5dr_match_param *mask,
296 bool inner, bool rx);
297 void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_build *sb,
298 struct mlx5dr_match_param *mask,
299 bool inner, bool rx);
300 void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_build *sb,
301 struct mlx5dr_match_param *mask,
302 bool inner, bool rx);
303 void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_build *sb,
304 struct mlx5dr_match_param *mask,
305 bool inner, bool rx);
306 void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_build *sb,
307 struct mlx5dr_match_param *mask,
308 bool inner, bool rx);
309 void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_build *sb,
310 struct mlx5dr_match_param *mask,
311 bool inner, bool rx);
312 void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_build *sb,
313 struct mlx5dr_match_param *mask,
314 bool inner, bool rx);
315 void mlx5dr_ste_build_ipv6_l3_l4(struct mlx5dr_ste_build *sb,
316 struct mlx5dr_match_param *mask,
317 bool inner, bool rx);
318 void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_build *sb,
319 struct mlx5dr_match_param *mask,
320 bool inner, bool rx);
321 void mlx5dr_ste_build_gre(struct mlx5dr_ste_build *sb,
322 struct mlx5dr_match_param *mask,
323 bool inner, bool rx);
324 void mlx5dr_ste_build_mpls(struct mlx5dr_ste_build *sb,
325 struct mlx5dr_match_param *mask,
326 bool inner, bool rx);
327 void mlx5dr_ste_build_flex_parser_0(struct mlx5dr_ste_build *sb,
328 struct mlx5dr_match_param *mask,
329 bool inner, bool rx);
330 int mlx5dr_ste_build_flex_parser_1(struct mlx5dr_ste_build *sb,
331 struct mlx5dr_match_param *mask,
332 struct mlx5dr_cmd_caps *caps,
333 bool inner, bool rx);
334 void mlx5dr_ste_build_flex_parser_tnl_vxlan_gpe(struct mlx5dr_ste_build *sb,
335 struct mlx5dr_match_param *mask,
336 bool inner, bool rx);
337 void mlx5dr_ste_build_flex_parser_tnl_geneve(struct mlx5dr_ste_build *sb,
338 struct mlx5dr_match_param *mask,
339 bool inner, bool rx);
340 void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_build *sb,
341 struct mlx5dr_match_param *mask,
342 bool inner, bool rx);
343 void mlx5dr_ste_build_register_0(struct mlx5dr_ste_build *sb,
344 struct mlx5dr_match_param *mask,
345 bool inner, bool rx);
346 void mlx5dr_ste_build_register_1(struct mlx5dr_ste_build *sb,
347 struct mlx5dr_match_param *mask,
348 bool inner, bool rx);
349 void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_build *sb,
350 struct mlx5dr_match_param *mask,
351 struct mlx5dr_domain *dmn,
352 bool inner, bool rx);
353 void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx);
356 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher,
357 struct mlx5dr_matcher_rx_tx *nic_matcher,
358 struct mlx5dr_action *actions[],
361 u32 *new_hw_ste_arr_sz);
363 struct mlx5dr_match_spec {
364 u32 smac_47_16; /* Source MAC address of incoming packet */
365 /* Incoming packet Ethertype - this is the Ethertype
366 * following the last VLAN tag of the packet
369 u32 smac_15_0:16; /* Source MAC address of incoming packet */
370 u32 dmac_47_16; /* Destination MAC address of incoming packet */
371 /* VLAN ID of first VLAN tag in the incoming packet.
372 * Valid only when cvlan_tag==1 or svlan_tag==1
375 /* CFI bit of first VLAN tag in the incoming packet.
376 * Valid only when cvlan_tag==1 or svlan_tag==1
379 /* Priority of first VLAN tag in the incoming packet.
380 * Valid only when cvlan_tag==1 or svlan_tag==1
383 u32 dmac_15_0:16; /* Destination MAC address of incoming packet */
384 /* TCP flags. ;Bit 0: FIN;Bit 1: SYN;Bit 2: RST;Bit 3: PSH;Bit 4: ACK;
385 * Bit 5: URG;Bit 6: ECE;Bit 7: CWR;Bit 8: NS
388 u32 ip_version:4; /* IP version */
389 u32 frag:1; /* Packet is an IP fragment */
390 /* The first vlan in the packet is s-vlan (0x8a88).
391 * cvlan_tag and svlan_tag cannot be set together
394 /* The first vlan in the packet is c-vlan (0x8100).
395 * cvlan_tag and svlan_tag cannot be set together
398 /* Explicit Congestion Notification derived from
399 * Traffic Class/TOS field of IPv6/v4
402 /* Differentiated Services Code Point derived from
403 * Traffic Class/TOS field of IPv6/v4
406 u32 ip_protocol:8; /* IP protocol */
407 /* TCP destination port.
408 * tcp and udp sport/dport are mutually exclusive
411 /* TCP source port.;tcp and udp sport/dport are mutually exclusive */
415 /* UDP destination port.;tcp and udp sport/dport are mutually exclusive */
417 /* UDP source port.;tcp and udp sport/dport are mutually exclusive */
419 /* IPv6 source address of incoming packets
420 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
421 * This field should be qualified by an appropriate ethertype
424 /* IPv6 source address of incoming packets
425 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
426 * This field should be qualified by an appropriate ethertype
429 /* IPv6 source address of incoming packets
430 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
431 * This field should be qualified by an appropriate ethertype
434 /* IPv6 source address of incoming packets
435 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
436 * This field should be qualified by an appropriate ethertype
439 /* IPv6 destination address of incoming packets
440 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
441 * This field should be qualified by an appropriate ethertype
444 /* IPv6 destination address of incoming packets
445 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
446 * This field should be qualified by an appropriate ethertype
449 /* IPv6 destination address of incoming packets
450 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
451 * This field should be qualified by an appropriate ethertype
454 /* IPv6 destination address of incoming packets
455 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
456 * This field should be qualified by an appropriate ethertype
461 struct mlx5dr_match_misc {
462 u32 source_sqn:24; /* Source SQN */
463 u32 source_vhca_port:4;
464 /* used with GRE, sequence number exist when gre_s_present == 1 */
466 /* used with GRE, key exist when gre_k_present == 1 */
468 u32 reserved_auto1:1;
469 /* used with GRE, checksum exist when gre_c_present == 1 */
471 /* Source port.;0xffff determines wire port */
473 u32 source_eswitch_owner_vhca_id:16;
474 /* VLAN ID of first VLAN tag the inner header of the incoming packet.
475 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1
477 u32 inner_second_vid:12;
478 /* CFI bit of first VLAN tag in the inner header of the incoming packet.
479 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1
481 u32 inner_second_cfi:1;
482 /* Priority of second VLAN tag in the inner header of the incoming packet.
483 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1
485 u32 inner_second_prio:3;
486 /* VLAN ID of first VLAN tag the outer header of the incoming packet.
487 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1
489 u32 outer_second_vid:12;
490 /* CFI bit of first VLAN tag in the outer header of the incoming packet.
491 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1
493 u32 outer_second_cfi:1;
494 /* Priority of second VLAN tag in the outer header of the incoming packet.
495 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1
497 u32 outer_second_prio:3;
498 u32 gre_protocol:16; /* GRE Protocol (outer) */
499 u32 reserved_auto3:12;
500 /* The second vlan in the inner header of the packet is s-vlan (0x8a88).
501 * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together
503 u32 inner_second_svlan_tag:1;
504 /* The second vlan in the outer header of the packet is s-vlan (0x8a88).
505 * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together
507 u32 outer_second_svlan_tag:1;
508 /* The second vlan in the inner header of the packet is c-vlan (0x8100).
509 * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together
511 u32 inner_second_cvlan_tag:1;
512 /* The second vlan in the outer header of the packet is c-vlan (0x8100).
513 * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together
515 u32 outer_second_cvlan_tag:1;
516 u32 gre_key_l:8; /* GRE Key [7:0] (outer) */
517 u32 gre_key_h:24; /* GRE Key[31:8] (outer) */
518 u32 reserved_auto4:8;
519 u32 vxlan_vni:24; /* VXLAN VNI (outer) */
520 u32 geneve_oam:1; /* GENEVE OAM field (outer) */
521 u32 reserved_auto5:7;
522 u32 geneve_vni:24; /* GENEVE VNI field (outer) */
523 u32 outer_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (outer) */
524 u32 reserved_auto6:12;
525 u32 inner_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (inner) */
526 u32 reserved_auto7:12;
527 u32 geneve_protocol_type:16; /* GENEVE protocol type (outer) */
528 u32 geneve_opt_len:6; /* GENEVE OptLen (outer) */
529 u32 reserved_auto8:10;
530 u32 bth_dst_qp:24; /* Destination QP in BTH header */
531 u32 reserved_auto9:8;
532 u8 reserved_auto10[20];
535 struct mlx5dr_match_misc2 {
536 u32 outer_first_mpls_ttl:8; /* First MPLS TTL (outer) */
537 u32 outer_first_mpls_s_bos:1; /* First MPLS S_BOS (outer) */
538 u32 outer_first_mpls_exp:3; /* First MPLS EXP (outer) */
539 u32 outer_first_mpls_label:20; /* First MPLS LABEL (outer) */
540 u32 inner_first_mpls_ttl:8; /* First MPLS TTL (inner) */
541 u32 inner_first_mpls_s_bos:1; /* First MPLS S_BOS (inner) */
542 u32 inner_first_mpls_exp:3; /* First MPLS EXP (inner) */
543 u32 inner_first_mpls_label:20; /* First MPLS LABEL (inner) */
544 u32 outer_first_mpls_over_gre_ttl:8; /* last MPLS TTL (outer) */
545 u32 outer_first_mpls_over_gre_s_bos:1; /* last MPLS S_BOS (outer) */
546 u32 outer_first_mpls_over_gre_exp:3; /* last MPLS EXP (outer) */
547 u32 outer_first_mpls_over_gre_label:20; /* last MPLS LABEL (outer) */
548 u32 outer_first_mpls_over_udp_ttl:8; /* last MPLS TTL (outer) */
549 u32 outer_first_mpls_over_udp_s_bos:1; /* last MPLS S_BOS (outer) */
550 u32 outer_first_mpls_over_udp_exp:3; /* last MPLS EXP (outer) */
551 u32 outer_first_mpls_over_udp_label:20; /* last MPLS LABEL (outer) */
552 u32 metadata_reg_c_7; /* metadata_reg_c_7 */
553 u32 metadata_reg_c_6; /* metadata_reg_c_6 */
554 u32 metadata_reg_c_5; /* metadata_reg_c_5 */
555 u32 metadata_reg_c_4; /* metadata_reg_c_4 */
556 u32 metadata_reg_c_3; /* metadata_reg_c_3 */
557 u32 metadata_reg_c_2; /* metadata_reg_c_2 */
558 u32 metadata_reg_c_1; /* metadata_reg_c_1 */
559 u32 metadata_reg_c_0; /* metadata_reg_c_0 */
560 u32 metadata_reg_a; /* metadata_reg_a */
561 u8 reserved_auto2[12];
564 struct mlx5dr_match_misc3 {
565 u32 inner_tcp_seq_num;
566 u32 outer_tcp_seq_num;
567 u32 inner_tcp_ack_num;
568 u32 outer_tcp_ack_num;
569 u32 outer_vxlan_gpe_vni:24;
570 u32 reserved_auto1:8;
571 u32 reserved_auto2:16;
572 u32 outer_vxlan_gpe_flags:8;
573 u32 outer_vxlan_gpe_next_protocol:8;
574 u32 icmpv4_header_data;
575 u32 icmpv6_header_data;
580 u8 reserved_auto3[0x1c];
583 struct mlx5dr_match_param {
584 struct mlx5dr_match_spec outer;
585 struct mlx5dr_match_misc misc;
586 struct mlx5dr_match_spec inner;
587 struct mlx5dr_match_misc2 misc2;
588 struct mlx5dr_match_misc3 misc3;
591 #define DR_MASK_IS_FLEX_PARSER_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \
592 (_misc3)->icmpv4_code || \
593 (_misc3)->icmpv4_header_data)
595 struct mlx5dr_esw_caps {
596 u64 drop_icm_address_rx;
597 u64 drop_icm_address_tx;
598 u64 uplink_icm_address_rx;
599 u64 uplink_icm_address_tx;
603 struct mlx5dr_cmd_vport_cap {
611 struct mlx5dr_cmd_caps {
613 u64 nic_rx_drop_address;
614 u64 nic_tx_drop_address;
615 u64 nic_tx_allow_address;
616 u64 esw_rx_drop_address;
617 u64 esw_tx_drop_address;
619 u64 hdr_modify_icm_addr;
621 u8 flex_parser_id_icmp_dw0;
622 u8 flex_parser_id_icmp_dw1;
623 u8 flex_parser_id_icmpv6_dw0;
624 u8 flex_parser_id_icmpv6_dw1;
626 u16 roce_min_src_udp;
628 bool eswitch_manager;
633 struct mlx5dr_esw_caps esw_caps;
634 struct mlx5dr_cmd_vport_cap *vports_caps;
635 bool prio_tag_required;
638 struct mlx5dr_domain_rx_tx {
640 u64 default_icm_addr;
641 enum mlx5dr_ste_entry_type ste_type;
642 struct mutex mutex; /* protect rx/tx domain */
645 struct mlx5dr_domain_info {
646 bool supp_sw_steering;
649 u32 max_log_sw_icm_sz;
650 u32 max_log_action_icm_sz;
651 struct mlx5dr_domain_rx_tx rx;
652 struct mlx5dr_domain_rx_tx tx;
653 struct mlx5dr_cmd_caps caps;
656 struct mlx5dr_domain_cache {
657 struct mlx5dr_fw_recalc_cs_ft **recalc_cs_ft;
660 struct mlx5dr_domain {
661 struct mlx5dr_domain *peer_dmn;
662 struct mlx5_core_dev *mdev;
664 struct mlx5_uars_page *uar;
665 enum mlx5dr_domain_type type;
667 struct mlx5dr_icm_pool *ste_icm_pool;
668 struct mlx5dr_icm_pool *action_icm_pool;
669 struct mlx5dr_send_ring *send_ring;
670 struct mlx5dr_domain_info info;
671 struct mlx5dr_domain_cache cache;
674 struct mlx5dr_table_rx_tx {
675 struct mlx5dr_ste_htbl *s_anchor;
676 struct mlx5dr_domain_rx_tx *nic_dmn;
677 u64 default_icm_addr;
680 struct mlx5dr_table {
681 struct mlx5dr_domain *dmn;
682 struct mlx5dr_table_rx_tx rx;
683 struct mlx5dr_table_rx_tx tx;
688 struct list_head matcher_list;
689 struct mlx5dr_action *miss_action;
693 struct mlx5dr_matcher_rx_tx {
694 struct mlx5dr_ste_htbl *s_htbl;
695 struct mlx5dr_ste_htbl *e_anchor;
696 struct mlx5dr_ste_build *ste_builder;
697 struct mlx5dr_ste_build ste_builder_arr[DR_RULE_IPV_MAX]
701 u8 num_of_builders_arr[DR_RULE_IPV_MAX][DR_RULE_IPV_MAX];
702 u64 default_icm_addr;
703 struct mlx5dr_table_rx_tx *nic_tbl;
706 struct mlx5dr_matcher {
707 struct mlx5dr_table *tbl;
708 struct mlx5dr_matcher_rx_tx rx;
709 struct mlx5dr_matcher_rx_tx tx;
710 struct list_head matcher_list;
712 struct mlx5dr_match_param mask;
715 struct mlx5dv_flow_matcher *dv_matcher;
718 struct mlx5dr_rule_member {
719 struct mlx5dr_ste *ste;
720 /* attached to mlx5dr_rule via this */
721 struct list_head list;
722 /* attached to mlx5dr_ste via this */
723 struct list_head use_ste_list;
726 struct mlx5dr_action {
727 enum mlx5dr_action_type action_type;
731 struct mlx5dr_domain *dmn;
732 struct mlx5dr_icm_chunk *chunk;
742 struct mlx5dr_domain *dmn;
749 struct mlx5dr_table *tbl;
751 struct mlx5dr_domain *dmn;
754 enum fs_flow_table_type type;
757 struct mlx5dr_action **ref_actions;
758 u32 num_of_ref_actions;
767 struct mlx5dr_domain *dmn;
768 struct mlx5dr_cmd_vport_cap *caps;
771 u32 vlan_hdr; /* tpid_pcp_dei_vid */
777 enum mlx5dr_connect_type {
782 struct mlx5dr_htbl_connect_info {
783 enum mlx5dr_connect_type type;
785 struct mlx5dr_ste_htbl *hit_next_htbl;
790 struct mlx5dr_rule_rx_tx {
791 struct list_head rule_members_list;
792 struct mlx5dr_matcher_rx_tx *nic_matcher;
796 struct mlx5dr_matcher *matcher;
797 struct mlx5dr_rule_rx_tx rx;
798 struct mlx5dr_rule_rx_tx tx;
799 struct list_head rule_actions_list;
802 void mlx5dr_rule_update_rule_member(struct mlx5dr_ste *new_ste,
803 struct mlx5dr_ste *ste);
805 struct mlx5dr_icm_chunk {
806 struct mlx5dr_icm_bucket *bucket;
807 struct list_head chunk_list;
814 /* Memory optimisation */
815 struct mlx5dr_ste *ste_arr;
817 struct list_head *miss_list;
820 static inline void mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx *nic_dmn)
822 mutex_lock(&nic_dmn->mutex);
825 static inline void mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx *nic_dmn)
827 mutex_unlock(&nic_dmn->mutex);
830 static inline void mlx5dr_domain_lock(struct mlx5dr_domain *dmn)
832 mlx5dr_domain_nic_lock(&dmn->info.rx);
833 mlx5dr_domain_nic_lock(&dmn->info.tx);
836 static inline void mlx5dr_domain_unlock(struct mlx5dr_domain *dmn)
838 mlx5dr_domain_nic_unlock(&dmn->info.tx);
839 mlx5dr_domain_nic_unlock(&dmn->info.rx);
843 mlx5dr_matcher_supp_flex_parser_icmp_v4(struct mlx5dr_cmd_caps *caps)
845 return caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V4_ENABLED;
849 mlx5dr_matcher_supp_flex_parser_icmp_v6(struct mlx5dr_cmd_caps *caps)
851 return caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V6_ENABLED;
854 int mlx5dr_matcher_select_builders(struct mlx5dr_matcher *matcher,
855 struct mlx5dr_matcher_rx_tx *nic_matcher,
856 enum mlx5dr_ipv outer_ipv,
857 enum mlx5dr_ipv inner_ipv);
860 mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size)
862 return 1 << chunk_size;
866 mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size,
867 enum mlx5dr_icm_type icm_type)
872 if (icm_type == DR_ICM_TYPE_STE)
873 entry_size = DR_STE_SIZE;
875 entry_size = DR_MODIFY_ACTION_SIZE;
877 num_of_entries = mlx5dr_icm_pool_chunk_size_to_entries(chunk_size);
879 return entry_size * num_of_entries;
882 static inline struct mlx5dr_cmd_vport_cap *
883 mlx5dr_get_vport_cap(struct mlx5dr_cmd_caps *caps, u32 vport)
885 if (!caps->vports_caps ||
886 (vport >= caps->num_vports && vport != WIRE_PORT))
889 if (vport == WIRE_PORT)
890 vport = caps->num_vports;
892 return &caps->vports_caps[vport];
895 struct mlx5dr_cmd_query_flow_table_details {
898 u64 sw_owner_icm_root_1;
899 u64 sw_owner_icm_root_0;
902 struct mlx5dr_cmd_create_flow_table_attr {
913 /* internal API functions */
914 int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev,
915 struct mlx5dr_cmd_caps *caps);
916 int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev,
917 bool other_vport, u16 vport_number,
919 u64 *icm_address_tx);
920 int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev,
921 bool other_vport, u16 vport_number, u16 *gvmi);
922 int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev,
923 struct mlx5dr_esw_caps *caps);
924 int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev);
925 int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev,
929 u32 modify_header_id,
931 int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev,
934 int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev,
938 u32 *modify_header_id);
939 int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev,
940 u32 modify_header_id);
941 int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev,
945 int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev,
949 int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev,
950 struct mlx5dr_cmd_create_flow_table_attr *attr,
951 u64 *fdb_rx_icm_addr,
953 int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev,
956 int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev,
957 enum fs_flow_table_type type,
959 struct mlx5dr_cmd_query_flow_table_details *output);
960 int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev,
961 enum mlx5_reformat_ctx_type rt,
962 size_t reformat_size,
965 void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev,
968 struct mlx5dr_cmd_gid_attr {
974 struct mlx5dr_cmd_qp_create_attr {
987 int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num,
988 u16 index, struct mlx5dr_cmd_gid_attr *attr);
990 struct mlx5dr_icm_pool *mlx5dr_icm_pool_create(struct mlx5dr_domain *dmn,
991 enum mlx5dr_icm_type icm_type);
992 void mlx5dr_icm_pool_destroy(struct mlx5dr_icm_pool *pool);
994 struct mlx5dr_icm_chunk *
995 mlx5dr_icm_alloc_chunk(struct mlx5dr_icm_pool *pool,
996 enum mlx5dr_icm_chunk_size chunk_size);
997 void mlx5dr_icm_free_chunk(struct mlx5dr_icm_chunk *chunk);
998 int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn,
999 struct mlx5dr_domain_rx_tx *nic_dmn,
1000 struct mlx5dr_ste_htbl *htbl,
1001 struct mlx5dr_htbl_connect_info *connect_info,
1002 bool update_hw_ste);
1003 void mlx5dr_ste_set_formatted_ste(u16 gvmi,
1004 struct mlx5dr_domain_rx_tx *nic_dmn,
1005 struct mlx5dr_ste_htbl *htbl,
1007 struct mlx5dr_htbl_connect_info *connect_info);
1008 void mlx5dr_ste_copy_param(u8 match_criteria,
1009 struct mlx5dr_match_param *set_param,
1010 struct mlx5dr_match_parameters *mask);
1013 struct mlx5_core_dev *mdev;
1014 struct mlx5_wq_qp wq;
1015 struct mlx5_uars_page *uar;
1016 struct mlx5_wq_ctrl wq_ctrl;
1022 unsigned int *wqe_head;
1023 unsigned int wqe_cnt;
1029 unsigned int wqe_cnt;
1031 int max_inline_data;
1035 struct mlx5_core_dev *mdev;
1036 struct mlx5_cqwq wq;
1037 struct mlx5_wq_ctrl wq_ctrl;
1038 struct mlx5_core_cq mcq;
1039 struct mlx5dr_qp *qp;
1043 struct mlx5_core_dev *mdev;
1044 struct mlx5_core_mkey mkey;
1045 dma_addr_t dma_addr;
1050 #define MAX_SEND_CQE 64
1051 #define MIN_READ_SYNC 64
1053 struct mlx5dr_send_ring {
1054 struct mlx5dr_cq *cq;
1055 struct mlx5dr_qp *qp;
1056 struct mlx5dr_mr *mr;
1057 /* How much wqes are waiting for completion */
1059 /* Signal request per this trash hold value */
1061 /* Each post_send_size less than max_post_send_size */
1062 u32 max_post_send_size;
1063 /* manage the send queue */
1067 struct ib_wc wc[MAX_SEND_CQE];
1068 u8 sync_buff[MIN_READ_SYNC];
1069 struct mlx5dr_mr *sync_mr;
1070 spinlock_t lock; /* Protect the data path of the send ring */
1073 int mlx5dr_send_ring_alloc(struct mlx5dr_domain *dmn);
1074 void mlx5dr_send_ring_free(struct mlx5dr_domain *dmn,
1075 struct mlx5dr_send_ring *send_ring);
1076 int mlx5dr_send_ring_force_drain(struct mlx5dr_domain *dmn);
1077 int mlx5dr_send_postsend_ste(struct mlx5dr_domain *dmn,
1078 struct mlx5dr_ste *ste,
1082 int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn,
1083 struct mlx5dr_ste_htbl *htbl,
1084 u8 *formatted_ste, u8 *mask);
1085 int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn,
1086 struct mlx5dr_ste_htbl *htbl,
1088 bool update_hw_ste);
1089 int mlx5dr_send_postsend_action(struct mlx5dr_domain *dmn,
1090 struct mlx5dr_action *action);
1092 struct mlx5dr_cmd_ft_info {
1095 enum fs_flow_table_type type;
1098 struct mlx5dr_cmd_flow_destination_hw_info {
1099 enum mlx5_flow_destination_type type;
1114 struct mlx5dr_cmd_fte_info {
1117 struct mlx5_flow_context flow_context;
1119 struct mlx5_flow_act action;
1120 struct mlx5dr_cmd_flow_destination_hw_info *dest_arr;
1123 int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev,
1124 int opmod, int modify_mask,
1125 struct mlx5dr_cmd_ft_info *ft,
1127 struct mlx5dr_cmd_fte_info *fte);
1129 struct mlx5dr_fw_recalc_cs_ft {
1136 struct mlx5dr_fw_recalc_cs_ft *
1137 mlx5dr_fw_create_recalc_cs_ft(struct mlx5dr_domain *dmn, u32 vport_num);
1138 void mlx5dr_fw_destroy_recalc_cs_ft(struct mlx5dr_domain *dmn,
1139 struct mlx5dr_fw_recalc_cs_ft *recalc_cs_ft);
1140 int mlx5dr_domain_cache_get_recalc_cs_ft_addr(struct mlx5dr_domain *dmn,
1143 int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn,
1144 struct mlx5dr_cmd_flow_destination_hw_info *dest,
1149 void mlx5dr_fw_destroy_md_tbl(struct mlx5dr_domain *dmn, u32 tbl_id,
1151 #endif /* _DR_TYPES_H_ */