drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v2.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
   3
   4 #include "dr_ste_v1.h"
   5
   6 enum {
   7         DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_0              = 0x00,
   8         DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_1              = 0x01,
   9         DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_2              = 0x02,
  10         DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_0          = 0x08,
  11         DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_1          = 0x09,
  12         DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0              = 0x0e,
  13         DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0              = 0x18,
  14         DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_1              = 0x19,
  15         DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_0            = 0x40,
  16         DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_1            = 0x41,
  17         DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_0        = 0x44,
  18         DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_1        = 0x45,
  19         DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_2        = 0x46,
  20         DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_3        = 0x47,
  21         DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_0        = 0x4c,
  22         DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_1        = 0x4d,
  23         DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_2        = 0x4e,
  24         DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_3        = 0x4f,
  25         DR_STE_V2_ACTION_MDFY_FLD_TCP_MISC_0            = 0x5e,
  26         DR_STE_V2_ACTION_MDFY_FLD_TCP_MISC_1            = 0x5f,
  27         DR_STE_V2_ACTION_MDFY_FLD_CFG_HDR_0_0           = 0x6f,
  28         DR_STE_V2_ACTION_MDFY_FLD_CFG_HDR_0_1           = 0x70,
  29         DR_STE_V2_ACTION_MDFY_FLD_METADATA_2_CQE        = 0x7b,
  30         DR_STE_V2_ACTION_MDFY_FLD_GNRL_PURPOSE          = 0x7c,
  31         DR_STE_V2_ACTION_MDFY_FLD_REGISTER_2_0          = 0x90,
  32         DR_STE_V2_ACTION_MDFY_FLD_REGISTER_2_1          = 0x91,
  33         DR_STE_V2_ACTION_MDFY_FLD_REGISTER_1_0          = 0x92,
  34         DR_STE_V2_ACTION_MDFY_FLD_REGISTER_1_1          = 0x93,
  35         DR_STE_V2_ACTION_MDFY_FLD_REGISTER_0_0          = 0x94,
  36         DR_STE_V2_ACTION_MDFY_FLD_REGISTER_0_1          = 0x95,
  37 };
  38
  39 static const struct mlx5dr_ste_action_modify_field dr_ste_v2_action_modify_field_arr[] = {
  40         [MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16] = {
  41                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_0, .start = 0, .end = 31,
  42         },
  43         [MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0] = {
  44                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_1, .start = 16, .end = 31,
  45         },
  46         [MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE] = {
  47                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_1, .start = 0, .end = 15,
  48         },
  49         [MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16] = {
  50                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_0, .start = 0, .end = 31,
  51         },
  52         [MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0] = {
  53                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_1, .start = 16, .end = 31,
  54         },
  55         [MLX5_ACTION_IN_FIELD_OUT_IP_DSCP] = {
  56                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0, .start = 18, .end = 23,
  57         },
  58         [MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS] = {
  59                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_1, .start = 16, .end = 24,
  60                 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP,
  61         },
  62         [MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT] = {
  63                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0, .start = 16, .end = 31,
  64                 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP,
  65         },
  66         [MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT] = {
  67                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0, .start = 0, .end = 15,
  68                 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP,
  69         },
  70         [MLX5_ACTION_IN_FIELD_OUT_IP_TTL] = {
  71                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0, .start = 8, .end = 15,
  72                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4,
  73         },
  74         [MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT] = {
  75                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0, .start = 8, .end = 15,
  76                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
  77         },
  78         [MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT] = {
  79                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0, .start = 16, .end = 31,
  80                 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_UDP,
  81         },
  82         [MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT] = {
  83                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0, .start = 0, .end = 15,
  84                 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_UDP,
  85         },
  86         [MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96] = {
  87                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_0, .start = 0, .end = 31,
  88                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
  89         },
  90         [MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64] = {
  91                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_1, .start = 0, .end = 31,
  92                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
  93         },
  94         [MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32] = {
  95                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_2, .start = 0, .end = 31,
  96                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
  97         },
  98         [MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0] = {
  99                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_3, .start = 0, .end = 31,
 100                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 101         },
 102         [MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96] = {
 103                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_0, .start = 0, .end = 31,
 104                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 105         },
 106         [MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64] = {
 107                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_1, .start = 0, .end = 31,
 108                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 109         },
 110         [MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32] = {
 111                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_2, .start = 0, .end = 31,
 112                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 113         },
 114         [MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0] = {
 115                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_3, .start = 0, .end = 31,
 116                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 117         },
 118         [MLX5_ACTION_IN_FIELD_OUT_SIPV4] = {
 119                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_0, .start = 0, .end = 31,
 120                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4,
 121         },
 122         [MLX5_ACTION_IN_FIELD_OUT_DIPV4] = {
 123                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_1, .start = 0, .end = 31,
 124                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4,
 125         },
 126         [MLX5_ACTION_IN_FIELD_METADATA_REG_A] = {
 127                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_GNRL_PURPOSE, .start = 0, .end = 31,
 128         },
 129         [MLX5_ACTION_IN_FIELD_METADATA_REG_B] = {
 130                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_METADATA_2_CQE, .start = 0, .end = 31,
 131         },
 132         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_0] = {
 133                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_0_0, .start = 0, .end = 31,
 134         },
 135         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_1] = {
 136                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_0_1, .start = 0, .end = 31,
 137         },
 138         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_2] = {
 139                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_1_0, .start = 0, .end = 31,
 140         },
 141         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_3] = {
 142                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_1_1, .start = 0, .end = 31,
 143         },
 144         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_4] = {
 145                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_2_0, .start = 0, .end = 31,
 146         },
 147         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_5] = {
 148                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_2_1, .start = 0, .end = 31,
 149         },
 150         [MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM] = {
 151                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_TCP_MISC_0, .start = 0, .end = 31,
 152         },
 153         [MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM] = {
 154                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_TCP_MISC_1, .start = 0, .end = 31,
 155         },
 156         [MLX5_ACTION_IN_FIELD_OUT_FIRST_VID] = {
 157                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_2, .start = 0, .end = 15,
 158         },
 159         [MLX5_ACTION_IN_FIELD_OUT_EMD_31_0] = {
 160                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_CFG_HDR_0_1, .start = 0, .end = 31,
 161         },
 162         [MLX5_ACTION_IN_FIELD_OUT_EMD_47_32] = {
 163                 .hw_field = DR_STE_V2_ACTION_MDFY_FLD_CFG_HDR_0_0, .start = 0, .end = 15,
 164         },
 165 };
 166
 167 static struct mlx5dr_ste_ctx ste_ctx_v2 = {
 168         /* Builders */
 169         .build_eth_l2_src_dst_init      = &dr_ste_v1_build_eth_l2_src_dst_init,
 170         .build_eth_l3_ipv6_src_init     = &dr_ste_v1_build_eth_l3_ipv6_src_init,
 171         .build_eth_l3_ipv6_dst_init     = &dr_ste_v1_build_eth_l3_ipv6_dst_init,
 172         .build_eth_l3_ipv4_5_tuple_init = &dr_ste_v1_build_eth_l3_ipv4_5_tuple_init,
 173         .build_eth_l2_src_init          = &dr_ste_v1_build_eth_l2_src_init,
 174         .build_eth_l2_dst_init          = &dr_ste_v1_build_eth_l2_dst_init,
 175         .build_eth_l2_tnl_init          = &dr_ste_v1_build_eth_l2_tnl_init,
 176         .build_eth_l3_ipv4_misc_init    = &dr_ste_v1_build_eth_l3_ipv4_misc_init,
 177         .build_eth_ipv6_l3_l4_init      = &dr_ste_v1_build_eth_ipv6_l3_l4_init,
 178         .build_mpls_init                = &dr_ste_v1_build_mpls_init,
 179         .build_tnl_gre_init             = &dr_ste_v1_build_tnl_gre_init,
 180         .build_tnl_mpls_init            = &dr_ste_v1_build_tnl_mpls_init,
 181         .build_tnl_mpls_over_udp_init   = &dr_ste_v1_build_tnl_mpls_over_udp_init,
 182         .build_tnl_mpls_over_gre_init   = &dr_ste_v1_build_tnl_mpls_over_gre_init,
 183         .build_icmp_init                = &dr_ste_v1_build_icmp_init,
 184         .build_general_purpose_init     = &dr_ste_v1_build_general_purpose_init,
 185         .build_eth_l4_misc_init         = &dr_ste_v1_build_eth_l4_misc_init,
 186         .build_tnl_vxlan_gpe_init       = &dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init,
 187         .build_tnl_geneve_init          = &dr_ste_v1_build_flex_parser_tnl_geneve_init,
 188         .build_tnl_geneve_tlv_opt_init  = &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init,
 189         .build_tnl_geneve_tlv_opt_exist_init =
 190                                   &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init,
 191         .build_register_0_init          = &dr_ste_v1_build_register_0_init,
 192         .build_register_1_init          = &dr_ste_v1_build_register_1_init,
 193         .build_src_gvmi_qpn_init        = &dr_ste_v1_build_src_gvmi_qpn_init,
 194         .build_flex_parser_0_init       = &dr_ste_v1_build_flex_parser_0_init,
 195         .build_flex_parser_1_init       = &dr_ste_v1_build_flex_parser_1_init,
 196         .build_tnl_gtpu_init            = &dr_ste_v1_build_flex_parser_tnl_gtpu_init,
 197         .build_tnl_header_0_1_init      = &dr_ste_v1_build_tnl_header_0_1_init,
 198         .build_tnl_gtpu_flex_parser_0_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_0_init,
 199         .build_tnl_gtpu_flex_parser_1_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_1_init,
 200
 201         /* Getters and Setters */
 202         .ste_init                       = &dr_ste_v1_init,
 203         .set_next_lu_type               = &dr_ste_v1_set_next_lu_type,
 204         .get_next_lu_type               = &dr_ste_v1_get_next_lu_type,
 205         .is_miss_addr_set               = &dr_ste_v1_is_miss_addr_set,
 206         .set_miss_addr                  = &dr_ste_v1_set_miss_addr,
 207         .get_miss_addr                  = &dr_ste_v1_get_miss_addr,
 208         .set_hit_addr                   = &dr_ste_v1_set_hit_addr,
 209         .set_byte_mask                  = &dr_ste_v1_set_byte_mask,
 210         .get_byte_mask                  = &dr_ste_v1_get_byte_mask,
 211
 212         /* Actions */
 213         .actions_caps                   = DR_STE_CTX_ACTION_CAP_TX_POP |
 214                                           DR_STE_CTX_ACTION_CAP_RX_PUSH |
 215                                           DR_STE_CTX_ACTION_CAP_RX_ENCAP,
 216         .set_actions_rx                 = &dr_ste_v1_set_actions_rx,
 217         .set_actions_tx                 = &dr_ste_v1_set_actions_tx,
 218         .modify_field_arr_sz            = ARRAY_SIZE(dr_ste_v2_action_modify_field_arr),
 219         .modify_field_arr               = dr_ste_v2_action_modify_field_arr,
 220         .set_action_set                 = &dr_ste_v1_set_action_set,
 221         .set_action_add                 = &dr_ste_v1_set_action_add,
 222         .set_action_copy                = &dr_ste_v1_set_action_copy,
 223         .set_action_decap_l3_list       = &dr_ste_v1_set_action_decap_l3_list,
 224         .alloc_modify_hdr_chunk         = &dr_ste_v1_alloc_modify_hdr_ptrn_arg,
 225         .dealloc_modify_hdr_chunk       = &dr_ste_v1_free_modify_hdr_ptrn_arg,
 226
 227         /* Send */
 228         .prepare_for_postsend           = &dr_ste_v1_prepare_for_postsend,
 229 };
 230
 231 struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v2(void)
 232 {
 233         return &ste_ctx_v2;
 234 }