drivers/net/ethernet/mellanox/mlx5/core/rl.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/mlx5/driver.h>
  36 #include <linux/mlx5/cmd.h>
  37 #include "mlx5_core.h"
  38
  39 /* Scheduling element fw management */
  40 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
  41                                        void *ctx, u32 *element_id)
  42 {
  43         u32 in[MLX5_ST_SZ_DW(create_scheduling_element_in)]  = {0};
  44         u32 out[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {0};
  45         void *schedc;
  46         int err;
  47
  48         schedc = MLX5_ADDR_OF(create_scheduling_element_in, in,
  49                               scheduling_context);
  50         MLX5_SET(create_scheduling_element_in, in, opcode,
  51                  MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT);
  52         MLX5_SET(create_scheduling_element_in, in, scheduling_hierarchy,
  53                  hierarchy);
  54         memcpy(schedc, ctx, MLX5_ST_SZ_BYTES(scheduling_context));
  55
  56         err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
  57         if (err)
  58                 return err;
  59
  60         *element_id = MLX5_GET(create_scheduling_element_out, out,
  61                                scheduling_element_id);
  62         return 0;
  63 }
  64
  65 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
  66                                        void *ctx, u32 element_id,
  67                                        u32 modify_bitmask)
  68 {
  69         u32 in[MLX5_ST_SZ_DW(modify_scheduling_element_in)]  = {0};
  70         u32 out[MLX5_ST_SZ_DW(modify_scheduling_element_in)] = {0};
  71         void *schedc;
  72
  73         schedc = MLX5_ADDR_OF(modify_scheduling_element_in, in,
  74                               scheduling_context);
  75         MLX5_SET(modify_scheduling_element_in, in, opcode,
  76                  MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT);
  77         MLX5_SET(modify_scheduling_element_in, in, scheduling_element_id,
  78                  element_id);
  79         MLX5_SET(modify_scheduling_element_in, in, modify_bitmask,
  80                  modify_bitmask);
  81         MLX5_SET(modify_scheduling_element_in, in, scheduling_hierarchy,
  82                  hierarchy);
  83         memcpy(schedc, ctx, MLX5_ST_SZ_BYTES(scheduling_context));
  84
  85         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
  86 }
  87
  88 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
  89                                         u32 element_id)
  90 {
  91         u32 in[MLX5_ST_SZ_DW(destroy_scheduling_element_in)]  = {0};
  92         u32 out[MLX5_ST_SZ_DW(destroy_scheduling_element_in)] = {0};
  93
  94         MLX5_SET(destroy_scheduling_element_in, in, opcode,
  95                  MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT);
  96         MLX5_SET(destroy_scheduling_element_in, in, scheduling_element_id,
  97                  element_id);
  98         MLX5_SET(destroy_scheduling_element_in, in, scheduling_hierarchy,
  99                  hierarchy);
 100
 101         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 102 }
 103
 104 static bool mlx5_rl_are_equal_raw(struct mlx5_rl_entry *entry, void *rl_in,
 105                                   u16 uid)
 106 {
 107         return (!memcmp(entry->rl_raw, rl_in, sizeof(entry->rl_raw)) &&
 108                 entry->uid == uid);
 109 }
 110
 111 /* Finds an entry where we can register the given rate
 112  * If the rate already exists, return the entry where it is registered,
 113  * otherwise return the first available entry.
 114  * If the table is full, return NULL
 115  */
 116 static struct mlx5_rl_entry *find_rl_entry(struct mlx5_rl_table *table,
 117                                            void *rl_in, u16 uid, bool dedicated)
 118 {
 119         struct mlx5_rl_entry *ret_entry = NULL;
 120         bool empty_found = false;
 121         int i;
 122
 123         for (i = 0; i < table->max_size; i++) {
 124                 if (dedicated) {
 125                         if (!table->rl_entry[i].refcount)
 126                                 return &table->rl_entry[i];
 127                         continue;
 128                 }
 129
 130                 if (table->rl_entry[i].refcount) {
 131                         if (table->rl_entry[i].dedicated)
 132                                 continue;
 133                         if (mlx5_rl_are_equal_raw(&table->rl_entry[i], rl_in,
 134                                                   uid))
 135                                 return &table->rl_entry[i];
 136                 } else if (!empty_found) {
 137                         empty_found = true;
 138                         ret_entry = &table->rl_entry[i];
 139                 }
 140         }
 141
 142         return ret_entry;
 143 }
 144
 145 static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev *dev,
 146                                       struct mlx5_rl_entry *entry, bool set)
 147 {
 148         u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)]   = {};
 149         u32 out[MLX5_ST_SZ_DW(set_pp_rate_limit_out)] = {};
 150         void *pp_context;
 151
 152         pp_context = MLX5_ADDR_OF(set_pp_rate_limit_in, in, ctx);
 153         MLX5_SET(set_pp_rate_limit_in, in, opcode,
 154                  MLX5_CMD_OP_SET_PP_RATE_LIMIT);
 155         MLX5_SET(set_pp_rate_limit_in, in, uid, entry->uid);
 156         MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, entry->index);
 157         if (set)
 158                 memcpy(pp_context, entry->rl_raw, sizeof(entry->rl_raw));
 159         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 160 }
 161
 162 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate)
 163 {
 164         struct mlx5_rl_table *table = &dev->priv.rl_table;
 165
 166         return (rate <= table->max_rate && rate >= table->min_rate);
 167 }
 168 EXPORT_SYMBOL(mlx5_rl_is_in_range);
 169
 170 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
 171                        struct mlx5_rate_limit *rl_1)
 172 {
 173         return ((rl_0->rate == rl_1->rate) &&
 174                 (rl_0->max_burst_sz == rl_1->max_burst_sz) &&
 175                 (rl_0->typical_pkt_sz == rl_1->typical_pkt_sz));
 176 }
 177 EXPORT_SYMBOL(mlx5_rl_are_equal);
 178
 179 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
 180                          bool dedicated_entry, u16 *index)
 181 {
 182         struct mlx5_rl_table *table = &dev->priv.rl_table;
 183         struct mlx5_rl_entry *entry;
 184         int err = 0;
 185         u32 rate;
 186
 187         rate = MLX5_GET(set_pp_rate_limit_context, rl_in, rate_limit);
 188         mutex_lock(&table->rl_lock);
 189
 190         if (!rate || !mlx5_rl_is_in_range(dev, rate)) {
 191                 mlx5_core_err(dev, "Invalid rate: %u, should be %u to %u\n",
 192                               rate, table->min_rate, table->max_rate);
 193                 err = -EINVAL;
 194                 goto out;
 195         }
 196
 197         entry = find_rl_entry(table, rl_in, uid, dedicated_entry);
 198         if (!entry) {
 199                 mlx5_core_err(dev, "Max number of %u rates reached\n",
 200                               table->max_size);
 201                 err = -ENOSPC;
 202                 goto out;
 203         }
 204         if (entry->refcount) {
 205                 /* rate already configured */
 206                 entry->refcount++;
 207         } else {
 208                 memcpy(entry->rl_raw, rl_in, sizeof(entry->rl_raw));
 209                 entry->uid = uid;
 210                 /* new rate limit */
 211                 err = mlx5_set_pp_rate_limit_cmd(dev, entry, true);
 212                 if (err) {
 213                         mlx5_core_err(
 214                                 dev,
 215                                 "Failed configuring rate limit(err %d): rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
 216                                 err, rate,
 217                                 MLX5_GET(set_pp_rate_limit_context, rl_in,
 218                                          burst_upper_bound),
 219                                 MLX5_GET(set_pp_rate_limit_context, rl_in,
 220                                          typical_packet_size));
 221                         goto out;
 222                 }
 223
 224                 entry->refcount = 1;
 225                 entry->dedicated = dedicated_entry;
 226         }
 227         *index = entry->index;
 228
 229 out:
 230         mutex_unlock(&table->rl_lock);
 231         return err;
 232 }
 233 EXPORT_SYMBOL(mlx5_rl_add_rate_raw);
 234
 235 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index)
 236 {
 237         struct mlx5_rl_table *table = &dev->priv.rl_table;
 238         struct mlx5_rl_entry *entry;
 239
 240         mutex_lock(&table->rl_lock);
 241         entry = &table->rl_entry[index - 1];
 242         entry->refcount--;
 243         if (!entry->refcount)
 244                 /* need to remove rate */
 245                 mlx5_set_pp_rate_limit_cmd(dev, entry, false);
 246         mutex_unlock(&table->rl_lock);
 247 }
 248 EXPORT_SYMBOL(mlx5_rl_remove_rate_raw);
 249
 250 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
 251                      struct mlx5_rate_limit *rl)
 252 {
 253         u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {};
 254
 255         MLX5_SET(set_pp_rate_limit_context, rl_raw, rate_limit, rl->rate);
 256         MLX5_SET(set_pp_rate_limit_context, rl_raw, burst_upper_bound,
 257                  rl->max_burst_sz);
 258         MLX5_SET(set_pp_rate_limit_context, rl_raw, typical_packet_size,
 259                  rl->typical_pkt_sz);
 260
 261         return mlx5_rl_add_rate_raw(dev, rl_raw,
 262                                     MLX5_CAP_QOS(dev, packet_pacing_uid) ?
 263                                         MLX5_SHARED_RESOURCE_UID : 0,
 264                                     false, index);
 265 }
 266 EXPORT_SYMBOL(mlx5_rl_add_rate);
 267
 268 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl)
 269 {
 270         u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {};
 271         struct mlx5_rl_table *table = &dev->priv.rl_table;
 272         struct mlx5_rl_entry *entry = NULL;
 273
 274         /* 0 is a reserved value for unlimited rate */
 275         if (rl->rate == 0)
 276                 return;
 277
 278         MLX5_SET(set_pp_rate_limit_context, rl_raw, rate_limit, rl->rate);
 279         MLX5_SET(set_pp_rate_limit_context, rl_raw, burst_upper_bound,
 280                  rl->max_burst_sz);
 281         MLX5_SET(set_pp_rate_limit_context, rl_raw, typical_packet_size,
 282                  rl->typical_pkt_sz);
 283
 284         mutex_lock(&table->rl_lock);
 285         entry = find_rl_entry(table, rl_raw,
 286                               MLX5_CAP_QOS(dev, packet_pacing_uid) ?
 287                                 MLX5_SHARED_RESOURCE_UID : 0, false);
 288         if (!entry || !entry->refcount) {
 289                 mlx5_core_warn(dev, "Rate %u, max_burst_sz %u typical_pkt_sz %u are not configured\n",
 290                                rl->rate, rl->max_burst_sz, rl->typical_pkt_sz);
 291                 goto out;
 292         }
 293
 294         entry->refcount--;
 295         if (!entry->refcount)
 296                 /* need to remove rate */
 297                 mlx5_set_pp_rate_limit_cmd(dev, entry, false);
 298
 299 out:
 300         mutex_unlock(&table->rl_lock);
 301 }
 302 EXPORT_SYMBOL(mlx5_rl_remove_rate);
 303
 304 int mlx5_init_rl_table(struct mlx5_core_dev *dev)
 305 {
 306         struct mlx5_rl_table *table = &dev->priv.rl_table;
 307         int i;
 308
 309         mutex_init(&table->rl_lock);
 310         if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, packet_pacing)) {
 311                 table->max_size = 0;
 312                 return 0;
 313         }
 314
 315         /* First entry is reserved for unlimited rate */
 316         table->max_size = MLX5_CAP_QOS(dev, packet_pacing_rate_table_size) - 1;
 317         table->max_rate = MLX5_CAP_QOS(dev, packet_pacing_max_rate);
 318         table->min_rate = MLX5_CAP_QOS(dev, packet_pacing_min_rate);
 319
 320         table->rl_entry = kcalloc(table->max_size, sizeof(struct mlx5_rl_entry),
 321                                   GFP_KERNEL);
 322         if (!table->rl_entry)
 323                 return -ENOMEM;
 324
 325         /* The index represents the index in HW rate limit table
 326          * Index 0 is reserved for unlimited rate
 327          */
 328         for (i = 0; i < table->max_size; i++)
 329                 table->rl_entry[i].index = i + 1;
 330
 331         /* Index 0 is reserved */
 332         mlx5_core_info(dev, "Rate limit: %u rates are supported, range: %uMbps to %uMbps\n",
 333                        table->max_size,
 334                        table->min_rate >> 10,
 335                        table->max_rate >> 10);
 336
 337         return 0;
 338 }
 339
 340 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev)
 341 {
 342         struct mlx5_rl_table *table = &dev->priv.rl_table;
 343         int i;
 344
 345         /* Clear all configured rates */
 346         for (i = 0; i < table->max_size; i++)
 347                 if (table->rl_entry[i].refcount)
 348                         mlx5_set_pp_rate_limit_cmd(dev, &table->rl_entry[i],
 349                                                    false);
 350
 351         kfree(dev->priv.rl_table.rl_entry);
 352 }