2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/mlx5/port.h>
34 #include "mlx5_core.h"
36 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
37 int size_in, void *data_out, int size_out,
38 u16 reg_id, int arg, int write)
40 int outlen = MLX5_ST_SZ_BYTES(access_register_out) + size_out;
41 int inlen = MLX5_ST_SZ_BYTES(access_register_in) + size_in;
47 in = kvzalloc(inlen, GFP_KERNEL);
48 out = kvzalloc(outlen, GFP_KERNEL);
52 data = MLX5_ADDR_OF(access_register_in, in, register_data);
53 memcpy(data, data_in, size_in);
55 MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG);
56 MLX5_SET(access_register_in, in, op_mod, !write);
57 MLX5_SET(access_register_in, in, argument, arg);
58 MLX5_SET(access_register_in, in, register_id, reg_id);
60 err = mlx5_cmd_exec(dev, in, inlen, out, outlen);
64 data = MLX5_ADDR_OF(access_register_out, out, register_data);
65 memcpy(data_out, data, size_out);
72 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
74 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
77 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0};
78 int sz = MLX5_ST_SZ_BYTES(pcam_reg);
80 MLX5_SET(pcam_reg, in, feature_group, feature_group);
81 MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group);
83 return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0);
86 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group,
89 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0};
90 int sz = MLX5_ST_SZ_BYTES(mcam_reg);
92 MLX5_SET(mcam_reg, in, feature_group, feature_group);
93 MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group);
95 return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
98 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
99 u8 feature_group, u8 access_reg_group)
101 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
102 int sz = MLX5_ST_SZ_BYTES(qcam_reg);
104 MLX5_SET(qcam_reg, in, feature_group, feature_group);
105 MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);
107 return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);
110 struct mlx5_reg_pcap {
120 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
122 struct mlx5_reg_pcap in;
123 struct mlx5_reg_pcap out;
125 memset(&in, 0, sizeof(in));
126 in.caps_127_96 = cpu_to_be32(caps);
127 in.port_num = port_num;
129 return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
130 sizeof(out), MLX5_REG_PCAP, 0, 1);
132 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
134 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
135 int ptys_size, int proto_mask, u8 local_port)
137 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
139 MLX5_SET(ptys_reg, in, local_port, local_port);
140 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
141 return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
142 ptys_size, MLX5_REG_PTYS, 0, 0);
144 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
146 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
148 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0};
149 u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
151 MLX5_SET(mlcr_reg, in, local_port, 1);
152 MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
153 return mlx5_core_access_reg(dev, in, sizeof(in), out,
154 sizeof(out), MLX5_REG_MLCR, 0, 1);
157 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
158 u8 *link_width_oper, u8 local_port)
160 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
163 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
167 *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
171 EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
173 int mlx5_query_port_ib_proto_oper(struct mlx5_core_dev *dev,
174 u8 *proto_oper, u8 local_port)
176 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
179 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB,
184 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
188 EXPORT_SYMBOL(mlx5_query_port_ib_proto_oper);
190 /* This function should be used after setting a port register only */
191 void mlx5_toggle_port_link(struct mlx5_core_dev *dev)
193 enum mlx5_port_status ps;
195 mlx5_query_port_admin_status(dev, &ps);
196 mlx5_set_port_admin_status(dev, MLX5_PORT_DOWN);
197 if (ps == MLX5_PORT_UP)
198 mlx5_set_port_admin_status(dev, MLX5_PORT_UP);
200 EXPORT_SYMBOL_GPL(mlx5_toggle_port_link);
202 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
203 enum mlx5_port_status status)
205 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
206 u32 out[MLX5_ST_SZ_DW(paos_reg)];
208 MLX5_SET(paos_reg, in, local_port, 1);
209 MLX5_SET(paos_reg, in, admin_status, status);
210 MLX5_SET(paos_reg, in, ase, 1);
211 return mlx5_core_access_reg(dev, in, sizeof(in), out,
212 sizeof(out), MLX5_REG_PAOS, 0, 1);
214 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
216 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
217 enum mlx5_port_status *status)
219 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
220 u32 out[MLX5_ST_SZ_DW(paos_reg)];
223 MLX5_SET(paos_reg, in, local_port, 1);
224 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
225 sizeof(out), MLX5_REG_PAOS, 0, 0);
228 *status = MLX5_GET(paos_reg, out, admin_status);
231 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
233 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu,
234 u16 *max_mtu, u16 *oper_mtu, u8 port)
236 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
237 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
239 MLX5_SET(pmtu_reg, in, local_port, port);
240 mlx5_core_access_reg(dev, in, sizeof(in), out,
241 sizeof(out), MLX5_REG_PMTU, 0, 0);
244 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
246 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
248 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
251 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
253 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
254 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
256 MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
257 MLX5_SET(pmtu_reg, in, local_port, port);
258 return mlx5_core_access_reg(dev, in, sizeof(in), out,
259 sizeof(out), MLX5_REG_PMTU, 0, 1);
261 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
263 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu,
266 mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
268 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
270 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
273 mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
275 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
277 static int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
279 u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
280 u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
284 MLX5_SET(pmlp_reg, in, local_port, 1);
285 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
286 MLX5_REG_PMLP, 0, 0);
290 module_mapping = MLX5_GET(pmlp_reg, out, lane0_module_mapping);
291 *module_num = module_mapping & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
296 static int mlx5_eeprom_page(int offset)
298 if (offset < MLX5_EEPROM_PAGE_LENGTH)
299 /* Addresses between 0-255 - page 00 */
302 /* Addresses between 256 - 639 belongs to pages 01, 02 and 03
303 * For example, offset = 400 belongs to page 02:
304 * 1 + ((400 - 256)/128) = 2
306 return 1 + ((offset - MLX5_EEPROM_PAGE_LENGTH) /
307 MLX5_EEPROM_HIGH_PAGE_LENGTH);
310 static int mlx5_eeprom_high_page_offset(int page_num)
312 if (!page_num) /* Page 0 always start from low page */
316 return page_num * MLX5_EEPROM_HIGH_PAGE_LENGTH;
319 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
320 u16 offset, u16 size, u8 *data)
322 int module_num, page_num, status, err;
323 u32 out[MLX5_ST_SZ_DW(mcia_reg)];
324 u32 in[MLX5_ST_SZ_DW(mcia_reg)];
326 void *ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
328 err = mlx5_query_module_num(dev, &module_num);
332 memset(in, 0, sizeof(in));
333 size = min_t(int, size, MLX5_EEPROM_MAX_BYTES);
335 /* Get the page number related to the given offset */
336 page_num = mlx5_eeprom_page(offset);
338 /* Set the right offset according to the page number,
339 * For page_num > 0, relative offset is always >= 128 (high page).
341 offset -= mlx5_eeprom_high_page_offset(page_num);
343 if (offset + size > MLX5_EEPROM_PAGE_LENGTH)
344 /* Cross pages read, read until offset 256 in low page */
345 size -= offset + size - MLX5_EEPROM_PAGE_LENGTH;
347 i2c_addr = MLX5_I2C_ADDR_LOW;
349 MLX5_SET(mcia_reg, in, l, 0);
350 MLX5_SET(mcia_reg, in, module, module_num);
351 MLX5_SET(mcia_reg, in, i2c_device_address, i2c_addr);
352 MLX5_SET(mcia_reg, in, page_number, page_num);
353 MLX5_SET(mcia_reg, in, device_address, offset);
354 MLX5_SET(mcia_reg, in, size, size);
356 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
357 sizeof(out), MLX5_REG_MCIA, 0, 0);
361 status = MLX5_GET(mcia_reg, out, status);
363 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
368 memcpy(data, ptr, size);
372 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom);
374 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
375 int pvlc_size, u8 local_port)
377 u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0};
379 MLX5_SET(pvlc_reg, in, local_port, local_port);
380 return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
381 pvlc_size, MLX5_REG_PVLC, 0, 0);
384 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
385 u8 *vl_hw_cap, u8 local_port)
387 u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
390 err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
394 *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
398 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
400 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
401 u8 port_num, void *out, size_t sz)
406 in = kvzalloc(sz, GFP_KERNEL);
412 MLX5_SET(ppcnt_reg, in, local_port, port_num);
414 MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
415 err = mlx5_core_access_reg(dev, in, sz, out,
416 sz, MLX5_REG_PPCNT, 0, 0);
421 EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
423 static int mlx5_query_pfcc_reg(struct mlx5_core_dev *dev, u32 *out,
426 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
428 MLX5_SET(pfcc_reg, in, local_port, 1);
430 return mlx5_core_access_reg(dev, in, sizeof(in), out,
431 out_size, MLX5_REG_PFCC, 0, 0);
434 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
436 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
437 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
439 MLX5_SET(pfcc_reg, in, local_port, 1);
440 MLX5_SET(pfcc_reg, in, pptx, tx_pause);
441 MLX5_SET(pfcc_reg, in, pprx, rx_pause);
443 return mlx5_core_access_reg(dev, in, sizeof(in), out,
444 sizeof(out), MLX5_REG_PFCC, 0, 1);
446 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
448 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
449 u32 *rx_pause, u32 *tx_pause)
451 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
454 err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
459 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
462 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
466 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
468 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
469 u16 stall_critical_watermark,
470 u16 stall_minor_watermark)
472 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
473 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
475 MLX5_SET(pfcc_reg, in, local_port, 1);
476 MLX5_SET(pfcc_reg, in, pptx_mask_n, 1);
477 MLX5_SET(pfcc_reg, in, pprx_mask_n, 1);
478 MLX5_SET(pfcc_reg, in, ppan_mask_n, 1);
479 MLX5_SET(pfcc_reg, in, critical_stall_mask, 1);
480 MLX5_SET(pfcc_reg, in, minor_stall_mask, 1);
481 MLX5_SET(pfcc_reg, in, device_stall_critical_watermark,
482 stall_critical_watermark);
483 MLX5_SET(pfcc_reg, in, device_stall_minor_watermark, stall_minor_watermark);
485 return mlx5_core_access_reg(dev, in, sizeof(in), out,
486 sizeof(out), MLX5_REG_PFCC, 0, 1);
489 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
490 u16 *stall_critical_watermark,
491 u16 *stall_minor_watermark)
493 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
496 err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
500 if (stall_critical_watermark)
501 *stall_critical_watermark = MLX5_GET(pfcc_reg, out,
502 device_stall_critical_watermark);
504 if (stall_minor_watermark)
505 *stall_minor_watermark = MLX5_GET(pfcc_reg, out,
506 device_stall_minor_watermark);
511 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
513 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
514 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
516 MLX5_SET(pfcc_reg, in, local_port, 1);
517 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
518 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
519 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
520 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
522 return mlx5_core_access_reg(dev, in, sizeof(in), out,
523 sizeof(out), MLX5_REG_PFCC, 0, 1);
525 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
527 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
529 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
532 err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
537 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
540 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
544 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
546 int mlx5_max_tc(struct mlx5_core_dev *mdev)
548 u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
553 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out)
555 u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0};
557 MLX5_SET(dcbx_param, in, port_number, 1);
559 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
560 sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0);
563 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in)
565 u32 out[MLX5_ST_SZ_DW(dcbx_param)];
567 MLX5_SET(dcbx_param, in, port_number, 1);
569 return mlx5_core_access_reg(mdev, in, sizeof(out), out,
570 sizeof(out), MLX5_REG_DCBX_PARAM, 0, 1);
573 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
575 u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0};
576 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
580 for (i = 0; i < 8; i++) {
581 if (prio_tc[i] > mlx5_max_tc(mdev))
584 MLX5_SET(qtct_reg, in, prio, i);
585 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
587 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
588 sizeof(out), MLX5_REG_QTCT, 0, 1);
595 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
597 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
600 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
601 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
604 memset(in, 0, sizeof(in));
605 memset(out, 0, sizeof(out));
607 MLX5_SET(qtct_reg, in, port_number, 1);
608 MLX5_SET(qtct_reg, in, prio, prio);
610 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
611 sizeof(out), MLX5_REG_QTCT, 0, 0);
613 *tc = MLX5_GET(qtct_reg, out, tclass);
617 EXPORT_SYMBOL_GPL(mlx5_query_port_prio_tc);
619 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
622 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
624 if (!MLX5_CAP_GEN(mdev, ets))
627 return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
628 MLX5_REG_QETCR, 0, 1);
631 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
634 u32 in[MLX5_ST_SZ_DW(qetc_reg)];
636 if (!MLX5_CAP_GEN(mdev, ets))
639 memset(in, 0, sizeof(in));
640 return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
641 MLX5_REG_QETCR, 0, 0);
644 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
646 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
649 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
650 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
651 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
654 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
656 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
658 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
661 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
665 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
669 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
670 tc_configuration[tc]);
672 *tc_group = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
677 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_group);
679 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
681 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
684 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
685 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
686 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
689 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
691 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
693 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
696 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
700 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
704 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
705 tc_configuration[tc]);
707 *bw_pct = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
712 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_bw_alloc);
714 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
718 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
722 MLX5_SET(qetc_reg, in, port_number, 1);
724 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
725 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
727 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
728 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
730 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
734 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
736 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
738 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
742 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
747 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
751 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
752 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
754 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
756 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
762 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
764 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
766 u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {0};
767 u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)] = {0};
769 MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
770 MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
771 MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
772 return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
774 EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
776 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
778 u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {0};
779 u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {0};
782 MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
783 err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
785 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
789 EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
791 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen)
793 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
795 MLX5_SET(pcmr_reg, in, local_port, 1);
796 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
797 outlen, MLX5_REG_PCMR, 0, 0);
800 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
802 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
804 return mlx5_core_access_reg(mdev, in, inlen, out,
805 sizeof(out), MLX5_REG_PCMR, 0, 1);
808 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
810 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
813 err = mlx5_query_ports_check(mdev, in, sizeof(in));
816 MLX5_SET(pcmr_reg, in, local_port, 1);
817 MLX5_SET(pcmr_reg, in, fcs_chk, enable);
818 return mlx5_set_ports_check(mdev, in, sizeof(in));
821 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
824 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
825 /* Default values for FW which do not support MLX5_REG_PCMR */
829 if (!MLX5_CAP_GEN(mdev, ports_check))
832 if (mlx5_query_ports_check(mdev, out, sizeof(out)))
835 *supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
836 *enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));
839 int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
841 u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
843 return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
844 mtpps_size, MLX5_REG_MTPPS, 0, 0);
847 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
849 u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
851 return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out,
852 sizeof(out), MLX5_REG_MTPPS, 0, 1);
855 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode)
857 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
858 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
861 MLX5_SET(mtppse_reg, in, pin, pin);
863 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
864 sizeof(out), MLX5_REG_MTPPSE, 0, 0);
868 *arm = MLX5_GET(mtppse_reg, in, event_arm);
869 *mode = MLX5_GET(mtppse_reg, in, event_generation_mode);
874 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode)
876 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
877 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
879 MLX5_SET(mtppse_reg, in, pin, pin);
880 MLX5_SET(mtppse_reg, in, event_arm, arm);
881 MLX5_SET(mtppse_reg, in, event_generation_mode, mode);
883 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
884 sizeof(out), MLX5_REG_MTPPSE, 0, 1);
887 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state)
889 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
890 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
893 MLX5_SET(qpts_reg, in, local_port, 1);
894 MLX5_SET(qpts_reg, in, trust_state, trust_state);
896 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
897 sizeof(out), MLX5_REG_QPTS, 0, 1);
901 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state)
903 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
904 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
907 MLX5_SET(qpts_reg, in, local_port, 1);
909 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
910 sizeof(out), MLX5_REG_QPTS, 0, 0);
912 *trust_state = MLX5_GET(qpts_reg, out, trust_state);
917 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio)
919 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
925 in = kzalloc(sz, GFP_KERNEL);
926 out = kzalloc(sz, GFP_KERNEL);
932 MLX5_SET(qpdpm_reg, in, local_port, 1);
933 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
938 MLX5_SET(qpdpm_reg, in, local_port, 1);
940 /* Update the corresponding dscp entry */
941 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[dscp]);
942 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, prio, prio);
943 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, e, 1);
944 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1);
952 /* dscp2prio[i]: priority that dscp i mapped to */
953 #define MLX5E_SUPPORTED_DSCP 64
954 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio)
956 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
963 in = kzalloc(sz, GFP_KERNEL);
964 out = kzalloc(sz, GFP_KERNEL);
970 MLX5_SET(qpdpm_reg, in, local_port, 1);
971 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
975 for (i = 0; i < (MLX5E_SUPPORTED_DSCP); i++) {
976 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, out, dscp[i]);
977 dscp2prio[i] = MLX5_GET16(qpdpm_dscp_reg, qpdpm_dscp, prio);