2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/mlx5/port.h>
34 #include "mlx5_core.h"
36 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
37 int size_in, void *data_out, int size_out,
38 u16 reg_id, int arg, int write)
40 int outlen = MLX5_ST_SZ_BYTES(access_register_out) + size_out;
41 int inlen = MLX5_ST_SZ_BYTES(access_register_in) + size_in;
47 in = kvzalloc(inlen, GFP_KERNEL);
48 out = kvzalloc(outlen, GFP_KERNEL);
52 data = MLX5_ADDR_OF(access_register_in, in, register_data);
53 memcpy(data, data_in, size_in);
55 MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG);
56 MLX5_SET(access_register_in, in, op_mod, !write);
57 MLX5_SET(access_register_in, in, argument, arg);
58 MLX5_SET(access_register_in, in, register_id, reg_id);
60 err = mlx5_cmd_exec(dev, in, inlen, out, outlen);
64 data = MLX5_ADDR_OF(access_register_out, out, register_data);
65 memcpy(data_out, data, size_out);
72 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
74 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
77 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0};
78 int sz = MLX5_ST_SZ_BYTES(pcam_reg);
80 MLX5_SET(pcam_reg, in, feature_group, feature_group);
81 MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group);
83 return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0);
86 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group,
89 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0};
90 int sz = MLX5_ST_SZ_BYTES(mcam_reg);
92 MLX5_SET(mcam_reg, in, feature_group, feature_group);
93 MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group);
95 return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
98 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
99 u8 feature_group, u8 access_reg_group)
101 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
102 int sz = MLX5_ST_SZ_BYTES(qcam_reg);
104 MLX5_SET(qcam_reg, in, feature_group, feature_group);
105 MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);
107 return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);
110 struct mlx5_reg_pcap {
120 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
122 struct mlx5_reg_pcap in;
123 struct mlx5_reg_pcap out;
125 memset(&in, 0, sizeof(in));
126 in.caps_127_96 = cpu_to_be32(caps);
127 in.port_num = port_num;
129 return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
130 sizeof(out), MLX5_REG_PCAP, 0, 1);
132 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
134 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
135 int ptys_size, int proto_mask, u8 local_port)
137 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
139 MLX5_SET(ptys_reg, in, local_port, local_port);
140 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
141 return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
142 ptys_size, MLX5_REG_PTYS, 0, 0);
144 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
146 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
148 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0};
149 u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
151 MLX5_SET(mlcr_reg, in, local_port, 1);
152 MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
153 return mlx5_core_access_reg(dev, in, sizeof(in), out,
154 sizeof(out), MLX5_REG_MLCR, 0, 1);
157 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
158 u8 *link_width_oper, u8 local_port)
160 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
163 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
167 *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
171 EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
173 int mlx5_query_port_ib_proto_oper(struct mlx5_core_dev *dev,
174 u8 *proto_oper, u8 local_port)
176 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
179 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB,
184 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
188 EXPORT_SYMBOL(mlx5_query_port_ib_proto_oper);
190 /* This function should be used after setting a port register only */
191 void mlx5_toggle_port_link(struct mlx5_core_dev *dev)
193 enum mlx5_port_status ps;
195 mlx5_query_port_admin_status(dev, &ps);
196 mlx5_set_port_admin_status(dev, MLX5_PORT_DOWN);
197 if (ps == MLX5_PORT_UP)
198 mlx5_set_port_admin_status(dev, MLX5_PORT_UP);
200 EXPORT_SYMBOL_GPL(mlx5_toggle_port_link);
202 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
203 enum mlx5_port_status status)
205 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
206 u32 out[MLX5_ST_SZ_DW(paos_reg)];
208 MLX5_SET(paos_reg, in, local_port, 1);
209 MLX5_SET(paos_reg, in, admin_status, status);
210 MLX5_SET(paos_reg, in, ase, 1);
211 return mlx5_core_access_reg(dev, in, sizeof(in), out,
212 sizeof(out), MLX5_REG_PAOS, 0, 1);
214 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
216 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
217 enum mlx5_port_status *status)
219 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
220 u32 out[MLX5_ST_SZ_DW(paos_reg)];
223 MLX5_SET(paos_reg, in, local_port, 1);
224 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
225 sizeof(out), MLX5_REG_PAOS, 0, 0);
228 *status = MLX5_GET(paos_reg, out, admin_status);
231 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
233 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu,
234 u16 *max_mtu, u16 *oper_mtu, u8 port)
236 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
237 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
239 MLX5_SET(pmtu_reg, in, local_port, port);
240 mlx5_core_access_reg(dev, in, sizeof(in), out,
241 sizeof(out), MLX5_REG_PMTU, 0, 0);
244 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
246 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
248 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
251 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
253 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
254 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
256 MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
257 MLX5_SET(pmtu_reg, in, local_port, port);
258 return mlx5_core_access_reg(dev, in, sizeof(in), out,
259 sizeof(out), MLX5_REG_PMTU, 0, 1);
261 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
263 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu,
266 mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
268 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
270 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
273 mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
275 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
277 static int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
279 u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
280 u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
284 MLX5_SET(pmlp_reg, in, local_port, 1);
285 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
286 MLX5_REG_PMLP, 0, 0);
290 module_mapping = MLX5_GET(pmlp_reg, out, lane0_module_mapping);
291 *module_num = module_mapping & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
296 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
297 u16 offset, u16 size, u8 *data)
299 u32 out[MLX5_ST_SZ_DW(mcia_reg)];
300 u32 in[MLX5_ST_SZ_DW(mcia_reg)];
305 void *ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
307 err = mlx5_query_module_num(dev, &module_num);
311 memset(in, 0, sizeof(in));
312 size = min_t(int, size, MLX5_EEPROM_MAX_BYTES);
314 if (offset < MLX5_EEPROM_PAGE_LENGTH &&
315 offset + size > MLX5_EEPROM_PAGE_LENGTH)
316 /* Cross pages read, read until offset 256 in low page */
317 size -= offset + size - MLX5_EEPROM_PAGE_LENGTH;
319 i2c_addr = MLX5_I2C_ADDR_LOW;
320 if (offset >= MLX5_EEPROM_PAGE_LENGTH) {
321 i2c_addr = MLX5_I2C_ADDR_HIGH;
322 offset -= MLX5_EEPROM_PAGE_LENGTH;
325 MLX5_SET(mcia_reg, in, l, 0);
326 MLX5_SET(mcia_reg, in, module, module_num);
327 MLX5_SET(mcia_reg, in, i2c_device_address, i2c_addr);
328 MLX5_SET(mcia_reg, in, page_number, 0);
329 MLX5_SET(mcia_reg, in, device_address, offset);
330 MLX5_SET(mcia_reg, in, size, size);
332 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
333 sizeof(out), MLX5_REG_MCIA, 0, 0);
337 status = MLX5_GET(mcia_reg, out, status);
339 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
344 memcpy(data, ptr, size);
348 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom);
350 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
351 int pvlc_size, u8 local_port)
353 u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0};
355 MLX5_SET(pvlc_reg, in, local_port, local_port);
356 return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
357 pvlc_size, MLX5_REG_PVLC, 0, 0);
360 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
361 u8 *vl_hw_cap, u8 local_port)
363 u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
366 err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
370 *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
374 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
376 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
377 u8 port_num, void *out, size_t sz)
382 in = kvzalloc(sz, GFP_KERNEL);
388 MLX5_SET(ppcnt_reg, in, local_port, port_num);
390 MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
391 err = mlx5_core_access_reg(dev, in, sz, out,
392 sz, MLX5_REG_PPCNT, 0, 0);
397 EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
399 static int mlx5_query_pfcc_reg(struct mlx5_core_dev *dev, u32 *out,
402 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
404 MLX5_SET(pfcc_reg, in, local_port, 1);
406 return mlx5_core_access_reg(dev, in, sizeof(in), out,
407 out_size, MLX5_REG_PFCC, 0, 0);
410 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
412 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
413 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
415 MLX5_SET(pfcc_reg, in, local_port, 1);
416 MLX5_SET(pfcc_reg, in, pptx, tx_pause);
417 MLX5_SET(pfcc_reg, in, pprx, rx_pause);
419 return mlx5_core_access_reg(dev, in, sizeof(in), out,
420 sizeof(out), MLX5_REG_PFCC, 0, 1);
422 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
424 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
425 u32 *rx_pause, u32 *tx_pause)
427 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
430 err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
435 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
438 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
442 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
444 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
445 u16 stall_critical_watermark,
446 u16 stall_minor_watermark)
448 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
449 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
451 MLX5_SET(pfcc_reg, in, local_port, 1);
452 MLX5_SET(pfcc_reg, in, pptx_mask_n, 1);
453 MLX5_SET(pfcc_reg, in, pprx_mask_n, 1);
454 MLX5_SET(pfcc_reg, in, ppan_mask_n, 1);
455 MLX5_SET(pfcc_reg, in, critical_stall_mask, 1);
456 MLX5_SET(pfcc_reg, in, minor_stall_mask, 1);
457 MLX5_SET(pfcc_reg, in, device_stall_critical_watermark,
458 stall_critical_watermark);
459 MLX5_SET(pfcc_reg, in, device_stall_minor_watermark, stall_minor_watermark);
461 return mlx5_core_access_reg(dev, in, sizeof(in), out,
462 sizeof(out), MLX5_REG_PFCC, 0, 1);
465 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
466 u16 *stall_critical_watermark,
467 u16 *stall_minor_watermark)
469 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
472 err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
476 if (stall_critical_watermark)
477 *stall_critical_watermark = MLX5_GET(pfcc_reg, out,
478 device_stall_critical_watermark);
480 if (stall_minor_watermark)
481 *stall_minor_watermark = MLX5_GET(pfcc_reg, out,
482 device_stall_minor_watermark);
487 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
489 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
490 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
492 MLX5_SET(pfcc_reg, in, local_port, 1);
493 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
494 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
495 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
496 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
498 return mlx5_core_access_reg(dev, in, sizeof(in), out,
499 sizeof(out), MLX5_REG_PFCC, 0, 1);
501 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
503 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
505 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
508 err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
513 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
516 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
520 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
522 int mlx5_max_tc(struct mlx5_core_dev *mdev)
524 u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
529 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out)
531 u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0};
533 MLX5_SET(dcbx_param, in, port_number, 1);
535 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
536 sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0);
539 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in)
541 u32 out[MLX5_ST_SZ_DW(dcbx_param)];
543 MLX5_SET(dcbx_param, in, port_number, 1);
545 return mlx5_core_access_reg(mdev, in, sizeof(out), out,
546 sizeof(out), MLX5_REG_DCBX_PARAM, 0, 1);
549 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
551 u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0};
552 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
556 for (i = 0; i < 8; i++) {
557 if (prio_tc[i] > mlx5_max_tc(mdev))
560 MLX5_SET(qtct_reg, in, prio, i);
561 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
563 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
564 sizeof(out), MLX5_REG_QTCT, 0, 1);
571 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
573 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
576 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
577 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
580 memset(in, 0, sizeof(in));
581 memset(out, 0, sizeof(out));
583 MLX5_SET(qtct_reg, in, port_number, 1);
584 MLX5_SET(qtct_reg, in, prio, prio);
586 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
587 sizeof(out), MLX5_REG_QTCT, 0, 0);
589 *tc = MLX5_GET(qtct_reg, out, tclass);
593 EXPORT_SYMBOL_GPL(mlx5_query_port_prio_tc);
595 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
598 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
600 if (!MLX5_CAP_GEN(mdev, ets))
603 return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
604 MLX5_REG_QETCR, 0, 1);
607 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
610 u32 in[MLX5_ST_SZ_DW(qetc_reg)];
612 if (!MLX5_CAP_GEN(mdev, ets))
615 memset(in, 0, sizeof(in));
616 return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
617 MLX5_REG_QETCR, 0, 0);
620 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
622 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
625 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
626 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
627 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
630 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
632 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
634 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
637 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
641 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
645 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
646 tc_configuration[tc]);
648 *tc_group = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
653 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_group);
655 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
657 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
660 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
661 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
662 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
665 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
667 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
669 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
672 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
676 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
680 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
681 tc_configuration[tc]);
683 *bw_pct = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
688 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_bw_alloc);
690 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
694 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
698 MLX5_SET(qetc_reg, in, port_number, 1);
700 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
701 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
703 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
704 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
706 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
710 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
712 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
714 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
718 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
723 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
727 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
728 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
730 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
732 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
738 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
740 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
742 u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {0};
743 u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)] = {0};
745 MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
746 MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
747 MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
748 return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
750 EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
752 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
754 u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {0};
755 u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {0};
758 MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
759 err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
761 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
765 EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
767 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen)
769 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
771 MLX5_SET(pcmr_reg, in, local_port, 1);
772 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
773 outlen, MLX5_REG_PCMR, 0, 0);
776 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
778 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
780 return mlx5_core_access_reg(mdev, in, inlen, out,
781 sizeof(out), MLX5_REG_PCMR, 0, 1);
784 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
786 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
789 err = mlx5_query_ports_check(mdev, in, sizeof(in));
792 MLX5_SET(pcmr_reg, in, local_port, 1);
793 MLX5_SET(pcmr_reg, in, fcs_chk, enable);
794 return mlx5_set_ports_check(mdev, in, sizeof(in));
797 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
800 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
801 /* Default values for FW which do not support MLX5_REG_PCMR */
805 if (!MLX5_CAP_GEN(mdev, ports_check))
808 if (mlx5_query_ports_check(mdev, out, sizeof(out)))
811 *supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
812 *enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));
815 int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
817 u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
819 return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
820 mtpps_size, MLX5_REG_MTPPS, 0, 0);
823 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
825 u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
827 return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out,
828 sizeof(out), MLX5_REG_MTPPS, 0, 1);
831 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode)
833 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
834 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
837 MLX5_SET(mtppse_reg, in, pin, pin);
839 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
840 sizeof(out), MLX5_REG_MTPPSE, 0, 0);
844 *arm = MLX5_GET(mtppse_reg, in, event_arm);
845 *mode = MLX5_GET(mtppse_reg, in, event_generation_mode);
850 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode)
852 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
853 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
855 MLX5_SET(mtppse_reg, in, pin, pin);
856 MLX5_SET(mtppse_reg, in, event_arm, arm);
857 MLX5_SET(mtppse_reg, in, event_generation_mode, mode);
859 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
860 sizeof(out), MLX5_REG_MTPPSE, 0, 1);
863 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state)
865 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
866 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
869 MLX5_SET(qpts_reg, in, local_port, 1);
870 MLX5_SET(qpts_reg, in, trust_state, trust_state);
872 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
873 sizeof(out), MLX5_REG_QPTS, 0, 1);
877 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state)
879 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
880 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
883 MLX5_SET(qpts_reg, in, local_port, 1);
885 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
886 sizeof(out), MLX5_REG_QPTS, 0, 0);
888 *trust_state = MLX5_GET(qpts_reg, out, trust_state);
893 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio)
895 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
901 in = kzalloc(sz, GFP_KERNEL);
902 out = kzalloc(sz, GFP_KERNEL);
908 MLX5_SET(qpdpm_reg, in, local_port, 1);
909 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
914 MLX5_SET(qpdpm_reg, in, local_port, 1);
916 /* Update the corresponding dscp entry */
917 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[dscp]);
918 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, prio, prio);
919 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, e, 1);
920 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1);
928 /* dscp2prio[i]: priority that dscp i mapped to */
929 #define MLX5E_SUPPORTED_DSCP 64
930 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio)
932 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
939 in = kzalloc(sz, GFP_KERNEL);
940 out = kzalloc(sz, GFP_KERNEL);
946 MLX5_SET(qpdpm_reg, in, local_port, 1);
947 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
951 for (i = 0; i < (MLX5E_SUPPORTED_DSCP); i++) {
952 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, out, dscp[i]);
953 dscp2prio[i] = MLX5_GET16(qpdpm_dscp_reg, qpdpm_dscp, prio);