2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
64 #include "fpga/core.h"
65 #include "fpga/ipsec.h"
66 #include "accel/ipsec.h"
67 #include "accel/tls.h"
68 #include "lib/clock.h"
69 #include "lib/vxlan.h"
70 #include "lib/geneve.h"
71 #include "lib/devcom.h"
72 #include "lib/pci_vsc.h"
73 #include "diag/fw_tracer.h"
75 #include "lib/hv_vhca.h"
76 #include "diag/rsc_dump.h"
77 #include "sf/vhca_event.h"
78 #include "sf/dev/dev.h"
82 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
83 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
84 MODULE_LICENSE("Dual BSD/GPL");
86 unsigned int mlx5_core_debug_mask;
87 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
88 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
90 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
91 module_param_named(prof_sel, prof_sel, uint, 0444);
92 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
94 static u32 sw_owner_id[4];
97 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
98 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
101 #define LOG_MAX_SUPPORTED_QPS 0xff
103 static struct mlx5_profile profile[] = {
108 .mask = MLX5_PROF_MASK_QP_SIZE,
112 .mask = MLX5_PROF_MASK_QP_SIZE |
113 MLX5_PROF_MASK_MR_CACHE,
114 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
182 static int fw_initializing(struct mlx5_core_dev *dev)
184 return ioread32be(&dev->iseg->initializing) >> 31;
187 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
190 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
191 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
194 while (fw_initializing(dev)) {
195 if (time_after(jiffies, end)) {
199 if (warn_time_mili && time_after(jiffies, warn)) {
200 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
201 jiffies_to_msecs(end - warn) / 1000);
202 warn = jiffies + msecs_to_jiffies(warn_time_mili);
204 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
210 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
212 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
214 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
215 int remaining_size = driver_ver_sz;
218 if (!MLX5_CAP_GEN(dev, driver_version))
221 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
223 strncpy(string, "Linux", remaining_size);
225 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
226 strncat(string, ",", remaining_size);
228 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
229 strncat(string, KBUILD_MODNAME, remaining_size);
231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
232 strncat(string, ",", remaining_size);
234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
236 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
237 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
238 LINUX_VERSION_SUBLEVEL);
241 MLX5_SET(set_driver_version_in, in, opcode,
242 MLX5_CMD_OP_SET_DRIVER_VERSION);
244 mlx5_cmd_exec_in(dev, set_driver_version, in);
247 static int set_dma_caps(struct pci_dev *pdev)
251 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
253 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
254 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
256 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
261 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
265 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
267 struct pci_dev *pdev = dev->pdev;
270 mutex_lock(&dev->pci_status_mutex);
271 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
272 err = pci_enable_device(pdev);
274 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
276 mutex_unlock(&dev->pci_status_mutex);
281 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
283 struct pci_dev *pdev = dev->pdev;
285 mutex_lock(&dev->pci_status_mutex);
286 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
287 pci_disable_device(pdev);
288 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
290 mutex_unlock(&dev->pci_status_mutex);
293 static int request_bar(struct pci_dev *pdev)
297 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
298 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
302 err = pci_request_regions(pdev, KBUILD_MODNAME);
304 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
309 static void release_bar(struct pci_dev *pdev)
311 pci_release_regions(pdev);
314 struct mlx5_reg_host_endianness {
319 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
322 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
323 MLX5_DEV_CAP_FLAG_DCT,
326 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
342 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
347 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
348 enum mlx5_cap_type cap_type,
349 enum mlx5_cap_mode cap_mode)
351 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
352 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
353 void *out, *hca_caps;
354 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
357 memset(in, 0, sizeof(in));
358 out = kzalloc(out_sz, GFP_KERNEL);
362 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
363 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
364 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
367 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
368 cap_type, cap_mode, err);
372 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
375 case HCA_CAP_OPMOD_GET_MAX:
376 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
377 MLX5_UN_SZ_BYTES(hca_cap_union));
379 case HCA_CAP_OPMOD_GET_CUR:
380 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
381 MLX5_UN_SZ_BYTES(hca_cap_union));
385 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
395 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
399 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
402 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
405 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
407 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
408 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
409 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
412 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
418 if (!MLX5_CAP_GEN(dev, atomic))
421 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
427 supported_atomic_req_8B_endianness_mode_1);
429 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
432 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
434 /* Set requestor to host endianness */
435 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
436 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
438 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
441 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
447 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
448 !MLX5_CAP_GEN(dev, pg))
451 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
455 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
456 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
457 MLX5_ST_SZ_BYTES(odp_cap));
459 #define ODP_CAP_SET_MAX(dev, field) \
461 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
464 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
468 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
469 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
470 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
471 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
472 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
473 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
474 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
475 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
476 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
477 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
478 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
479 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
480 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
481 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
486 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
489 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
491 struct devlink *devlink = priv_to_devlink(dev);
492 union devlink_param_value val;
495 err = devlink_param_driverinit_value_get(devlink,
496 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
500 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
504 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
506 struct mlx5_profile *prof = &dev->profile;
511 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
515 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
517 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
518 MLX5_ST_SZ_BYTES(cmd_hca_cap));
520 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
521 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
523 /* we limit the size of the pkey table to 128 entries for now */
524 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
525 to_fw_pkey_sz(dev, 128));
527 /* Check log_max_qp from HCA caps to set in current profile */
528 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
529 prof->log_max_qp = min_t(u8, 17, MLX5_CAP_GEN_MAX(dev, log_max_qp));
530 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
531 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
533 MLX5_CAP_GEN_MAX(dev, log_max_qp));
534 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
536 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
537 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
540 /* disable cmdif checksum */
541 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
543 /* Enable 4K UAR only when HCA supports it and page size is bigger
546 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
547 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
549 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
551 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
552 MLX5_SET(cmd_hca_cap,
555 cache_line_size() >= 128 ? 1 : 0);
557 if (MLX5_CAP_GEN_MAX(dev, dct))
558 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
560 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
561 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
563 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
564 MLX5_SET(cmd_hca_cap,
567 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
569 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
570 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
572 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
573 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
575 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
577 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
578 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
579 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
581 if (MLX5_CAP_GEN(dev, roce_rw_supported))
582 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, mlx5_is_roce_init_enabled(dev));
584 max_uc_list = max_uc_list_get_devlink_param(dev);
586 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
589 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
592 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
594 * In case RoCE cap is writable in FW and user/devlink requested to change the
595 * cap, we are yet to query the final state of the above cap.
596 * Hence, the need for this function.
600 * 1) RoCE cap is read only in FW and already disabled
602 * 2) RoCE cap is writable in FW and user/devlink requested it off.
604 * In any other case, return False.
606 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
608 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_init_enabled(dev)) ||
609 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
612 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
617 if (is_roce_fw_disabled(dev))
620 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
624 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
625 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
628 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
629 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
630 MLX5_ST_SZ_BYTES(roce_cap));
631 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
633 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
637 static int set_hca_cap(struct mlx5_core_dev *dev)
639 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
643 set_ctx = kzalloc(set_sz, GFP_KERNEL);
647 err = handle_hca_cap(dev, set_ctx);
649 mlx5_core_err(dev, "handle_hca_cap failed\n");
653 memset(set_ctx, 0, set_sz);
654 err = handle_hca_cap_atomic(dev, set_ctx);
656 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
660 memset(set_ctx, 0, set_sz);
661 err = handle_hca_cap_odp(dev, set_ctx);
663 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
667 memset(set_ctx, 0, set_sz);
668 err = handle_hca_cap_roce(dev, set_ctx);
670 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
679 static int set_hca_ctrl(struct mlx5_core_dev *dev)
681 struct mlx5_reg_host_endianness he_in;
682 struct mlx5_reg_host_endianness he_out;
685 if (!mlx5_core_is_pf(dev))
688 memset(&he_in, 0, sizeof(he_in));
689 he_in.he = MLX5_SET_HOST_ENDIANNESS;
690 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
691 &he_out, sizeof(he_out),
692 MLX5_REG_HOST_ENDIANNESS, 0, 1);
696 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
700 /* Disable local_lb by default */
701 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
702 ret = mlx5_nic_vport_update_local_lb(dev, false);
707 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
709 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
711 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
712 MLX5_SET(enable_hca_in, in, function_id, func_id);
713 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
714 dev->caps.embedded_cpu);
715 return mlx5_cmd_exec_in(dev, enable_hca, in);
718 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
720 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
722 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
723 MLX5_SET(disable_hca_in, in, function_id, func_id);
724 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
725 dev->caps.embedded_cpu);
726 return mlx5_cmd_exec_in(dev, disable_hca, in);
729 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
731 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
732 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
736 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
737 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
739 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
740 u8 status = MLX5_GET(query_issi_out, query_out, status);
742 if (!status || syndrome == MLX5_DRIVER_SYND) {
743 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
744 err, status, syndrome);
748 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
753 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
755 if (sup_issi & (1 << 1)) {
756 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
758 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
759 MLX5_SET(set_issi_in, set_in, current_issi, 1);
760 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
762 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
770 } else if (sup_issi & (1 << 0) || !sup_issi) {
777 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
778 const struct pci_device_id *id)
782 mutex_init(&dev->pci_status_mutex);
783 pci_set_drvdata(dev->pdev, dev);
785 dev->bar_addr = pci_resource_start(pdev, 0);
787 err = mlx5_pci_enable_device(dev);
789 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
793 err = request_bar(pdev);
795 mlx5_core_err(dev, "error requesting BARs, aborting\n");
799 pci_set_master(pdev);
801 err = set_dma_caps(pdev);
803 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
807 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
808 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
809 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
810 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
812 dev->iseg_base = dev->bar_addr;
813 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
816 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
820 mlx5_pci_vsc_init(dev);
821 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
825 pci_clear_master(dev->pdev);
826 release_bar(dev->pdev);
828 mlx5_pci_disable_device(dev);
832 static void mlx5_pci_close(struct mlx5_core_dev *dev)
834 /* health work might still be active, and it needs pci bar in
835 * order to know the NIC state. Therefore, drain the health WQ
836 * before removing the pci bars
838 mlx5_drain_health_wq(dev);
840 pci_clear_master(dev->pdev);
841 release_bar(dev->pdev);
842 mlx5_pci_disable_device(dev);
845 static int mlx5_init_once(struct mlx5_core_dev *dev)
849 dev->priv.devcom = mlx5_devcom_register_device(dev);
850 if (IS_ERR(dev->priv.devcom))
851 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
854 err = mlx5_query_board_id(dev);
856 mlx5_core_err(dev, "query board id failed\n");
860 err = mlx5_irq_table_init(dev);
862 mlx5_core_err(dev, "failed to initialize irq table\n");
866 err = mlx5_eq_table_init(dev);
868 mlx5_core_err(dev, "failed to initialize eq\n");
869 goto err_irq_cleanup;
872 err = mlx5_events_init(dev);
874 mlx5_core_err(dev, "failed to initialize events\n");
878 err = mlx5_fw_reset_init(dev);
880 mlx5_core_err(dev, "failed to initialize fw reset events\n");
881 goto err_events_cleanup;
884 mlx5_cq_debugfs_init(dev);
886 mlx5_init_reserved_gids(dev);
888 mlx5_init_clock(dev);
890 dev->vxlan = mlx5_vxlan_create(dev);
891 dev->geneve = mlx5_geneve_create(dev);
893 err = mlx5_init_rl_table(dev);
895 mlx5_core_err(dev, "Failed to init rate limiting\n");
896 goto err_tables_cleanup;
899 err = mlx5_mpfs_init(dev);
901 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
905 err = mlx5_sriov_init(dev);
907 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
908 goto err_mpfs_cleanup;
911 err = mlx5_eswitch_init(dev);
913 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
914 goto err_sriov_cleanup;
917 err = mlx5_fpga_init(dev);
919 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
920 goto err_eswitch_cleanup;
923 err = mlx5_vhca_event_init(dev);
925 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
926 goto err_fpga_cleanup;
929 err = mlx5_sf_hw_table_init(dev);
931 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
932 goto err_sf_hw_table_cleanup;
935 err = mlx5_sf_table_init(dev);
937 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
938 goto err_sf_table_cleanup;
941 dev->dm = mlx5_dm_create(dev);
943 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
945 dev->tracer = mlx5_fw_tracer_create(dev);
946 dev->hv_vhca = mlx5_hv_vhca_create(dev);
947 dev->rsc_dump = mlx5_rsc_dump_create(dev);
951 err_sf_table_cleanup:
952 mlx5_sf_hw_table_cleanup(dev);
953 err_sf_hw_table_cleanup:
954 mlx5_vhca_event_cleanup(dev);
956 mlx5_fpga_cleanup(dev);
958 mlx5_eswitch_cleanup(dev->priv.eswitch);
960 mlx5_sriov_cleanup(dev);
962 mlx5_mpfs_cleanup(dev);
964 mlx5_cleanup_rl_table(dev);
966 mlx5_geneve_destroy(dev->geneve);
967 mlx5_vxlan_destroy(dev->vxlan);
968 mlx5_cq_debugfs_cleanup(dev);
969 mlx5_fw_reset_cleanup(dev);
971 mlx5_events_cleanup(dev);
973 mlx5_eq_table_cleanup(dev);
975 mlx5_irq_table_cleanup(dev);
977 mlx5_devcom_unregister_device(dev->priv.devcom);
982 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
984 mlx5_rsc_dump_destroy(dev);
985 mlx5_hv_vhca_destroy(dev->hv_vhca);
986 mlx5_fw_tracer_destroy(dev->tracer);
987 mlx5_dm_cleanup(dev);
988 mlx5_sf_table_cleanup(dev);
989 mlx5_sf_hw_table_cleanup(dev);
990 mlx5_vhca_event_cleanup(dev);
991 mlx5_fpga_cleanup(dev);
992 mlx5_eswitch_cleanup(dev->priv.eswitch);
993 mlx5_sriov_cleanup(dev);
994 mlx5_mpfs_cleanup(dev);
995 mlx5_cleanup_rl_table(dev);
996 mlx5_geneve_destroy(dev->geneve);
997 mlx5_vxlan_destroy(dev->vxlan);
998 mlx5_cleanup_clock(dev);
999 mlx5_cleanup_reserved_gids(dev);
1000 mlx5_cq_debugfs_cleanup(dev);
1001 mlx5_fw_reset_cleanup(dev);
1002 mlx5_events_cleanup(dev);
1003 mlx5_eq_table_cleanup(dev);
1004 mlx5_irq_table_cleanup(dev);
1005 mlx5_devcom_unregister_device(dev->priv.devcom);
1008 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
1012 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1013 fw_rev_min(dev), fw_rev_sub(dev));
1015 /* Only PFs hold the relevant PCIe information for this query */
1016 if (mlx5_core_is_pf(dev))
1017 pcie_print_link_status(dev->pdev);
1019 mlx5_tout_set_def_val(dev);
1021 /* wait for firmware to accept initialization segments configurations
1023 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT),
1024 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL));
1026 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n",
1027 mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1031 err = mlx5_cmd_init(dev);
1033 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1037 mlx5_tout_query_iseg(dev);
1039 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0);
1041 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n",
1042 mlx5_tout_ms(dev, FW_INIT));
1043 goto err_cmd_cleanup;
1046 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1048 err = mlx5_core_enable_hca(dev, 0);
1050 mlx5_core_err(dev, "enable hca failed\n");
1051 goto err_cmd_cleanup;
1054 err = mlx5_core_set_issi(dev);
1056 mlx5_core_err(dev, "failed to set issi\n");
1057 goto err_disable_hca;
1060 err = mlx5_satisfy_startup_pages(dev, 1);
1062 mlx5_core_err(dev, "failed to allocate boot pages\n");
1063 goto err_disable_hca;
1066 err = mlx5_tout_query_dtor(dev);
1068 mlx5_core_err(dev, "failed to read dtor\n");
1069 goto reclaim_boot_pages;
1072 err = set_hca_ctrl(dev);
1074 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1075 goto reclaim_boot_pages;
1078 err = set_hca_cap(dev);
1080 mlx5_core_err(dev, "set_hca_cap failed\n");
1081 goto reclaim_boot_pages;
1084 err = mlx5_satisfy_startup_pages(dev, 0);
1086 mlx5_core_err(dev, "failed to allocate init pages\n");
1087 goto reclaim_boot_pages;
1090 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1092 mlx5_core_err(dev, "init hca failed\n");
1093 goto reclaim_boot_pages;
1096 mlx5_set_driver_version(dev);
1098 err = mlx5_query_hca_caps(dev);
1100 mlx5_core_err(dev, "query hca failed\n");
1101 goto reclaim_boot_pages;
1104 mlx5_start_health_poll(dev);
1109 mlx5_reclaim_startup_pages(dev);
1111 mlx5_core_disable_hca(dev, 0);
1113 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1114 mlx5_cmd_cleanup(dev);
1119 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1123 mlx5_stop_health_poll(dev, boot);
1124 err = mlx5_cmd_teardown_hca(dev);
1126 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1129 mlx5_reclaim_startup_pages(dev);
1130 mlx5_core_disable_hca(dev, 0);
1131 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1132 mlx5_cmd_cleanup(dev);
1137 static int mlx5_load(struct mlx5_core_dev *dev)
1141 dev->priv.uar = mlx5_get_uars_page(dev);
1142 if (IS_ERR(dev->priv.uar)) {
1143 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1144 err = PTR_ERR(dev->priv.uar);
1148 mlx5_events_start(dev);
1149 mlx5_pagealloc_start(dev);
1151 err = mlx5_irq_table_create(dev);
1153 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1157 err = mlx5_eq_table_create(dev);
1159 mlx5_core_err(dev, "Failed to create EQs\n");
1163 err = mlx5_fw_tracer_init(dev->tracer);
1165 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1166 mlx5_fw_tracer_destroy(dev->tracer);
1170 mlx5_fw_reset_events_start(dev);
1171 mlx5_hv_vhca_init(dev->hv_vhca);
1173 err = mlx5_rsc_dump_init(dev);
1175 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1176 mlx5_rsc_dump_destroy(dev);
1177 dev->rsc_dump = NULL;
1180 err = mlx5_fpga_device_start(dev);
1182 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1183 goto err_fpga_start;
1186 mlx5_accel_ipsec_init(dev);
1188 err = mlx5_accel_tls_init(dev);
1190 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1194 err = mlx5_init_fs(dev);
1196 mlx5_core_err(dev, "Failed to init flow steering\n");
1200 err = mlx5_core_set_hca_defaults(dev);
1202 mlx5_core_err(dev, "Failed to set hca defaults\n");
1206 mlx5_vhca_event_start(dev);
1208 err = mlx5_sf_hw_table_create(dev);
1210 mlx5_core_err(dev, "sf table create failed %d\n", err);
1214 err = mlx5_ec_init(dev);
1216 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1220 mlx5_lag_add_mdev(dev);
1221 err = mlx5_sriov_attach(dev);
1223 mlx5_core_err(dev, "sriov init failed %d\n", err);
1227 mlx5_sf_dev_table_create(dev);
1232 mlx5_lag_remove_mdev(dev);
1233 mlx5_ec_cleanup(dev);
1235 mlx5_sf_hw_table_destroy(dev);
1237 mlx5_vhca_event_stop(dev);
1239 mlx5_cleanup_fs(dev);
1241 mlx5_accel_tls_cleanup(dev);
1243 mlx5_accel_ipsec_cleanup(dev);
1244 mlx5_fpga_device_stop(dev);
1246 mlx5_rsc_dump_cleanup(dev);
1247 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1248 mlx5_fw_reset_events_stop(dev);
1249 mlx5_fw_tracer_cleanup(dev->tracer);
1250 mlx5_eq_table_destroy(dev);
1252 mlx5_irq_table_destroy(dev);
1254 mlx5_pagealloc_stop(dev);
1255 mlx5_events_stop(dev);
1256 mlx5_put_uars_page(dev, dev->priv.uar);
1260 static void mlx5_unload(struct mlx5_core_dev *dev)
1262 mlx5_sf_dev_table_destroy(dev);
1263 mlx5_sriov_detach(dev);
1264 mlx5_lag_remove_mdev(dev);
1265 mlx5_ec_cleanup(dev);
1266 mlx5_sf_hw_table_destroy(dev);
1267 mlx5_vhca_event_stop(dev);
1268 mlx5_cleanup_fs(dev);
1269 mlx5_accel_ipsec_cleanup(dev);
1270 mlx5_accel_tls_cleanup(dev);
1271 mlx5_fpga_device_stop(dev);
1272 mlx5_rsc_dump_cleanup(dev);
1273 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1274 mlx5_fw_reset_events_stop(dev);
1275 mlx5_fw_tracer_cleanup(dev->tracer);
1276 mlx5_eq_table_destroy(dev);
1277 mlx5_irq_table_destroy(dev);
1278 mlx5_pagealloc_stop(dev);
1279 mlx5_events_stop(dev);
1280 mlx5_put_uars_page(dev, dev->priv.uar);
1283 int mlx5_init_one(struct mlx5_core_dev *dev)
1287 mutex_lock(&dev->intf_state_mutex);
1288 dev->state = MLX5_DEVICE_STATE_UP;
1290 err = mlx5_function_setup(dev, true);
1294 err = mlx5_init_once(dev);
1296 mlx5_core_err(dev, "sw objs init failed\n");
1297 goto function_teardown;
1300 err = mlx5_load(dev);
1304 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1306 err = mlx5_devlink_register(priv_to_devlink(dev));
1308 goto err_devlink_reg;
1310 err = mlx5_register_device(dev);
1314 mutex_unlock(&dev->intf_state_mutex);
1318 mlx5_devlink_unregister(priv_to_devlink(dev));
1320 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1323 mlx5_cleanup_once(dev);
1325 mlx5_function_teardown(dev, true);
1327 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1328 mutex_unlock(&dev->intf_state_mutex);
1332 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1334 mutex_lock(&dev->intf_state_mutex);
1336 mlx5_unregister_device(dev);
1337 mlx5_devlink_unregister(priv_to_devlink(dev));
1339 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1340 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1342 mlx5_cleanup_once(dev);
1346 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1348 mlx5_cleanup_once(dev);
1349 mlx5_function_teardown(dev, true);
1351 mutex_unlock(&dev->intf_state_mutex);
1354 int mlx5_load_one(struct mlx5_core_dev *dev)
1358 mutex_lock(&dev->intf_state_mutex);
1359 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1360 mlx5_core_warn(dev, "interface is up, NOP\n");
1363 /* remove any previous indication of internal error */
1364 dev->state = MLX5_DEVICE_STATE_UP;
1366 err = mlx5_function_setup(dev, false);
1370 err = mlx5_load(dev);
1374 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1376 err = mlx5_attach_device(dev);
1380 mutex_unlock(&dev->intf_state_mutex);
1384 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1387 mlx5_function_teardown(dev, false);
1389 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1391 mutex_unlock(&dev->intf_state_mutex);
1395 void mlx5_unload_one(struct mlx5_core_dev *dev)
1397 mutex_lock(&dev->intf_state_mutex);
1399 mlx5_detach_device(dev);
1401 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1402 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1407 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1409 mlx5_function_teardown(dev, false);
1411 mutex_unlock(&dev->intf_state_mutex);
1414 static const int types[] = {
1417 MLX5_CAP_ETHERNET_OFFLOADS,
1418 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1422 MLX5_CAP_IPOIB_OFFLOADS,
1423 MLX5_CAP_FLOW_TABLE,
1424 MLX5_CAP_ESWITCH_FLOW_TABLE,
1426 MLX5_CAP_VECTOR_CALC,
1432 MLX5_CAP_VDPA_EMULATION,
1434 MLX5_CAP_PORT_SELECTION,
1435 MLX5_CAP_DEV_SHAMPO,
1438 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1443 for (i = 0; i < ARRAY_SIZE(types); i++) {
1445 kfree(dev->caps.hca[type]);
1449 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1451 struct mlx5_hca_cap *cap;
1455 for (i = 0; i < ARRAY_SIZE(types); i++) {
1456 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1460 dev->caps.hca[type] = cap;
1466 mlx5_hca_caps_free(dev);
1470 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1472 struct mlx5_priv *priv = &dev->priv;
1475 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1476 INIT_LIST_HEAD(&priv->ctx_list);
1477 spin_lock_init(&priv->ctx_lock);
1478 mutex_init(&dev->intf_state_mutex);
1480 mutex_init(&priv->bfregs.reg_head.lock);
1481 mutex_init(&priv->bfregs.wc_head.lock);
1482 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1483 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1485 mutex_init(&priv->alloc_mutex);
1486 mutex_init(&priv->pgdir_mutex);
1487 INIT_LIST_HEAD(&priv->pgdir_list);
1489 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1490 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1492 INIT_LIST_HEAD(&priv->traps);
1494 err = mlx5_tout_init(dev);
1496 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1497 goto err_timeout_init;
1500 err = mlx5_health_init(dev);
1502 goto err_health_init;
1504 err = mlx5_pagealloc_init(dev);
1506 goto err_pagealloc_init;
1508 err = mlx5_adev_init(dev);
1512 err = mlx5_hca_caps_alloc(dev);
1519 mlx5_adev_cleanup(dev);
1521 mlx5_pagealloc_cleanup(dev);
1523 mlx5_health_cleanup(dev);
1525 mlx5_tout_cleanup(dev);
1527 debugfs_remove(dev->priv.dbg.dbg_root);
1528 mutex_destroy(&priv->pgdir_mutex);
1529 mutex_destroy(&priv->alloc_mutex);
1530 mutex_destroy(&priv->bfregs.wc_head.lock);
1531 mutex_destroy(&priv->bfregs.reg_head.lock);
1532 mutex_destroy(&dev->intf_state_mutex);
1536 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1538 struct mlx5_priv *priv = &dev->priv;
1540 mlx5_hca_caps_free(dev);
1541 mlx5_adev_cleanup(dev);
1542 mlx5_pagealloc_cleanup(dev);
1543 mlx5_health_cleanup(dev);
1544 mlx5_tout_cleanup(dev);
1545 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1546 mutex_destroy(&priv->pgdir_mutex);
1547 mutex_destroy(&priv->alloc_mutex);
1548 mutex_destroy(&priv->bfregs.wc_head.lock);
1549 mutex_destroy(&priv->bfregs.reg_head.lock);
1550 mutex_destroy(&dev->intf_state_mutex);
1553 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1555 struct mlx5_core_dev *dev;
1556 struct devlink *devlink;
1559 devlink = mlx5_devlink_alloc(&pdev->dev);
1561 dev_err(&pdev->dev, "devlink alloc failed\n");
1565 dev = devlink_priv(devlink);
1566 dev->device = &pdev->dev;
1569 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1570 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1572 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1573 if (dev->priv.adev_idx < 0) {
1574 err = dev->priv.adev_idx;
1578 err = mlx5_mdev_init(dev, prof_sel);
1582 err = mlx5_pci_init(dev, pdev, id);
1584 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1589 err = mlx5_init_one(dev);
1591 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1596 err = mlx5_crdump_enable(dev);
1598 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1600 pci_save_state(pdev);
1601 devlink_register(devlink);
1605 mlx5_pci_close(dev);
1607 mlx5_mdev_uninit(dev);
1609 mlx5_adev_idx_free(dev->priv.adev_idx);
1611 mlx5_devlink_free(devlink);
1616 static void remove_one(struct pci_dev *pdev)
1618 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1619 struct devlink *devlink = priv_to_devlink(dev);
1621 devlink_unregister(devlink);
1622 mlx5_crdump_disable(dev);
1623 mlx5_drain_health_wq(dev);
1624 mlx5_uninit_one(dev);
1625 mlx5_pci_close(dev);
1626 mlx5_mdev_uninit(dev);
1627 mlx5_adev_idx_free(dev->priv.adev_idx);
1628 mlx5_devlink_free(devlink);
1631 #define mlx5_pci_trace(dev, fmt, ...) ({ \
1632 struct mlx5_core_dev *__dev = (dev); \
1633 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
1634 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
1635 __dev->pci_status, ##__VA_ARGS__); \
1638 static const char *result2str(enum pci_ers_result result)
1640 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
1641 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
1642 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
1646 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1647 pci_channel_state_t state)
1649 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1650 enum pci_ers_result res;
1652 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
1654 mlx5_enter_error_state(dev, false);
1655 mlx5_error_sw_reset(dev);
1656 mlx5_unload_one(dev);
1657 mlx5_drain_health_wq(dev);
1658 mlx5_pci_disable_device(dev);
1660 res = state == pci_channel_io_perm_failure ?
1661 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1663 mlx5_pci_trace(dev, "Exit, result = %d, %s\n", res, result2str(res));
1667 /* wait for the device to show vital signs by waiting
1668 * for the health counter to start counting.
1670 static int wait_vital(struct pci_dev *pdev)
1672 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1673 struct mlx5_core_health *health = &dev->priv.health;
1674 const int niter = 100;
1679 for (i = 0; i < niter; i++) {
1680 count = ioread32be(health->health_counter);
1681 if (count && count != 0xffffffff) {
1682 if (last_count && last_count != count) {
1684 "wait vital counter value 0x%x after %d iterations\n",
1696 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1698 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
1699 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1702 mlx5_pci_trace(dev, "Enter\n");
1704 err = mlx5_pci_enable_device(dev);
1706 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1711 pci_set_master(pdev);
1712 pci_restore_state(pdev);
1713 pci_save_state(pdev);
1715 err = wait_vital(pdev);
1717 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
1722 res = PCI_ERS_RESULT_RECOVERED;
1724 mlx5_pci_trace(dev, "Exit, err = %d, result = %d, %s\n", err, res, result2str(res));
1728 static void mlx5_pci_resume(struct pci_dev *pdev)
1730 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1733 mlx5_pci_trace(dev, "Enter, loading driver..\n");
1735 err = mlx5_load_one(dev);
1737 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
1738 !err ? "recovered" : "Failed");
1741 static const struct pci_error_handlers mlx5_err_handler = {
1742 .error_detected = mlx5_pci_err_detected,
1743 .slot_reset = mlx5_pci_slot_reset,
1744 .resume = mlx5_pci_resume
1747 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1749 bool fast_teardown = false, force_teardown = false;
1752 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1753 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1755 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1756 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1758 if (!fast_teardown && !force_teardown)
1761 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1762 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1766 /* Panic tear down fw command will stop the PCI bus communication
1767 * with the HCA, so the health polll is no longer needed.
1769 mlx5_drain_health_wq(dev);
1770 mlx5_stop_health_poll(dev, false);
1772 ret = mlx5_cmd_fast_teardown_hca(dev);
1776 ret = mlx5_cmd_force_teardown_hca(dev);
1780 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1781 mlx5_start_health_poll(dev);
1785 mlx5_enter_error_state(dev, true);
1787 /* Some platforms requiring freeing the IRQ's in the shutdown
1788 * flow. If they aren't freed they can't be allocated after
1789 * kexec. There is no need to cleanup the mlx5_core software
1792 mlx5_core_eq_free_irqs(dev);
1797 static void shutdown(struct pci_dev *pdev)
1799 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1802 mlx5_core_info(dev, "Shutdown was called\n");
1803 err = mlx5_try_fast_unload(dev);
1805 mlx5_unload_one(dev);
1806 mlx5_pci_disable_device(dev);
1809 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1811 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1813 mlx5_unload_one(dev);
1818 static int mlx5_resume(struct pci_dev *pdev)
1820 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1822 return mlx5_load_one(dev);
1825 static const struct pci_device_id mlx5_core_pci_table[] = {
1826 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1827 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1828 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1829 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1830 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1831 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1832 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1833 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1834 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1835 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1836 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1837 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1838 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1839 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1840 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1841 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1842 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
1843 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1844 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1845 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1846 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
1847 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
1851 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1853 void mlx5_disable_device(struct mlx5_core_dev *dev)
1855 mlx5_error_sw_reset(dev);
1856 mlx5_unload_one(dev);
1859 int mlx5_recover_device(struct mlx5_core_dev *dev)
1861 if (!mlx5_core_is_sf(dev)) {
1862 mlx5_pci_disable_device(dev);
1863 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
1867 return mlx5_load_one(dev);
1870 static struct pci_driver mlx5_core_driver = {
1871 .name = KBUILD_MODNAME,
1872 .id_table = mlx5_core_pci_table,
1874 .remove = remove_one,
1875 .suspend = mlx5_suspend,
1876 .resume = mlx5_resume,
1877 .shutdown = shutdown,
1878 .err_handler = &mlx5_err_handler,
1879 .sriov_configure = mlx5_core_sriov_configure,
1880 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
1881 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
1884 static void mlx5_core_verify_params(void)
1886 if (prof_sel >= ARRAY_SIZE(profile)) {
1887 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1889 ARRAY_SIZE(profile) - 1,
1891 prof_sel = MLX5_DEFAULT_PROF;
1895 static int __init init(void)
1899 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
1900 "mlx5_core name not in sync with kernel module name");
1902 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1904 mlx5_core_verify_params();
1905 mlx5_fpga_ipsec_build_fs_cmds();
1906 mlx5_register_debugfs();
1908 err = pci_register_driver(&mlx5_core_driver);
1912 err = mlx5_sf_driver_register();
1923 mlx5_sf_driver_unregister();
1925 pci_unregister_driver(&mlx5_core_driver);
1927 mlx5_unregister_debugfs();
1931 static void __exit cleanup(void)
1934 mlx5_sf_driver_unregister();
1935 pci_unregister_driver(&mlx5_core_driver);
1936 mlx5_unregister_debugfs();
1940 module_exit(cleanup);