2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
64 #include "fpga/core.h"
65 #include "fpga/ipsec.h"
66 #include "accel/ipsec.h"
67 #include "accel/tls.h"
68 #include "lib/clock.h"
69 #include "lib/vxlan.h"
70 #include "lib/geneve.h"
71 #include "lib/devcom.h"
72 #include "lib/pci_vsc.h"
73 #include "diag/fw_tracer.h"
75 #include "lib/hv_vhca.h"
76 #include "diag/rsc_dump.h"
77 #include "sf/vhca_event.h"
78 #include "sf/dev/dev.h"
82 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
83 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
84 MODULE_LICENSE("Dual BSD/GPL");
86 unsigned int mlx5_core_debug_mask;
87 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
88 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
90 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
91 module_param_named(prof_sel, prof_sel, uint, 0444);
92 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
94 static u32 sw_owner_id[4];
97 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
98 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
101 #define LOG_MAX_SUPPORTED_QPS 0xff
103 static struct mlx5_profile profile[] = {
108 .mask = MLX5_PROF_MASK_QP_SIZE,
112 .mask = MLX5_PROF_MASK_QP_SIZE |
113 MLX5_PROF_MASK_MR_CACHE,
114 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
182 static int fw_initializing(struct mlx5_core_dev *dev)
184 return ioread32be(&dev->iseg->initializing) >> 31;
187 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
190 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
191 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
194 while (fw_initializing(dev)) {
195 if (time_after(jiffies, end)) {
199 if (warn_time_mili && time_after(jiffies, warn)) {
200 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
201 jiffies_to_msecs(end - warn) / 1000);
202 warn = jiffies + msecs_to_jiffies(warn_time_mili);
204 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
210 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
212 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
214 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
215 int remaining_size = driver_ver_sz;
218 if (!MLX5_CAP_GEN(dev, driver_version))
221 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
223 strncpy(string, "Linux", remaining_size);
225 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
226 strncat(string, ",", remaining_size);
228 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
229 strncat(string, KBUILD_MODNAME, remaining_size);
231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
232 strncat(string, ",", remaining_size);
234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
236 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
237 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
238 LINUX_VERSION_SUBLEVEL);
241 MLX5_SET(set_driver_version_in, in, opcode,
242 MLX5_CMD_OP_SET_DRIVER_VERSION);
244 mlx5_cmd_exec_in(dev, set_driver_version, in);
247 static int set_dma_caps(struct pci_dev *pdev)
251 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
253 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
254 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
256 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
261 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
265 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
267 struct pci_dev *pdev = dev->pdev;
270 mutex_lock(&dev->pci_status_mutex);
271 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
272 err = pci_enable_device(pdev);
274 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
276 mutex_unlock(&dev->pci_status_mutex);
281 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
283 struct pci_dev *pdev = dev->pdev;
285 mutex_lock(&dev->pci_status_mutex);
286 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
287 pci_disable_device(pdev);
288 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
290 mutex_unlock(&dev->pci_status_mutex);
293 static int request_bar(struct pci_dev *pdev)
297 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
298 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
302 err = pci_request_regions(pdev, KBUILD_MODNAME);
304 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
309 static void release_bar(struct pci_dev *pdev)
311 pci_release_regions(pdev);
314 struct mlx5_reg_host_endianness {
319 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
322 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
323 MLX5_DEV_CAP_FLAG_DCT,
326 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
342 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
347 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
348 enum mlx5_cap_type cap_type,
349 enum mlx5_cap_mode cap_mode)
351 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
352 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
353 void *out, *hca_caps;
354 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
357 memset(in, 0, sizeof(in));
358 out = kzalloc(out_sz, GFP_KERNEL);
362 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
363 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
364 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
367 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
368 cap_type, cap_mode, err);
372 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
375 case HCA_CAP_OPMOD_GET_MAX:
376 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
377 MLX5_UN_SZ_BYTES(hca_cap_union));
379 case HCA_CAP_OPMOD_GET_CUR:
380 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
381 MLX5_UN_SZ_BYTES(hca_cap_union));
385 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
395 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
399 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
402 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
405 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
407 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
408 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
409 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
412 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
418 if (!MLX5_CAP_GEN(dev, atomic))
421 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
427 supported_atomic_req_8B_endianness_mode_1);
429 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
432 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
434 /* Set requestor to host endianness */
435 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
436 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
438 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
441 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
447 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
448 !MLX5_CAP_GEN(dev, pg))
451 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
455 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
456 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
457 MLX5_ST_SZ_BYTES(odp_cap));
459 #define ODP_CAP_SET_MAX(dev, field) \
461 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
464 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
468 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
469 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
470 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
471 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
472 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
473 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
474 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
475 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
476 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
477 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
478 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
479 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
480 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
481 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
486 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
489 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
491 struct devlink *devlink = priv_to_devlink(dev);
492 union devlink_param_value val;
495 err = devlink_param_driverinit_value_get(devlink,
496 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
500 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
504 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
506 struct mlx5_profile *prof = &dev->profile;
511 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
515 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
517 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
518 MLX5_ST_SZ_BYTES(cmd_hca_cap));
520 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
521 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
523 /* we limit the size of the pkey table to 128 entries for now */
524 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
525 to_fw_pkey_sz(dev, 128));
527 /* Check log_max_qp from HCA caps to set in current profile */
528 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
529 prof->log_max_qp = min_t(u8, 17, MLX5_CAP_GEN_MAX(dev, log_max_qp));
530 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
531 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
533 MLX5_CAP_GEN_MAX(dev, log_max_qp));
534 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
536 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
537 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
540 /* disable cmdif checksum */
541 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
543 /* Enable 4K UAR only when HCA supports it and page size is bigger
546 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
547 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
549 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
551 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
552 MLX5_SET(cmd_hca_cap,
555 cache_line_size() >= 128 ? 1 : 0);
557 if (MLX5_CAP_GEN_MAX(dev, dct))
558 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
560 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
561 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
563 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
564 MLX5_SET(cmd_hca_cap,
567 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
569 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
570 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
572 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
573 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
575 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
577 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
578 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
579 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
581 if (MLX5_CAP_GEN(dev, roce_rw_supported))
582 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, mlx5_is_roce_init_enabled(dev));
584 max_uc_list = max_uc_list_get_devlink_param(dev);
586 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
589 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
592 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
594 * In case RoCE cap is writable in FW and user/devlink requested to change the
595 * cap, we are yet to query the final state of the above cap.
596 * Hence, the need for this function.
600 * 1) RoCE cap is read only in FW and already disabled
602 * 2) RoCE cap is writable in FW and user/devlink requested it off.
604 * In any other case, return False.
606 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
608 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_init_enabled(dev)) ||
609 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
612 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
617 if (is_roce_fw_disabled(dev))
620 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
624 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
625 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
628 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
629 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
630 MLX5_ST_SZ_BYTES(roce_cap));
631 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
633 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
637 static int set_hca_cap(struct mlx5_core_dev *dev)
639 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
643 set_ctx = kzalloc(set_sz, GFP_KERNEL);
647 err = handle_hca_cap(dev, set_ctx);
649 mlx5_core_err(dev, "handle_hca_cap failed\n");
653 memset(set_ctx, 0, set_sz);
654 err = handle_hca_cap_atomic(dev, set_ctx);
656 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
660 memset(set_ctx, 0, set_sz);
661 err = handle_hca_cap_odp(dev, set_ctx);
663 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
667 memset(set_ctx, 0, set_sz);
668 err = handle_hca_cap_roce(dev, set_ctx);
670 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
679 static int set_hca_ctrl(struct mlx5_core_dev *dev)
681 struct mlx5_reg_host_endianness he_in;
682 struct mlx5_reg_host_endianness he_out;
685 if (!mlx5_core_is_pf(dev))
688 memset(&he_in, 0, sizeof(he_in));
689 he_in.he = MLX5_SET_HOST_ENDIANNESS;
690 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
691 &he_out, sizeof(he_out),
692 MLX5_REG_HOST_ENDIANNESS, 0, 1);
696 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
700 /* Disable local_lb by default */
701 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
702 ret = mlx5_nic_vport_update_local_lb(dev, false);
707 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
709 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
711 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
712 MLX5_SET(enable_hca_in, in, function_id, func_id);
713 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
714 dev->caps.embedded_cpu);
715 return mlx5_cmd_exec_in(dev, enable_hca, in);
718 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
720 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
722 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
723 MLX5_SET(disable_hca_in, in, function_id, func_id);
724 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
725 dev->caps.embedded_cpu);
726 return mlx5_cmd_exec_in(dev, disable_hca, in);
729 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
731 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
732 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
736 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
737 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
742 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
743 if (!status || syndrome == MLX5_DRIVER_SYND) {
744 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
745 err, status, syndrome);
749 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
754 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
756 if (sup_issi & (1 << 1)) {
757 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
759 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
760 MLX5_SET(set_issi_in, set_in, current_issi, 1);
761 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
763 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
771 } else if (sup_issi & (1 << 0) || !sup_issi) {
778 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
779 const struct pci_device_id *id)
783 mutex_init(&dev->pci_status_mutex);
784 pci_set_drvdata(dev->pdev, dev);
786 dev->bar_addr = pci_resource_start(pdev, 0);
788 err = mlx5_pci_enable_device(dev);
790 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
794 err = request_bar(pdev);
796 mlx5_core_err(dev, "error requesting BARs, aborting\n");
800 pci_set_master(pdev);
802 err = set_dma_caps(pdev);
804 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
808 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
809 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
810 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
811 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
813 dev->iseg_base = dev->bar_addr;
814 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
817 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
821 mlx5_pci_vsc_init(dev);
822 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
826 pci_clear_master(dev->pdev);
827 release_bar(dev->pdev);
829 mlx5_pci_disable_device(dev);
833 static void mlx5_pci_close(struct mlx5_core_dev *dev)
835 /* health work might still be active, and it needs pci bar in
836 * order to know the NIC state. Therefore, drain the health WQ
837 * before removing the pci bars
839 mlx5_drain_health_wq(dev);
841 pci_clear_master(dev->pdev);
842 release_bar(dev->pdev);
843 mlx5_pci_disable_device(dev);
846 static int mlx5_init_once(struct mlx5_core_dev *dev)
850 dev->priv.devcom = mlx5_devcom_register_device(dev);
851 if (IS_ERR(dev->priv.devcom))
852 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
855 err = mlx5_query_board_id(dev);
857 mlx5_core_err(dev, "query board id failed\n");
861 err = mlx5_irq_table_init(dev);
863 mlx5_core_err(dev, "failed to initialize irq table\n");
867 err = mlx5_eq_table_init(dev);
869 mlx5_core_err(dev, "failed to initialize eq\n");
870 goto err_irq_cleanup;
873 err = mlx5_events_init(dev);
875 mlx5_core_err(dev, "failed to initialize events\n");
879 err = mlx5_fw_reset_init(dev);
881 mlx5_core_err(dev, "failed to initialize fw reset events\n");
882 goto err_events_cleanup;
885 mlx5_cq_debugfs_init(dev);
887 mlx5_init_reserved_gids(dev);
889 mlx5_init_clock(dev);
891 dev->vxlan = mlx5_vxlan_create(dev);
892 dev->geneve = mlx5_geneve_create(dev);
894 err = mlx5_init_rl_table(dev);
896 mlx5_core_err(dev, "Failed to init rate limiting\n");
897 goto err_tables_cleanup;
900 err = mlx5_mpfs_init(dev);
902 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
906 err = mlx5_sriov_init(dev);
908 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
909 goto err_mpfs_cleanup;
912 err = mlx5_eswitch_init(dev);
914 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
915 goto err_sriov_cleanup;
918 err = mlx5_fpga_init(dev);
920 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
921 goto err_eswitch_cleanup;
924 err = mlx5_vhca_event_init(dev);
926 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
927 goto err_fpga_cleanup;
930 err = mlx5_sf_hw_table_init(dev);
932 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
933 goto err_sf_hw_table_cleanup;
936 err = mlx5_sf_table_init(dev);
938 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
939 goto err_sf_table_cleanup;
942 dev->dm = mlx5_dm_create(dev);
944 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
946 dev->tracer = mlx5_fw_tracer_create(dev);
947 dev->hv_vhca = mlx5_hv_vhca_create(dev);
948 dev->rsc_dump = mlx5_rsc_dump_create(dev);
952 err_sf_table_cleanup:
953 mlx5_sf_hw_table_cleanup(dev);
954 err_sf_hw_table_cleanup:
955 mlx5_vhca_event_cleanup(dev);
957 mlx5_fpga_cleanup(dev);
959 mlx5_eswitch_cleanup(dev->priv.eswitch);
961 mlx5_sriov_cleanup(dev);
963 mlx5_mpfs_cleanup(dev);
965 mlx5_cleanup_rl_table(dev);
967 mlx5_geneve_destroy(dev->geneve);
968 mlx5_vxlan_destroy(dev->vxlan);
969 mlx5_cq_debugfs_cleanup(dev);
970 mlx5_fw_reset_cleanup(dev);
972 mlx5_events_cleanup(dev);
974 mlx5_eq_table_cleanup(dev);
976 mlx5_irq_table_cleanup(dev);
978 mlx5_devcom_unregister_device(dev->priv.devcom);
983 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
985 mlx5_rsc_dump_destroy(dev);
986 mlx5_hv_vhca_destroy(dev->hv_vhca);
987 mlx5_fw_tracer_destroy(dev->tracer);
988 mlx5_dm_cleanup(dev);
989 mlx5_sf_table_cleanup(dev);
990 mlx5_sf_hw_table_cleanup(dev);
991 mlx5_vhca_event_cleanup(dev);
992 mlx5_fpga_cleanup(dev);
993 mlx5_eswitch_cleanup(dev->priv.eswitch);
994 mlx5_sriov_cleanup(dev);
995 mlx5_mpfs_cleanup(dev);
996 mlx5_cleanup_rl_table(dev);
997 mlx5_geneve_destroy(dev->geneve);
998 mlx5_vxlan_destroy(dev->vxlan);
999 mlx5_cleanup_clock(dev);
1000 mlx5_cleanup_reserved_gids(dev);
1001 mlx5_cq_debugfs_cleanup(dev);
1002 mlx5_fw_reset_cleanup(dev);
1003 mlx5_events_cleanup(dev);
1004 mlx5_eq_table_cleanup(dev);
1005 mlx5_irq_table_cleanup(dev);
1006 mlx5_devcom_unregister_device(dev->priv.devcom);
1009 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
1013 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1014 fw_rev_min(dev), fw_rev_sub(dev));
1016 /* Only PFs hold the relevant PCIe information for this query */
1017 if (mlx5_core_is_pf(dev))
1018 pcie_print_link_status(dev->pdev);
1020 mlx5_tout_set_def_val(dev);
1022 /* wait for firmware to accept initialization segments configurations
1024 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT),
1025 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL));
1027 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n",
1028 mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1032 err = mlx5_cmd_init(dev);
1034 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1038 mlx5_tout_query_iseg(dev);
1040 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0);
1042 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n",
1043 mlx5_tout_ms(dev, FW_INIT));
1044 goto err_cmd_cleanup;
1047 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1049 err = mlx5_core_enable_hca(dev, 0);
1051 mlx5_core_err(dev, "enable hca failed\n");
1052 goto err_cmd_cleanup;
1055 err = mlx5_core_set_issi(dev);
1057 mlx5_core_err(dev, "failed to set issi\n");
1058 goto err_disable_hca;
1061 err = mlx5_satisfy_startup_pages(dev, 1);
1063 mlx5_core_err(dev, "failed to allocate boot pages\n");
1064 goto err_disable_hca;
1067 err = mlx5_tout_query_dtor(dev);
1069 mlx5_core_err(dev, "failed to read dtor\n");
1070 goto reclaim_boot_pages;
1073 err = set_hca_ctrl(dev);
1075 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1076 goto reclaim_boot_pages;
1079 err = set_hca_cap(dev);
1081 mlx5_core_err(dev, "set_hca_cap failed\n");
1082 goto reclaim_boot_pages;
1085 err = mlx5_satisfy_startup_pages(dev, 0);
1087 mlx5_core_err(dev, "failed to allocate init pages\n");
1088 goto reclaim_boot_pages;
1091 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1093 mlx5_core_err(dev, "init hca failed\n");
1094 goto reclaim_boot_pages;
1097 mlx5_set_driver_version(dev);
1099 err = mlx5_query_hca_caps(dev);
1101 mlx5_core_err(dev, "query hca failed\n");
1102 goto reclaim_boot_pages;
1105 mlx5_start_health_poll(dev);
1110 mlx5_reclaim_startup_pages(dev);
1112 mlx5_core_disable_hca(dev, 0);
1114 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1115 mlx5_cmd_cleanup(dev);
1120 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1124 mlx5_stop_health_poll(dev, boot);
1125 err = mlx5_cmd_teardown_hca(dev);
1127 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1130 mlx5_reclaim_startup_pages(dev);
1131 mlx5_core_disable_hca(dev, 0);
1132 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1133 mlx5_cmd_cleanup(dev);
1138 static int mlx5_load(struct mlx5_core_dev *dev)
1142 dev->priv.uar = mlx5_get_uars_page(dev);
1143 if (IS_ERR(dev->priv.uar)) {
1144 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1145 err = PTR_ERR(dev->priv.uar);
1149 mlx5_events_start(dev);
1150 mlx5_pagealloc_start(dev);
1152 err = mlx5_irq_table_create(dev);
1154 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1158 err = mlx5_eq_table_create(dev);
1160 mlx5_core_err(dev, "Failed to create EQs\n");
1164 err = mlx5_fw_tracer_init(dev->tracer);
1166 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1167 mlx5_fw_tracer_destroy(dev->tracer);
1171 mlx5_fw_reset_events_start(dev);
1172 mlx5_hv_vhca_init(dev->hv_vhca);
1174 err = mlx5_rsc_dump_init(dev);
1176 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1177 mlx5_rsc_dump_destroy(dev);
1178 dev->rsc_dump = NULL;
1181 err = mlx5_fpga_device_start(dev);
1183 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1184 goto err_fpga_start;
1187 mlx5_accel_ipsec_init(dev);
1189 err = mlx5_accel_tls_init(dev);
1191 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1195 err = mlx5_init_fs(dev);
1197 mlx5_core_err(dev, "Failed to init flow steering\n");
1201 err = mlx5_core_set_hca_defaults(dev);
1203 mlx5_core_err(dev, "Failed to set hca defaults\n");
1207 mlx5_vhca_event_start(dev);
1209 err = mlx5_sf_hw_table_create(dev);
1211 mlx5_core_err(dev, "sf table create failed %d\n", err);
1215 err = mlx5_ec_init(dev);
1217 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1221 mlx5_lag_add_mdev(dev);
1222 err = mlx5_sriov_attach(dev);
1224 mlx5_core_err(dev, "sriov init failed %d\n", err);
1228 mlx5_sf_dev_table_create(dev);
1233 mlx5_lag_remove_mdev(dev);
1234 mlx5_ec_cleanup(dev);
1236 mlx5_sf_hw_table_destroy(dev);
1238 mlx5_vhca_event_stop(dev);
1240 mlx5_cleanup_fs(dev);
1242 mlx5_accel_tls_cleanup(dev);
1244 mlx5_accel_ipsec_cleanup(dev);
1245 mlx5_fpga_device_stop(dev);
1247 mlx5_rsc_dump_cleanup(dev);
1248 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1249 mlx5_fw_reset_events_stop(dev);
1250 mlx5_fw_tracer_cleanup(dev->tracer);
1251 mlx5_eq_table_destroy(dev);
1253 mlx5_irq_table_destroy(dev);
1255 mlx5_pagealloc_stop(dev);
1256 mlx5_events_stop(dev);
1257 mlx5_put_uars_page(dev, dev->priv.uar);
1261 static void mlx5_unload(struct mlx5_core_dev *dev)
1263 mlx5_sf_dev_table_destroy(dev);
1264 mlx5_sriov_detach(dev);
1265 mlx5_lag_remove_mdev(dev);
1266 mlx5_ec_cleanup(dev);
1267 mlx5_sf_hw_table_destroy(dev);
1268 mlx5_vhca_event_stop(dev);
1269 mlx5_cleanup_fs(dev);
1270 mlx5_accel_ipsec_cleanup(dev);
1271 mlx5_accel_tls_cleanup(dev);
1272 mlx5_fpga_device_stop(dev);
1273 mlx5_rsc_dump_cleanup(dev);
1274 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1275 mlx5_fw_reset_events_stop(dev);
1276 mlx5_fw_tracer_cleanup(dev->tracer);
1277 mlx5_eq_table_destroy(dev);
1278 mlx5_irq_table_destroy(dev);
1279 mlx5_pagealloc_stop(dev);
1280 mlx5_events_stop(dev);
1281 mlx5_put_uars_page(dev, dev->priv.uar);
1284 int mlx5_init_one(struct mlx5_core_dev *dev)
1288 mutex_lock(&dev->intf_state_mutex);
1289 dev->state = MLX5_DEVICE_STATE_UP;
1291 err = mlx5_function_setup(dev, true);
1295 err = mlx5_init_once(dev);
1297 mlx5_core_err(dev, "sw objs init failed\n");
1298 goto function_teardown;
1301 err = mlx5_load(dev);
1305 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1307 err = mlx5_devlink_register(priv_to_devlink(dev));
1309 goto err_devlink_reg;
1311 err = mlx5_register_device(dev);
1315 mutex_unlock(&dev->intf_state_mutex);
1319 mlx5_devlink_unregister(priv_to_devlink(dev));
1321 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1324 mlx5_cleanup_once(dev);
1326 mlx5_function_teardown(dev, true);
1328 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1329 mutex_unlock(&dev->intf_state_mutex);
1333 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1335 mutex_lock(&dev->intf_state_mutex);
1337 mlx5_unregister_device(dev);
1338 mlx5_devlink_unregister(priv_to_devlink(dev));
1340 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1341 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1343 mlx5_cleanup_once(dev);
1347 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1349 mlx5_cleanup_once(dev);
1350 mlx5_function_teardown(dev, true);
1352 mutex_unlock(&dev->intf_state_mutex);
1355 int mlx5_load_one(struct mlx5_core_dev *dev)
1359 mutex_lock(&dev->intf_state_mutex);
1360 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1361 mlx5_core_warn(dev, "interface is up, NOP\n");
1364 /* remove any previous indication of internal error */
1365 dev->state = MLX5_DEVICE_STATE_UP;
1367 err = mlx5_function_setup(dev, false);
1371 err = mlx5_load(dev);
1375 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1377 err = mlx5_attach_device(dev);
1381 mutex_unlock(&dev->intf_state_mutex);
1385 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1388 mlx5_function_teardown(dev, false);
1390 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1392 mutex_unlock(&dev->intf_state_mutex);
1396 void mlx5_unload_one(struct mlx5_core_dev *dev)
1398 mutex_lock(&dev->intf_state_mutex);
1400 mlx5_detach_device(dev);
1402 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1403 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1408 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1410 mlx5_function_teardown(dev, false);
1412 mutex_unlock(&dev->intf_state_mutex);
1415 static const int types[] = {
1418 MLX5_CAP_ETHERNET_OFFLOADS,
1419 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1423 MLX5_CAP_IPOIB_OFFLOADS,
1424 MLX5_CAP_FLOW_TABLE,
1425 MLX5_CAP_ESWITCH_FLOW_TABLE,
1427 MLX5_CAP_VECTOR_CALC,
1433 MLX5_CAP_VDPA_EMULATION,
1435 MLX5_CAP_PORT_SELECTION,
1436 MLX5_CAP_DEV_SHAMPO,
1439 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1444 for (i = 0; i < ARRAY_SIZE(types); i++) {
1446 kfree(dev->caps.hca[type]);
1450 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1452 struct mlx5_hca_cap *cap;
1456 for (i = 0; i < ARRAY_SIZE(types); i++) {
1457 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1461 dev->caps.hca[type] = cap;
1467 mlx5_hca_caps_free(dev);
1471 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1473 struct mlx5_priv *priv = &dev->priv;
1476 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1477 INIT_LIST_HEAD(&priv->ctx_list);
1478 spin_lock_init(&priv->ctx_lock);
1479 mutex_init(&dev->intf_state_mutex);
1481 mutex_init(&priv->bfregs.reg_head.lock);
1482 mutex_init(&priv->bfregs.wc_head.lock);
1483 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1484 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1486 mutex_init(&priv->alloc_mutex);
1487 mutex_init(&priv->pgdir_mutex);
1488 INIT_LIST_HEAD(&priv->pgdir_list);
1490 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1491 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1493 INIT_LIST_HEAD(&priv->traps);
1495 err = mlx5_tout_init(dev);
1497 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1498 goto err_timeout_init;
1501 err = mlx5_health_init(dev);
1503 goto err_health_init;
1505 err = mlx5_pagealloc_init(dev);
1507 goto err_pagealloc_init;
1509 err = mlx5_adev_init(dev);
1513 err = mlx5_hca_caps_alloc(dev);
1520 mlx5_adev_cleanup(dev);
1522 mlx5_pagealloc_cleanup(dev);
1524 mlx5_health_cleanup(dev);
1526 mlx5_tout_cleanup(dev);
1528 debugfs_remove(dev->priv.dbg_root);
1529 mutex_destroy(&priv->pgdir_mutex);
1530 mutex_destroy(&priv->alloc_mutex);
1531 mutex_destroy(&priv->bfregs.wc_head.lock);
1532 mutex_destroy(&priv->bfregs.reg_head.lock);
1533 mutex_destroy(&dev->intf_state_mutex);
1537 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1539 struct mlx5_priv *priv = &dev->priv;
1541 mlx5_hca_caps_free(dev);
1542 mlx5_adev_cleanup(dev);
1543 mlx5_pagealloc_cleanup(dev);
1544 mlx5_health_cleanup(dev);
1545 mlx5_tout_cleanup(dev);
1546 debugfs_remove_recursive(dev->priv.dbg_root);
1547 mutex_destroy(&priv->pgdir_mutex);
1548 mutex_destroy(&priv->alloc_mutex);
1549 mutex_destroy(&priv->bfregs.wc_head.lock);
1550 mutex_destroy(&priv->bfregs.reg_head.lock);
1551 mutex_destroy(&dev->intf_state_mutex);
1554 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1556 struct mlx5_core_dev *dev;
1557 struct devlink *devlink;
1560 devlink = mlx5_devlink_alloc(&pdev->dev);
1562 dev_err(&pdev->dev, "devlink alloc failed\n");
1566 dev = devlink_priv(devlink);
1567 dev->device = &pdev->dev;
1570 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1571 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1573 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1574 if (dev->priv.adev_idx < 0) {
1575 err = dev->priv.adev_idx;
1579 err = mlx5_mdev_init(dev, prof_sel);
1583 err = mlx5_pci_init(dev, pdev, id);
1585 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1590 err = mlx5_init_one(dev);
1592 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1597 err = mlx5_crdump_enable(dev);
1599 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1601 pci_save_state(pdev);
1602 devlink_register(devlink);
1606 mlx5_pci_close(dev);
1608 mlx5_mdev_uninit(dev);
1610 mlx5_adev_idx_free(dev->priv.adev_idx);
1612 mlx5_devlink_free(devlink);
1617 static void remove_one(struct pci_dev *pdev)
1619 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1620 struct devlink *devlink = priv_to_devlink(dev);
1622 devlink_unregister(devlink);
1623 mlx5_crdump_disable(dev);
1624 mlx5_drain_health_wq(dev);
1625 mlx5_uninit_one(dev);
1626 mlx5_pci_close(dev);
1627 mlx5_mdev_uninit(dev);
1628 mlx5_adev_idx_free(dev->priv.adev_idx);
1629 mlx5_devlink_free(devlink);
1632 #define mlx5_pci_trace(dev, fmt, ...) ({ \
1633 struct mlx5_core_dev *__dev = (dev); \
1634 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
1635 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
1636 __dev->pci_status, ##__VA_ARGS__); \
1639 static const char *result2str(enum pci_ers_result result)
1641 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
1642 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
1643 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
1647 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1648 pci_channel_state_t state)
1650 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1651 enum pci_ers_result res;
1653 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
1655 mlx5_enter_error_state(dev, false);
1656 mlx5_error_sw_reset(dev);
1657 mlx5_unload_one(dev);
1658 mlx5_drain_health_wq(dev);
1659 mlx5_pci_disable_device(dev);
1661 res = state == pci_channel_io_perm_failure ?
1662 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1664 mlx5_pci_trace(dev, "Exit, result = %d, %s\n", res, result2str(res));
1668 /* wait for the device to show vital signs by waiting
1669 * for the health counter to start counting.
1671 static int wait_vital(struct pci_dev *pdev)
1673 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1674 struct mlx5_core_health *health = &dev->priv.health;
1675 const int niter = 100;
1680 for (i = 0; i < niter; i++) {
1681 count = ioread32be(health->health_counter);
1682 if (count && count != 0xffffffff) {
1683 if (last_count && last_count != count) {
1685 "wait vital counter value 0x%x after %d iterations\n",
1697 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1699 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
1700 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1703 mlx5_pci_trace(dev, "Enter\n");
1705 err = mlx5_pci_enable_device(dev);
1707 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1712 pci_set_master(pdev);
1713 pci_restore_state(pdev);
1714 pci_save_state(pdev);
1716 err = wait_vital(pdev);
1718 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
1723 res = PCI_ERS_RESULT_RECOVERED;
1725 mlx5_pci_trace(dev, "Exit, err = %d, result = %d, %s\n", err, res, result2str(res));
1729 static void mlx5_pci_resume(struct pci_dev *pdev)
1731 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1734 mlx5_pci_trace(dev, "Enter, loading driver..\n");
1736 err = mlx5_load_one(dev);
1738 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
1739 !err ? "recovered" : "Failed");
1742 static const struct pci_error_handlers mlx5_err_handler = {
1743 .error_detected = mlx5_pci_err_detected,
1744 .slot_reset = mlx5_pci_slot_reset,
1745 .resume = mlx5_pci_resume
1748 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1750 bool fast_teardown = false, force_teardown = false;
1753 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1754 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1756 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1757 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1759 if (!fast_teardown && !force_teardown)
1762 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1763 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1767 /* Panic tear down fw command will stop the PCI bus communication
1768 * with the HCA, so the health polll is no longer needed.
1770 mlx5_drain_health_wq(dev);
1771 mlx5_stop_health_poll(dev, false);
1773 ret = mlx5_cmd_fast_teardown_hca(dev);
1777 ret = mlx5_cmd_force_teardown_hca(dev);
1781 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1782 mlx5_start_health_poll(dev);
1786 mlx5_enter_error_state(dev, true);
1788 /* Some platforms requiring freeing the IRQ's in the shutdown
1789 * flow. If they aren't freed they can't be allocated after
1790 * kexec. There is no need to cleanup the mlx5_core software
1793 mlx5_core_eq_free_irqs(dev);
1798 static void shutdown(struct pci_dev *pdev)
1800 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1803 mlx5_core_info(dev, "Shutdown was called\n");
1804 err = mlx5_try_fast_unload(dev);
1806 mlx5_unload_one(dev);
1807 mlx5_pci_disable_device(dev);
1810 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1812 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1814 mlx5_unload_one(dev);
1819 static int mlx5_resume(struct pci_dev *pdev)
1821 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1823 return mlx5_load_one(dev);
1826 static const struct pci_device_id mlx5_core_pci_table[] = {
1827 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1828 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1829 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1830 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1831 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1832 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1833 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1834 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1835 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1836 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1837 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1838 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1839 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1840 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1841 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1842 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1843 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
1844 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1845 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1846 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1847 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
1848 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
1852 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1854 void mlx5_disable_device(struct mlx5_core_dev *dev)
1856 mlx5_error_sw_reset(dev);
1857 mlx5_unload_one(dev);
1860 int mlx5_recover_device(struct mlx5_core_dev *dev)
1862 if (!mlx5_core_is_sf(dev)) {
1863 mlx5_pci_disable_device(dev);
1864 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
1868 return mlx5_load_one(dev);
1871 static struct pci_driver mlx5_core_driver = {
1872 .name = KBUILD_MODNAME,
1873 .id_table = mlx5_core_pci_table,
1875 .remove = remove_one,
1876 .suspend = mlx5_suspend,
1877 .resume = mlx5_resume,
1878 .shutdown = shutdown,
1879 .err_handler = &mlx5_err_handler,
1880 .sriov_configure = mlx5_core_sriov_configure,
1881 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
1882 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
1885 static void mlx5_core_verify_params(void)
1887 if (prof_sel >= ARRAY_SIZE(profile)) {
1888 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1890 ARRAY_SIZE(profile) - 1,
1892 prof_sel = MLX5_DEFAULT_PROF;
1896 static int __init init(void)
1900 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
1901 "mlx5_core name not in sync with kernel module name");
1903 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1905 mlx5_core_verify_params();
1906 mlx5_fpga_ipsec_build_fs_cmds();
1907 mlx5_register_debugfs();
1909 err = pci_register_driver(&mlx5_core_driver);
1913 err = mlx5_sf_driver_register();
1924 mlx5_sf_driver_unregister();
1926 pci_unregister_driver(&mlx5_core_driver);
1928 mlx5_unregister_debugfs();
1932 static void __exit cleanup(void)
1935 mlx5_sf_driver_unregister();
1936 pci_unregister_driver(&mlx5_core_driver);
1937 mlx5_unregister_debugfs();
1941 module_exit(cleanup);