2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
61 #include "fpga/core.h"
62 #include "fpga/ipsec.h"
63 #include "accel/ipsec.h"
64 #include "accel/tls.h"
65 #include "lib/clock.h"
66 #include "lib/vxlan.h"
67 #include "lib/geneve.h"
68 #include "lib/devcom.h"
69 #include "lib/pci_vsc.h"
70 #include "diag/fw_tracer.h"
72 #include "lib/hv_vhca.h"
73 #include "diag/rsc_dump.h"
75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
77 MODULE_LICENSE("Dual BSD/GPL");
78 MODULE_VERSION(DRIVER_VERSION);
80 unsigned int mlx5_core_debug_mask;
81 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
82 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
84 #define MLX5_DEFAULT_PROF 2
85 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
86 module_param_named(prof_sel, prof_sel, uint, 0444);
87 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
89 static u32 sw_owner_id[4];
92 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
93 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
96 static struct mlx5_profile profile[] = {
101 .mask = MLX5_PROF_MASK_QP_SIZE,
105 .mask = MLX5_PROF_MASK_QP_SIZE |
106 MLX5_PROF_MASK_MR_CACHE,
175 #define FW_INIT_TIMEOUT_MILI 2000
176 #define FW_INIT_WAIT_MS 2
177 #define FW_PRE_INIT_TIMEOUT_MILI 120000
178 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
180 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
183 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
184 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
187 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL);
189 while (fw_initializing(dev)) {
190 if (time_after(jiffies, end)) {
194 if (warn_time_mili && time_after(jiffies, warn)) {
195 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
196 jiffies_to_msecs(end - warn) / 1000);
197 warn = jiffies + msecs_to_jiffies(warn_time_mili);
199 msleep(FW_INIT_WAIT_MS);
205 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
207 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
209 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
210 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
211 int remaining_size = driver_ver_sz;
214 if (!MLX5_CAP_GEN(dev, driver_version))
217 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
219 strncpy(string, "Linux", remaining_size);
221 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
222 strncat(string, ",", remaining_size);
224 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
225 strncat(string, DRIVER_NAME, remaining_size);
227 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
228 strncat(string, ",", remaining_size);
230 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
231 strncat(string, DRIVER_VERSION, remaining_size);
234 MLX5_SET(set_driver_version_in, in, opcode,
235 MLX5_CMD_OP_SET_DRIVER_VERSION);
237 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
240 static int set_dma_caps(struct pci_dev *pdev)
244 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
246 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
247 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
249 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
254 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
257 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
258 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
261 "Can't set consistent PCI DMA mask, aborting\n");
266 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
270 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
272 struct pci_dev *pdev = dev->pdev;
275 mutex_lock(&dev->pci_status_mutex);
276 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
277 err = pci_enable_device(pdev);
279 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
281 mutex_unlock(&dev->pci_status_mutex);
286 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
288 struct pci_dev *pdev = dev->pdev;
290 mutex_lock(&dev->pci_status_mutex);
291 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
292 pci_disable_device(pdev);
293 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
295 mutex_unlock(&dev->pci_status_mutex);
298 static int request_bar(struct pci_dev *pdev)
302 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
303 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
307 err = pci_request_regions(pdev, DRIVER_NAME);
309 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
314 static void release_bar(struct pci_dev *pdev)
316 pci_release_regions(pdev);
319 struct mlx5_reg_host_endianness {
324 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
327 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
328 MLX5_DEV_CAP_FLAG_DCT,
331 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
347 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
352 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
353 enum mlx5_cap_type cap_type,
354 enum mlx5_cap_mode cap_mode)
356 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
357 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
358 void *out, *hca_caps;
359 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
362 memset(in, 0, sizeof(in));
363 out = kzalloc(out_sz, GFP_KERNEL);
367 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
368 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
369 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
372 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
373 cap_type, cap_mode, err);
377 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
380 case HCA_CAP_OPMOD_GET_MAX:
381 memcpy(dev->caps.hca_max[cap_type], hca_caps,
382 MLX5_UN_SZ_BYTES(hca_cap_union));
384 case HCA_CAP_OPMOD_GET_CUR:
385 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
386 MLX5_UN_SZ_BYTES(hca_cap_union));
390 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
400 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
404 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
407 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
410 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
412 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
414 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
415 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
416 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
419 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
423 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
427 if (MLX5_CAP_GEN(dev, atomic)) {
428 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
437 supported_atomic_req_8B_endianness_mode_1);
439 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
442 set_ctx = kzalloc(set_sz, GFP_KERNEL);
446 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
448 /* Set requestor to host endianness */
449 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
450 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
452 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
458 static int handle_hca_cap_odp(struct mlx5_core_dev *dev)
466 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
467 !MLX5_CAP_GEN(dev, pg))
470 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
474 set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
475 set_ctx = kzalloc(set_sz, GFP_KERNEL);
479 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
480 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
481 MLX5_ST_SZ_BYTES(odp_cap));
483 #define ODP_CAP_SET_MAX(dev, field) \
485 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
488 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
492 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
493 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
494 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
495 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
496 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
497 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
498 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
499 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
500 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
501 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
502 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
503 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
504 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
505 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
508 err = set_caps(dev, set_ctx, set_sz,
509 MLX5_SET_HCA_CAP_OP_MOD_ODP);
516 static int handle_hca_cap(struct mlx5_core_dev *dev)
518 void *set_ctx = NULL;
519 struct mlx5_profile *prof = dev->profile;
521 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
524 set_ctx = kzalloc(set_sz, GFP_KERNEL);
528 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
532 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
534 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
535 MLX5_ST_SZ_BYTES(cmd_hca_cap));
537 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
538 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
540 /* we limit the size of the pkey table to 128 entries for now */
541 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
542 to_fw_pkey_sz(dev, 128));
544 /* Check log_max_qp from HCA caps to set in current profile */
545 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
546 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
547 profile[prof_sel].log_max_qp,
548 MLX5_CAP_GEN_MAX(dev, log_max_qp));
549 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
551 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
552 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
555 /* disable cmdif checksum */
556 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
558 /* Enable 4K UAR only when HCA supports it and page size is bigger
561 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
562 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
564 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
566 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
567 MLX5_SET(cmd_hca_cap,
570 cache_line_size() >= 128 ? 1 : 0);
572 if (MLX5_CAP_GEN_MAX(dev, dct))
573 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
575 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
576 MLX5_SET(cmd_hca_cap,
579 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
581 err = set_caps(dev, set_ctx, set_sz,
582 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
589 static int set_hca_cap(struct mlx5_core_dev *dev)
593 err = handle_hca_cap(dev);
595 mlx5_core_err(dev, "handle_hca_cap failed\n");
599 err = handle_hca_cap_atomic(dev);
601 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
605 err = handle_hca_cap_odp(dev);
607 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
615 static int set_hca_ctrl(struct mlx5_core_dev *dev)
617 struct mlx5_reg_host_endianness he_in;
618 struct mlx5_reg_host_endianness he_out;
621 if (!mlx5_core_is_pf(dev))
624 memset(&he_in, 0, sizeof(he_in));
625 he_in.he = MLX5_SET_HOST_ENDIANNESS;
626 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
627 &he_out, sizeof(he_out),
628 MLX5_REG_HOST_ENDIANNESS, 0, 1);
632 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
636 /* Disable local_lb by default */
637 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
638 ret = mlx5_nic_vport_update_local_lb(dev, false);
643 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
645 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
646 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
648 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
649 MLX5_SET(enable_hca_in, in, function_id, func_id);
650 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
651 dev->caps.embedded_cpu);
652 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
655 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
657 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
658 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
660 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
661 MLX5_SET(disable_hca_in, in, function_id, func_id);
662 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
663 dev->caps.embedded_cpu);
664 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
667 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
668 struct ptp_system_timestamp *sts)
670 u32 timer_h, timer_h1, timer_l;
672 timer_h = ioread32be(&dev->iseg->internal_timer_h);
673 ptp_read_system_prets(sts);
674 timer_l = ioread32be(&dev->iseg->internal_timer_l);
675 ptp_read_system_postts(sts);
676 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
677 if (timer_h != timer_h1) {
679 ptp_read_system_prets(sts);
680 timer_l = ioread32be(&dev->iseg->internal_timer_l);
681 ptp_read_system_postts(sts);
684 return (u64)timer_l | (u64)timer_h1 << 32;
687 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
689 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
690 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
694 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
695 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
696 query_out, sizeof(query_out));
701 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
702 if (!status || syndrome == MLX5_DRIVER_SYND) {
703 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
704 err, status, syndrome);
708 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
713 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
715 if (sup_issi & (1 << 1)) {
716 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
717 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
719 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
720 MLX5_SET(set_issi_in, set_in, current_issi, 1);
721 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
722 set_out, sizeof(set_out));
724 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
732 } else if (sup_issi & (1 << 0) || !sup_issi) {
739 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
740 const struct pci_device_id *id)
742 struct mlx5_priv *priv = &dev->priv;
745 mutex_init(&dev->pci_status_mutex);
746 pci_set_drvdata(dev->pdev, dev);
748 dev->bar_addr = pci_resource_start(pdev, 0);
749 priv->numa_node = dev_to_node(&dev->pdev->dev);
751 err = mlx5_pci_enable_device(dev);
753 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
757 err = request_bar(pdev);
759 mlx5_core_err(dev, "error requesting BARs, aborting\n");
763 pci_set_master(pdev);
765 err = set_dma_caps(pdev);
767 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
771 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
772 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
773 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
774 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
776 dev->iseg_base = dev->bar_addr;
777 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
780 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
784 mlx5_pci_vsc_init(dev);
785 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
789 pci_clear_master(dev->pdev);
790 release_bar(dev->pdev);
792 mlx5_pci_disable_device(dev);
796 static void mlx5_pci_close(struct mlx5_core_dev *dev)
799 pci_clear_master(dev->pdev);
800 release_bar(dev->pdev);
801 mlx5_pci_disable_device(dev);
804 static int mlx5_init_once(struct mlx5_core_dev *dev)
808 dev->priv.devcom = mlx5_devcom_register_device(dev);
809 if (IS_ERR(dev->priv.devcom))
810 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
813 err = mlx5_query_board_id(dev);
815 mlx5_core_err(dev, "query board id failed\n");
819 err = mlx5_irq_table_init(dev);
821 mlx5_core_err(dev, "failed to initialize irq table\n");
825 err = mlx5_eq_table_init(dev);
827 mlx5_core_err(dev, "failed to initialize eq\n");
828 goto err_irq_cleanup;
831 err = mlx5_events_init(dev);
833 mlx5_core_err(dev, "failed to initialize events\n");
837 mlx5_cq_debugfs_init(dev);
839 mlx5_init_qp_table(dev);
841 mlx5_init_reserved_gids(dev);
843 mlx5_init_clock(dev);
845 dev->vxlan = mlx5_vxlan_create(dev);
846 dev->geneve = mlx5_geneve_create(dev);
848 err = mlx5_init_rl_table(dev);
850 mlx5_core_err(dev, "Failed to init rate limiting\n");
851 goto err_tables_cleanup;
854 err = mlx5_mpfs_init(dev);
856 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
860 err = mlx5_sriov_init(dev);
862 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
863 goto err_mpfs_cleanup;
866 err = mlx5_eswitch_init(dev);
868 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
869 goto err_sriov_cleanup;
872 err = mlx5_fpga_init(dev);
874 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
875 goto err_eswitch_cleanup;
878 dev->dm = mlx5_dm_create(dev);
880 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
882 dev->tracer = mlx5_fw_tracer_create(dev);
883 dev->hv_vhca = mlx5_hv_vhca_create(dev);
884 dev->rsc_dump = mlx5_rsc_dump_create(dev);
889 mlx5_eswitch_cleanup(dev->priv.eswitch);
891 mlx5_sriov_cleanup(dev);
893 mlx5_mpfs_cleanup(dev);
895 mlx5_cleanup_rl_table(dev);
897 mlx5_geneve_destroy(dev->geneve);
898 mlx5_vxlan_destroy(dev->vxlan);
899 mlx5_cleanup_qp_table(dev);
900 mlx5_cq_debugfs_cleanup(dev);
901 mlx5_events_cleanup(dev);
903 mlx5_eq_table_cleanup(dev);
905 mlx5_irq_table_cleanup(dev);
907 mlx5_devcom_unregister_device(dev->priv.devcom);
912 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
914 mlx5_rsc_dump_destroy(dev);
915 mlx5_hv_vhca_destroy(dev->hv_vhca);
916 mlx5_fw_tracer_destroy(dev->tracer);
917 mlx5_dm_cleanup(dev);
918 mlx5_fpga_cleanup(dev);
919 mlx5_eswitch_cleanup(dev->priv.eswitch);
920 mlx5_sriov_cleanup(dev);
921 mlx5_mpfs_cleanup(dev);
922 mlx5_cleanup_rl_table(dev);
923 mlx5_geneve_destroy(dev->geneve);
924 mlx5_vxlan_destroy(dev->vxlan);
925 mlx5_cleanup_clock(dev);
926 mlx5_cleanup_reserved_gids(dev);
927 mlx5_cleanup_qp_table(dev);
928 mlx5_cq_debugfs_cleanup(dev);
929 mlx5_events_cleanup(dev);
930 mlx5_eq_table_cleanup(dev);
931 mlx5_irq_table_cleanup(dev);
932 mlx5_devcom_unregister_device(dev->priv.devcom);
935 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
939 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
940 fw_rev_min(dev), fw_rev_sub(dev));
942 /* Only PFs hold the relevant PCIe information for this query */
943 if (mlx5_core_is_pf(dev))
944 pcie_print_link_status(dev->pdev);
946 /* wait for firmware to accept initialization segments configurations
948 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL);
950 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
951 FW_PRE_INIT_TIMEOUT_MILI);
955 err = mlx5_cmd_init(dev);
957 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
961 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
963 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
964 FW_INIT_TIMEOUT_MILI);
965 goto err_cmd_cleanup;
968 err = mlx5_core_enable_hca(dev, 0);
970 mlx5_core_err(dev, "enable hca failed\n");
971 goto err_cmd_cleanup;
974 err = mlx5_core_set_issi(dev);
976 mlx5_core_err(dev, "failed to set issi\n");
977 goto err_disable_hca;
980 err = mlx5_satisfy_startup_pages(dev, 1);
982 mlx5_core_err(dev, "failed to allocate boot pages\n");
983 goto err_disable_hca;
986 err = set_hca_ctrl(dev);
988 mlx5_core_err(dev, "set_hca_ctrl failed\n");
989 goto reclaim_boot_pages;
992 err = set_hca_cap(dev);
994 mlx5_core_err(dev, "set_hca_cap failed\n");
995 goto reclaim_boot_pages;
998 err = mlx5_satisfy_startup_pages(dev, 0);
1000 mlx5_core_err(dev, "failed to allocate init pages\n");
1001 goto reclaim_boot_pages;
1004 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1006 mlx5_core_err(dev, "init hca failed\n");
1007 goto reclaim_boot_pages;
1010 mlx5_set_driver_version(dev);
1012 mlx5_start_health_poll(dev);
1014 err = mlx5_query_hca_caps(dev);
1016 mlx5_core_err(dev, "query hca failed\n");
1023 mlx5_stop_health_poll(dev, boot);
1025 mlx5_reclaim_startup_pages(dev);
1027 mlx5_core_disable_hca(dev, 0);
1029 mlx5_cmd_cleanup(dev);
1034 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1038 mlx5_stop_health_poll(dev, boot);
1039 err = mlx5_cmd_teardown_hca(dev);
1041 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1044 mlx5_reclaim_startup_pages(dev);
1045 mlx5_core_disable_hca(dev, 0);
1046 mlx5_cmd_cleanup(dev);
1051 static int mlx5_load(struct mlx5_core_dev *dev)
1055 dev->priv.uar = mlx5_get_uars_page(dev);
1056 if (IS_ERR(dev->priv.uar)) {
1057 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1058 err = PTR_ERR(dev->priv.uar);
1062 mlx5_events_start(dev);
1063 mlx5_pagealloc_start(dev);
1065 err = mlx5_irq_table_create(dev);
1067 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1071 err = mlx5_eq_table_create(dev);
1073 mlx5_core_err(dev, "Failed to create EQs\n");
1077 err = mlx5_fw_tracer_init(dev->tracer);
1079 mlx5_core_err(dev, "Failed to init FW tracer\n");
1083 mlx5_hv_vhca_init(dev->hv_vhca);
1085 err = mlx5_rsc_dump_init(dev);
1087 mlx5_core_err(dev, "Failed to init Resource dump\n");
1091 err = mlx5_fpga_device_start(dev);
1093 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1094 goto err_fpga_start;
1097 err = mlx5_accel_ipsec_init(dev);
1099 mlx5_core_err(dev, "IPSec device start failed %d\n", err);
1100 goto err_ipsec_start;
1103 err = mlx5_accel_tls_init(dev);
1105 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1109 err = mlx5_init_fs(dev);
1111 mlx5_core_err(dev, "Failed to init flow steering\n");
1115 err = mlx5_core_set_hca_defaults(dev);
1117 mlx5_core_err(dev, "Failed to set hca defaults\n");
1121 err = mlx5_sriov_attach(dev);
1123 mlx5_core_err(dev, "sriov init failed %d\n", err);
1127 err = mlx5_ec_init(dev);
1129 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1136 mlx5_sriov_detach(dev);
1138 mlx5_cleanup_fs(dev);
1140 mlx5_accel_tls_cleanup(dev);
1142 mlx5_accel_ipsec_cleanup(dev);
1144 mlx5_fpga_device_stop(dev);
1146 mlx5_rsc_dump_cleanup(dev);
1148 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1149 mlx5_fw_tracer_cleanup(dev->tracer);
1151 mlx5_eq_table_destroy(dev);
1153 mlx5_irq_table_destroy(dev);
1155 mlx5_pagealloc_stop(dev);
1156 mlx5_events_stop(dev);
1157 mlx5_put_uars_page(dev, dev->priv.uar);
1161 static void mlx5_unload(struct mlx5_core_dev *dev)
1163 mlx5_ec_cleanup(dev);
1164 mlx5_sriov_detach(dev);
1165 mlx5_cleanup_fs(dev);
1166 mlx5_accel_ipsec_cleanup(dev);
1167 mlx5_accel_tls_cleanup(dev);
1168 mlx5_fpga_device_stop(dev);
1169 mlx5_rsc_dump_cleanup(dev);
1170 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1171 mlx5_fw_tracer_cleanup(dev->tracer);
1172 mlx5_eq_table_destroy(dev);
1173 mlx5_irq_table_destroy(dev);
1174 mlx5_pagealloc_stop(dev);
1175 mlx5_events_stop(dev);
1176 mlx5_put_uars_page(dev, dev->priv.uar);
1179 int mlx5_load_one(struct mlx5_core_dev *dev, bool boot)
1183 mutex_lock(&dev->intf_state_mutex);
1184 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1185 mlx5_core_warn(dev, "interface is up, NOP\n");
1188 /* remove any previous indication of internal error */
1189 dev->state = MLX5_DEVICE_STATE_UP;
1191 err = mlx5_function_setup(dev, boot);
1196 err = mlx5_init_once(dev);
1198 mlx5_core_err(dev, "sw objs init failed\n");
1199 goto function_teardown;
1203 err = mlx5_load(dev);
1208 err = mlx5_devlink_register(priv_to_devlink(dev), dev->device);
1210 goto err_devlink_reg;
1213 if (mlx5_device_registered(dev))
1214 mlx5_attach_device(dev);
1216 mlx5_register_device(dev);
1218 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1220 mutex_unlock(&dev->intf_state_mutex);
1228 mlx5_cleanup_once(dev);
1230 mlx5_function_teardown(dev, boot);
1231 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1232 mutex_unlock(&dev->intf_state_mutex);
1237 void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup)
1240 mlx5_unregister_device(dev);
1241 mlx5_drain_health_wq(dev);
1244 mutex_lock(&dev->intf_state_mutex);
1245 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1246 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1249 mlx5_cleanup_once(dev);
1253 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1255 if (mlx5_device_registered(dev))
1256 mlx5_detach_device(dev);
1261 mlx5_cleanup_once(dev);
1263 mlx5_function_teardown(dev, cleanup);
1265 mutex_unlock(&dev->intf_state_mutex);
1268 static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1270 struct mlx5_priv *priv = &dev->priv;
1273 dev->profile = &profile[profile_idx];
1275 INIT_LIST_HEAD(&priv->ctx_list);
1276 spin_lock_init(&priv->ctx_lock);
1277 mutex_init(&dev->intf_state_mutex);
1279 mutex_init(&priv->bfregs.reg_head.lock);
1280 mutex_init(&priv->bfregs.wc_head.lock);
1281 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1282 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1284 mutex_init(&priv->alloc_mutex);
1285 mutex_init(&priv->pgdir_mutex);
1286 INIT_LIST_HEAD(&priv->pgdir_list);
1288 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1290 if (!priv->dbg_root) {
1291 dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n");
1295 err = mlx5_health_init(dev);
1297 goto err_health_init;
1299 err = mlx5_pagealloc_init(dev);
1301 goto err_pagealloc_init;
1306 mlx5_health_cleanup(dev);
1308 debugfs_remove(dev->priv.dbg_root);
1313 static void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1315 mlx5_pagealloc_cleanup(dev);
1316 mlx5_health_cleanup(dev);
1317 debugfs_remove_recursive(dev->priv.dbg_root);
1320 #define MLX5_IB_MOD "mlx5_ib"
1321 static int init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1323 struct mlx5_core_dev *dev;
1324 struct devlink *devlink;
1327 devlink = mlx5_devlink_alloc();
1329 dev_err(&pdev->dev, "devlink alloc failed\n");
1333 dev = devlink_priv(devlink);
1334 dev->device = &pdev->dev;
1337 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1338 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1340 err = mlx5_mdev_init(dev, prof_sel);
1344 err = mlx5_pci_init(dev, pdev, id);
1346 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1351 err = mlx5_load_one(dev, true);
1353 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n",
1358 request_module_nowait(MLX5_IB_MOD);
1360 err = mlx5_crdump_enable(dev);
1362 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1364 pci_save_state(pdev);
1368 mlx5_pci_close(dev);
1370 mlx5_mdev_uninit(dev);
1372 mlx5_devlink_free(devlink);
1377 static void remove_one(struct pci_dev *pdev)
1379 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1380 struct devlink *devlink = priv_to_devlink(dev);
1382 mlx5_crdump_disable(dev);
1383 mlx5_devlink_unregister(devlink);
1385 mlx5_unload_one(dev, true);
1386 mlx5_pci_close(dev);
1387 mlx5_mdev_uninit(dev);
1388 mlx5_devlink_free(devlink);
1391 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1392 pci_channel_state_t state)
1394 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1396 mlx5_core_info(dev, "%s was called\n", __func__);
1398 mlx5_enter_error_state(dev, false);
1399 mlx5_error_sw_reset(dev);
1400 mlx5_unload_one(dev, false);
1401 mlx5_drain_health_wq(dev);
1402 mlx5_pci_disable_device(dev);
1404 return state == pci_channel_io_perm_failure ?
1405 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1408 /* wait for the device to show vital signs by waiting
1409 * for the health counter to start counting.
1411 static int wait_vital(struct pci_dev *pdev)
1413 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1414 struct mlx5_core_health *health = &dev->priv.health;
1415 const int niter = 100;
1420 for (i = 0; i < niter; i++) {
1421 count = ioread32be(health->health_counter);
1422 if (count && count != 0xffffffff) {
1423 if (last_count && last_count != count) {
1425 "wait vital counter value 0x%x after %d iterations\n",
1437 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1439 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1442 mlx5_core_info(dev, "%s was called\n", __func__);
1444 err = mlx5_pci_enable_device(dev);
1446 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1448 return PCI_ERS_RESULT_DISCONNECT;
1451 pci_set_master(pdev);
1452 pci_restore_state(pdev);
1453 pci_save_state(pdev);
1455 if (wait_vital(pdev)) {
1456 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1457 return PCI_ERS_RESULT_DISCONNECT;
1460 return PCI_ERS_RESULT_RECOVERED;
1463 static void mlx5_pci_resume(struct pci_dev *pdev)
1465 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1468 mlx5_core_info(dev, "%s was called\n", __func__);
1470 err = mlx5_load_one(dev, false);
1472 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1475 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1478 static const struct pci_error_handlers mlx5_err_handler = {
1479 .error_detected = mlx5_pci_err_detected,
1480 .slot_reset = mlx5_pci_slot_reset,
1481 .resume = mlx5_pci_resume
1484 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1486 bool fast_teardown = false, force_teardown = false;
1489 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1490 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1492 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1493 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1495 if (!fast_teardown && !force_teardown)
1498 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1499 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1503 /* Panic tear down fw command will stop the PCI bus communication
1504 * with the HCA, so the health polll is no longer needed.
1506 mlx5_drain_health_wq(dev);
1507 mlx5_stop_health_poll(dev, false);
1509 ret = mlx5_cmd_fast_teardown_hca(dev);
1513 ret = mlx5_cmd_force_teardown_hca(dev);
1517 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1518 mlx5_start_health_poll(dev);
1522 mlx5_enter_error_state(dev, true);
1524 /* Some platforms requiring freeing the IRQ's in the shutdown
1525 * flow. If they aren't freed they can't be allocated after
1526 * kexec. There is no need to cleanup the mlx5_core software
1529 mlx5_core_eq_free_irqs(dev);
1534 static void shutdown(struct pci_dev *pdev)
1536 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1539 mlx5_core_info(dev, "Shutdown was called\n");
1540 err = mlx5_try_fast_unload(dev);
1542 mlx5_unload_one(dev, false);
1543 mlx5_pci_disable_device(dev);
1546 static const struct pci_device_id mlx5_core_pci_table[] = {
1547 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1548 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1549 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1550 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1551 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1552 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1553 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1554 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1555 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1556 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1557 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1558 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1559 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1560 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1561 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1562 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1563 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1564 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1565 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1569 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1571 void mlx5_disable_device(struct mlx5_core_dev *dev)
1573 mlx5_error_sw_reset(dev);
1574 mlx5_unload_one(dev, false);
1577 void mlx5_recover_device(struct mlx5_core_dev *dev)
1579 mlx5_pci_disable_device(dev);
1580 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1581 mlx5_pci_resume(dev->pdev);
1584 static struct pci_driver mlx5_core_driver = {
1585 .name = DRIVER_NAME,
1586 .id_table = mlx5_core_pci_table,
1588 .remove = remove_one,
1589 .shutdown = shutdown,
1590 .err_handler = &mlx5_err_handler,
1591 .sriov_configure = mlx5_core_sriov_configure,
1594 static void mlx5_core_verify_params(void)
1596 if (prof_sel >= ARRAY_SIZE(profile)) {
1597 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1599 ARRAY_SIZE(profile) - 1,
1601 prof_sel = MLX5_DEFAULT_PROF;
1605 static int __init init(void)
1609 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1611 mlx5_core_verify_params();
1612 mlx5_accel_ipsec_build_fs_cmds();
1613 mlx5_register_debugfs();
1615 err = pci_register_driver(&mlx5_core_driver);
1619 #ifdef CONFIG_MLX5_CORE_EN
1626 mlx5_unregister_debugfs();
1630 static void __exit cleanup(void)
1632 #ifdef CONFIG_MLX5_CORE_EN
1635 pci_unregister_driver(&mlx5_core_driver);
1636 mlx5_unregister_debugfs();
1640 module_exit(cleanup);