2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
61 #include "fpga/core.h"
62 #include "fpga/ipsec.h"
63 #include "accel/ipsec.h"
64 #include "accel/tls.h"
65 #include "lib/clock.h"
66 #include "lib/vxlan.h"
67 #include "lib/geneve.h"
68 #include "lib/devcom.h"
69 #include "lib/pci_vsc.h"
70 #include "diag/fw_tracer.h"
72 #include "lib/hv_vhca.h"
73 #include "diag/rsc_dump.h"
75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
77 MODULE_LICENSE("Dual BSD/GPL");
78 MODULE_VERSION(DRIVER_VERSION);
80 unsigned int mlx5_core_debug_mask;
81 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
82 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
84 #define MLX5_DEFAULT_PROF 2
85 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
86 module_param_named(prof_sel, prof_sel, uint, 0444);
87 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
89 static u32 sw_owner_id[4];
92 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
93 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
96 static struct mlx5_profile profile[] = {
101 .mask = MLX5_PROF_MASK_QP_SIZE,
105 .mask = MLX5_PROF_MASK_QP_SIZE |
106 MLX5_PROF_MASK_MR_CACHE,
175 #define FW_INIT_TIMEOUT_MILI 2000
176 #define FW_INIT_WAIT_MS 2
177 #define FW_PRE_INIT_TIMEOUT_MILI 120000
178 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
180 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
183 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
184 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
187 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL);
189 while (fw_initializing(dev)) {
190 if (time_after(jiffies, end)) {
194 if (warn_time_mili && time_after(jiffies, warn)) {
195 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
196 jiffies_to_msecs(end - warn) / 1000);
197 warn = jiffies + msecs_to_jiffies(warn_time_mili);
199 msleep(FW_INIT_WAIT_MS);
205 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
207 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
209 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
210 int remaining_size = driver_ver_sz;
213 if (!MLX5_CAP_GEN(dev, driver_version))
216 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
218 strncpy(string, "Linux", remaining_size);
220 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
221 strncat(string, ",", remaining_size);
223 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
224 strncat(string, DRIVER_NAME, remaining_size);
226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
227 strncat(string, ",", remaining_size);
229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
230 strncat(string, DRIVER_VERSION, remaining_size);
233 MLX5_SET(set_driver_version_in, in, opcode,
234 MLX5_CMD_OP_SET_DRIVER_VERSION);
236 mlx5_cmd_exec_in(dev, set_driver_version, in);
239 static int set_dma_caps(struct pci_dev *pdev)
243 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
245 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
246 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
248 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
253 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
256 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
257 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
260 "Can't set consistent PCI DMA mask, aborting\n");
265 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
269 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
271 struct pci_dev *pdev = dev->pdev;
274 mutex_lock(&dev->pci_status_mutex);
275 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
276 err = pci_enable_device(pdev);
278 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
280 mutex_unlock(&dev->pci_status_mutex);
285 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
287 struct pci_dev *pdev = dev->pdev;
289 mutex_lock(&dev->pci_status_mutex);
290 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
291 pci_disable_device(pdev);
292 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
294 mutex_unlock(&dev->pci_status_mutex);
297 static int request_bar(struct pci_dev *pdev)
301 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
302 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
306 err = pci_request_regions(pdev, DRIVER_NAME);
308 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
313 static void release_bar(struct pci_dev *pdev)
315 pci_release_regions(pdev);
318 struct mlx5_reg_host_endianness {
323 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
326 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
327 MLX5_DEV_CAP_FLAG_DCT,
330 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
346 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
351 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
352 enum mlx5_cap_type cap_type,
353 enum mlx5_cap_mode cap_mode)
355 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
356 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
357 void *out, *hca_caps;
358 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
361 memset(in, 0, sizeof(in));
362 out = kzalloc(out_sz, GFP_KERNEL);
366 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
367 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
368 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
371 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
372 cap_type, cap_mode, err);
376 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
379 case HCA_CAP_OPMOD_GET_MAX:
380 memcpy(dev->caps.hca_max[cap_type], hca_caps,
381 MLX5_UN_SZ_BYTES(hca_cap_union));
383 case HCA_CAP_OPMOD_GET_CUR:
384 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
385 MLX5_UN_SZ_BYTES(hca_cap_union));
389 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
399 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
403 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
406 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
409 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
411 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
412 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
413 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
416 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
422 if (!MLX5_CAP_GEN(dev, atomic))
425 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
431 supported_atomic_req_8B_endianness_mode_1);
433 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
436 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
438 /* Set requestor to host endianness */
439 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
440 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
442 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
445 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
451 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
452 !MLX5_CAP_GEN(dev, pg))
455 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
459 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
460 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
461 MLX5_ST_SZ_BYTES(odp_cap));
463 #define ODP_CAP_SET_MAX(dev, field) \
465 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
468 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
472 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
473 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
474 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
475 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
476 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
477 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
478 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
479 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
480 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
481 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
482 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
483 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
484 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
485 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
490 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
493 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
495 struct mlx5_profile *prof = dev->profile;
499 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
503 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
505 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
506 MLX5_ST_SZ_BYTES(cmd_hca_cap));
508 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
509 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
511 /* we limit the size of the pkey table to 128 entries for now */
512 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
513 to_fw_pkey_sz(dev, 128));
515 /* Check log_max_qp from HCA caps to set in current profile */
516 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
517 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
518 profile[prof_sel].log_max_qp,
519 MLX5_CAP_GEN_MAX(dev, log_max_qp));
520 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
522 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
523 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
526 /* disable cmdif checksum */
527 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
529 /* Enable 4K UAR only when HCA supports it and page size is bigger
532 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
533 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
535 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
537 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
538 MLX5_SET(cmd_hca_cap,
541 cache_line_size() >= 128 ? 1 : 0);
543 if (MLX5_CAP_GEN_MAX(dev, dct))
544 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
546 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
547 MLX5_SET(cmd_hca_cap,
550 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
552 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
553 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
555 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
558 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
563 if (!MLX5_CAP_GEN(dev, roce))
566 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
570 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
571 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
574 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
575 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE],
576 MLX5_ST_SZ_BYTES(roce_cap));
577 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
579 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
583 static int set_hca_cap(struct mlx5_core_dev *dev)
585 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
589 set_ctx = kzalloc(set_sz, GFP_KERNEL);
593 err = handle_hca_cap(dev, set_ctx);
595 mlx5_core_err(dev, "handle_hca_cap failed\n");
599 memset(set_ctx, 0, set_sz);
600 err = handle_hca_cap_atomic(dev, set_ctx);
602 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
606 memset(set_ctx, 0, set_sz);
607 err = handle_hca_cap_odp(dev, set_ctx);
609 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
613 memset(set_ctx, 0, set_sz);
614 err = handle_hca_cap_roce(dev, set_ctx);
616 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
625 static int set_hca_ctrl(struct mlx5_core_dev *dev)
627 struct mlx5_reg_host_endianness he_in;
628 struct mlx5_reg_host_endianness he_out;
631 if (!mlx5_core_is_pf(dev))
634 memset(&he_in, 0, sizeof(he_in));
635 he_in.he = MLX5_SET_HOST_ENDIANNESS;
636 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
637 &he_out, sizeof(he_out),
638 MLX5_REG_HOST_ENDIANNESS, 0, 1);
642 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
646 /* Disable local_lb by default */
647 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
648 ret = mlx5_nic_vport_update_local_lb(dev, false);
653 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
655 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
657 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
658 MLX5_SET(enable_hca_in, in, function_id, func_id);
659 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
660 dev->caps.embedded_cpu);
661 return mlx5_cmd_exec_in(dev, enable_hca, in);
664 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
666 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
668 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
669 MLX5_SET(disable_hca_in, in, function_id, func_id);
670 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
671 dev->caps.embedded_cpu);
672 return mlx5_cmd_exec_in(dev, disable_hca, in);
675 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
676 struct ptp_system_timestamp *sts)
678 u32 timer_h, timer_h1, timer_l;
680 timer_h = ioread32be(&dev->iseg->internal_timer_h);
681 ptp_read_system_prets(sts);
682 timer_l = ioread32be(&dev->iseg->internal_timer_l);
683 ptp_read_system_postts(sts);
684 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
685 if (timer_h != timer_h1) {
687 ptp_read_system_prets(sts);
688 timer_l = ioread32be(&dev->iseg->internal_timer_l);
689 ptp_read_system_postts(sts);
692 return (u64)timer_l | (u64)timer_h1 << 32;
695 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
697 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
698 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
702 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
703 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
708 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
709 if (!status || syndrome == MLX5_DRIVER_SYND) {
710 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
711 err, status, syndrome);
715 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
720 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
722 if (sup_issi & (1 << 1)) {
723 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
725 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
726 MLX5_SET(set_issi_in, set_in, current_issi, 1);
727 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
729 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
737 } else if (sup_issi & (1 << 0) || !sup_issi) {
744 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
745 const struct pci_device_id *id)
747 struct mlx5_priv *priv = &dev->priv;
750 mutex_init(&dev->pci_status_mutex);
751 pci_set_drvdata(dev->pdev, dev);
753 dev->bar_addr = pci_resource_start(pdev, 0);
754 priv->numa_node = dev_to_node(&dev->pdev->dev);
756 err = mlx5_pci_enable_device(dev);
758 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
762 err = request_bar(pdev);
764 mlx5_core_err(dev, "error requesting BARs, aborting\n");
768 pci_set_master(pdev);
770 err = set_dma_caps(pdev);
772 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
776 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
777 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
778 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
779 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
781 dev->iseg_base = dev->bar_addr;
782 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
785 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
789 mlx5_pci_vsc_init(dev);
790 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
794 pci_clear_master(dev->pdev);
795 release_bar(dev->pdev);
797 mlx5_pci_disable_device(dev);
801 static void mlx5_pci_close(struct mlx5_core_dev *dev)
804 pci_clear_master(dev->pdev);
805 release_bar(dev->pdev);
806 mlx5_pci_disable_device(dev);
809 static int mlx5_init_once(struct mlx5_core_dev *dev)
813 dev->priv.devcom = mlx5_devcom_register_device(dev);
814 if (IS_ERR(dev->priv.devcom))
815 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
818 err = mlx5_query_board_id(dev);
820 mlx5_core_err(dev, "query board id failed\n");
824 err = mlx5_irq_table_init(dev);
826 mlx5_core_err(dev, "failed to initialize irq table\n");
830 err = mlx5_eq_table_init(dev);
832 mlx5_core_err(dev, "failed to initialize eq\n");
833 goto err_irq_cleanup;
836 err = mlx5_events_init(dev);
838 mlx5_core_err(dev, "failed to initialize events\n");
842 mlx5_cq_debugfs_init(dev);
844 mlx5_init_reserved_gids(dev);
846 mlx5_init_clock(dev);
848 dev->vxlan = mlx5_vxlan_create(dev);
849 dev->geneve = mlx5_geneve_create(dev);
851 err = mlx5_init_rl_table(dev);
853 mlx5_core_err(dev, "Failed to init rate limiting\n");
854 goto err_tables_cleanup;
857 err = mlx5_mpfs_init(dev);
859 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
863 err = mlx5_sriov_init(dev);
865 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
866 goto err_mpfs_cleanup;
869 err = mlx5_eswitch_init(dev);
871 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
872 goto err_sriov_cleanup;
875 err = mlx5_fpga_init(dev);
877 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
878 goto err_eswitch_cleanup;
881 dev->dm = mlx5_dm_create(dev);
883 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
885 dev->tracer = mlx5_fw_tracer_create(dev);
886 dev->hv_vhca = mlx5_hv_vhca_create(dev);
887 dev->rsc_dump = mlx5_rsc_dump_create(dev);
892 mlx5_eswitch_cleanup(dev->priv.eswitch);
894 mlx5_sriov_cleanup(dev);
896 mlx5_mpfs_cleanup(dev);
898 mlx5_cleanup_rl_table(dev);
900 mlx5_geneve_destroy(dev->geneve);
901 mlx5_vxlan_destroy(dev->vxlan);
902 mlx5_cq_debugfs_cleanup(dev);
903 mlx5_events_cleanup(dev);
905 mlx5_eq_table_cleanup(dev);
907 mlx5_irq_table_cleanup(dev);
909 mlx5_devcom_unregister_device(dev->priv.devcom);
914 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
916 mlx5_rsc_dump_destroy(dev);
917 mlx5_hv_vhca_destroy(dev->hv_vhca);
918 mlx5_fw_tracer_destroy(dev->tracer);
919 mlx5_dm_cleanup(dev);
920 mlx5_fpga_cleanup(dev);
921 mlx5_eswitch_cleanup(dev->priv.eswitch);
922 mlx5_sriov_cleanup(dev);
923 mlx5_mpfs_cleanup(dev);
924 mlx5_cleanup_rl_table(dev);
925 mlx5_geneve_destroy(dev->geneve);
926 mlx5_vxlan_destroy(dev->vxlan);
927 mlx5_cleanup_clock(dev);
928 mlx5_cleanup_reserved_gids(dev);
929 mlx5_cq_debugfs_cleanup(dev);
930 mlx5_events_cleanup(dev);
931 mlx5_eq_table_cleanup(dev);
932 mlx5_irq_table_cleanup(dev);
933 mlx5_devcom_unregister_device(dev->priv.devcom);
936 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
940 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
941 fw_rev_min(dev), fw_rev_sub(dev));
943 /* Only PFs hold the relevant PCIe information for this query */
944 if (mlx5_core_is_pf(dev))
945 pcie_print_link_status(dev->pdev);
947 /* wait for firmware to accept initialization segments configurations
949 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL);
951 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
952 FW_PRE_INIT_TIMEOUT_MILI);
956 err = mlx5_cmd_init(dev);
958 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
962 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
964 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
965 FW_INIT_TIMEOUT_MILI);
966 goto err_cmd_cleanup;
969 err = mlx5_core_enable_hca(dev, 0);
971 mlx5_core_err(dev, "enable hca failed\n");
972 goto err_cmd_cleanup;
975 err = mlx5_core_set_issi(dev);
977 mlx5_core_err(dev, "failed to set issi\n");
978 goto err_disable_hca;
981 err = mlx5_satisfy_startup_pages(dev, 1);
983 mlx5_core_err(dev, "failed to allocate boot pages\n");
984 goto err_disable_hca;
987 err = set_hca_ctrl(dev);
989 mlx5_core_err(dev, "set_hca_ctrl failed\n");
990 goto reclaim_boot_pages;
993 err = set_hca_cap(dev);
995 mlx5_core_err(dev, "set_hca_cap failed\n");
996 goto reclaim_boot_pages;
999 err = mlx5_satisfy_startup_pages(dev, 0);
1001 mlx5_core_err(dev, "failed to allocate init pages\n");
1002 goto reclaim_boot_pages;
1005 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1007 mlx5_core_err(dev, "init hca failed\n");
1008 goto reclaim_boot_pages;
1011 mlx5_set_driver_version(dev);
1013 mlx5_start_health_poll(dev);
1015 err = mlx5_query_hca_caps(dev);
1017 mlx5_core_err(dev, "query hca failed\n");
1024 mlx5_stop_health_poll(dev, boot);
1026 mlx5_reclaim_startup_pages(dev);
1028 mlx5_core_disable_hca(dev, 0);
1030 mlx5_cmd_cleanup(dev);
1035 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1039 mlx5_stop_health_poll(dev, boot);
1040 err = mlx5_cmd_teardown_hca(dev);
1042 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1045 mlx5_reclaim_startup_pages(dev);
1046 mlx5_core_disable_hca(dev, 0);
1047 mlx5_cmd_cleanup(dev);
1052 static int mlx5_load(struct mlx5_core_dev *dev)
1056 dev->priv.uar = mlx5_get_uars_page(dev);
1057 if (IS_ERR(dev->priv.uar)) {
1058 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1059 err = PTR_ERR(dev->priv.uar);
1063 mlx5_events_start(dev);
1064 mlx5_pagealloc_start(dev);
1066 err = mlx5_irq_table_create(dev);
1068 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1072 err = mlx5_eq_table_create(dev);
1074 mlx5_core_err(dev, "Failed to create EQs\n");
1078 err = mlx5_fw_tracer_init(dev->tracer);
1080 mlx5_core_err(dev, "Failed to init FW tracer\n");
1084 mlx5_hv_vhca_init(dev->hv_vhca);
1086 err = mlx5_rsc_dump_init(dev);
1088 mlx5_core_err(dev, "Failed to init Resource dump\n");
1092 err = mlx5_fpga_device_start(dev);
1094 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1095 goto err_fpga_start;
1098 err = mlx5_accel_ipsec_init(dev);
1100 mlx5_core_err(dev, "IPSec device start failed %d\n", err);
1101 goto err_ipsec_start;
1104 err = mlx5_accel_tls_init(dev);
1106 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1110 err = mlx5_init_fs(dev);
1112 mlx5_core_err(dev, "Failed to init flow steering\n");
1116 err = mlx5_core_set_hca_defaults(dev);
1118 mlx5_core_err(dev, "Failed to set hca defaults\n");
1122 err = mlx5_sriov_attach(dev);
1124 mlx5_core_err(dev, "sriov init failed %d\n", err);
1128 err = mlx5_ec_init(dev);
1130 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1137 mlx5_sriov_detach(dev);
1139 mlx5_cleanup_fs(dev);
1141 mlx5_accel_tls_cleanup(dev);
1143 mlx5_accel_ipsec_cleanup(dev);
1145 mlx5_fpga_device_stop(dev);
1147 mlx5_rsc_dump_cleanup(dev);
1149 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1150 mlx5_fw_tracer_cleanup(dev->tracer);
1152 mlx5_eq_table_destroy(dev);
1154 mlx5_irq_table_destroy(dev);
1156 mlx5_pagealloc_stop(dev);
1157 mlx5_events_stop(dev);
1158 mlx5_put_uars_page(dev, dev->priv.uar);
1162 static void mlx5_unload(struct mlx5_core_dev *dev)
1164 mlx5_ec_cleanup(dev);
1165 mlx5_sriov_detach(dev);
1166 mlx5_cleanup_fs(dev);
1167 mlx5_accel_ipsec_cleanup(dev);
1168 mlx5_accel_tls_cleanup(dev);
1169 mlx5_fpga_device_stop(dev);
1170 mlx5_rsc_dump_cleanup(dev);
1171 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1172 mlx5_fw_tracer_cleanup(dev->tracer);
1173 mlx5_eq_table_destroy(dev);
1174 mlx5_irq_table_destroy(dev);
1175 mlx5_pagealloc_stop(dev);
1176 mlx5_events_stop(dev);
1177 mlx5_put_uars_page(dev, dev->priv.uar);
1180 int mlx5_load_one(struct mlx5_core_dev *dev, bool boot)
1184 mutex_lock(&dev->intf_state_mutex);
1185 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1186 mlx5_core_warn(dev, "interface is up, NOP\n");
1189 /* remove any previous indication of internal error */
1190 dev->state = MLX5_DEVICE_STATE_UP;
1192 err = mlx5_function_setup(dev, boot);
1197 err = mlx5_init_once(dev);
1199 mlx5_core_err(dev, "sw objs init failed\n");
1200 goto function_teardown;
1204 err = mlx5_load(dev);
1209 err = mlx5_devlink_register(priv_to_devlink(dev), dev->device);
1211 goto err_devlink_reg;
1214 if (mlx5_device_registered(dev))
1215 mlx5_attach_device(dev);
1217 mlx5_register_device(dev);
1219 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1221 mutex_unlock(&dev->intf_state_mutex);
1229 mlx5_cleanup_once(dev);
1231 mlx5_function_teardown(dev, boot);
1232 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1233 mutex_unlock(&dev->intf_state_mutex);
1238 void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup)
1241 mlx5_unregister_device(dev);
1242 mlx5_drain_health_wq(dev);
1245 mutex_lock(&dev->intf_state_mutex);
1246 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1247 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1250 mlx5_cleanup_once(dev);
1254 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1256 if (mlx5_device_registered(dev))
1257 mlx5_detach_device(dev);
1262 mlx5_cleanup_once(dev);
1264 mlx5_function_teardown(dev, cleanup);
1266 mutex_unlock(&dev->intf_state_mutex);
1269 static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1271 struct mlx5_priv *priv = &dev->priv;
1274 dev->profile = &profile[profile_idx];
1276 INIT_LIST_HEAD(&priv->ctx_list);
1277 spin_lock_init(&priv->ctx_lock);
1278 mutex_init(&dev->intf_state_mutex);
1280 mutex_init(&priv->bfregs.reg_head.lock);
1281 mutex_init(&priv->bfregs.wc_head.lock);
1282 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1283 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1285 mutex_init(&priv->alloc_mutex);
1286 mutex_init(&priv->pgdir_mutex);
1287 INIT_LIST_HEAD(&priv->pgdir_list);
1289 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1291 if (!priv->dbg_root) {
1292 dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n");
1296 err = mlx5_health_init(dev);
1298 goto err_health_init;
1300 err = mlx5_pagealloc_init(dev);
1302 goto err_pagealloc_init;
1307 mlx5_health_cleanup(dev);
1309 debugfs_remove(dev->priv.dbg_root);
1314 static void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1316 mlx5_pagealloc_cleanup(dev);
1317 mlx5_health_cleanup(dev);
1318 debugfs_remove_recursive(dev->priv.dbg_root);
1321 #define MLX5_IB_MOD "mlx5_ib"
1322 static int init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1324 struct mlx5_core_dev *dev;
1325 struct devlink *devlink;
1328 devlink = mlx5_devlink_alloc();
1330 dev_err(&pdev->dev, "devlink alloc failed\n");
1334 dev = devlink_priv(devlink);
1335 dev->device = &pdev->dev;
1338 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1339 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1341 err = mlx5_mdev_init(dev, prof_sel);
1345 err = mlx5_pci_init(dev, pdev, id);
1347 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1352 err = mlx5_load_one(dev, true);
1354 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n",
1359 request_module_nowait(MLX5_IB_MOD);
1361 err = mlx5_crdump_enable(dev);
1363 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1365 pci_save_state(pdev);
1369 mlx5_pci_close(dev);
1371 mlx5_mdev_uninit(dev);
1373 mlx5_devlink_free(devlink);
1378 static void remove_one(struct pci_dev *pdev)
1380 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1381 struct devlink *devlink = priv_to_devlink(dev);
1383 mlx5_crdump_disable(dev);
1384 mlx5_devlink_unregister(devlink);
1386 mlx5_unload_one(dev, true);
1387 mlx5_pci_close(dev);
1388 mlx5_mdev_uninit(dev);
1389 mlx5_devlink_free(devlink);
1392 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1393 pci_channel_state_t state)
1395 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1397 mlx5_core_info(dev, "%s was called\n", __func__);
1399 mlx5_enter_error_state(dev, false);
1400 mlx5_error_sw_reset(dev);
1401 mlx5_unload_one(dev, false);
1402 mlx5_drain_health_wq(dev);
1403 mlx5_pci_disable_device(dev);
1405 return state == pci_channel_io_perm_failure ?
1406 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1409 /* wait for the device to show vital signs by waiting
1410 * for the health counter to start counting.
1412 static int wait_vital(struct pci_dev *pdev)
1414 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1415 struct mlx5_core_health *health = &dev->priv.health;
1416 const int niter = 100;
1421 for (i = 0; i < niter; i++) {
1422 count = ioread32be(health->health_counter);
1423 if (count && count != 0xffffffff) {
1424 if (last_count && last_count != count) {
1426 "wait vital counter value 0x%x after %d iterations\n",
1438 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1440 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1443 mlx5_core_info(dev, "%s was called\n", __func__);
1445 err = mlx5_pci_enable_device(dev);
1447 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1449 return PCI_ERS_RESULT_DISCONNECT;
1452 pci_set_master(pdev);
1453 pci_restore_state(pdev);
1454 pci_save_state(pdev);
1456 if (wait_vital(pdev)) {
1457 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1458 return PCI_ERS_RESULT_DISCONNECT;
1461 return PCI_ERS_RESULT_RECOVERED;
1464 static void mlx5_pci_resume(struct pci_dev *pdev)
1466 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1469 mlx5_core_info(dev, "%s was called\n", __func__);
1471 err = mlx5_load_one(dev, false);
1473 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1476 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1479 static const struct pci_error_handlers mlx5_err_handler = {
1480 .error_detected = mlx5_pci_err_detected,
1481 .slot_reset = mlx5_pci_slot_reset,
1482 .resume = mlx5_pci_resume
1485 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1487 bool fast_teardown = false, force_teardown = false;
1490 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1491 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1493 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1494 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1496 if (!fast_teardown && !force_teardown)
1499 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1500 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1504 /* Panic tear down fw command will stop the PCI bus communication
1505 * with the HCA, so the health polll is no longer needed.
1507 mlx5_drain_health_wq(dev);
1508 mlx5_stop_health_poll(dev, false);
1510 ret = mlx5_cmd_fast_teardown_hca(dev);
1514 ret = mlx5_cmd_force_teardown_hca(dev);
1518 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1519 mlx5_start_health_poll(dev);
1523 mlx5_enter_error_state(dev, true);
1525 /* Some platforms requiring freeing the IRQ's in the shutdown
1526 * flow. If they aren't freed they can't be allocated after
1527 * kexec. There is no need to cleanup the mlx5_core software
1530 mlx5_core_eq_free_irqs(dev);
1535 static void shutdown(struct pci_dev *pdev)
1537 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1540 mlx5_core_info(dev, "Shutdown was called\n");
1541 err = mlx5_try_fast_unload(dev);
1543 mlx5_unload_one(dev, false);
1544 mlx5_pci_disable_device(dev);
1547 static const struct pci_device_id mlx5_core_pci_table[] = {
1548 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1549 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1550 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1551 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1552 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1553 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1554 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1555 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1556 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1557 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1558 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1559 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1560 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1561 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1562 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1563 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1564 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1565 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1566 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1570 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1572 void mlx5_disable_device(struct mlx5_core_dev *dev)
1574 mlx5_error_sw_reset(dev);
1575 mlx5_unload_one(dev, false);
1578 void mlx5_recover_device(struct mlx5_core_dev *dev)
1580 mlx5_pci_disable_device(dev);
1581 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1582 mlx5_pci_resume(dev->pdev);
1585 static struct pci_driver mlx5_core_driver = {
1586 .name = DRIVER_NAME,
1587 .id_table = mlx5_core_pci_table,
1589 .remove = remove_one,
1590 .shutdown = shutdown,
1591 .err_handler = &mlx5_err_handler,
1592 .sriov_configure = mlx5_core_sriov_configure,
1595 static void mlx5_core_verify_params(void)
1597 if (prof_sel >= ARRAY_SIZE(profile)) {
1598 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1600 ARRAY_SIZE(profile) - 1,
1602 prof_sel = MLX5_DEFAULT_PROF;
1606 static int __init init(void)
1610 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1612 mlx5_core_verify_params();
1613 mlx5_accel_ipsec_build_fs_cmds();
1614 mlx5_register_debugfs();
1616 err = pci_register_driver(&mlx5_core_driver);
1620 #ifdef CONFIG_MLX5_CORE_EN
1627 mlx5_unregister_debugfs();
1631 static void __exit cleanup(void)
1633 #ifdef CONFIG_MLX5_CORE_EN
1636 pci_unregister_driver(&mlx5_core_driver);
1637 mlx5_unregister_debugfs();
1641 module_exit(cleanup);