2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
60 #include "fpga/core.h"
61 #include "fpga/ipsec.h"
62 #include "accel/ipsec.h"
63 #include "accel/tls.h"
64 #include "lib/clock.h"
65 #include "lib/vxlan.h"
66 #include "lib/devcom.h"
67 #include "diag/fw_tracer.h"
69 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
70 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
71 MODULE_LICENSE("Dual BSD/GPL");
72 MODULE_VERSION(DRIVER_VERSION);
74 unsigned int mlx5_core_debug_mask;
75 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
76 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
78 #define MLX5_DEFAULT_PROF 2
79 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
80 module_param_named(prof_sel, prof_sel, uint, 0444);
81 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
83 static u32 sw_owner_id[4];
86 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
87 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
90 static struct mlx5_profile profile[] = {
95 .mask = MLX5_PROF_MASK_QP_SIZE,
99 .mask = MLX5_PROF_MASK_QP_SIZE |
100 MLX5_PROF_MASK_MR_CACHE,
189 #define FW_INIT_TIMEOUT_MILI 2000
190 #define FW_INIT_WAIT_MS 2
191 #define FW_PRE_INIT_TIMEOUT_MILI 10000
193 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
195 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
198 while (fw_initializing(dev)) {
199 if (time_after(jiffies, end)) {
203 msleep(FW_INIT_WAIT_MS);
209 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
211 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
213 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
214 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
215 int remaining_size = driver_ver_sz;
218 if (!MLX5_CAP_GEN(dev, driver_version))
221 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
223 strncpy(string, "Linux", remaining_size);
225 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
226 strncat(string, ",", remaining_size);
228 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
229 strncat(string, DRIVER_NAME, remaining_size);
231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
232 strncat(string, ",", remaining_size);
234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
235 strncat(string, DRIVER_VERSION, remaining_size);
238 MLX5_SET(set_driver_version_in, in, opcode,
239 MLX5_CMD_OP_SET_DRIVER_VERSION);
241 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
244 static int set_dma_caps(struct pci_dev *pdev)
248 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
250 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
251 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
253 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
258 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
261 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
262 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
265 "Can't set consistent PCI DMA mask, aborting\n");
270 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
274 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
276 struct pci_dev *pdev = dev->pdev;
279 mutex_lock(&dev->pci_status_mutex);
280 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
281 err = pci_enable_device(pdev);
283 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
285 mutex_unlock(&dev->pci_status_mutex);
290 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
292 struct pci_dev *pdev = dev->pdev;
294 mutex_lock(&dev->pci_status_mutex);
295 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
296 pci_disable_device(pdev);
297 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
299 mutex_unlock(&dev->pci_status_mutex);
302 static int request_bar(struct pci_dev *pdev)
306 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
307 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
311 err = pci_request_regions(pdev, DRIVER_NAME);
313 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
318 static void release_bar(struct pci_dev *pdev)
320 pci_release_regions(pdev);
323 struct mlx5_reg_host_endianness {
328 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
331 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
332 MLX5_DEV_CAP_FLAG_DCT,
335 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
351 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
356 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
357 enum mlx5_cap_type cap_type,
358 enum mlx5_cap_mode cap_mode)
360 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
361 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
362 void *out, *hca_caps;
363 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
366 memset(in, 0, sizeof(in));
367 out = kzalloc(out_sz, GFP_KERNEL);
371 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
372 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
373 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
376 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
377 cap_type, cap_mode, err);
381 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
384 case HCA_CAP_OPMOD_GET_MAX:
385 memcpy(dev->caps.hca_max[cap_type], hca_caps,
386 MLX5_UN_SZ_BYTES(hca_cap_union));
388 case HCA_CAP_OPMOD_GET_CUR:
389 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
390 MLX5_UN_SZ_BYTES(hca_cap_union));
394 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
404 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
408 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
411 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
414 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
416 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
418 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
419 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
420 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
423 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
427 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
431 if (MLX5_CAP_GEN(dev, atomic)) {
432 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
441 supported_atomic_req_8B_endianness_mode_1);
443 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
446 set_ctx = kzalloc(set_sz, GFP_KERNEL);
450 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
452 /* Set requestor to host endianness */
453 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
454 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
456 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
462 static int handle_hca_cap(struct mlx5_core_dev *dev)
464 void *set_ctx = NULL;
465 struct mlx5_profile *prof = dev->profile;
467 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
470 set_ctx = kzalloc(set_sz, GFP_KERNEL);
474 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
478 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
480 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
481 MLX5_ST_SZ_BYTES(cmd_hca_cap));
483 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
484 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
486 /* we limit the size of the pkey table to 128 entries for now */
487 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
488 to_fw_pkey_sz(dev, 128));
490 /* Check log_max_qp from HCA caps to set in current profile */
491 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
492 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
493 profile[prof_sel].log_max_qp,
494 MLX5_CAP_GEN_MAX(dev, log_max_qp));
495 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
497 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
498 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
501 /* disable cmdif checksum */
502 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
504 /* Enable 4K UAR only when HCA supports it and page size is bigger
507 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
508 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
510 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
512 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
513 MLX5_SET(cmd_hca_cap,
516 cache_line_size() >= 128 ? 1 : 0);
518 if (MLX5_CAP_GEN_MAX(dev, dct))
519 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
521 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
522 MLX5_SET(cmd_hca_cap,
525 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
527 err = set_caps(dev, set_ctx, set_sz,
528 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
535 static int set_hca_ctrl(struct mlx5_core_dev *dev)
537 struct mlx5_reg_host_endianness he_in;
538 struct mlx5_reg_host_endianness he_out;
541 if (!mlx5_core_is_pf(dev))
544 memset(&he_in, 0, sizeof(he_in));
545 he_in.he = MLX5_SET_HOST_ENDIANNESS;
546 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
547 &he_out, sizeof(he_out),
548 MLX5_REG_HOST_ENDIANNESS, 0, 1);
552 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
556 /* Disable local_lb by default */
557 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
558 ret = mlx5_nic_vport_update_local_lb(dev, false);
563 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
565 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
566 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
568 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
569 MLX5_SET(enable_hca_in, in, function_id, func_id);
570 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
573 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
575 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
576 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
578 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
579 MLX5_SET(disable_hca_in, in, function_id, func_id);
580 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
583 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
584 struct ptp_system_timestamp *sts)
586 u32 timer_h, timer_h1, timer_l;
588 timer_h = ioread32be(&dev->iseg->internal_timer_h);
589 ptp_read_system_prets(sts);
590 timer_l = ioread32be(&dev->iseg->internal_timer_l);
591 ptp_read_system_postts(sts);
592 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
593 if (timer_h != timer_h1) {
595 ptp_read_system_prets(sts);
596 timer_l = ioread32be(&dev->iseg->internal_timer_l);
597 ptp_read_system_postts(sts);
600 return (u64)timer_l | (u64)timer_h1 << 32;
603 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
605 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
606 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
610 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
611 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
612 query_out, sizeof(query_out));
617 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
618 if (!status || syndrome == MLX5_DRIVER_SYND) {
619 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
620 err, status, syndrome);
624 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
629 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
631 if (sup_issi & (1 << 1)) {
632 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
633 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
635 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
636 MLX5_SET(set_issi_in, set_in, current_issi, 1);
637 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
638 set_out, sizeof(set_out));
640 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
648 } else if (sup_issi & (1 << 0) || !sup_issi) {
655 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
657 struct pci_dev *pdev = dev->pdev;
660 pci_set_drvdata(dev->pdev, dev);
661 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
662 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
664 mutex_init(&priv->pgdir_mutex);
665 INIT_LIST_HEAD(&priv->pgdir_list);
666 spin_lock_init(&priv->mkey_lock);
668 mutex_init(&priv->alloc_mutex);
670 priv->numa_node = dev_to_node(&dev->pdev->dev);
672 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
673 if (!priv->dbg_root) {
674 dev_err(&pdev->dev, "Cannot create debugfs dir, aborting\n");
678 err = mlx5_pci_enable_device(dev);
680 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
684 err = request_bar(pdev);
686 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
690 pci_set_master(pdev);
692 err = set_dma_caps(pdev);
694 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
698 dev->iseg_base = pci_resource_start(dev->pdev, 0);
699 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
702 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
709 pci_clear_master(dev->pdev);
710 release_bar(dev->pdev);
712 mlx5_pci_disable_device(dev);
715 debugfs_remove(priv->dbg_root);
719 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
722 pci_clear_master(dev->pdev);
723 release_bar(dev->pdev);
724 mlx5_pci_disable_device(dev);
725 debugfs_remove_recursive(priv->dbg_root);
728 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
730 struct pci_dev *pdev = dev->pdev;
733 priv->devcom = mlx5_devcom_register_device(dev);
734 if (IS_ERR(priv->devcom))
735 dev_err(&pdev->dev, "failed to register with devcom (0x%p)\n",
738 err = mlx5_query_board_id(dev);
740 dev_err(&pdev->dev, "query board id failed\n");
744 err = mlx5_eq_table_init(dev);
746 dev_err(&pdev->dev, "failed to initialize eq\n");
750 err = mlx5_events_init(dev);
752 dev_err(&pdev->dev, "failed to initialize events\n");
756 err = mlx5_cq_debugfs_init(dev);
758 dev_err(&pdev->dev, "failed to initialize cq debugfs\n");
759 goto err_events_cleanup;
762 mlx5_init_qp_table(dev);
764 mlx5_init_mkey_table(dev);
766 mlx5_init_reserved_gids(dev);
768 mlx5_init_clock(dev);
770 dev->vxlan = mlx5_vxlan_create(dev);
772 err = mlx5_init_rl_table(dev);
774 dev_err(&pdev->dev, "Failed to init rate limiting\n");
775 goto err_tables_cleanup;
778 err = mlx5_mpfs_init(dev);
780 dev_err(&pdev->dev, "Failed to init l2 table %d\n", err);
784 err = mlx5_eswitch_init(dev);
786 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
787 goto err_mpfs_cleanup;
790 err = mlx5_sriov_init(dev);
792 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
793 goto err_eswitch_cleanup;
796 err = mlx5_fpga_init(dev);
798 dev_err(&pdev->dev, "Failed to init fpga device %d\n", err);
799 goto err_sriov_cleanup;
802 dev->tracer = mlx5_fw_tracer_create(dev);
807 mlx5_sriov_cleanup(dev);
809 mlx5_eswitch_cleanup(dev->priv.eswitch);
811 mlx5_mpfs_cleanup(dev);
813 mlx5_cleanup_rl_table(dev);
815 mlx5_vxlan_destroy(dev->vxlan);
816 mlx5_cleanup_mkey_table(dev);
817 mlx5_cleanup_qp_table(dev);
818 mlx5_cq_debugfs_cleanup(dev);
820 mlx5_events_cleanup(dev);
822 mlx5_eq_table_cleanup(dev);
824 mlx5_devcom_unregister_device(dev->priv.devcom);
829 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
831 mlx5_fw_tracer_destroy(dev->tracer);
832 mlx5_fpga_cleanup(dev);
833 mlx5_sriov_cleanup(dev);
834 mlx5_eswitch_cleanup(dev->priv.eswitch);
835 mlx5_mpfs_cleanup(dev);
836 mlx5_cleanup_rl_table(dev);
837 mlx5_vxlan_destroy(dev->vxlan);
838 mlx5_cleanup_clock(dev);
839 mlx5_cleanup_reserved_gids(dev);
840 mlx5_cleanup_mkey_table(dev);
841 mlx5_cleanup_qp_table(dev);
842 mlx5_cq_debugfs_cleanup(dev);
843 mlx5_events_cleanup(dev);
844 mlx5_eq_table_cleanup(dev);
845 mlx5_devcom_unregister_device(dev->priv.devcom);
848 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
851 struct pci_dev *pdev = dev->pdev;
854 mutex_lock(&dev->intf_state_mutex);
855 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
856 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
861 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
862 fw_rev_min(dev), fw_rev_sub(dev));
864 /* Only PFs hold the relevant PCIe information for this query */
865 if (mlx5_core_is_pf(dev))
866 pcie_print_link_status(dev->pdev);
868 /* on load removing any previous indication of internal error, device is
871 dev->state = MLX5_DEVICE_STATE_UP;
873 /* wait for firmware to accept initialization segments configurations
875 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
877 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
878 FW_PRE_INIT_TIMEOUT_MILI);
882 err = mlx5_cmd_init(dev);
884 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
888 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
890 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
891 FW_INIT_TIMEOUT_MILI);
892 goto err_cmd_cleanup;
895 err = mlx5_core_enable_hca(dev, 0);
897 dev_err(&pdev->dev, "enable hca failed\n");
898 goto err_cmd_cleanup;
901 err = mlx5_core_set_issi(dev);
903 dev_err(&pdev->dev, "failed to set issi\n");
904 goto err_disable_hca;
907 err = mlx5_satisfy_startup_pages(dev, 1);
909 dev_err(&pdev->dev, "failed to allocate boot pages\n");
910 goto err_disable_hca;
913 err = set_hca_ctrl(dev);
915 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
916 goto reclaim_boot_pages;
919 err = handle_hca_cap(dev);
921 dev_err(&pdev->dev, "handle_hca_cap failed\n");
922 goto reclaim_boot_pages;
925 err = handle_hca_cap_atomic(dev);
927 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
928 goto reclaim_boot_pages;
931 err = mlx5_satisfy_startup_pages(dev, 0);
933 dev_err(&pdev->dev, "failed to allocate init pages\n");
934 goto reclaim_boot_pages;
937 err = mlx5_cmd_init_hca(dev, sw_owner_id);
939 dev_err(&pdev->dev, "init hca failed\n");
940 goto reclaim_boot_pages;
943 mlx5_set_driver_version(dev);
945 mlx5_start_health_poll(dev);
947 err = mlx5_query_hca_caps(dev);
949 dev_err(&pdev->dev, "query hca failed\n");
954 err = mlx5_init_once(dev, priv);
956 dev_err(&pdev->dev, "sw objs init failed\n");
961 dev->priv.uar = mlx5_get_uars_page(dev);
962 if (IS_ERR(dev->priv.uar)) {
963 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
964 err = PTR_ERR(dev->priv.uar);
968 mlx5_events_start(dev);
969 mlx5_pagealloc_start(dev);
971 err = mlx5_eq_table_create(dev);
973 dev_err(&pdev->dev, "Failed to create EQs\n");
977 err = mlx5_fw_tracer_init(dev->tracer);
979 dev_err(&pdev->dev, "Failed to init FW tracer\n");
983 err = mlx5_fpga_device_start(dev);
985 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
989 err = mlx5_accel_ipsec_init(dev);
991 dev_err(&pdev->dev, "IPSec device start failed %d\n", err);
992 goto err_ipsec_start;
995 err = mlx5_accel_tls_init(dev);
997 dev_err(&pdev->dev, "TLS device start failed %d\n", err);
1001 err = mlx5_init_fs(dev);
1003 dev_err(&pdev->dev, "Failed to init flow steering\n");
1007 err = mlx5_core_set_hca_defaults(dev);
1009 dev_err(&pdev->dev, "Failed to set hca defaults\n");
1013 err = mlx5_sriov_attach(dev);
1015 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1019 if (mlx5_device_registered(dev)) {
1020 mlx5_attach_device(dev);
1022 err = mlx5_register_device(dev);
1024 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1029 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1031 mutex_unlock(&dev->intf_state_mutex);
1036 mlx5_sriov_detach(dev);
1039 mlx5_cleanup_fs(dev);
1042 mlx5_accel_tls_cleanup(dev);
1045 mlx5_accel_ipsec_cleanup(dev);
1048 mlx5_fpga_device_stop(dev);
1051 mlx5_fw_tracer_cleanup(dev->tracer);
1054 mlx5_eq_table_destroy(dev);
1057 mlx5_pagealloc_stop(dev);
1058 mlx5_events_stop(dev);
1059 mlx5_put_uars_page(dev, priv->uar);
1063 mlx5_cleanup_once(dev);
1066 mlx5_stop_health_poll(dev, boot);
1067 if (mlx5_cmd_teardown_hca(dev)) {
1068 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1073 mlx5_reclaim_startup_pages(dev);
1076 mlx5_core_disable_hca(dev, 0);
1079 mlx5_cmd_cleanup(dev);
1082 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1083 mutex_unlock(&dev->intf_state_mutex);
1088 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1094 mlx5_drain_health_recovery(dev);
1096 mutex_lock(&dev->intf_state_mutex);
1097 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1098 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1101 mlx5_cleanup_once(dev);
1105 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1107 if (mlx5_device_registered(dev))
1108 mlx5_detach_device(dev);
1110 mlx5_sriov_detach(dev);
1111 mlx5_cleanup_fs(dev);
1112 mlx5_accel_ipsec_cleanup(dev);
1113 mlx5_accel_tls_cleanup(dev);
1114 mlx5_fpga_device_stop(dev);
1115 mlx5_fw_tracer_cleanup(dev->tracer);
1116 mlx5_eq_table_destroy(dev);
1117 mlx5_pagealloc_stop(dev);
1118 mlx5_events_stop(dev);
1119 mlx5_put_uars_page(dev, priv->uar);
1121 mlx5_cleanup_once(dev);
1122 mlx5_stop_health_poll(dev, cleanup);
1124 err = mlx5_cmd_teardown_hca(dev);
1126 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1129 mlx5_reclaim_startup_pages(dev);
1130 mlx5_core_disable_hca(dev, 0);
1131 mlx5_cmd_cleanup(dev);
1134 mutex_unlock(&dev->intf_state_mutex);
1138 static const struct devlink_ops mlx5_devlink_ops = {
1139 #ifdef CONFIG_MLX5_ESWITCH
1140 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1141 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1142 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1143 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1144 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1145 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
1149 #define MLX5_IB_MOD "mlx5_ib"
1150 static int init_one(struct pci_dev *pdev,
1151 const struct pci_device_id *id)
1153 struct mlx5_core_dev *dev;
1154 struct devlink *devlink;
1155 struct mlx5_priv *priv;
1158 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1160 dev_err(&pdev->dev, "kzalloc failed\n");
1164 dev = devlink_priv(devlink);
1166 priv->pci_dev_data = id->driver_data;
1168 pci_set_drvdata(pdev, dev);
1171 dev->profile = &profile[prof_sel];
1173 INIT_LIST_HEAD(&priv->ctx_list);
1174 spin_lock_init(&priv->ctx_lock);
1175 mutex_init(&dev->pci_status_mutex);
1176 mutex_init(&dev->intf_state_mutex);
1178 mutex_init(&priv->bfregs.reg_head.lock);
1179 mutex_init(&priv->bfregs.wc_head.lock);
1180 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1181 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1183 err = mlx5_pci_init(dev, priv);
1185 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1189 err = mlx5_health_init(dev);
1191 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1195 err = mlx5_pagealloc_init(dev);
1197 goto err_pagealloc_init;
1199 err = mlx5_load_one(dev, priv, true);
1201 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1205 request_module_nowait(MLX5_IB_MOD);
1207 err = devlink_register(devlink, &pdev->dev);
1211 pci_save_state(pdev);
1215 mlx5_unload_one(dev, priv, true);
1217 mlx5_pagealloc_cleanup(dev);
1219 mlx5_health_cleanup(dev);
1221 mlx5_pci_close(dev, priv);
1223 devlink_free(devlink);
1228 static void remove_one(struct pci_dev *pdev)
1230 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1231 struct devlink *devlink = priv_to_devlink(dev);
1232 struct mlx5_priv *priv = &dev->priv;
1234 devlink_unregister(devlink);
1235 mlx5_unregister_device(dev);
1237 if (mlx5_unload_one(dev, priv, true)) {
1238 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1239 mlx5_health_cleanup(dev);
1243 mlx5_pagealloc_cleanup(dev);
1244 mlx5_health_cleanup(dev);
1245 mlx5_pci_close(dev, priv);
1246 devlink_free(devlink);
1249 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1250 pci_channel_state_t state)
1252 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1253 struct mlx5_priv *priv = &dev->priv;
1255 dev_info(&pdev->dev, "%s was called\n", __func__);
1257 mlx5_enter_error_state(dev, false);
1258 mlx5_unload_one(dev, priv, false);
1259 /* In case of kernel call drain the health wq */
1261 mlx5_drain_health_wq(dev);
1262 mlx5_pci_disable_device(dev);
1265 return state == pci_channel_io_perm_failure ?
1266 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1269 /* wait for the device to show vital signs by waiting
1270 * for the health counter to start counting.
1272 static int wait_vital(struct pci_dev *pdev)
1274 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1275 struct mlx5_core_health *health = &dev->priv.health;
1276 const int niter = 100;
1281 for (i = 0; i < niter; i++) {
1282 count = ioread32be(health->health_counter);
1283 if (count && count != 0xffffffff) {
1284 if (last_count && last_count != count) {
1285 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1296 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1298 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1301 dev_info(&pdev->dev, "%s was called\n", __func__);
1303 err = mlx5_pci_enable_device(dev);
1305 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1307 return PCI_ERS_RESULT_DISCONNECT;
1310 pci_set_master(pdev);
1311 pci_restore_state(pdev);
1312 pci_save_state(pdev);
1314 if (wait_vital(pdev)) {
1315 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1316 return PCI_ERS_RESULT_DISCONNECT;
1319 return PCI_ERS_RESULT_RECOVERED;
1322 static void mlx5_pci_resume(struct pci_dev *pdev)
1324 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1325 struct mlx5_priv *priv = &dev->priv;
1328 dev_info(&pdev->dev, "%s was called\n", __func__);
1330 err = mlx5_load_one(dev, priv, false);
1332 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1335 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1338 static const struct pci_error_handlers mlx5_err_handler = {
1339 .error_detected = mlx5_pci_err_detected,
1340 .slot_reset = mlx5_pci_slot_reset,
1341 .resume = mlx5_pci_resume
1344 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1346 bool fast_teardown = false, force_teardown = false;
1349 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1350 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1352 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1353 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1355 if (!fast_teardown && !force_teardown)
1358 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1359 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1363 /* Panic tear down fw command will stop the PCI bus communication
1364 * with the HCA, so the health polll is no longer needed.
1366 mlx5_drain_health_wq(dev);
1367 mlx5_stop_health_poll(dev, false);
1369 ret = mlx5_cmd_fast_teardown_hca(dev);
1373 ret = mlx5_cmd_force_teardown_hca(dev);
1377 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1378 mlx5_start_health_poll(dev);
1382 mlx5_enter_error_state(dev, true);
1384 /* Some platforms requiring freeing the IRQ's in the shutdown
1385 * flow. If they aren't freed they can't be allocated after
1386 * kexec. There is no need to cleanup the mlx5_core software
1389 mlx5_core_eq_free_irqs(dev);
1394 static void shutdown(struct pci_dev *pdev)
1396 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1397 struct mlx5_priv *priv = &dev->priv;
1400 dev_info(&pdev->dev, "Shutdown was called\n");
1401 err = mlx5_try_fast_unload(dev);
1403 mlx5_unload_one(dev, priv, false);
1404 mlx5_pci_disable_device(dev);
1407 static const struct pci_device_id mlx5_core_pci_table[] = {
1408 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1409 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1410 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1411 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1412 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1413 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1414 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1415 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1416 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1417 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1418 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1419 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1420 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1421 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1425 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1427 void mlx5_disable_device(struct mlx5_core_dev *dev)
1429 mlx5_pci_err_detected(dev->pdev, 0);
1432 void mlx5_recover_device(struct mlx5_core_dev *dev)
1434 mlx5_pci_disable_device(dev);
1435 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1436 mlx5_pci_resume(dev->pdev);
1439 static struct pci_driver mlx5_core_driver = {
1440 .name = DRIVER_NAME,
1441 .id_table = mlx5_core_pci_table,
1443 .remove = remove_one,
1444 .shutdown = shutdown,
1445 .err_handler = &mlx5_err_handler,
1446 .sriov_configure = mlx5_core_sriov_configure,
1449 static void mlx5_core_verify_params(void)
1451 if (prof_sel >= ARRAY_SIZE(profile)) {
1452 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1454 ARRAY_SIZE(profile) - 1,
1456 prof_sel = MLX5_DEFAULT_PROF;
1460 static int __init init(void)
1464 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1466 mlx5_core_verify_params();
1467 mlx5_fpga_ipsec_build_fs_cmds();
1468 mlx5_register_debugfs();
1470 err = pci_register_driver(&mlx5_core_driver);
1474 #ifdef CONFIG_MLX5_CORE_EN
1481 mlx5_unregister_debugfs();
1485 static void __exit cleanup(void)
1487 #ifdef CONFIG_MLX5_CORE_EN
1490 pci_unregister_driver(&mlx5_core_driver);
1491 mlx5_unregister_debugfs();
1495 module_exit(cleanup);