2 * Copyright (c) 2017, Mellanox Technologies. All rights reserved.
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33 #include <linux/mlx5/driver.h>
34 #include <linux/etherdevice.h>
35 #include <linux/idr.h>
36 #include "mlx5_core.h"
39 void mlx5_init_reserved_gids(struct mlx5_core_dev *dev)
41 unsigned int tblsz = MLX5_CAP_ROCE(dev, roce_address_table_size);
43 ida_init(&dev->roce.reserved_gids.ida);
44 dev->roce.reserved_gids.start = tblsz;
45 dev->roce.reserved_gids.count = 0;
48 void mlx5_cleanup_reserved_gids(struct mlx5_core_dev *dev)
50 WARN_ON(!ida_is_empty(&dev->roce.reserved_gids.ida));
51 dev->roce.reserved_gids.start = 0;
52 dev->roce.reserved_gids.count = 0;
53 ida_destroy(&dev->roce.reserved_gids.ida);
56 int mlx5_core_reserve_gids(struct mlx5_core_dev *dev, unsigned int count)
58 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
59 mlx5_core_err(dev, "Cannot reserve GIDs when interfaces are up\n");
62 if (dev->roce.reserved_gids.start < count) {
63 mlx5_core_warn(dev, "GID table exhausted attempting to reserve %d more GIDs\n",
67 if (dev->roce.reserved_gids.count + count > MLX5_MAX_RESERVED_GIDS) {
68 mlx5_core_warn(dev, "Unable to reserve %d more GIDs\n", count);
72 dev->roce.reserved_gids.start -= count;
73 dev->roce.reserved_gids.count += count;
74 mlx5_core_dbg(dev, "Reserved %u GIDs starting at %u\n",
75 dev->roce.reserved_gids.count,
76 dev->roce.reserved_gids.start);
80 void mlx5_core_unreserve_gids(struct mlx5_core_dev *dev, unsigned int count)
82 WARN(test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state), "Unreserving GIDs when interfaces are up");
83 WARN(count > dev->roce.reserved_gids.count, "Unreserving %u GIDs when only %u reserved",
84 count, dev->roce.reserved_gids.count);
86 dev->roce.reserved_gids.start += count;
87 dev->roce.reserved_gids.count -= count;
88 mlx5_core_dbg(dev, "%u GIDs starting at %u left reserved\n",
89 dev->roce.reserved_gids.count,
90 dev->roce.reserved_gids.start);
93 int mlx5_core_reserved_gid_alloc(struct mlx5_core_dev *dev, int *gid_index)
95 int end = dev->roce.reserved_gids.start +
96 dev->roce.reserved_gids.count;
99 index = ida_simple_get(&dev->roce.reserved_gids.ida,
100 dev->roce.reserved_gids.start, end,
105 mlx5_core_dbg(dev, "Allocating reserved GID %u\n", index);
110 void mlx5_core_reserved_gid_free(struct mlx5_core_dev *dev, int gid_index)
112 mlx5_core_dbg(dev, "Freeing reserved GID %u\n", gid_index);
113 ida_simple_remove(&dev->roce.reserved_gids.ida, gid_index);
116 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev)
118 return dev->roce.reserved_gids.count;
120 EXPORT_SYMBOL_GPL(mlx5_core_reserved_gids_count);
122 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
123 u8 roce_version, u8 roce_l3_type, const u8 *gid,
124 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num)
126 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
127 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
128 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
129 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
130 char *addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, in_addr,
132 void *addr_mac = MLX5_ADDR_OF(roce_addr_layout, in_addr,
134 int gidsz = MLX5_FLD_SZ_BYTES(roce_addr_layout, source_l3_address);
136 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
141 MLX5_SET_RA(in_addr, vlan_valid, 1);
142 MLX5_SET_RA(in_addr, vlan_id, vlan_id);
145 ether_addr_copy(addr_mac, mac);
146 MLX5_SET_RA(in_addr, roce_version, roce_version);
147 MLX5_SET_RA(in_addr, roce_l3_type, roce_l3_type);
148 memcpy(addr_l3_addr, gid, gidsz);
151 if (MLX5_CAP_GEN(dev, num_vhca_ports) > 0)
152 MLX5_SET(set_roce_address_in, in, vhca_port_num, port_num);
154 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
155 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
156 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
158 EXPORT_SYMBOL(mlx5_core_roce_gid_set);