drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /* Copyright (c) 2020, Mellanox Technologies inc.  All rights reserved. */
   3
   4 #include <devlink.h>
   5
   6 #include "fw_reset.h"
   7 #include "diag/fw_tracer.h"
   8 #include "lib/tout.h"
   9
  10 enum {
  11         MLX5_FW_RESET_FLAGS_RESET_REQUESTED,
  12         MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
  13         MLX5_FW_RESET_FLAGS_PENDING_COMP,
  14         MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS,
  15         MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED
  16 };
  17
  18 struct mlx5_fw_reset {
  19         struct mlx5_core_dev *dev;
  20         struct mlx5_nb nb;
  21         struct workqueue_struct *wq;
  22         struct work_struct fw_live_patch_work;
  23         struct work_struct reset_request_work;
  24         struct work_struct reset_unload_work;
  25         struct work_struct reset_reload_work;
  26         struct work_struct reset_now_work;
  27         struct work_struct reset_abort_work;
  28         unsigned long reset_flags;
  29         u8 reset_method;
  30         struct timer_list timer;
  31         struct completion done;
  32         int ret;
  33 };
  34
  35 enum {
  36         MLX5_FW_RST_STATE_IDLE = 0,
  37         MLX5_FW_RST_STATE_TOGGLE_REQ = 4,
  38 };
  39
  40 enum {
  41         MLX5_RST_STATE_BIT_NUM = 12,
  42         MLX5_RST_ACK_BIT_NUM = 22,
  43 };
  44
  45 static u8 mlx5_get_fw_rst_state(struct mlx5_core_dev *dev)
  46 {
  47         return (ioread32be(&dev->iseg->initializing) >> MLX5_RST_STATE_BIT_NUM) & 0xF;
  48 }
  49
  50 static void mlx5_set_fw_rst_ack(struct mlx5_core_dev *dev)
  51 {
  52         iowrite32be(BIT(MLX5_RST_ACK_BIT_NUM), &dev->iseg->initializing);
  53 }
  54
  55 static int mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink *devlink, u32 id,
  56                                                      struct devlink_param_gset_ctx *ctx,
  57                                                      struct netlink_ext_ack *extack)
  58 {
  59         struct mlx5_core_dev *dev = devlink_priv(devlink);
  60         struct mlx5_fw_reset *fw_reset;
  61
  62         fw_reset = dev->priv.fw_reset;
  63
  64         if (ctx->val.vbool)
  65                 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
  66         else
  67                 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
  68         return 0;
  69 }
  70
  71 static int mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink *devlink, u32 id,
  72                                                      struct devlink_param_gset_ctx *ctx)
  73 {
  74         struct mlx5_core_dev *dev = devlink_priv(devlink);
  75         struct mlx5_fw_reset *fw_reset;
  76
  77         fw_reset = dev->priv.fw_reset;
  78
  79         ctx->val.vbool = !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
  80                                    &fw_reset->reset_flags);
  81         return 0;
  82 }
  83
  84 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
  85                              u8 reset_type_sel, u8 sync_resp, bool sync_start)
  86 {
  87         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
  88         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
  89
  90         MLX5_SET(mfrl_reg, in, reset_level, reset_level);
  91         MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
  92         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp);
  93         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start);
  94
  95         return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1);
  96 }
  97
  98 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level,
  99                                u8 *reset_type, u8 *reset_state, u8 *reset_method)
 100 {
 101         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 102         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 103         int err;
 104
 105         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0);
 106         if (err)
 107                 return err;
 108
 109         if (reset_level)
 110                 *reset_level = MLX5_GET(mfrl_reg, out, reset_level);
 111         if (reset_type)
 112                 *reset_type = MLX5_GET(mfrl_reg, out, reset_type);
 113         if (reset_state)
 114                 *reset_state = MLX5_GET(mfrl_reg, out, reset_state);
 115         if (reset_method)
 116                 *reset_method = MLX5_GET(mfrl_reg, out, pci_reset_req_method);
 117
 118         return 0;
 119 }
 120
 121 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type)
 122 {
 123         return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL, NULL);
 124 }
 125
 126 static int mlx5_fw_reset_get_reset_method(struct mlx5_core_dev *dev,
 127                                           u8 *reset_method)
 128 {
 129         if (!MLX5_CAP_GEN(dev, pcie_reset_using_hotreset_method)) {
 130                 *reset_method = MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE;
 131                 return 0;
 132         }
 133
 134         return mlx5_reg_mfrl_query(dev, NULL, NULL, NULL, reset_method);
 135 }
 136
 137 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev,
 138                                              struct netlink_ext_ack *extack)
 139 {
 140         u8 reset_state;
 141
 142         if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state, NULL))
 143                 goto out;
 144
 145         if (!reset_state)
 146                 return 0;
 147
 148         switch (reset_state) {
 149         case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION:
 150         case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS:
 151                 NL_SET_ERR_MSG_MOD(extack, "Sync reset still in progress");
 152                 return -EBUSY;
 153         case MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT:
 154                 NL_SET_ERR_MSG_MOD(extack, "Sync reset negotiation timeout");
 155                 return -ETIMEDOUT;
 156         case MLX5_MFRL_REG_RESET_STATE_NACK:
 157                 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset");
 158                 return -EPERM;
 159         case MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT:
 160                 NL_SET_ERR_MSG_MOD(extack, "Sync reset unload timeout");
 161                 return -ETIMEDOUT;
 162         }
 163
 164 out:
 165         NL_SET_ERR_MSG_MOD(extack, "Sync reset failed");
 166         return -EIO;
 167 }
 168
 169 int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel,
 170                                  struct netlink_ext_ack *extack)
 171 {
 172         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 173         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 174         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 175         int err, rst_res;
 176
 177         set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 178
 179         MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3);
 180         MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
 181         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1);
 182         err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out),
 183                               MLX5_REG_MFRL, 0, 1, false);
 184         if (!err)
 185                 return 0;
 186
 187         clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 188         if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state)) {
 189                 rst_res = mlx5_fw_reset_get_reset_state_err(dev, extack);
 190                 return rst_res ? rst_res : err;
 191         }
 192
 193         NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed");
 194         return mlx5_cmd_check(dev, err, in, out);
 195 }
 196
 197 int mlx5_fw_reset_verify_fw_complete(struct mlx5_core_dev *dev,
 198                                      struct netlink_ext_ack *extack)
 199 {
 200         u8 rst_state;
 201         int err;
 202
 203         err = mlx5_fw_reset_get_reset_state_err(dev, extack);
 204         if (err)
 205                 return err;
 206
 207         rst_state = mlx5_get_fw_rst_state(dev);
 208         if (!rst_state)
 209                 return 0;
 210
 211         mlx5_core_err(dev, "Sync reset did not complete, state=%d\n", rst_state);
 212         NL_SET_ERR_MSG_MOD(extack, "Sync reset did not complete successfully");
 213         return rst_state;
 214 }
 215
 216 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
 217 {
 218         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false);
 219 }
 220
 221 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool unloaded)
 222 {
 223         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 224         struct devlink *devlink = priv_to_devlink(dev);
 225
 226         /* if this is the driver that initiated the fw reset, devlink completed the reload */
 227         if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
 228                 complete(&fw_reset->done);
 229         } else {
 230                 if (!unloaded)
 231                         mlx5_unload_one(dev, false);
 232                 if (mlx5_health_wait_pci_up(dev))
 233                         mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
 234                 else
 235                         mlx5_load_one(dev, true);
 236                 devl_lock(devlink);
 237                 devlink_remote_reload_actions_performed(devlink, 0,
 238                                                         BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
 239                                                         BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
 240                 devl_unlock(devlink);
 241         }
 242 }
 243
 244 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
 245 {
 246         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 247
 248         del_timer_sync(&fw_reset->timer);
 249 }
 250
 251 static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
 252 {
 253         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 254
 255         if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
 256                 mlx5_core_warn(dev, "Reset request was already cleared\n");
 257                 return -EALREADY;
 258         }
 259
 260         mlx5_stop_sync_reset_poll(dev);
 261         if (poll_health)
 262                 mlx5_start_health_poll(dev);
 263         return 0;
 264 }
 265
 266 static void mlx5_sync_reset_reload_work(struct work_struct *work)
 267 {
 268         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 269                                                       reset_reload_work);
 270         struct mlx5_core_dev *dev = fw_reset->dev;
 271
 272         mlx5_sync_reset_clear_reset_requested(dev, false);
 273         mlx5_enter_error_state(dev, true);
 274         mlx5_fw_reset_complete_reload(dev, false);
 275 }
 276
 277 #define MLX5_RESET_POLL_INTERVAL        (HZ / 10)
 278 static void poll_sync_reset(struct timer_list *t)
 279 {
 280         struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer);
 281         struct mlx5_core_dev *dev = fw_reset->dev;
 282         u32 fatal_error;
 283
 284         if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
 285                 return;
 286
 287         fatal_error = mlx5_health_check_fatal_sensors(dev);
 288
 289         if (fatal_error) {
 290                 mlx5_core_warn(dev, "Got Device Reset\n");
 291                 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
 292                         queue_work(fw_reset->wq, &fw_reset->reset_reload_work);
 293                 else
 294                         mlx5_core_err(dev, "Device is being removed, Drop new reset work\n");
 295                 return;
 296         }
 297
 298         mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL));
 299 }
 300
 301 static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev)
 302 {
 303         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 304
 305         timer_setup(&fw_reset->timer, poll_sync_reset, 0);
 306         fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL);
 307         add_timer(&fw_reset->timer);
 308 }
 309
 310 static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev)
 311 {
 312         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false);
 313 }
 314
 315 static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev)
 316 {
 317         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false);
 318 }
 319
 320 static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
 321 {
 322         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 323
 324         if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
 325                 mlx5_core_warn(dev, "Reset request was already set\n");
 326                 return -EALREADY;
 327         }
 328         mlx5_stop_health_poll(dev, true);
 329         mlx5_start_sync_reset_poll(dev);
 330         return 0;
 331 }
 332
 333 static void mlx5_fw_live_patch_event(struct work_struct *work)
 334 {
 335         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 336                                                       fw_live_patch_work);
 337         struct mlx5_core_dev *dev = fw_reset->dev;
 338
 339         mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev),
 340                        fw_rev_min(dev), fw_rev_sub(dev));
 341
 342         if (mlx5_fw_tracer_reload(dev->tracer))
 343                 mlx5_core_err(dev, "Failed to reload FW tracer\n");
 344 }
 345
 346 #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)
 347 static int mlx5_check_hotplug_interrupt(struct mlx5_core_dev *dev)
 348 {
 349         struct pci_dev *bridge = dev->pdev->bus->self;
 350         u16 reg16;
 351         int err;
 352
 353         if (!bridge)
 354                 return -EOPNOTSUPP;
 355
 356         err = pcie_capability_read_word(bridge, PCI_EXP_SLTCTL, &reg16);
 357         if (err)
 358                 return err;
 359
 360         if ((reg16 & PCI_EXP_SLTCTL_HPIE) && (reg16 & PCI_EXP_SLTCTL_DLLSCE)) {
 361                 mlx5_core_warn(dev, "FW reset is not supported as HotPlug is enabled\n");
 362                 return -EOPNOTSUPP;
 363         }
 364
 365         return 0;
 366 }
 367 #endif
 368
 369 static const struct pci_device_id mgt_ifc_device_ids[] = {
 370         { PCI_VDEVICE(MELLANOX, 0xc2d2) }, /* BlueField1 MGT interface device ID */
 371         { PCI_VDEVICE(MELLANOX, 0xc2d3) }, /* BlueField2 MGT interface device ID */
 372         { PCI_VDEVICE(MELLANOX, 0xc2d4) }, /* BlueField3-Lx MGT interface device ID */
 373         { PCI_VDEVICE(MELLANOX, 0xc2d5) }, /* BlueField3 MGT interface device ID */
 374         { PCI_VDEVICE(MELLANOX, 0xc2d6) }, /* BlueField4 MGT interface device ID */
 375 };
 376
 377 static bool mlx5_is_mgt_ifc_pci_device(struct mlx5_core_dev *dev, u16 dev_id)
 378 {
 379         int i;
 380
 381         for (i = 0; i < ARRAY_SIZE(mgt_ifc_device_ids); ++i)
 382                 if (mgt_ifc_device_ids[i].device == dev_id)
 383                         return true;
 384
 385         return false;
 386 }
 387
 388 static int mlx5_check_dev_ids(struct mlx5_core_dev *dev, u16 dev_id)
 389 {
 390         struct pci_bus *bridge_bus = dev->pdev->bus;
 391         struct pci_dev *sdev;
 392         u16 sdev_id;
 393         int err;
 394
 395         /* Check that all functions under the pci bridge are PFs of
 396          * this device otherwise fail this function.
 397          */
 398         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 399                 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id);
 400                 if (err)
 401                         return pcibios_err_to_errno(err);
 402
 403                 if (sdev_id == dev_id)
 404                         continue;
 405
 406                 if (mlx5_is_mgt_ifc_pci_device(dev, sdev_id))
 407                         continue;
 408
 409                 mlx5_core_warn(dev, "unrecognized dev_id (0x%x)\n", sdev_id);
 410                 return -EPERM;
 411         }
 412         return 0;
 413 }
 414
 415 static bool mlx5_is_reset_now_capable(struct mlx5_core_dev *dev,
 416                                       u8 reset_method)
 417 {
 418         u16 dev_id;
 419         int err;
 420
 421         if (!MLX5_CAP_GEN(dev, fast_teardown)) {
 422                 mlx5_core_warn(dev, "fast teardown is not supported by firmware\n");
 423                 return false;
 424         }
 425
 426 #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)
 427         if (reset_method != MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET) {
 428                 err = mlx5_check_hotplug_interrupt(dev);
 429                 if (err)
 430                         return false;
 431         }
 432 #endif
 433
 434         err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
 435         if (err)
 436                 return false;
 437         return (!mlx5_check_dev_ids(dev, dev_id));
 438 }
 439
 440 static void mlx5_sync_reset_request_event(struct work_struct *work)
 441 {
 442         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 443                                                       reset_request_work);
 444         struct mlx5_core_dev *dev = fw_reset->dev;
 445         int err;
 446
 447         err = mlx5_fw_reset_get_reset_method(dev, &fw_reset->reset_method);
 448         if (err)
 449                 mlx5_core_warn(dev, "Failed reading MFRL, err %d\n", err);
 450
 451         if (err || test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags) ||
 452             !mlx5_is_reset_now_capable(dev, fw_reset->reset_method)) {
 453                 err = mlx5_fw_reset_set_reset_sync_nack(dev);
 454                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s",
 455                                err ? "Failed" : "Sent");
 456                 return;
 457         }
 458         if (mlx5_sync_reset_set_reset_requested(dev))
 459                 return;
 460
 461         err = mlx5_fw_reset_set_reset_sync_ack(dev);
 462         if (err)
 463                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err);
 464         else
 465                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n");
 466 }
 467
 468 static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev, u16 dev_id)
 469 {
 470         struct pci_bus *bridge_bus = dev->pdev->bus;
 471         struct pci_dev *bridge = bridge_bus->self;
 472         unsigned long timeout;
 473         struct pci_dev *sdev;
 474         int cap, err;
 475         u16 reg16;
 476
 477         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
 478         if (!cap)
 479                 return -EOPNOTSUPP;
 480
 481         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 482                 pci_save_state(sdev);
 483                 pci_cfg_access_lock(sdev);
 484         }
 485         /* PCI link toggle */
 486         err = pcie_capability_set_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD);
 487         if (err)
 488                 return pcibios_err_to_errno(err);
 489         msleep(500);
 490         err = pcie_capability_clear_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD);
 491         if (err)
 492                 return pcibios_err_to_errno(err);
 493
 494         /* Check link */
 495         if (!bridge->link_active_reporting) {
 496                 mlx5_core_warn(dev, "No PCI link reporting capability\n");
 497                 msleep(1000);
 498                 goto restore;
 499         }
 500
 501         timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE));
 502         do {
 503                 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, &reg16);
 504                 if (err)
 505                         return pcibios_err_to_errno(err);
 506                 if (reg16 & PCI_EXP_LNKSTA_DLLLA)
 507                         break;
 508                 msleep(20);
 509         } while (!time_after(jiffies, timeout));
 510
 511         if (reg16 & PCI_EXP_LNKSTA_DLLLA) {
 512                 mlx5_core_info(dev, "PCI Link up\n");
 513         } else {
 514                 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n",
 515                               reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
 516                 err = -ETIMEDOUT;
 517                 goto restore;
 518         }
 519
 520         do {
 521                 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &reg16);
 522                 if (err)
 523                         return pcibios_err_to_errno(err);
 524                 if (reg16 == dev_id)
 525                         break;
 526                 msleep(20);
 527         } while (!time_after(jiffies, timeout));
 528
 529         if (reg16 == dev_id) {
 530                 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n");
 531         } else {
 532                 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n",
 533                               reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
 534                 err = -ETIMEDOUT;
 535         }
 536
 537 restore:
 538         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 539                 pci_cfg_access_unlock(sdev);
 540                 pci_restore_state(sdev);
 541         }
 542
 543         return err;
 544 }
 545
 546 static int mlx5_pci_reset_bus(struct mlx5_core_dev *dev)
 547 {
 548         if (!MLX5_CAP_GEN(dev, pcie_reset_using_hotreset_method))
 549                 return -EOPNOTSUPP;
 550
 551         return pci_reset_bus(dev->pdev);
 552 }
 553
 554 static int mlx5_sync_pci_reset(struct mlx5_core_dev *dev, u8 reset_method)
 555 {
 556         u16 dev_id;
 557         int err;
 558
 559         err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
 560         if (err)
 561                 return pcibios_err_to_errno(err);
 562         err = mlx5_check_dev_ids(dev, dev_id);
 563         if (err)
 564                 return err;
 565
 566         switch (reset_method) {
 567         case MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE:
 568                 err = mlx5_pci_link_toggle(dev, dev_id);
 569                 if (err)
 570                         mlx5_core_warn(dev, "mlx5_pci_link_toggle failed\n");
 571                 break;
 572         case MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET:
 573                 err = mlx5_pci_reset_bus(dev);
 574                 if (err)
 575                         mlx5_core_warn(dev, "mlx5_pci_reset_bus failed\n");
 576                 break;
 577         default:
 578                 return -EOPNOTSUPP;
 579         }
 580
 581         return err;
 582 }
 583
 584 static void mlx5_sync_reset_now_event(struct work_struct *work)
 585 {
 586         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 587                                                       reset_now_work);
 588         struct mlx5_core_dev *dev = fw_reset->dev;
 589         int err;
 590
 591         if (mlx5_sync_reset_clear_reset_requested(dev, false))
 592                 return;
 593
 594         mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n");
 595
 596         err = mlx5_cmd_fast_teardown_hca(dev);
 597         if (err) {
 598                 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err);
 599                 goto done;
 600         }
 601
 602         err = mlx5_sync_pci_reset(dev, fw_reset->reset_method);
 603         if (err) {
 604                 mlx5_core_warn(dev, "mlx5_sync_pci_reset failed, no reset done, err %d\n", err);
 605                 set_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags);
 606         }
 607
 608         mlx5_enter_error_state(dev, true);
 609 done:
 610         fw_reset->ret = err;
 611         mlx5_fw_reset_complete_reload(dev, false);
 612 }
 613
 614 static void mlx5_sync_reset_unload_event(struct work_struct *work)
 615 {
 616         struct mlx5_fw_reset *fw_reset;
 617         struct mlx5_core_dev *dev;
 618         unsigned long timeout;
 619         bool reset_action;
 620         u8 rst_state;
 621         int err;
 622
 623         fw_reset = container_of(work, struct mlx5_fw_reset, reset_unload_work);
 624         dev = fw_reset->dev;
 625
 626         if (mlx5_sync_reset_clear_reset_requested(dev, false))
 627                 return;
 628
 629         mlx5_core_warn(dev, "Sync Reset Unload. Function is forced down.\n");
 630
 631         err = mlx5_cmd_fast_teardown_hca(dev);
 632         if (err)
 633                 mlx5_core_warn(dev, "Fast teardown failed, unloading, err %d\n", err);
 634         else
 635                 mlx5_enter_error_state(dev, true);
 636
 637         if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags))
 638                 mlx5_unload_one_devl_locked(dev, false);
 639         else
 640                 mlx5_unload_one(dev, false);
 641
 642         mlx5_set_fw_rst_ack(dev);
 643         mlx5_core_warn(dev, "Sync Reset Unload done, device reset expected\n");
 644
 645         reset_action = false;
 646         timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, RESET_UNLOAD));
 647         do {
 648                 rst_state = mlx5_get_fw_rst_state(dev);
 649                 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ ||
 650                     rst_state == MLX5_FW_RST_STATE_IDLE) {
 651                         reset_action = true;
 652                         break;
 653                 }
 654                 msleep(20);
 655         } while (!time_after(jiffies, timeout));
 656
 657         if (!reset_action) {
 658                 mlx5_core_err(dev, "Got timeout waiting for sync reset action, state = %u\n",
 659                               rst_state);
 660                 fw_reset->ret = -ETIMEDOUT;
 661                 goto done;
 662         }
 663
 664         mlx5_core_warn(dev, "Sync Reset, got reset action. rst_state = %u\n", rst_state);
 665         if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ) {
 666                 err = mlx5_sync_pci_reset(dev, fw_reset->reset_method);
 667                 if (err) {
 668                         mlx5_core_warn(dev, "mlx5_sync_pci_reset failed, err %d\n", err);
 669                         fw_reset->ret = err;
 670                 }
 671         }
 672
 673 done:
 674         mlx5_fw_reset_complete_reload(dev, true);
 675 }
 676
 677 static void mlx5_sync_reset_abort_event(struct work_struct *work)
 678 {
 679         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 680                                                       reset_abort_work);
 681         struct mlx5_core_dev *dev = fw_reset->dev;
 682
 683         if (mlx5_sync_reset_clear_reset_requested(dev, true))
 684                 return;
 685         mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");
 686 }
 687
 688 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe)
 689 {
 690         struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe;
 691         u8 sync_event_rst_type;
 692
 693         sync_fw_update_eqe = &eqe->data.sync_fw_update;
 694         sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK;
 695         switch (sync_event_rst_type) {
 696         case MLX5_SYNC_RST_STATE_RESET_REQUEST:
 697                 queue_work(fw_reset->wq, &fw_reset->reset_request_work);
 698                 break;
 699         case MLX5_SYNC_RST_STATE_RESET_UNLOAD:
 700                 queue_work(fw_reset->wq, &fw_reset->reset_unload_work);
 701                 break;
 702         case MLX5_SYNC_RST_STATE_RESET_NOW:
 703                 queue_work(fw_reset->wq, &fw_reset->reset_now_work);
 704                 break;
 705         case MLX5_SYNC_RST_STATE_RESET_ABORT:
 706                 queue_work(fw_reset->wq, &fw_reset->reset_abort_work);
 707                 break;
 708         }
 709 }
 710
 711 static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data)
 712 {
 713         struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb);
 714         struct mlx5_eqe *eqe = data;
 715
 716         if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
 717                 return NOTIFY_DONE;
 718
 719         switch (eqe->sub_type) {
 720         case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT:
 721                 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work);
 722                 break;
 723         case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT:
 724                 mlx5_sync_reset_events_handle(fw_reset, eqe);
 725                 break;
 726         default:
 727                 return NOTIFY_DONE;
 728         }
 729
 730         return NOTIFY_OK;
 731 }
 732
 733 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
 734 {
 735         unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE);
 736         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 737         unsigned long timeout;
 738         int err;
 739
 740         if (MLX5_CAP_GEN(dev, pci_sync_for_fw_update_with_driver_unload))
 741                 pci_sync_update_timeout += mlx5_tout_ms(dev, RESET_UNLOAD);
 742         timeout = msecs_to_jiffies(pci_sync_update_timeout);
 743         if (!wait_for_completion_timeout(&fw_reset->done, timeout)) {
 744                 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n",
 745                                pci_sync_update_timeout / 1000);
 746                 err = -ETIMEDOUT;
 747                 goto out;
 748         }
 749         err = fw_reset->ret;
 750         if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) {
 751                 mlx5_unload_one_devl_locked(dev, false);
 752                 mlx5_load_one_devl_locked(dev, true);
 753         }
 754 out:
 755         clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 756         return err;
 757 }
 758
 759 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
 760 {
 761         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 762
 763         if (!fw_reset)
 764                 return;
 765
 766         MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT);
 767         mlx5_eq_notifier_register(dev, &fw_reset->nb);
 768 }
 769
 770 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev)
 771 {
 772         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 773
 774         if (!fw_reset)
 775                 return;
 776
 777         mlx5_eq_notifier_unregister(dev, &fw_reset->nb);
 778 }
 779
 780 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev)
 781 {
 782         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 783
 784         if (!fw_reset)
 785                 return;
 786
 787         set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags);
 788         cancel_work_sync(&fw_reset->fw_live_patch_work);
 789         cancel_work_sync(&fw_reset->reset_request_work);
 790         cancel_work_sync(&fw_reset->reset_unload_work);
 791         cancel_work_sync(&fw_reset->reset_reload_work);
 792         cancel_work_sync(&fw_reset->reset_now_work);
 793         cancel_work_sync(&fw_reset->reset_abort_work);
 794 }
 795
 796 static const struct devlink_param mlx5_fw_reset_devlink_params[] = {
 797         DEVLINK_PARAM_GENERIC(ENABLE_REMOTE_DEV_RESET, BIT(DEVLINK_PARAM_CMODE_RUNTIME),
 798                               mlx5_fw_reset_enable_remote_dev_reset_get,
 799                               mlx5_fw_reset_enable_remote_dev_reset_set, NULL),
 800 };
 801
 802 int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
 803 {
 804         struct mlx5_fw_reset *fw_reset;
 805         int err;
 806
 807         if (!MLX5_CAP_MCAM_REG(dev, mfrl))
 808                 return 0;
 809
 810         fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
 811         if (!fw_reset)
 812                 return -ENOMEM;
 813         fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events");
 814         if (!fw_reset->wq) {
 815                 kfree(fw_reset);
 816                 return -ENOMEM;
 817         }
 818
 819         fw_reset->dev = dev;
 820         dev->priv.fw_reset = fw_reset;
 821
 822         err = devl_params_register(priv_to_devlink(dev),
 823                                    mlx5_fw_reset_devlink_params,
 824                                    ARRAY_SIZE(mlx5_fw_reset_devlink_params));
 825         if (err) {
 826                 destroy_workqueue(fw_reset->wq);
 827                 kfree(fw_reset);
 828                 return err;
 829         }
 830
 831         INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event);
 832         INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event);
 833         INIT_WORK(&fw_reset->reset_unload_work, mlx5_sync_reset_unload_event);
 834         INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work);
 835         INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event);
 836         INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event);
 837
 838         init_completion(&fw_reset->done);
 839         return 0;
 840 }
 841
 842 void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev)
 843 {
 844         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 845
 846         if (!fw_reset)
 847                 return;
 848
 849         devl_params_unregister(priv_to_devlink(dev),
 850                                mlx5_fw_reset_devlink_params,
 851                                ARRAY_SIZE(mlx5_fw_reset_devlink_params));
 852         destroy_workqueue(fw_reset->wq);
 853         kfree(dev->priv.fw_reset);
 854 }