drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /* Copyright (c) 2020, Mellanox Technologies inc.  All rights reserved. */
   3
   4 #include <devlink.h>
   5
   6 #include "fw_reset.h"
   7 #include "diag/fw_tracer.h"
   8 #include "lib/tout.h"
   9
  10 enum {
  11         MLX5_FW_RESET_FLAGS_RESET_REQUESTED,
  12         MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
  13         MLX5_FW_RESET_FLAGS_PENDING_COMP,
  14         MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS,
  15         MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED
  16 };
  17
  18 struct mlx5_fw_reset {
  19         struct mlx5_core_dev *dev;
  20         struct mlx5_nb nb;
  21         struct workqueue_struct *wq;
  22         struct work_struct fw_live_patch_work;
  23         struct work_struct reset_request_work;
  24         struct work_struct reset_unload_work;
  25         struct work_struct reset_reload_work;
  26         struct work_struct reset_now_work;
  27         struct work_struct reset_abort_work;
  28         unsigned long reset_flags;
  29         struct timer_list timer;
  30         struct completion done;
  31         int ret;
  32 };
  33
  34 enum {
  35         MLX5_FW_RST_STATE_IDLE = 0,
  36         MLX5_FW_RST_STATE_TOGGLE_REQ = 4,
  37 };
  38
  39 enum {
  40         MLX5_RST_STATE_BIT_NUM = 12,
  41         MLX5_RST_ACK_BIT_NUM = 22,
  42 };
  43
  44 static u8 mlx5_get_fw_rst_state(struct mlx5_core_dev *dev)
  45 {
  46         return (ioread32be(&dev->iseg->initializing) >> MLX5_RST_STATE_BIT_NUM) & 0xF;
  47 }
  48
  49 static void mlx5_set_fw_rst_ack(struct mlx5_core_dev *dev)
  50 {
  51         iowrite32be(BIT(MLX5_RST_ACK_BIT_NUM), &dev->iseg->initializing);
  52 }
  53
  54 static int mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink *devlink, u32 id,
  55                                                      struct devlink_param_gset_ctx *ctx)
  56 {
  57         struct mlx5_core_dev *dev = devlink_priv(devlink);
  58         struct mlx5_fw_reset *fw_reset;
  59
  60         fw_reset = dev->priv.fw_reset;
  61
  62         if (ctx->val.vbool)
  63                 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
  64         else
  65                 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
  66         return 0;
  67 }
  68
  69 static int mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink *devlink, u32 id,
  70                                                      struct devlink_param_gset_ctx *ctx)
  71 {
  72         struct mlx5_core_dev *dev = devlink_priv(devlink);
  73         struct mlx5_fw_reset *fw_reset;
  74
  75         fw_reset = dev->priv.fw_reset;
  76
  77         ctx->val.vbool = !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
  78                                    &fw_reset->reset_flags);
  79         return 0;
  80 }
  81
  82 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
  83                              u8 reset_type_sel, u8 sync_resp, bool sync_start)
  84 {
  85         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
  86         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
  87
  88         MLX5_SET(mfrl_reg, in, reset_level, reset_level);
  89         MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
  90         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp);
  91         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start);
  92
  93         return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1);
  94 }
  95
  96 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level,
  97                                u8 *reset_type, u8 *reset_state)
  98 {
  99         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 100         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 101         int err;
 102
 103         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0);
 104         if (err)
 105                 return err;
 106
 107         if (reset_level)
 108                 *reset_level = MLX5_GET(mfrl_reg, out, reset_level);
 109         if (reset_type)
 110                 *reset_type = MLX5_GET(mfrl_reg, out, reset_type);
 111         if (reset_state)
 112                 *reset_state = MLX5_GET(mfrl_reg, out, reset_state);
 113
 114         return 0;
 115 }
 116
 117 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type)
 118 {
 119         return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL);
 120 }
 121
 122 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev,
 123                                              struct netlink_ext_ack *extack)
 124 {
 125         u8 reset_state;
 126
 127         if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state))
 128                 goto out;
 129
 130         switch (reset_state) {
 131         case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION:
 132         case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS:
 133                 NL_SET_ERR_MSG_MOD(extack, "Sync reset was already triggered");
 134                 return -EBUSY;
 135         case MLX5_MFRL_REG_RESET_STATE_TIMEOUT:
 136                 NL_SET_ERR_MSG_MOD(extack, "Sync reset got timeout");
 137                 return -ETIMEDOUT;
 138         case MLX5_MFRL_REG_RESET_STATE_NACK:
 139                 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset");
 140                 return -EPERM;
 141         }
 142
 143 out:
 144         NL_SET_ERR_MSG_MOD(extack, "Sync reset failed");
 145         return -EIO;
 146 }
 147
 148 int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel,
 149                                  struct netlink_ext_ack *extack)
 150 {
 151         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 152         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 153         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 154         int err;
 155
 156         set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 157
 158         MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3);
 159         MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
 160         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1);
 161         err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out),
 162                               MLX5_REG_MFRL, 0, 1, false);
 163         if (!err)
 164                 return 0;
 165
 166         clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 167         if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state))
 168                 return mlx5_fw_reset_get_reset_state_err(dev, extack);
 169
 170         NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed");
 171         return mlx5_cmd_check(dev, err, in, out);
 172 }
 173
 174 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
 175 {
 176         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false);
 177 }
 178
 179 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool unloaded)
 180 {
 181         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 182
 183         /* if this is the driver that initiated the fw reset, devlink completed the reload */
 184         if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
 185                 complete(&fw_reset->done);
 186         } else {
 187                 if (!unloaded)
 188                         mlx5_unload_one(dev, false);
 189                 if (mlx5_health_wait_pci_up(dev))
 190                         mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
 191                 else
 192                         mlx5_load_one(dev, true);
 193                 devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0,
 194                                                         BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
 195                                                         BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
 196         }
 197 }
 198
 199 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
 200 {
 201         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 202
 203         del_timer_sync(&fw_reset->timer);
 204 }
 205
 206 static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
 207 {
 208         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 209
 210         if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
 211                 mlx5_core_warn(dev, "Reset request was already cleared\n");
 212                 return -EALREADY;
 213         }
 214
 215         mlx5_stop_sync_reset_poll(dev);
 216         if (poll_health)
 217                 mlx5_start_health_poll(dev);
 218         return 0;
 219 }
 220
 221 static void mlx5_sync_reset_reload_work(struct work_struct *work)
 222 {
 223         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 224                                                       reset_reload_work);
 225         struct mlx5_core_dev *dev = fw_reset->dev;
 226
 227         mlx5_sync_reset_clear_reset_requested(dev, false);
 228         mlx5_enter_error_state(dev, true);
 229         mlx5_fw_reset_complete_reload(dev, false);
 230 }
 231
 232 #define MLX5_RESET_POLL_INTERVAL        (HZ / 10)
 233 static void poll_sync_reset(struct timer_list *t)
 234 {
 235         struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer);
 236         struct mlx5_core_dev *dev = fw_reset->dev;
 237         u32 fatal_error;
 238
 239         if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
 240                 return;
 241
 242         fatal_error = mlx5_health_check_fatal_sensors(dev);
 243
 244         if (fatal_error) {
 245                 mlx5_core_warn(dev, "Got Device Reset\n");
 246                 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
 247                         queue_work(fw_reset->wq, &fw_reset->reset_reload_work);
 248                 else
 249                         mlx5_core_err(dev, "Device is being removed, Drop new reset work\n");
 250                 return;
 251         }
 252
 253         mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL));
 254 }
 255
 256 static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev)
 257 {
 258         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 259
 260         timer_setup(&fw_reset->timer, poll_sync_reset, 0);
 261         fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL);
 262         add_timer(&fw_reset->timer);
 263 }
 264
 265 static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev)
 266 {
 267         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false);
 268 }
 269
 270 static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev)
 271 {
 272         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false);
 273 }
 274
 275 static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
 276 {
 277         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 278
 279         if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
 280                 mlx5_core_warn(dev, "Reset request was already set\n");
 281                 return -EALREADY;
 282         }
 283         mlx5_stop_health_poll(dev, true);
 284         mlx5_start_sync_reset_poll(dev);
 285         return 0;
 286 }
 287
 288 static void mlx5_fw_live_patch_event(struct work_struct *work)
 289 {
 290         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 291                                                       fw_live_patch_work);
 292         struct mlx5_core_dev *dev = fw_reset->dev;
 293
 294         mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev),
 295                        fw_rev_min(dev), fw_rev_sub(dev));
 296
 297         if (mlx5_fw_tracer_reload(dev->tracer))
 298                 mlx5_core_err(dev, "Failed to reload FW tracer\n");
 299 }
 300
 301 static int mlx5_check_dev_ids(struct mlx5_core_dev *dev, u16 dev_id)
 302 {
 303         struct pci_bus *bridge_bus = dev->pdev->bus;
 304         struct pci_dev *sdev;
 305         u16 sdev_id;
 306         int err;
 307
 308         /* Check that all functions under the pci bridge are PFs of
 309          * this device otherwise fail this function.
 310          */
 311         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 312                 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id);
 313                 if (err)
 314                         return err;
 315                 if (sdev_id != dev_id) {
 316                         mlx5_core_warn(dev, "unrecognized dev_id (0x%x)\n", sdev_id);
 317                         return -EPERM;
 318                 }
 319         }
 320         return 0;
 321 }
 322
 323 static bool mlx5_is_reset_now_capable(struct mlx5_core_dev *dev)
 324 {
 325         u16 dev_id;
 326         int err;
 327
 328         if (!MLX5_CAP_GEN(dev, fast_teardown)) {
 329                 mlx5_core_warn(dev, "fast teardown is not supported by firmware\n");
 330                 return false;
 331         }
 332
 333         err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
 334         if (err)
 335                 return false;
 336         return (!mlx5_check_dev_ids(dev, dev_id));
 337 }
 338
 339 static void mlx5_sync_reset_request_event(struct work_struct *work)
 340 {
 341         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 342                                                       reset_request_work);
 343         struct mlx5_core_dev *dev = fw_reset->dev;
 344         int err;
 345
 346         if (test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags) ||
 347             !mlx5_is_reset_now_capable(dev)) {
 348                 err = mlx5_fw_reset_set_reset_sync_nack(dev);
 349                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s",
 350                                err ? "Failed" : "Sent");
 351                 return;
 352         }
 353         if (mlx5_sync_reset_set_reset_requested(dev))
 354                 return;
 355
 356         err = mlx5_fw_reset_set_reset_sync_ack(dev);
 357         if (err)
 358                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err);
 359         else
 360                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n");
 361 }
 362
 363 static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev)
 364 {
 365         struct pci_bus *bridge_bus = dev->pdev->bus;
 366         struct pci_dev *bridge = bridge_bus->self;
 367         unsigned long timeout;
 368         struct pci_dev *sdev;
 369         u16 reg16, dev_id;
 370         int cap, err;
 371         u32 reg32;
 372
 373         err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
 374         if (err)
 375                 return err;
 376         err = mlx5_check_dev_ids(dev, dev_id);
 377         if (err)
 378                 return err;
 379         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
 380         if (!cap)
 381                 return -EOPNOTSUPP;
 382
 383         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 384                 pci_save_state(sdev);
 385                 pci_cfg_access_lock(sdev);
 386         }
 387         /* PCI link toggle */
 388         err = pci_read_config_word(bridge, cap + PCI_EXP_LNKCTL, &reg16);
 389         if (err)
 390                 return err;
 391         reg16 |= PCI_EXP_LNKCTL_LD;
 392         err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16);
 393         if (err)
 394                 return err;
 395         msleep(500);
 396         reg16 &= ~PCI_EXP_LNKCTL_LD;
 397         err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16);
 398         if (err)
 399                 return err;
 400
 401         /* Check link */
 402         err = pci_read_config_dword(bridge, cap + PCI_EXP_LNKCAP, &reg32);
 403         if (err)
 404                 return err;
 405         if (!(reg32 & PCI_EXP_LNKCAP_DLLLARC)) {
 406                 mlx5_core_warn(dev, "No PCI link reporting capability (0x%08x)\n", reg32);
 407                 msleep(1000);
 408                 goto restore;
 409         }
 410
 411         timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE));
 412         do {
 413                 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, &reg16);
 414                 if (err)
 415                         return err;
 416                 if (reg16 & PCI_EXP_LNKSTA_DLLLA)
 417                         break;
 418                 msleep(20);
 419         } while (!time_after(jiffies, timeout));
 420
 421         if (reg16 & PCI_EXP_LNKSTA_DLLLA) {
 422                 mlx5_core_info(dev, "PCI Link up\n");
 423         } else {
 424                 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n",
 425                               reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
 426                 err = -ETIMEDOUT;
 427                 goto restore;
 428         }
 429
 430         do {
 431                 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &reg16);
 432                 if (err)
 433                         return err;
 434                 if (reg16 == dev_id)
 435                         break;
 436                 msleep(20);
 437         } while (!time_after(jiffies, timeout));
 438
 439         if (reg16 == dev_id) {
 440                 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n");
 441         } else {
 442                 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n",
 443                               reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
 444                 err = -ETIMEDOUT;
 445         }
 446
 447 restore:
 448         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 449                 pci_cfg_access_unlock(sdev);
 450                 pci_restore_state(sdev);
 451         }
 452
 453         return err;
 454 }
 455
 456 static void mlx5_sync_reset_now_event(struct work_struct *work)
 457 {
 458         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 459                                                       reset_now_work);
 460         struct mlx5_core_dev *dev = fw_reset->dev;
 461         int err;
 462
 463         if (mlx5_sync_reset_clear_reset_requested(dev, false))
 464                 return;
 465
 466         mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n");
 467
 468         err = mlx5_cmd_fast_teardown_hca(dev);
 469         if (err) {
 470                 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err);
 471                 goto done;
 472         }
 473
 474         err = mlx5_pci_link_toggle(dev);
 475         if (err) {
 476                 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, no reset done, err %d\n", err);
 477                 set_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags);
 478         }
 479
 480         mlx5_enter_error_state(dev, true);
 481 done:
 482         fw_reset->ret = err;
 483         mlx5_fw_reset_complete_reload(dev, false);
 484 }
 485
 486 static void mlx5_sync_reset_unload_event(struct work_struct *work)
 487 {
 488         struct mlx5_fw_reset *fw_reset;
 489         struct mlx5_core_dev *dev;
 490         unsigned long timeout;
 491         bool reset_action;
 492         u8 rst_state;
 493         int err;
 494
 495         fw_reset = container_of(work, struct mlx5_fw_reset, reset_unload_work);
 496         dev = fw_reset->dev;
 497
 498         if (mlx5_sync_reset_clear_reset_requested(dev, false))
 499                 return;
 500
 501         mlx5_core_warn(dev, "Sync Reset Unload. Function is forced down.\n");
 502
 503         err = mlx5_cmd_fast_teardown_hca(dev);
 504         if (err)
 505                 mlx5_core_warn(dev, "Fast teardown failed, unloading, err %d\n", err);
 506         else
 507                 mlx5_enter_error_state(dev, true);
 508
 509         if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags))
 510                 mlx5_unload_one_devl_locked(dev, false);
 511         else
 512                 mlx5_unload_one(dev, false);
 513
 514         mlx5_set_fw_rst_ack(dev);
 515         mlx5_core_warn(dev, "Sync Reset Unload done, device reset expected\n");
 516
 517         reset_action = false;
 518         timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, RESET_UNLOAD));
 519         do {
 520                 rst_state = mlx5_get_fw_rst_state(dev);
 521                 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ ||
 522                     rst_state == MLX5_FW_RST_STATE_IDLE) {
 523                         reset_action = true;
 524                         break;
 525                 }
 526                 msleep(20);
 527         } while (!time_after(jiffies, timeout));
 528
 529         if (!reset_action) {
 530                 mlx5_core_err(dev, "Got timeout waiting for sync reset action, state = %u\n",
 531                               rst_state);
 532                 fw_reset->ret = -ETIMEDOUT;
 533                 goto done;
 534         }
 535
 536         mlx5_core_warn(dev, "Sync Reset, got reset action. rst_state = %u\n", rst_state);
 537         if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ) {
 538                 err = mlx5_pci_link_toggle(dev);
 539                 if (err) {
 540                         mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, err %d\n", err);
 541                         fw_reset->ret = err;
 542                 }
 543         }
 544
 545 done:
 546         mlx5_fw_reset_complete_reload(dev, true);
 547 }
 548
 549 static void mlx5_sync_reset_abort_event(struct work_struct *work)
 550 {
 551         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 552                                                       reset_abort_work);
 553         struct mlx5_core_dev *dev = fw_reset->dev;
 554
 555         if (mlx5_sync_reset_clear_reset_requested(dev, true))
 556                 return;
 557         mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");
 558 }
 559
 560 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe)
 561 {
 562         struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe;
 563         u8 sync_event_rst_type;
 564
 565         sync_fw_update_eqe = &eqe->data.sync_fw_update;
 566         sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK;
 567         switch (sync_event_rst_type) {
 568         case MLX5_SYNC_RST_STATE_RESET_REQUEST:
 569                 queue_work(fw_reset->wq, &fw_reset->reset_request_work);
 570                 break;
 571         case MLX5_SYNC_RST_STATE_RESET_UNLOAD:
 572                 queue_work(fw_reset->wq, &fw_reset->reset_unload_work);
 573                 break;
 574         case MLX5_SYNC_RST_STATE_RESET_NOW:
 575                 queue_work(fw_reset->wq, &fw_reset->reset_now_work);
 576                 break;
 577         case MLX5_SYNC_RST_STATE_RESET_ABORT:
 578                 queue_work(fw_reset->wq, &fw_reset->reset_abort_work);
 579                 break;
 580         }
 581 }
 582
 583 static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data)
 584 {
 585         struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb);
 586         struct mlx5_eqe *eqe = data;
 587
 588         if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
 589                 return NOTIFY_DONE;
 590
 591         switch (eqe->sub_type) {
 592         case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT:
 593                 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work);
 594                 break;
 595         case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT:
 596                 mlx5_sync_reset_events_handle(fw_reset, eqe);
 597                 break;
 598         default:
 599                 return NOTIFY_DONE;
 600         }
 601
 602         return NOTIFY_OK;
 603 }
 604
 605 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
 606 {
 607         unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE);
 608         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 609         unsigned long timeout;
 610         int err;
 611
 612         if (MLX5_CAP_GEN(dev, pci_sync_for_fw_update_with_driver_unload))
 613                 pci_sync_update_timeout += mlx5_tout_ms(dev, RESET_UNLOAD);
 614         timeout = msecs_to_jiffies(pci_sync_update_timeout);
 615         if (!wait_for_completion_timeout(&fw_reset->done, timeout)) {
 616                 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n",
 617                                pci_sync_update_timeout / 1000);
 618                 err = -ETIMEDOUT;
 619                 goto out;
 620         }
 621         err = fw_reset->ret;
 622         if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) {
 623                 mlx5_unload_one_devl_locked(dev, false);
 624                 mlx5_load_one_devl_locked(dev, true);
 625         }
 626 out:
 627         clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 628         return err;
 629 }
 630
 631 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
 632 {
 633         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 634
 635         MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT);
 636         mlx5_eq_notifier_register(dev, &fw_reset->nb);
 637 }
 638
 639 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev)
 640 {
 641         mlx5_eq_notifier_unregister(dev, &dev->priv.fw_reset->nb);
 642 }
 643
 644 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev)
 645 {
 646         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 647
 648         set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags);
 649         cancel_work_sync(&fw_reset->fw_live_patch_work);
 650         cancel_work_sync(&fw_reset->reset_request_work);
 651         cancel_work_sync(&fw_reset->reset_unload_work);
 652         cancel_work_sync(&fw_reset->reset_reload_work);
 653         cancel_work_sync(&fw_reset->reset_now_work);
 654         cancel_work_sync(&fw_reset->reset_abort_work);
 655 }
 656
 657 static const struct devlink_param mlx5_fw_reset_devlink_params[] = {
 658         DEVLINK_PARAM_GENERIC(ENABLE_REMOTE_DEV_RESET, BIT(DEVLINK_PARAM_CMODE_RUNTIME),
 659                               mlx5_fw_reset_enable_remote_dev_reset_get,
 660                               mlx5_fw_reset_enable_remote_dev_reset_set, NULL),
 661 };
 662
 663 int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
 664 {
 665         struct mlx5_fw_reset *fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
 666         int err;
 667
 668         if (!fw_reset)
 669                 return -ENOMEM;
 670         fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events");
 671         if (!fw_reset->wq) {
 672                 kfree(fw_reset);
 673                 return -ENOMEM;
 674         }
 675
 676         fw_reset->dev = dev;
 677         dev->priv.fw_reset = fw_reset;
 678
 679         err = devl_params_register(priv_to_devlink(dev),
 680                                    mlx5_fw_reset_devlink_params,
 681                                    ARRAY_SIZE(mlx5_fw_reset_devlink_params));
 682         if (err) {
 683                 destroy_workqueue(fw_reset->wq);
 684                 kfree(fw_reset);
 685                 return err;
 686         }
 687
 688         INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event);
 689         INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event);
 690         INIT_WORK(&fw_reset->reset_unload_work, mlx5_sync_reset_unload_event);
 691         INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work);
 692         INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event);
 693         INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event);
 694
 695         init_completion(&fw_reset->done);
 696         return 0;
 697 }
 698
 699 void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev)
 700 {
 701         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 702
 703         devl_params_unregister(priv_to_devlink(dev),
 704                                mlx5_fw_reset_devlink_params,
 705                                ARRAY_SIZE(mlx5_fw_reset_devlink_params));
 706         destroy_workqueue(fw_reset->wq);
 707         kfree(dev->priv.fw_reset);
 708 }