drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /* Copyright (c) 2020, Mellanox Technologies inc.  All rights reserved. */
   3
   4 #include <devlink.h>
   5
   6 #include "fw_reset.h"
   7 #include "diag/fw_tracer.h"
   8 #include "lib/tout.h"
   9
  10 enum {
  11         MLX5_FW_RESET_FLAGS_RESET_REQUESTED,
  12         MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
  13         MLX5_FW_RESET_FLAGS_PENDING_COMP,
  14         MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS,
  15         MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED
  16 };
  17
  18 struct mlx5_fw_reset {
  19         struct mlx5_core_dev *dev;
  20         struct mlx5_nb nb;
  21         struct workqueue_struct *wq;
  22         struct work_struct fw_live_patch_work;
  23         struct work_struct reset_request_work;
  24         struct work_struct reset_unload_work;
  25         struct work_struct reset_reload_work;
  26         struct work_struct reset_now_work;
  27         struct work_struct reset_abort_work;
  28         unsigned long reset_flags;
  29         struct timer_list timer;
  30         struct completion done;
  31         int ret;
  32 };
  33
  34 enum {
  35         MLX5_FW_RST_STATE_IDLE = 0,
  36         MLX5_FW_RST_STATE_TOGGLE_REQ = 4,
  37 };
  38
  39 enum {
  40         MLX5_RST_STATE_BIT_NUM = 12,
  41         MLX5_RST_ACK_BIT_NUM = 22,
  42 };
  43
  44 static u8 mlx5_get_fw_rst_state(struct mlx5_core_dev *dev)
  45 {
  46         return (ioread32be(&dev->iseg->initializing) >> MLX5_RST_STATE_BIT_NUM) & 0xF;
  47 }
  48
  49 static void mlx5_set_fw_rst_ack(struct mlx5_core_dev *dev)
  50 {
  51         iowrite32be(BIT(MLX5_RST_ACK_BIT_NUM), &dev->iseg->initializing);
  52 }
  53
  54 static int mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink *devlink, u32 id,
  55                                                      struct devlink_param_gset_ctx *ctx)
  56 {
  57         struct mlx5_core_dev *dev = devlink_priv(devlink);
  58         struct mlx5_fw_reset *fw_reset;
  59
  60         fw_reset = dev->priv.fw_reset;
  61
  62         if (ctx->val.vbool)
  63                 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
  64         else
  65                 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
  66         return 0;
  67 }
  68
  69 static int mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink *devlink, u32 id,
  70                                                      struct devlink_param_gset_ctx *ctx)
  71 {
  72         struct mlx5_core_dev *dev = devlink_priv(devlink);
  73         struct mlx5_fw_reset *fw_reset;
  74
  75         fw_reset = dev->priv.fw_reset;
  76
  77         ctx->val.vbool = !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
  78                                    &fw_reset->reset_flags);
  79         return 0;
  80 }
  81
  82 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
  83                              u8 reset_type_sel, u8 sync_resp, bool sync_start)
  84 {
  85         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
  86         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
  87
  88         MLX5_SET(mfrl_reg, in, reset_level, reset_level);
  89         MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
  90         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp);
  91         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start);
  92
  93         return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1);
  94 }
  95
  96 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level,
  97                                u8 *reset_type, u8 *reset_state)
  98 {
  99         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 100         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 101         int err;
 102
 103         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0);
 104         if (err)
 105                 return err;
 106
 107         if (reset_level)
 108                 *reset_level = MLX5_GET(mfrl_reg, out, reset_level);
 109         if (reset_type)
 110                 *reset_type = MLX5_GET(mfrl_reg, out, reset_type);
 111         if (reset_state)
 112                 *reset_state = MLX5_GET(mfrl_reg, out, reset_state);
 113
 114         return 0;
 115 }
 116
 117 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type)
 118 {
 119         return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL);
 120 }
 121
 122 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev,
 123                                              struct netlink_ext_ack *extack)
 124 {
 125         u8 reset_state;
 126
 127         if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state))
 128                 goto out;
 129
 130         switch (reset_state) {
 131         case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION:
 132         case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS:
 133                 NL_SET_ERR_MSG_MOD(extack, "Sync reset was already triggered");
 134                 return -EBUSY;
 135         case MLX5_MFRL_REG_RESET_STATE_TIMEOUT:
 136                 NL_SET_ERR_MSG_MOD(extack, "Sync reset got timeout");
 137                 return -ETIMEDOUT;
 138         case MLX5_MFRL_REG_RESET_STATE_NACK:
 139                 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset");
 140                 return -EPERM;
 141         }
 142
 143 out:
 144         NL_SET_ERR_MSG_MOD(extack, "Sync reset failed");
 145         return -EIO;
 146 }
 147
 148 int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel,
 149                                  struct netlink_ext_ack *extack)
 150 {
 151         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 152         u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 153         u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
 154         int err;
 155
 156         set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 157
 158         MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3);
 159         MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
 160         MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1);
 161         err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out),
 162                               MLX5_REG_MFRL, 0, 1, false);
 163         if (!err)
 164                 return 0;
 165
 166         clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 167         if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state))
 168                 return mlx5_fw_reset_get_reset_state_err(dev, extack);
 169
 170         NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed");
 171         return mlx5_cmd_check(dev, err, in, out);
 172 }
 173
 174 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
 175 {
 176         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false);
 177 }
 178
 179 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool unloaded)
 180 {
 181         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 182
 183         /* if this is the driver that initiated the fw reset, devlink completed the reload */
 184         if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
 185                 complete(&fw_reset->done);
 186         } else {
 187                 if (!unloaded)
 188                         mlx5_unload_one(dev, false);
 189                 if (mlx5_health_wait_pci_up(dev))
 190                         mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
 191                 else
 192                         mlx5_load_one(dev, true);
 193                 devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0,
 194                                                         BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
 195                                                         BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
 196         }
 197 }
 198
 199 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
 200 {
 201         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 202
 203         del_timer_sync(&fw_reset->timer);
 204 }
 205
 206 static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
 207 {
 208         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 209
 210         if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
 211                 mlx5_core_warn(dev, "Reset request was already cleared\n");
 212                 return -EALREADY;
 213         }
 214
 215         mlx5_stop_sync_reset_poll(dev);
 216         if (poll_health)
 217                 mlx5_start_health_poll(dev);
 218         return 0;
 219 }
 220
 221 static void mlx5_sync_reset_reload_work(struct work_struct *work)
 222 {
 223         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 224                                                       reset_reload_work);
 225         struct mlx5_core_dev *dev = fw_reset->dev;
 226
 227         mlx5_sync_reset_clear_reset_requested(dev, false);
 228         mlx5_enter_error_state(dev, true);
 229         mlx5_fw_reset_complete_reload(dev, false);
 230 }
 231
 232 #define MLX5_RESET_POLL_INTERVAL        (HZ / 10)
 233 static void poll_sync_reset(struct timer_list *t)
 234 {
 235         struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer);
 236         struct mlx5_core_dev *dev = fw_reset->dev;
 237         u32 fatal_error;
 238
 239         if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
 240                 return;
 241
 242         fatal_error = mlx5_health_check_fatal_sensors(dev);
 243
 244         if (fatal_error) {
 245                 mlx5_core_warn(dev, "Got Device Reset\n");
 246                 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
 247                         queue_work(fw_reset->wq, &fw_reset->reset_reload_work);
 248                 else
 249                         mlx5_core_err(dev, "Device is being removed, Drop new reset work\n");
 250                 return;
 251         }
 252
 253         mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL));
 254 }
 255
 256 static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev)
 257 {
 258         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 259
 260         timer_setup(&fw_reset->timer, poll_sync_reset, 0);
 261         fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL);
 262         add_timer(&fw_reset->timer);
 263 }
 264
 265 static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev)
 266 {
 267         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false);
 268 }
 269
 270 static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev)
 271 {
 272         return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false);
 273 }
 274
 275 static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
 276 {
 277         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 278
 279         if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
 280                 mlx5_core_warn(dev, "Reset request was already set\n");
 281                 return -EALREADY;
 282         }
 283         mlx5_stop_health_poll(dev, true);
 284         mlx5_start_sync_reset_poll(dev);
 285         return 0;
 286 }
 287
 288 static void mlx5_fw_live_patch_event(struct work_struct *work)
 289 {
 290         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 291                                                       fw_live_patch_work);
 292         struct mlx5_core_dev *dev = fw_reset->dev;
 293
 294         mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev),
 295                        fw_rev_min(dev), fw_rev_sub(dev));
 296
 297         if (mlx5_fw_tracer_reload(dev->tracer))
 298                 mlx5_core_err(dev, "Failed to reload FW tracer\n");
 299 }
 300
 301 static int mlx5_check_dev_ids(struct mlx5_core_dev *dev, u16 dev_id)
 302 {
 303         struct pci_bus *bridge_bus = dev->pdev->bus;
 304         struct pci_dev *sdev;
 305         u16 sdev_id;
 306         int err;
 307
 308         /* Check that all functions under the pci bridge are PFs of
 309          * this device otherwise fail this function.
 310          */
 311         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 312                 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id);
 313                 if (err)
 314                         return err;
 315                 if (sdev_id != dev_id) {
 316                         mlx5_core_warn(dev, "unrecognized dev_id (0x%x)\n", sdev_id);
 317                         return -EPERM;
 318                 }
 319         }
 320         return 0;
 321 }
 322
 323 static bool mlx5_is_reset_now_capable(struct mlx5_core_dev *dev)
 324 {
 325         u16 dev_id;
 326         int err;
 327
 328         if (!MLX5_CAP_GEN(dev, fast_teardown)) {
 329                 mlx5_core_warn(dev, "fast teardown is not supported by firmware\n");
 330                 return false;
 331         }
 332
 333         err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
 334         if (err)
 335                 return false;
 336         return (!mlx5_check_dev_ids(dev, dev_id));
 337 }
 338
 339 static void mlx5_sync_reset_request_event(struct work_struct *work)
 340 {
 341         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 342                                                       reset_request_work);
 343         struct mlx5_core_dev *dev = fw_reset->dev;
 344         int err;
 345
 346         if (test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags) ||
 347             !mlx5_is_reset_now_capable(dev)) {
 348                 err = mlx5_fw_reset_set_reset_sync_nack(dev);
 349                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s",
 350                                err ? "Failed" : "Sent");
 351                 return;
 352         }
 353         if (mlx5_sync_reset_set_reset_requested(dev))
 354                 return;
 355
 356         err = mlx5_fw_reset_set_reset_sync_ack(dev);
 357         if (err)
 358                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err);
 359         else
 360                 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n");
 361 }
 362
 363 static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev)
 364 {
 365         struct pci_bus *bridge_bus = dev->pdev->bus;
 366         struct pci_dev *bridge = bridge_bus->self;
 367         unsigned long timeout;
 368         struct pci_dev *sdev;
 369         u16 reg16, dev_id;
 370         int cap, err;
 371
 372         err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
 373         if (err)
 374                 return err;
 375         err = mlx5_check_dev_ids(dev, dev_id);
 376         if (err)
 377                 return err;
 378         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
 379         if (!cap)
 380                 return -EOPNOTSUPP;
 381
 382         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 383                 pci_save_state(sdev);
 384                 pci_cfg_access_lock(sdev);
 385         }
 386         /* PCI link toggle */
 387         err = pci_read_config_word(bridge, cap + PCI_EXP_LNKCTL, &reg16);
 388         if (err)
 389                 return err;
 390         reg16 |= PCI_EXP_LNKCTL_LD;
 391         err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16);
 392         if (err)
 393                 return err;
 394         msleep(500);
 395         reg16 &= ~PCI_EXP_LNKCTL_LD;
 396         err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16);
 397         if (err)
 398                 return err;
 399
 400         /* Check link */
 401         if (!bridge->link_active_reporting) {
 402                 mlx5_core_warn(dev, "No PCI link reporting capability\n");
 403                 msleep(1000);
 404                 goto restore;
 405         }
 406
 407         timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE));
 408         do {
 409                 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, &reg16);
 410                 if (err)
 411                         return err;
 412                 if (reg16 & PCI_EXP_LNKSTA_DLLLA)
 413                         break;
 414                 msleep(20);
 415         } while (!time_after(jiffies, timeout));
 416
 417         if (reg16 & PCI_EXP_LNKSTA_DLLLA) {
 418                 mlx5_core_info(dev, "PCI Link up\n");
 419         } else {
 420                 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n",
 421                               reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
 422                 err = -ETIMEDOUT;
 423                 goto restore;
 424         }
 425
 426         do {
 427                 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &reg16);
 428                 if (err)
 429                         return err;
 430                 if (reg16 == dev_id)
 431                         break;
 432                 msleep(20);
 433         } while (!time_after(jiffies, timeout));
 434
 435         if (reg16 == dev_id) {
 436                 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n");
 437         } else {
 438                 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n",
 439                               reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
 440                 err = -ETIMEDOUT;
 441         }
 442
 443 restore:
 444         list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
 445                 pci_cfg_access_unlock(sdev);
 446                 pci_restore_state(sdev);
 447         }
 448
 449         return err;
 450 }
 451
 452 static void mlx5_sync_reset_now_event(struct work_struct *work)
 453 {
 454         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 455                                                       reset_now_work);
 456         struct mlx5_core_dev *dev = fw_reset->dev;
 457         int err;
 458
 459         if (mlx5_sync_reset_clear_reset_requested(dev, false))
 460                 return;
 461
 462         mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n");
 463
 464         err = mlx5_cmd_fast_teardown_hca(dev);
 465         if (err) {
 466                 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err);
 467                 goto done;
 468         }
 469
 470         err = mlx5_pci_link_toggle(dev);
 471         if (err) {
 472                 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, no reset done, err %d\n", err);
 473                 set_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags);
 474         }
 475
 476         mlx5_enter_error_state(dev, true);
 477 done:
 478         fw_reset->ret = err;
 479         mlx5_fw_reset_complete_reload(dev, false);
 480 }
 481
 482 static void mlx5_sync_reset_unload_event(struct work_struct *work)
 483 {
 484         struct mlx5_fw_reset *fw_reset;
 485         struct mlx5_core_dev *dev;
 486         unsigned long timeout;
 487         bool reset_action;
 488         u8 rst_state;
 489         int err;
 490
 491         fw_reset = container_of(work, struct mlx5_fw_reset, reset_unload_work);
 492         dev = fw_reset->dev;
 493
 494         if (mlx5_sync_reset_clear_reset_requested(dev, false))
 495                 return;
 496
 497         mlx5_core_warn(dev, "Sync Reset Unload. Function is forced down.\n");
 498
 499         err = mlx5_cmd_fast_teardown_hca(dev);
 500         if (err)
 501                 mlx5_core_warn(dev, "Fast teardown failed, unloading, err %d\n", err);
 502         else
 503                 mlx5_enter_error_state(dev, true);
 504
 505         if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags))
 506                 mlx5_unload_one_devl_locked(dev, false);
 507         else
 508                 mlx5_unload_one(dev, false);
 509
 510         mlx5_set_fw_rst_ack(dev);
 511         mlx5_core_warn(dev, "Sync Reset Unload done, device reset expected\n");
 512
 513         reset_action = false;
 514         timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, RESET_UNLOAD));
 515         do {
 516                 rst_state = mlx5_get_fw_rst_state(dev);
 517                 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ ||
 518                     rst_state == MLX5_FW_RST_STATE_IDLE) {
 519                         reset_action = true;
 520                         break;
 521                 }
 522                 msleep(20);
 523         } while (!time_after(jiffies, timeout));
 524
 525         if (!reset_action) {
 526                 mlx5_core_err(dev, "Got timeout waiting for sync reset action, state = %u\n",
 527                               rst_state);
 528                 fw_reset->ret = -ETIMEDOUT;
 529                 goto done;
 530         }
 531
 532         mlx5_core_warn(dev, "Sync Reset, got reset action. rst_state = %u\n", rst_state);
 533         if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ) {
 534                 err = mlx5_pci_link_toggle(dev);
 535                 if (err) {
 536                         mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, err %d\n", err);
 537                         fw_reset->ret = err;
 538                 }
 539         }
 540
 541 done:
 542         mlx5_fw_reset_complete_reload(dev, true);
 543 }
 544
 545 static void mlx5_sync_reset_abort_event(struct work_struct *work)
 546 {
 547         struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 548                                                       reset_abort_work);
 549         struct mlx5_core_dev *dev = fw_reset->dev;
 550
 551         if (mlx5_sync_reset_clear_reset_requested(dev, true))
 552                 return;
 553         mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");
 554 }
 555
 556 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe)
 557 {
 558         struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe;
 559         u8 sync_event_rst_type;
 560
 561         sync_fw_update_eqe = &eqe->data.sync_fw_update;
 562         sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK;
 563         switch (sync_event_rst_type) {
 564         case MLX5_SYNC_RST_STATE_RESET_REQUEST:
 565                 queue_work(fw_reset->wq, &fw_reset->reset_request_work);
 566                 break;
 567         case MLX5_SYNC_RST_STATE_RESET_UNLOAD:
 568                 queue_work(fw_reset->wq, &fw_reset->reset_unload_work);
 569                 break;
 570         case MLX5_SYNC_RST_STATE_RESET_NOW:
 571                 queue_work(fw_reset->wq, &fw_reset->reset_now_work);
 572                 break;
 573         case MLX5_SYNC_RST_STATE_RESET_ABORT:
 574                 queue_work(fw_reset->wq, &fw_reset->reset_abort_work);
 575                 break;
 576         }
 577 }
 578
 579 static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data)
 580 {
 581         struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb);
 582         struct mlx5_eqe *eqe = data;
 583
 584         if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
 585                 return NOTIFY_DONE;
 586
 587         switch (eqe->sub_type) {
 588         case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT:
 589                 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work);
 590                 break;
 591         case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT:
 592                 mlx5_sync_reset_events_handle(fw_reset, eqe);
 593                 break;
 594         default:
 595                 return NOTIFY_DONE;
 596         }
 597
 598         return NOTIFY_OK;
 599 }
 600
 601 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
 602 {
 603         unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE);
 604         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 605         unsigned long timeout;
 606         int err;
 607
 608         if (MLX5_CAP_GEN(dev, pci_sync_for_fw_update_with_driver_unload))
 609                 pci_sync_update_timeout += mlx5_tout_ms(dev, RESET_UNLOAD);
 610         timeout = msecs_to_jiffies(pci_sync_update_timeout);
 611         if (!wait_for_completion_timeout(&fw_reset->done, timeout)) {
 612                 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n",
 613                                pci_sync_update_timeout / 1000);
 614                 err = -ETIMEDOUT;
 615                 goto out;
 616         }
 617         err = fw_reset->ret;
 618         if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) {
 619                 mlx5_unload_one_devl_locked(dev, false);
 620                 mlx5_load_one_devl_locked(dev, true);
 621         }
 622 out:
 623         clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 624         return err;
 625 }
 626
 627 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
 628 {
 629         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 630
 631         MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT);
 632         mlx5_eq_notifier_register(dev, &fw_reset->nb);
 633 }
 634
 635 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev)
 636 {
 637         mlx5_eq_notifier_unregister(dev, &dev->priv.fw_reset->nb);
 638 }
 639
 640 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev)
 641 {
 642         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 643
 644         set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags);
 645         cancel_work_sync(&fw_reset->fw_live_patch_work);
 646         cancel_work_sync(&fw_reset->reset_request_work);
 647         cancel_work_sync(&fw_reset->reset_unload_work);
 648         cancel_work_sync(&fw_reset->reset_reload_work);
 649         cancel_work_sync(&fw_reset->reset_now_work);
 650         cancel_work_sync(&fw_reset->reset_abort_work);
 651 }
 652
 653 static const struct devlink_param mlx5_fw_reset_devlink_params[] = {
 654         DEVLINK_PARAM_GENERIC(ENABLE_REMOTE_DEV_RESET, BIT(DEVLINK_PARAM_CMODE_RUNTIME),
 655                               mlx5_fw_reset_enable_remote_dev_reset_get,
 656                               mlx5_fw_reset_enable_remote_dev_reset_set, NULL),
 657 };
 658
 659 int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
 660 {
 661         struct mlx5_fw_reset *fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
 662         int err;
 663
 664         if (!fw_reset)
 665                 return -ENOMEM;
 666         fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events");
 667         if (!fw_reset->wq) {
 668                 kfree(fw_reset);
 669                 return -ENOMEM;
 670         }
 671
 672         fw_reset->dev = dev;
 673         dev->priv.fw_reset = fw_reset;
 674
 675         err = devl_params_register(priv_to_devlink(dev),
 676                                    mlx5_fw_reset_devlink_params,
 677                                    ARRAY_SIZE(mlx5_fw_reset_devlink_params));
 678         if (err) {
 679                 destroy_workqueue(fw_reset->wq);
 680                 kfree(fw_reset);
 681                 return err;
 682         }
 683
 684         INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event);
 685         INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event);
 686         INIT_WORK(&fw_reset->reset_unload_work, mlx5_sync_reset_unload_event);
 687         INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work);
 688         INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event);
 689         INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event);
 690
 691         init_completion(&fw_reset->done);
 692         return 0;
 693 }
 694
 695 void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev)
 696 {
 697         struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 698
 699         devl_params_unregister(priv_to_devlink(dev),
 700                                mlx5_fw_reset_devlink_params,
 701                                ARRAY_SIZE(mlx5_fw_reset_devlink_params));
 702         destroy_workqueue(fw_reset->wq);
 703         kfree(dev->priv.fw_reset);
 704 }