2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/etherdevice.h>
34 #include <linux/idr.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/mlx5_ifc.h>
37 #include <linux/mlx5/vport.h>
38 #include <linux/mlx5/fs.h>
39 #include "mlx5_core.h"
41 #include "esw/indir_table.h"
42 #include "esw/acl/ofld.h"
46 #include "lib/devcom.h"
48 #include "lib/fs_chains.h"
50 #include "en/mapping.h"
53 #include "en/tc/post_meter.h"
55 #define mlx5_esw_for_each_rep(esw, i, rep) \
56 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
58 #define mlx5_esw_for_each_sf_rep(esw, i, rep) \
59 xa_for_each_marked(&((esw)->offloads.vport_reps), i, rep, MLX5_ESW_VPT_SF)
61 #define mlx5_esw_for_each_vf_rep(esw, index, rep) \
62 mlx5_esw_for_each_entry_marked(&((esw)->offloads.vport_reps), index, \
63 rep, (esw)->esw_funcs.num_vfs, MLX5_ESW_VPT_VF)
65 /* There are two match-all miss flows, one for unicast dst mac and
68 #define MLX5_ESW_MISS_FLOWS (2)
69 #define UPLINK_REP_INDEX 0
71 #define MLX5_ESW_VPORT_TBL_SIZE 128
72 #define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
74 #define MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
76 static struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
77 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
78 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
82 static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
85 return xa_load(&esw->offloads.vport_reps, vport_num);
89 mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
90 struct mlx5_flow_spec *spec,
91 struct mlx5_esw_flow_attr *attr)
93 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) || !attr || !attr->in_rep)
97 spec->flow_context.flow_source = mlx5e_tc_int_port_get_flow_source(attr->int_port);
102 spec->flow_context.flow_source = (attr->in_rep->vport == MLX5_VPORT_UPLINK) ?
103 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
104 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
107 /* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
108 * are not needed as well in the following process. So clear them all for simplicity.
111 mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
113 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
116 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
117 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
119 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
120 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
122 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
123 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
128 mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
129 struct mlx5_flow_spec *spec,
130 struct mlx5_flow_attr *attr,
131 struct mlx5_eswitch *src_esw,
134 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
139 /* Use metadata matching because vport is not represented by single
140 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
142 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
143 if (mlx5_esw_indir_table_decap_vport(attr))
144 vport = mlx5_esw_indir_table_decap_vport(attr);
146 if (!attr->chain && esw_attr && esw_attr->int_port)
148 mlx5e_tc_int_port_get_metadata_for_match(esw_attr->int_port);
151 mlx5_eswitch_get_vport_metadata_for_match(src_esw, vport);
153 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
154 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, metadata);
156 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
157 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
158 mlx5_eswitch_get_vport_metadata_mask());
160 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
162 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
163 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
165 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
166 MLX5_SET(fte_match_set_misc, misc,
167 source_eswitch_owner_vhca_id,
168 MLX5_CAP_GEN(src_esw->dev, vhca_id));
170 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
171 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
172 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
173 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
174 source_eswitch_owner_vhca_id);
176 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
181 esw_setup_decap_indir(struct mlx5_eswitch *esw,
182 struct mlx5_flow_attr *attr)
184 struct mlx5_flow_table *ft;
186 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
189 ft = mlx5_esw_indir_table_get(esw, attr,
190 mlx5_esw_indir_table_decap_vport(attr), true);
191 return PTR_ERR_OR_ZERO(ft);
195 esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
196 struct mlx5_flow_attr *attr)
198 if (mlx5_esw_indir_table_decap_vport(attr))
199 mlx5_esw_indir_table_put(esw,
200 mlx5_esw_indir_table_decap_vport(attr),
205 esw_setup_mtu_dest(struct mlx5_flow_destination *dest,
206 struct mlx5e_meter_attr *meter,
209 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_RANGE;
210 dest[i].range.field = MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN;
211 dest[i].range.min = 0;
212 dest[i].range.max = meter->params.mtu;
213 dest[i].range.hit_ft = mlx5e_post_meter_get_mtu_true_ft(meter->post_meter);
214 dest[i].range.miss_ft = mlx5e_post_meter_get_mtu_false_ft(meter->post_meter);
220 esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
221 struct mlx5_flow_act *flow_act,
225 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
226 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
227 dest[i].sampler_id = sampler_id;
233 esw_setup_ft_dest(struct mlx5_flow_destination *dest,
234 struct mlx5_flow_act *flow_act,
235 struct mlx5_eswitch *esw,
236 struct mlx5_flow_attr *attr,
239 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
240 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
241 dest[i].ft = attr->dest_ft;
243 if (mlx5_esw_indir_table_decap_vport(attr))
244 return esw_setup_decap_indir(esw, attr);
249 esw_setup_accept_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
250 struct mlx5_fs_chains *chains, int i)
252 if (mlx5_chains_ignore_flow_level_supported(chains))
253 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
254 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
255 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
259 esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
260 struct mlx5_eswitch *esw, int i)
262 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level))
263 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
264 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
265 dest[i].ft = mlx5_eswitch_get_slow_fdb(esw);
269 esw_setup_chain_dest(struct mlx5_flow_destination *dest,
270 struct mlx5_flow_act *flow_act,
271 struct mlx5_fs_chains *chains,
272 u32 chain, u32 prio, u32 level,
275 struct mlx5_flow_table *ft;
277 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
278 ft = mlx5_chains_get_table(chains, chain, prio, level);
282 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
287 static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
290 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
291 struct mlx5_fs_chains *chains = esw_chains(esw);
294 for (i = from; i < to; i++)
295 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
296 mlx5_chains_put_table(chains, 0, 1, 0);
297 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
298 esw_attr->dests[i].mdev))
299 mlx5_esw_indir_table_put(esw, esw_attr->dests[i].rep->vport,
304 esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
308 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
309 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
315 esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
316 struct mlx5_flow_act *flow_act,
317 struct mlx5_eswitch *esw,
318 struct mlx5_fs_chains *chains,
319 struct mlx5_flow_attr *attr,
322 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
325 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
328 /* flow steering cannot handle more than one dest with the same ft
331 if (esw_attr->out_count - esw_attr->split_count > 1)
334 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
338 if (esw_attr->dests[esw_attr->split_count].pkt_reformat) {
339 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
340 flow_act->pkt_reformat = esw_attr->dests[esw_attr->split_count].pkt_reformat;
347 static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
348 struct mlx5_flow_attr *attr)
350 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
352 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
356 esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
358 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
362 /* Indirect table is supported only for flows with in_port uplink
363 * and the destination is vport on the same eswitch as the uplink,
364 * return false in case at least one of destinations doesn't meet
367 for (i = esw_attr->split_count; i < esw_attr->out_count; i++) {
368 if (esw_attr->dests[i].rep &&
369 mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
370 esw_attr->dests[i].mdev)) {
381 esw_setup_indir_table(struct mlx5_flow_destination *dest,
382 struct mlx5_flow_act *flow_act,
383 struct mlx5_eswitch *esw,
384 struct mlx5_flow_attr *attr,
385 bool ignore_flow_lvl,
388 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
391 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
394 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
396 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
397 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
399 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr,
400 esw_attr->dests[j].rep->vport, false);
401 if (IS_ERR(dest[*i].ft)) {
402 err = PTR_ERR(dest[*i].ft);
403 goto err_indir_tbl_get;
407 if (mlx5_esw_indir_table_decap_vport(attr)) {
408 err = esw_setup_decap_indir(esw, attr);
410 goto err_indir_tbl_get;
416 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
420 static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
422 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
424 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
425 esw_cleanup_decap_indir(esw, attr);
429 esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
431 mlx5_chains_put_table(chains, chain, prio, level);
435 esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
436 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
437 int attr_idx, int dest_idx, bool pkt_reformat)
439 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
440 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport;
441 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
442 dest[dest_idx].vport.vhca_id =
443 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
444 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
445 if (dest[dest_idx].vport.num == MLX5_VPORT_UPLINK &&
446 mlx5_lag_is_mpesw(esw->dev))
447 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_UPLINK;
449 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
451 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
452 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
454 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
455 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
460 esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
461 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
466 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
467 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
472 esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
474 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
475 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
476 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
480 esw_setup_dests(struct mlx5_flow_destination *dest,
481 struct mlx5_flow_act *flow_act,
482 struct mlx5_eswitch *esw,
483 struct mlx5_flow_attr *attr,
484 struct mlx5_flow_spec *spec,
487 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
488 struct mlx5_fs_chains *chains = esw_chains(esw);
491 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
492 esw_src_port_rewrite_supported(esw))
493 attr->flags |= MLX5_ATTR_FLAG_SRC_REWRITE;
495 if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH) {
496 esw_setup_slow_path_dest(dest, flow_act, esw, *i);
501 if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
502 esw_setup_sampler_dest(dest, flow_act, attr->sample_attr.sampler_id, *i);
504 } else if (attr->flags & MLX5_ATTR_FLAG_ACCEPT) {
505 esw_setup_accept_dest(dest, flow_act, chains, *i);
507 } else if (attr->flags & MLX5_ATTR_FLAG_MTU) {
508 err = esw_setup_mtu_dest(dest, &attr->meter_attr, *i);
510 } else if (esw_is_indir_table(esw, attr)) {
511 err = esw_setup_indir_table(dest, flow_act, esw, attr, true, i);
512 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
513 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
515 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
518 err = esw_setup_ft_dest(dest, flow_act, esw, attr, *i);
520 } else if (attr->dest_chain) {
521 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
532 esw_cleanup_dests(struct mlx5_eswitch *esw,
533 struct mlx5_flow_attr *attr)
535 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
536 struct mlx5_fs_chains *chains = esw_chains(esw);
539 esw_cleanup_decap_indir(esw, attr);
540 } else if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
541 if (attr->dest_chain)
542 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
543 else if (esw_is_indir_table(esw, attr))
544 esw_cleanup_indir_table(esw, attr);
545 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
546 esw_cleanup_chain_src_port_rewrite(esw, attr);
551 esw_setup_meter(struct mlx5_flow_attr *attr, struct mlx5_flow_act *flow_act)
553 struct mlx5e_flow_meter_handle *meter;
555 meter = attr->meter_attr.meter;
556 flow_act->exe_aso.type = attr->exe_aso_type;
557 flow_act->exe_aso.object_id = meter->obj_id;
558 flow_act->exe_aso.flow_meter.meter_idx = meter->idx;
559 flow_act->exe_aso.flow_meter.init_color = MLX5_FLOW_METER_COLOR_GREEN;
560 /* use metadata reg 5 for packet color */
561 flow_act->exe_aso.return_reg_id = 5;
564 struct mlx5_flow_handle *
565 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
566 struct mlx5_flow_spec *spec,
567 struct mlx5_flow_attr *attr)
569 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
570 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
571 struct mlx5_fs_chains *chains = esw_chains(esw);
572 bool split = !!(esw_attr->split_count);
573 struct mlx5_vport_tbl_attr fwd_attr;
574 struct mlx5_flow_destination *dest;
575 struct mlx5_flow_handle *rule;
576 struct mlx5_flow_table *fdb;
579 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
580 return ERR_PTR(-EOPNOTSUPP);
582 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
583 return ERR_PTR(-EOPNOTSUPP);
585 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
587 return ERR_PTR(-ENOMEM);
589 flow_act.action = attr->action;
591 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
592 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
593 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
594 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
595 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
596 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
597 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
598 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
602 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
604 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
607 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
610 goto err_create_goto_table;
614 if (esw_attr->decap_pkt_reformat)
615 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
617 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
618 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
619 dest[i].counter_id = mlx5_fc_id(attr->counter);
623 if (attr->outer_match_level != MLX5_MATCH_NONE)
624 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
625 if (attr->inner_match_level != MLX5_MATCH_NONE)
626 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
628 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
629 flow_act.modify_hdr = attr->modify_hdr;
631 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
632 attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)
633 esw_setup_meter(attr, &flow_act);
636 fwd_attr.chain = attr->chain;
637 fwd_attr.prio = attr->prio;
638 fwd_attr.vport = esw_attr->in_rep->vport;
639 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
641 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
643 if (attr->chain || attr->prio)
644 fdb = mlx5_chains_get_table(chains, attr->chain,
649 if (!(attr->flags & MLX5_ATTR_FLAG_NO_IN_PORT))
650 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
651 esw_attr->in_mdev->priv.eswitch,
652 esw_attr->in_rep->vport);
655 rule = ERR_CAST(fdb);
664 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
665 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
668 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
672 atomic64_inc(&esw->offloads.num_flows);
679 mlx5_esw_vporttbl_put(esw, &fwd_attr);
680 else if (attr->chain || attr->prio)
681 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
683 esw_cleanup_dests(esw, attr);
684 err_create_goto_table:
689 struct mlx5_flow_handle *
690 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
691 struct mlx5_flow_spec *spec,
692 struct mlx5_flow_attr *attr)
694 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
695 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
696 struct mlx5_fs_chains *chains = esw_chains(esw);
697 struct mlx5_vport_tbl_attr fwd_attr;
698 struct mlx5_flow_destination *dest;
699 struct mlx5_flow_table *fast_fdb;
700 struct mlx5_flow_table *fwd_fdb;
701 struct mlx5_flow_handle *rule;
704 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
706 return ERR_PTR(-ENOMEM);
708 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
709 if (IS_ERR(fast_fdb)) {
710 rule = ERR_CAST(fast_fdb);
714 fwd_attr.chain = attr->chain;
715 fwd_attr.prio = attr->prio;
716 fwd_attr.vport = esw_attr->in_rep->vport;
717 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
718 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
719 if (IS_ERR(fwd_fdb)) {
720 rule = ERR_CAST(fwd_fdb);
724 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
725 for (i = 0; i < esw_attr->split_count; i++) {
726 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
727 /* Source port rewrite (forward to ovs internal port or statck device) isn't
728 * supported in the rule of split action.
732 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
736 goto err_chain_src_rewrite;
739 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
740 dest[i].ft = fwd_fdb;
743 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
744 esw_attr->in_mdev->priv.eswitch,
745 esw_attr->in_rep->vport);
747 if (attr->outer_match_level != MLX5_MATCH_NONE)
748 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
750 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
751 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
754 i = esw_attr->split_count;
755 goto err_chain_src_rewrite;
758 atomic64_inc(&esw->offloads.num_flows);
762 err_chain_src_rewrite:
763 mlx5_esw_vporttbl_put(esw, &fwd_attr);
765 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
772 __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
773 struct mlx5_flow_handle *rule,
774 struct mlx5_flow_attr *attr,
777 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
778 struct mlx5_fs_chains *chains = esw_chains(esw);
779 bool split = (esw_attr->split_count > 0);
780 struct mlx5_vport_tbl_attr fwd_attr;
783 mlx5_del_flow_rules(rule);
785 if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
786 /* unref the term table */
787 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
788 if (esw_attr->dests[i].termtbl)
789 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
793 atomic64_dec(&esw->offloads.num_flows);
795 if (fwd_rule || split) {
796 fwd_attr.chain = attr->chain;
797 fwd_attr.prio = attr->prio;
798 fwd_attr.vport = esw_attr->in_rep->vport;
799 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
803 mlx5_esw_vporttbl_put(esw, &fwd_attr);
804 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
807 mlx5_esw_vporttbl_put(esw, &fwd_attr);
808 else if (attr->chain || attr->prio)
809 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
810 esw_cleanup_dests(esw, attr);
815 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
816 struct mlx5_flow_handle *rule,
817 struct mlx5_flow_attr *attr)
819 __mlx5_eswitch_del_rule(esw, rule, attr, false);
823 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
824 struct mlx5_flow_handle *rule,
825 struct mlx5_flow_attr *attr)
827 __mlx5_eswitch_del_rule(esw, rule, attr, true);
830 struct mlx5_flow_handle *
831 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
832 struct mlx5_eswitch *from_esw,
833 struct mlx5_eswitch_rep *rep,
836 struct mlx5_flow_act flow_act = {0};
837 struct mlx5_flow_destination dest = {};
838 struct mlx5_flow_handle *flow_rule;
839 struct mlx5_flow_spec *spec;
843 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
845 flow_rule = ERR_PTR(-ENOMEM);
849 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
850 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
852 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
853 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
855 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
857 /* source vport is the esw manager */
858 vport = from_esw->manager_vport;
860 if (mlx5_eswitch_vport_match_metadata_enabled(on_esw)) {
861 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
862 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
863 mlx5_eswitch_get_vport_metadata_for_match(from_esw, vport));
865 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
866 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
867 mlx5_eswitch_get_vport_metadata_mask());
869 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
871 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
872 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
874 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
875 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
876 MLX5_CAP_GEN(from_esw->dev, vhca_id));
878 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
879 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
881 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
882 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
883 source_eswitch_owner_vhca_id);
885 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
888 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
889 dest.vport.num = rep->vport;
890 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
891 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
892 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
894 if (MLX5_CAP_ESW_FLOWTABLE(on_esw->dev, flow_source) &&
895 rep->vport == MLX5_VPORT_UPLINK)
896 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
898 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(on_esw),
899 spec, &flow_act, &dest, 1);
900 if (IS_ERR(flow_rule))
901 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
907 EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
909 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
911 mlx5_del_flow_rules(rule);
914 void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule)
917 mlx5_del_flow_rules(rule);
920 struct mlx5_flow_handle *
921 mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num)
923 struct mlx5_flow_destination dest = {};
924 struct mlx5_flow_act flow_act = {0};
925 struct mlx5_flow_handle *flow_rule;
926 struct mlx5_flow_spec *spec;
928 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
930 return ERR_PTR(-ENOMEM);
932 MLX5_SET(fte_match_param, spec->match_criteria,
933 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
934 MLX5_SET(fte_match_param, spec->match_criteria,
935 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
936 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
937 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
939 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
940 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
941 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
943 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
944 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
945 dest.vport.num = vport_num;
947 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
948 spec, &flow_act, &dest, 1);
949 if (IS_ERR(flow_rule))
950 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule vport %d, err %ld\n",
951 vport_num, PTR_ERR(flow_rule));
957 static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
959 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
960 MLX5_FDB_TO_VPORT_REG_C_1;
963 static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
965 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
966 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
967 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
971 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
972 !mlx5_eswitch_vport_match_metadata_enabled(esw))
975 MLX5_SET(query_esw_vport_context_in, in, opcode,
976 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
977 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
981 curr = MLX5_GET(query_esw_vport_context_out, out,
982 esw_vport_context.fdb_to_vport_reg_c_id);
983 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
984 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
985 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
992 MLX5_SET(modify_esw_vport_context_in, min,
993 esw_vport_context.fdb_to_vport_reg_c_id, curr);
994 MLX5_SET(modify_esw_vport_context_in, min,
995 field_select.fdb_to_vport_reg_c_id, 1);
997 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
999 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1000 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1002 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1008 static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1009 struct mlx5_core_dev *peer_dev,
1010 struct mlx5_flow_spec *spec,
1011 struct mlx5_flow_destination *dest)
1015 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1016 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1018 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1019 mlx5_eswitch_get_vport_metadata_mask());
1021 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1023 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1026 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1027 MLX5_CAP_GEN(peer_dev, vhca_id));
1029 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1031 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1033 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1034 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1035 source_eswitch_owner_vhca_id);
1038 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1039 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
1040 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
1041 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1044 static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1045 struct mlx5_eswitch *peer_esw,
1046 struct mlx5_flow_spec *spec,
1051 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1052 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1054 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1055 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1058 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1060 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1064 static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1065 struct mlx5_core_dev *peer_dev)
1067 struct mlx5_flow_destination dest = {};
1068 struct mlx5_flow_act flow_act = {0};
1069 struct mlx5_flow_handle **flows;
1070 /* total vports is the same for both e-switches */
1071 int nvports = esw->total_vports;
1072 struct mlx5_flow_handle *flow;
1073 struct mlx5_flow_spec *spec;
1074 struct mlx5_vport *vport;
1079 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1083 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
1085 flows = kvcalloc(nvports, sizeof(*flows), GFP_KERNEL);
1088 goto alloc_flows_err;
1091 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1092 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1095 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1096 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1097 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1098 spec, MLX5_VPORT_PF);
1100 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1101 spec, &flow_act, &dest, 1);
1103 err = PTR_ERR(flow);
1104 goto add_pf_flow_err;
1106 flows[vport->index] = flow;
1109 if (mlx5_ecpf_vport_exists(esw->dev)) {
1110 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1111 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
1112 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1113 spec, &flow_act, &dest, 1);
1115 err = PTR_ERR(flow);
1116 goto add_ecpf_flow_err;
1118 flows[vport->index] = flow;
1121 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1122 esw_set_peer_miss_rule_source_port(esw,
1123 peer_dev->priv.eswitch,
1124 spec, vport->vport);
1126 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1127 spec, &flow_act, &dest, 1);
1129 err = PTR_ERR(flow);
1130 goto add_vf_flow_err;
1132 flows[vport->index] = flow;
1135 esw->fdb_table.offloads.peer_miss_rules[mlx5_get_dev_index(peer_dev)] = flows;
1141 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1142 if (!flows[vport->index])
1144 mlx5_del_flow_rules(flows[vport->index]);
1146 if (mlx5_ecpf_vport_exists(esw->dev)) {
1147 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1148 mlx5_del_flow_rules(flows[vport->index]);
1151 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1152 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1153 mlx5_del_flow_rules(flows[vport->index]);
1156 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
1163 static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1164 struct mlx5_core_dev *peer_dev)
1166 struct mlx5_flow_handle **flows;
1167 struct mlx5_vport *vport;
1170 flows = esw->fdb_table.offloads.peer_miss_rules[mlx5_get_dev_index(peer_dev)];
1172 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1173 mlx5_del_flow_rules(flows[vport->index]);
1175 if (mlx5_ecpf_vport_exists(esw->dev)) {
1176 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1177 mlx5_del_flow_rules(flows[vport->index]);
1180 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1181 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1182 mlx5_del_flow_rules(flows[vport->index]);
1187 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1189 struct mlx5_flow_act flow_act = {0};
1190 struct mlx5_flow_destination dest = {};
1191 struct mlx5_flow_handle *flow_rule = NULL;
1192 struct mlx5_flow_spec *spec;
1199 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1205 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1206 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1208 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1209 outer_headers.dmac_47_16);
1212 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1213 dest.vport.num = esw->manager_vport;
1214 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1216 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1217 spec, &flow_act, &dest, 1);
1218 if (IS_ERR(flow_rule)) {
1219 err = PTR_ERR(flow_rule);
1220 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
1224 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1226 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1228 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1229 outer_headers.dmac_47_16);
1231 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1232 spec, &flow_act, &dest, 1);
1233 if (IS_ERR(flow_rule)) {
1234 err = PTR_ERR(flow_rule);
1235 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1236 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1240 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1247 struct mlx5_flow_handle *
1248 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1250 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1251 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1252 struct mlx5_flow_context *flow_context;
1253 struct mlx5_flow_handle *flow_rule;
1254 struct mlx5_flow_destination dest;
1255 struct mlx5_flow_spec *spec;
1258 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1259 return ERR_PTR(-EOPNOTSUPP);
1261 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1263 return ERR_PTR(-ENOMEM);
1265 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1267 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1268 ESW_REG_C0_USER_DATA_METADATA_MASK);
1269 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1271 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1272 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1273 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1274 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1275 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
1277 flow_context = &spec->flow_context;
1278 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1279 flow_context->flow_tag = tag;
1280 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1281 dest.ft = esw->offloads.ft_offloads;
1283 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
1286 if (IS_ERR(flow_rule))
1288 "Failed to create restore rule for tag: %d, err(%d)\n",
1289 tag, (int)PTR_ERR(flow_rule));
1294 #define MAX_PF_SQ 256
1295 #define MAX_SQ_NVPORTS 32
1298 mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1302 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1306 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1307 MLX5_SET(create_flow_group_in, flow_group_in,
1308 match_criteria_enable,
1309 MLX5_MATCH_MISC_PARAMETERS_2 | match_params);
1311 MLX5_SET(fte_match_param, match_criteria,
1312 misc_parameters_2.metadata_reg_c_0,
1313 mlx5_eswitch_get_vport_metadata_mask());
1315 MLX5_SET(create_flow_group_in, flow_group_in,
1316 match_criteria_enable,
1317 MLX5_MATCH_MISC_PARAMETERS | match_params);
1319 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1320 misc_parameters.source_port);
1324 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
1325 static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
1327 struct mlx5_vport_tbl_attr attr;
1328 struct mlx5_vport *vport;
1333 mlx5_esw_for_each_vport(esw, i, vport) {
1334 attr.vport = vport->vport;
1335 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1336 mlx5_esw_vporttbl_put(esw, &attr);
1340 static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
1342 struct mlx5_vport_tbl_attr attr;
1343 struct mlx5_flow_table *fdb;
1344 struct mlx5_vport *vport;
1349 mlx5_esw_for_each_vport(esw, i, vport) {
1350 attr.vport = vport->vport;
1351 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1352 fdb = mlx5_esw_vporttbl_get(esw, &attr);
1359 esw_vport_tbl_put(esw);
1360 return PTR_ERR(fdb);
1363 #define fdb_modify_header_fwd_to_table_supported(esw) \
1364 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1365 static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1367 struct mlx5_core_dev *dev = esw->dev;
1369 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1370 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1372 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1373 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1374 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1375 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1376 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1377 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1378 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1379 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1380 /* Disabled when ttl workaround is needed, e.g
1381 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1384 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1385 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1387 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1388 esw_info(dev, "Supported tc chains and prios offload\n");
1391 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1392 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1396 esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1398 struct mlx5_core_dev *dev = esw->dev;
1399 struct mlx5_flow_table *nf_ft, *ft;
1400 struct mlx5_chains_attr attr = {};
1401 struct mlx5_fs_chains *chains;
1404 esw_init_chains_offload_flags(esw, &attr.flags);
1405 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1406 attr.fs_base_prio = FDB_TC_OFFLOAD;
1407 attr.max_grp_num = esw->params.large_group_num;
1408 attr.default_ft = miss_fdb;
1409 attr.mapping = esw->offloads.reg_c0_obj_pool;
1411 chains = mlx5_chains_create(dev, &attr);
1412 if (IS_ERR(chains)) {
1413 err = PTR_ERR(chains);
1414 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1417 mlx5_chains_print_info(chains);
1419 esw->fdb_table.offloads.esw_chains_priv = chains;
1421 /* Create tc_end_ft which is the always created ft chain */
1422 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1424 if (IS_ERR(nf_ft)) {
1425 err = PTR_ERR(nf_ft);
1429 /* Always open the root for fast path */
1430 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1436 /* Open level 1 for split fdb rules now if prios isn't supported */
1437 if (!mlx5_chains_prios_supported(chains)) {
1438 err = esw_vport_tbl_get(esw);
1443 mlx5_chains_set_end_ft(chains, nf_ft);
1448 mlx5_chains_put_table(chains, 0, 1, 0);
1450 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1452 mlx5_chains_destroy(chains);
1453 esw->fdb_table.offloads.esw_chains_priv = NULL;
1459 esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1461 if (!mlx5_chains_prios_supported(chains))
1462 esw_vport_tbl_put(esw);
1463 mlx5_chains_put_table(chains, 0, 1, 0);
1464 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1465 mlx5_chains_destroy(chains);
1468 #else /* CONFIG_MLX5_CLS_ACT */
1471 esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1475 esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1481 esw_create_send_to_vport_group(struct mlx5_eswitch *esw,
1482 struct mlx5_flow_table *fdb,
1486 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1487 struct mlx5_flow_group *g;
1488 void *match_criteria;
1491 memset(flow_group_in, 0, inlen);
1493 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, MLX5_MATCH_MISC_PARAMETERS);
1495 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1496 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1498 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
1499 MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1500 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1501 misc_parameters.source_eswitch_owner_vhca_id);
1502 MLX5_SET(create_flow_group_in, flow_group_in,
1503 source_eswitch_owner_vhca_id_valid, 1);
1506 /* See comment at table_size calculation */
1507 count = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ);
1508 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1509 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, *ix + count - 1);
1512 g = mlx5_create_flow_group(fdb, flow_group_in);
1515 esw_warn(esw->dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1518 esw->fdb_table.offloads.send_to_vport_grp = g;
1525 esw_create_meta_send_to_vport_group(struct mlx5_eswitch *esw,
1526 struct mlx5_flow_table *fdb,
1530 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1531 struct mlx5_flow_group *g;
1532 void *match_criteria;
1535 if (!esw_src_port_rewrite_supported(esw))
1538 memset(flow_group_in, 0, inlen);
1540 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1541 MLX5_MATCH_MISC_PARAMETERS_2);
1543 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1545 MLX5_SET(fte_match_param, match_criteria,
1546 misc_parameters_2.metadata_reg_c_0,
1547 mlx5_eswitch_get_vport_metadata_mask());
1548 MLX5_SET(fte_match_param, match_criteria,
1549 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1551 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1552 MLX5_SET(create_flow_group_in, flow_group_in,
1553 end_flow_index, *ix + esw->total_vports - 1);
1554 *ix += esw->total_vports;
1556 g = mlx5_create_flow_group(fdb, flow_group_in);
1560 "Failed to create send-to-vport meta flow group err(%d)\n", err);
1561 goto send_vport_meta_err;
1563 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
1567 send_vport_meta_err:
1572 esw_create_peer_esw_miss_group(struct mlx5_eswitch *esw,
1573 struct mlx5_flow_table *fdb,
1577 int max_peer_ports = (esw->total_vports - 1) * (MLX5_MAX_PORTS - 1);
1578 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1579 struct mlx5_flow_group *g;
1580 void *match_criteria;
1583 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1586 memset(flow_group_in, 0, inlen);
1588 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
1590 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1591 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1595 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1596 misc_parameters.source_eswitch_owner_vhca_id);
1598 MLX5_SET(create_flow_group_in, flow_group_in,
1599 source_eswitch_owner_vhca_id_valid, 1);
1602 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1603 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1604 *ix + max_peer_ports);
1605 *ix += max_peer_ports + 1;
1607 g = mlx5_create_flow_group(fdb, flow_group_in);
1610 esw_warn(esw->dev, "Failed to create peer miss flow group err(%d)\n", err);
1613 esw->fdb_table.offloads.peer_miss_grp = g;
1620 esw_create_miss_group(struct mlx5_eswitch *esw,
1621 struct mlx5_flow_table *fdb,
1625 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1626 struct mlx5_flow_group *g;
1627 void *match_criteria;
1631 memset(flow_group_in, 0, inlen);
1633 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1634 MLX5_MATCH_OUTER_HEADERS);
1635 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1637 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1638 outer_headers.dmac_47_16);
1641 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1642 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1643 *ix + MLX5_ESW_MISS_FLOWS);
1645 g = mlx5_create_flow_group(fdb, flow_group_in);
1648 esw_warn(esw->dev, "Failed to create miss flow group err(%d)\n", err);
1651 esw->fdb_table.offloads.miss_grp = g;
1653 err = esw_add_fdb_miss_rule(esw);
1660 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1665 static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1667 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1668 struct mlx5_flow_table_attr ft_attr = {};
1669 struct mlx5_core_dev *dev = esw->dev;
1670 struct mlx5_flow_namespace *root_ns;
1671 struct mlx5_flow_table *fdb = NULL;
1672 int table_size, ix = 0, err = 0;
1673 u32 flags = 0, *flow_group_in;
1675 esw_debug(esw->dev, "Create offloads FDB Tables\n");
1677 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1681 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1683 esw_warn(dev, "Failed to get FDB flow namespace\n");
1687 esw->fdb_table.offloads.ns = root_ns;
1688 err = mlx5_flow_namespace_set_mode(root_ns,
1689 esw->dev->priv.steering->mode);
1691 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1695 /* To be strictly correct:
1696 * MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ)
1698 * esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1699 * peer_esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ
1700 * but as the peer device might not be in switchdev mode it's not
1701 * possible. We use the fact that by default FW sets max vfs and max sfs
1702 * to the same value on both devices. If it needs to be changed in the future note
1703 * the peer miss group should also be created based on the number of
1704 * total vports of the peer (currently is also uses esw->total_vports).
1706 table_size = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) +
1707 esw->total_vports * MLX5_MAX_PORTS + MLX5_ESW_MISS_FLOWS;
1709 /* create the slow path fdb with encap set, so further table instances
1710 * can be created at run time while VFs are probed if the FW allows that.
1712 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1713 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1714 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1716 ft_attr.flags = flags;
1717 ft_attr.max_fte = table_size;
1718 ft_attr.prio = FDB_SLOW_PATH;
1720 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1723 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1726 esw->fdb_table.offloads.slow_fdb = fdb;
1728 /* Create empty TC-miss managed table. This allows plugging in following
1729 * priorities without directly exposing their level 0 table to
1730 * eswitch_offloads and passing it as miss_fdb to following call to
1731 * esw_chains_create().
1733 memset(&ft_attr, 0, sizeof(ft_attr));
1734 ft_attr.prio = FDB_TC_MISS;
1735 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1736 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1737 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1738 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1739 goto tc_miss_table_err;
1742 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
1744 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
1745 goto fdb_chains_err;
1748 err = esw_create_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1750 goto send_vport_err;
1752 err = esw_create_meta_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1754 goto send_vport_meta_err;
1756 err = esw_create_peer_esw_miss_group(esw, fdb, flow_group_in, &ix);
1760 err = esw_create_miss_group(esw, fdb, flow_group_in, &ix);
1764 kvfree(flow_group_in);
1768 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1769 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1771 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1772 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1773 send_vport_meta_err:
1774 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1776 esw_chains_destroy(esw, esw_chains(esw));
1778 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1780 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1782 /* Holds true only as long as DMFS is the default */
1783 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
1785 kvfree(flow_group_in);
1789 static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
1791 if (!mlx5_eswitch_get_slow_fdb(esw))
1794 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
1795 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1796 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1797 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1798 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1799 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1800 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1801 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1802 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1804 esw_chains_destroy(esw, esw_chains(esw));
1806 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1807 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1808 /* Holds true only as long as DMFS is the default */
1809 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1810 MLX5_FLOW_STEERING_MODE_DMFS);
1811 atomic64_set(&esw->user_count, 0);
1814 static int esw_get_nr_ft_offloads_steering_src_ports(struct mlx5_eswitch *esw)
1818 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1819 if (mlx5e_tc_int_port_supported(esw))
1820 nvports += MLX5E_TC_MAX_INT_PORT_NUM;
1825 static int esw_create_offloads_table(struct mlx5_eswitch *esw)
1827 struct mlx5_flow_table_attr ft_attr = {};
1828 struct mlx5_core_dev *dev = esw->dev;
1829 struct mlx5_flow_table *ft_offloads;
1830 struct mlx5_flow_namespace *ns;
1833 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1835 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1839 ft_attr.max_fte = esw_get_nr_ft_offloads_steering_src_ports(esw) +
1840 MLX5_ESW_FT_OFFLOADS_DROP_RULE;
1843 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
1844 if (IS_ERR(ft_offloads)) {
1845 err = PTR_ERR(ft_offloads);
1846 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1850 esw->offloads.ft_offloads = ft_offloads;
1854 static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1856 struct mlx5_esw_offload *offloads = &esw->offloads;
1858 mlx5_destroy_flow_table(offloads->ft_offloads);
1861 static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
1863 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1864 struct mlx5_flow_group *g;
1869 nvports = esw_get_nr_ft_offloads_steering_src_ports(esw);
1870 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1874 /* create vport rx group */
1875 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
1877 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1878 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1880 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1884 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1888 esw->offloads.vport_rx_group = g;
1890 kvfree(flow_group_in);
1894 static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1896 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1899 static int esw_create_vport_rx_drop_rule_index(struct mlx5_eswitch *esw)
1901 /* ft_offloads table is enlarged by MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
1902 * for the drop rule, which is placed at the end of the table.
1903 * So return the total of vport and int_port as rule index.
1905 return esw_get_nr_ft_offloads_steering_src_ports(esw);
1908 static int esw_create_vport_rx_drop_group(struct mlx5_eswitch *esw)
1910 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1911 struct mlx5_flow_group *g;
1916 flow_index = esw_create_vport_rx_drop_rule_index(esw);
1918 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1922 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, flow_index);
1923 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, flow_index);
1925 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1929 mlx5_core_warn(esw->dev, "Failed to create vport rx drop group err %d\n", err);
1933 esw->offloads.vport_rx_drop_group = g;
1935 kvfree(flow_group_in);
1939 static void esw_destroy_vport_rx_drop_group(struct mlx5_eswitch *esw)
1941 if (esw->offloads.vport_rx_drop_group)
1942 mlx5_destroy_flow_group(esw->offloads.vport_rx_drop_group);
1946 mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw,
1948 struct mlx5_flow_spec *spec)
1952 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1953 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1954 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1955 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
1957 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
1958 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1959 mlx5_eswitch_get_vport_metadata_mask());
1961 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1963 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1964 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1966 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1967 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1969 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1973 struct mlx5_flow_handle *
1974 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
1975 struct mlx5_flow_destination *dest)
1977 struct mlx5_flow_act flow_act = {0};
1978 struct mlx5_flow_handle *flow_rule;
1979 struct mlx5_flow_spec *spec;
1981 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1983 flow_rule = ERR_PTR(-ENOMEM);
1987 mlx5_esw_set_spec_source_port(esw, vport, spec);
1989 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1990 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
1991 &flow_act, dest, 1);
1992 if (IS_ERR(flow_rule)) {
1993 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
2002 static int esw_create_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2004 struct mlx5_flow_act flow_act = {};
2005 struct mlx5_flow_handle *flow_rule;
2007 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2008 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, NULL,
2009 &flow_act, NULL, 0);
2010 if (IS_ERR(flow_rule)) {
2012 "fs offloads: Failed to add vport rx drop rule err %ld\n",
2013 PTR_ERR(flow_rule));
2014 return PTR_ERR(flow_rule);
2017 esw->offloads.vport_rx_drop_rule = flow_rule;
2022 static void esw_destroy_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2024 if (esw->offloads.vport_rx_drop_rule)
2025 mlx5_del_flow_rules(esw->offloads.vport_rx_drop_rule);
2028 static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
2030 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2031 struct mlx5_core_dev *dev = esw->dev;
2032 struct mlx5_vport *vport;
2035 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2038 if (!mlx5_esw_is_fdb_created(esw))
2041 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2042 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2043 mlx5_mode = MLX5_INLINE_MODE_NONE;
2045 case MLX5_CAP_INLINE_MODE_L2:
2046 mlx5_mode = MLX5_INLINE_MODE_L2;
2048 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2053 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
2054 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
2055 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
2056 if (prev_mlx5_mode != mlx5_mode)
2058 prev_mlx5_mode = mlx5_mode;
2066 static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
2068 struct mlx5_esw_offload *offloads = &esw->offloads;
2070 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2073 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
2074 mlx5_destroy_flow_group(offloads->restore_group);
2075 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2078 static int esw_create_restore_table(struct mlx5_eswitch *esw)
2080 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
2081 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2082 struct mlx5_flow_table_attr ft_attr = {};
2083 struct mlx5_core_dev *dev = esw->dev;
2084 struct mlx5_flow_namespace *ns;
2085 struct mlx5_modify_hdr *mod_hdr;
2086 void *match_criteria, *misc;
2087 struct mlx5_flow_table *ft;
2088 struct mlx5_flow_group *g;
2092 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2095 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2097 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2101 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2102 if (!flow_group_in) {
2107 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
2108 ft = mlx5_create_flow_table(ns, &ft_attr);
2111 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2116 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2118 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2121 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2122 ESW_REG_C0_USER_DATA_METADATA_MASK);
2123 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2124 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2125 ft_attr.max_fte - 1);
2126 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2127 MLX5_MATCH_MISC_PARAMETERS_2);
2128 g = mlx5_create_flow_group(ft, flow_group_in);
2131 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2136 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2137 MLX5_SET(copy_action_in, modact, src_field,
2138 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2139 MLX5_SET(copy_action_in, modact, dst_field,
2140 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2141 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2142 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2144 if (IS_ERR(mod_hdr)) {
2145 err = PTR_ERR(mod_hdr);
2146 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2151 esw->offloads.ft_offloads_restore = ft;
2152 esw->offloads.restore_group = g;
2153 esw->offloads.restore_copy_hdr_id = mod_hdr;
2155 kvfree(flow_group_in);
2160 mlx5_destroy_flow_group(g);
2162 mlx5_destroy_flow_table(ft);
2164 kvfree(flow_group_in);
2169 static int esw_offloads_start(struct mlx5_eswitch *esw,
2170 struct netlink_ext_ack *extack)
2174 esw->mode = MLX5_ESWITCH_OFFLOADS;
2175 err = mlx5_eswitch_enable_locked(esw, esw->dev->priv.sriov.num_vfs);
2177 NL_SET_ERR_MSG_MOD(extack,
2178 "Failed setting eswitch to offloads");
2179 esw->mode = MLX5_ESWITCH_LEGACY;
2180 mlx5_rescan_drivers(esw->dev);
2182 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2183 if (mlx5_eswitch_inline_mode_get(esw,
2184 &esw->offloads.inline_mode)) {
2185 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
2186 NL_SET_ERR_MSG_MOD(extack,
2187 "Inline mode is different between vports");
2193 static void mlx5_esw_offloads_rep_mark_set(struct mlx5_eswitch *esw,
2194 struct mlx5_eswitch_rep *rep,
2199 /* Copy the mark from vport to its rep */
2200 mark_set = xa_get_mark(&esw->vports, rep->vport, mark);
2202 xa_set_mark(&esw->offloads.vport_reps, rep->vport, mark);
2205 static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
2207 struct mlx5_eswitch_rep *rep;
2211 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2215 rep->vport = vport->vport;
2216 rep->vport_index = vport->index;
2217 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2218 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
2220 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2224 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_HOST_FN);
2225 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_VF);
2226 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_SF);
2234 static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2235 struct mlx5_eswitch_rep *rep)
2237 xa_erase(&esw->offloads.vport_reps, rep->vport);
2241 static void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
2243 struct mlx5_eswitch_rep *rep;
2246 mlx5_esw_for_each_rep(esw, i, rep)
2247 mlx5_esw_offloads_rep_cleanup(esw, rep);
2248 xa_destroy(&esw->offloads.vport_reps);
2251 static int esw_offloads_init_reps(struct mlx5_eswitch *esw)
2253 struct mlx5_vport *vport;
2257 xa_init(&esw->offloads.vport_reps);
2259 mlx5_esw_for_each_vport(esw, i, vport) {
2260 err = mlx5_esw_offloads_rep_init(esw, vport);
2267 esw_offloads_cleanup_reps(esw);
2271 static int esw_port_metadata_set(struct devlink *devlink, u32 id,
2272 struct devlink_param_gset_ctx *ctx)
2274 struct mlx5_core_dev *dev = devlink_priv(devlink);
2275 struct mlx5_eswitch *esw = dev->priv.eswitch;
2278 down_write(&esw->mode_lock);
2279 if (mlx5_esw_is_fdb_created(esw)) {
2283 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2288 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2290 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2292 up_write(&esw->mode_lock);
2296 static int esw_port_metadata_get(struct devlink *devlink, u32 id,
2297 struct devlink_param_gset_ctx *ctx)
2299 struct mlx5_core_dev *dev = devlink_priv(devlink);
2301 ctx->val.vbool = mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch);
2305 static int esw_port_metadata_validate(struct devlink *devlink, u32 id,
2306 union devlink_param_value val,
2307 struct netlink_ext_ack *extack)
2309 struct mlx5_core_dev *dev = devlink_priv(devlink);
2312 esw_mode = mlx5_eswitch_mode(dev);
2313 if (esw_mode == MLX5_ESWITCH_OFFLOADS) {
2314 NL_SET_ERR_MSG_MOD(extack,
2315 "E-Switch must either disabled or non switchdev mode");
2321 static const struct devlink_param esw_devlink_params[] = {
2322 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_ESW_PORT_METADATA,
2323 "esw_port_metadata", DEVLINK_PARAM_TYPE_BOOL,
2324 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
2325 esw_port_metadata_get,
2326 esw_port_metadata_set,
2327 esw_port_metadata_validate),
2330 int esw_offloads_init(struct mlx5_eswitch *esw)
2334 err = esw_offloads_init_reps(esw);
2338 err = devl_params_register(priv_to_devlink(esw->dev),
2340 ARRAY_SIZE(esw_devlink_params));
2347 esw_offloads_cleanup_reps(esw);
2351 void esw_offloads_cleanup(struct mlx5_eswitch *esw)
2353 devl_params_unregister(priv_to_devlink(esw->dev),
2355 ARRAY_SIZE(esw_devlink_params));
2356 esw_offloads_cleanup_reps(esw);
2359 static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2360 struct mlx5_eswitch_rep *rep, u8 rep_type)
2362 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2363 REP_LOADED, REP_REGISTERED) == REP_LOADED)
2364 esw->offloads.rep_ops[rep_type]->unload(rep);
2367 static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type)
2369 struct mlx5_eswitch_rep *rep;
2372 mlx5_esw_for_each_sf_rep(esw, i, rep)
2373 __esw_offloads_unload_rep(esw, rep, rep_type);
2376 static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
2378 struct mlx5_eswitch_rep *rep;
2381 __unload_reps_sf_vport(esw, rep_type);
2383 mlx5_esw_for_each_vf_rep(esw, i, rep)
2384 __esw_offloads_unload_rep(esw, rep, rep_type);
2386 if (mlx5_ecpf_vport_exists(esw->dev)) {
2387 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
2388 __esw_offloads_unload_rep(esw, rep, rep_type);
2391 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
2392 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
2393 __esw_offloads_unload_rep(esw, rep, rep_type);
2396 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
2397 __esw_offloads_unload_rep(esw, rep, rep_type);
2400 int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
2402 struct mlx5_eswitch_rep *rep;
2406 rep = mlx5_eswitch_get_rep(esw, vport_num);
2407 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2408 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2409 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
2410 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2418 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2419 for (--rep_type; rep_type >= 0; rep_type--)
2420 __esw_offloads_unload_rep(esw, rep, rep_type);
2424 void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
2426 struct mlx5_eswitch_rep *rep;
2429 rep = mlx5_eswitch_get_rep(esw, vport_num);
2430 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2431 __esw_offloads_unload_rep(esw, rep, rep_type);
2434 int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
2438 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2441 if (vport_num != MLX5_VPORT_UPLINK) {
2442 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
2447 err = mlx5_esw_offloads_rep_load(esw, vport_num);
2453 if (vport_num != MLX5_VPORT_UPLINK)
2454 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
2458 void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
2460 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2463 mlx5_esw_offloads_rep_unload(esw, vport_num);
2465 if (vport_num != MLX5_VPORT_UPLINK)
2466 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
2469 static int esw_set_slave_root_fdb(struct mlx5_core_dev *master,
2470 struct mlx5_core_dev *slave)
2472 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
2473 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};
2474 struct mlx5_flow_root_namespace *root;
2475 struct mlx5_flow_namespace *ns;
2478 MLX5_SET(set_flow_table_root_in, in, opcode,
2479 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);
2480 MLX5_SET(set_flow_table_root_in, in, table_type,
2484 ns = mlx5_get_flow_namespace(master,
2485 MLX5_FLOW_NAMESPACE_FDB);
2486 root = find_root(&ns->node);
2487 mutex_lock(&root->chain_lock);
2488 MLX5_SET(set_flow_table_root_in, in,
2489 table_eswitch_owner_vhca_id_valid, 1);
2490 MLX5_SET(set_flow_table_root_in, in,
2491 table_eswitch_owner_vhca_id,
2492 MLX5_CAP_GEN(master, vhca_id));
2493 MLX5_SET(set_flow_table_root_in, in, table_id,
2496 ns = mlx5_get_flow_namespace(slave,
2497 MLX5_FLOW_NAMESPACE_FDB);
2498 root = find_root(&ns->node);
2499 mutex_lock(&root->chain_lock);
2500 MLX5_SET(set_flow_table_root_in, in, table_id,
2504 err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out));
2505 mutex_unlock(&root->chain_lock);
2510 static int __esw_set_master_egress_rule(struct mlx5_core_dev *master,
2511 struct mlx5_core_dev *slave,
2512 struct mlx5_vport *vport,
2513 struct mlx5_flow_table *acl)
2515 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
2516 struct mlx5_flow_handle *flow_rule = NULL;
2517 struct mlx5_flow_destination dest = {};
2518 struct mlx5_flow_act flow_act = {};
2519 struct mlx5_flow_spec *spec;
2523 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2527 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2528 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2530 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK);
2531 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id, slave_index);
2533 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2534 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2535 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
2536 source_eswitch_owner_vhca_id);
2538 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2539 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
2540 dest.vport.num = slave->priv.eswitch->manager_vport;
2541 dest.vport.vhca_id = MLX5_CAP_GEN(slave, vhca_id);
2542 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
2544 flow_rule = mlx5_add_flow_rules(acl, spec, &flow_act,
2546 if (IS_ERR(flow_rule)) {
2547 err = PTR_ERR(flow_rule);
2549 err = xa_insert(&vport->egress.offloads.bounce_rules,
2550 slave_index, flow_rule, GFP_KERNEL);
2552 mlx5_del_flow_rules(flow_rule);
2559 static int esw_master_egress_create_resources(struct mlx5_flow_namespace *egress_ns,
2560 struct mlx5_vport *vport, size_t count)
2562 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2563 struct mlx5_flow_table_attr ft_attr = {
2564 .max_fte = count, .prio = 0, .level = 0,
2565 .flags = MLX5_FLOW_TABLE_OTHER_VPORT,
2567 struct mlx5_flow_table *acl;
2568 struct mlx5_flow_group *g;
2569 void *match_criteria;
2573 if (vport->egress.acl)
2576 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2580 acl = mlx5_create_vport_flow_table(egress_ns, &ft_attr, vport->vport);
2586 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2588 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2589 misc_parameters.source_port);
2590 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2591 misc_parameters.source_eswitch_owner_vhca_id);
2592 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2593 MLX5_MATCH_MISC_PARAMETERS);
2595 MLX5_SET(create_flow_group_in, flow_group_in,
2596 source_eswitch_owner_vhca_id_valid, 1);
2597 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2598 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, count);
2600 g = mlx5_create_flow_group(acl, flow_group_in);
2606 vport->egress.acl = acl;
2607 vport->egress.offloads.bounce_grp = g;
2608 vport->egress.type = VPORT_EGRESS_ACL_TYPE_SHARED_FDB;
2609 xa_init_flags(&vport->egress.offloads.bounce_rules, XA_FLAGS_ALLOC);
2611 kvfree(flow_group_in);
2616 mlx5_destroy_flow_table(acl);
2618 kvfree(flow_group_in);
2622 static void esw_master_egress_destroy_resources(struct mlx5_vport *vport)
2624 mlx5_destroy_flow_group(vport->egress.offloads.bounce_grp);
2625 mlx5_destroy_flow_table(vport->egress.acl);
2628 static int esw_set_master_egress_rule(struct mlx5_core_dev *master,
2629 struct mlx5_core_dev *slave, size_t count)
2631 struct mlx5_eswitch *esw = master->priv.eswitch;
2632 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
2633 struct mlx5_flow_namespace *egress_ns;
2634 struct mlx5_vport *vport;
2637 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
2639 return PTR_ERR(vport);
2641 egress_ns = mlx5_get_flow_vport_acl_namespace(master,
2642 MLX5_FLOW_NAMESPACE_ESW_EGRESS,
2647 if (vport->egress.acl && vport->egress.type != VPORT_EGRESS_ACL_TYPE_SHARED_FDB)
2650 err = esw_master_egress_create_resources(egress_ns, vport, count);
2654 if (xa_load(&vport->egress.offloads.bounce_rules, slave_index))
2657 err = __esw_set_master_egress_rule(master, slave, vport, vport->egress.acl);
2664 esw_master_egress_destroy_resources(vport);
2668 static void esw_unset_master_egress_rule(struct mlx5_core_dev *dev,
2669 struct mlx5_core_dev *slave_dev)
2671 struct mlx5_vport *vport;
2673 vport = mlx5_eswitch_get_vport(dev->priv.eswitch,
2674 dev->priv.eswitch->manager_vport);
2676 esw_acl_egress_ofld_bounce_rule_destroy(vport, MLX5_CAP_GEN(slave_dev, vhca_id));
2678 if (xa_empty(&vport->egress.offloads.bounce_rules)) {
2679 esw_acl_egress_ofld_cleanup(vport);
2680 xa_destroy(&vport->egress.offloads.bounce_rules);
2684 int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw,
2685 struct mlx5_eswitch *slave_esw, int max_slaves)
2689 err = esw_set_slave_root_fdb(master_esw->dev,
2694 err = esw_set_master_egress_rule(master_esw->dev,
2695 slave_esw->dev, max_slaves);
2702 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2706 void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw,
2707 struct mlx5_eswitch *slave_esw)
2709 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2710 esw_unset_master_egress_rule(master_esw->dev, slave_esw->dev);
2713 #define ESW_OFFLOADS_DEVCOM_PAIR (0)
2714 #define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2716 static void mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch *esw,
2717 struct mlx5_eswitch *peer_esw)
2719 const struct mlx5_eswitch_rep_ops *ops;
2720 struct mlx5_eswitch_rep *rep;
2724 mlx5_esw_for_each_rep(esw, i, rep) {
2725 rep_type = NUM_REP_TYPES;
2726 while (rep_type--) {
2727 ops = esw->offloads.rep_ops[rep_type];
2728 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2730 ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_UNPAIR, peer_esw);
2735 static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw,
2736 struct mlx5_eswitch *peer_esw)
2738 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
2739 mlx5e_tc_clean_fdb_peer_flows(esw);
2741 mlx5_esw_offloads_rep_event_unpair(esw, peer_esw);
2742 esw_del_fdb_peer_miss_rules(esw, peer_esw->dev);
2745 static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2746 struct mlx5_eswitch *peer_esw)
2748 const struct mlx5_eswitch_rep_ops *ops;
2749 struct mlx5_eswitch_rep *rep;
2754 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
2758 mlx5_esw_for_each_rep(esw, i, rep) {
2759 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2760 ops = esw->offloads.rep_ops[rep_type];
2761 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2763 err = ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_PAIR, peer_esw);
2773 mlx5_esw_offloads_unpair(esw, peer_esw);
2777 static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2778 struct mlx5_eswitch *peer_esw,
2781 u8 peer_idx = mlx5_get_dev_index(peer_esw->dev);
2782 struct mlx5_flow_root_namespace *peer_ns;
2783 u8 idx = mlx5_get_dev_index(esw->dev);
2784 struct mlx5_flow_root_namespace *ns;
2787 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2788 ns = esw->dev->priv.steering->fdb_root_ns;
2791 err = mlx5_flow_namespace_set_peer(ns, peer_ns, peer_idx);
2795 err = mlx5_flow_namespace_set_peer(peer_ns, ns, idx);
2797 mlx5_flow_namespace_set_peer(ns, NULL, peer_idx);
2801 mlx5_flow_namespace_set_peer(ns, NULL, peer_idx);
2802 mlx5_flow_namespace_set_peer(peer_ns, NULL, idx);
2808 static int mlx5_esw_offloads_devcom_event(int event,
2812 struct mlx5_eswitch *esw = my_data;
2813 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2814 struct mlx5_eswitch *peer_esw = event_data;
2818 case ESW_OFFLOADS_DEVCOM_PAIR:
2819 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
2820 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
2823 if (esw->paired[mlx5_get_dev_index(peer_esw->dev)])
2826 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
2829 err = mlx5_esw_offloads_pair(esw, peer_esw);
2833 err = mlx5_esw_offloads_pair(peer_esw, esw);
2837 esw->paired[mlx5_get_dev_index(peer_esw->dev)] = true;
2838 peer_esw->paired[mlx5_get_dev_index(esw->dev)] = true;
2839 mlx5_devcom_comp_set_ready(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
2842 case ESW_OFFLOADS_DEVCOM_UNPAIR:
2843 if (!esw->paired[mlx5_get_dev_index(peer_esw->dev)])
2846 mlx5_devcom_comp_set_ready(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
2847 esw->paired[mlx5_get_dev_index(peer_esw->dev)] = false;
2848 peer_esw->paired[mlx5_get_dev_index(esw->dev)] = false;
2849 mlx5_esw_offloads_unpair(peer_esw, esw);
2850 mlx5_esw_offloads_unpair(esw, peer_esw);
2851 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
2858 mlx5_esw_offloads_unpair(esw, peer_esw);
2860 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
2862 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
2867 void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw)
2869 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2872 for (i = 0; i < MLX5_MAX_PORTS; i++)
2873 INIT_LIST_HEAD(&esw->offloads.peer_flows[i]);
2874 mutex_init(&esw->offloads.peer_mutex);
2876 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2879 if (!mlx5_is_lag_supported(esw->dev))
2882 mlx5_devcom_register_component(devcom,
2883 MLX5_DEVCOM_ESW_OFFLOADS,
2884 mlx5_esw_offloads_devcom_event,
2887 mlx5_devcom_send_event(devcom,
2888 MLX5_DEVCOM_ESW_OFFLOADS,
2889 ESW_OFFLOADS_DEVCOM_PAIR, esw);
2892 void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
2894 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2896 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2899 if (!mlx5_is_lag_supported(esw->dev))
2902 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
2903 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2905 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2908 bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
2910 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2913 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2914 MLX5_FDB_TO_VPORT_REG_C_0))
2920 #define MLX5_ESW_METADATA_RSVD_UPLINK 1
2922 /* Share the same metadata for uplink's. This is fine because:
2923 * (a) In shared FDB mode (LAG) both uplink's are treated the
2924 * same and tagged with the same metadata.
2925 * (b) In non shared FDB mode, packets from physical port0
2926 * cannot hit eswitch of PF1 and vice versa.
2928 static u32 mlx5_esw_match_metadata_reserved(struct mlx5_eswitch *esw)
2930 return MLX5_ESW_METADATA_RSVD_UPLINK;
2933 u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2935 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
2936 /* Reserve 0xf for internal port offload */
2937 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 2;
2941 /* Only 4 bits of pf_num */
2942 pf_num = mlx5_get_dev_index(esw->dev);
2943 if (pf_num > max_pf_num)
2946 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
2947 /* Use only non-zero vport_id (2-4095) for all PF's */
2948 id = ida_alloc_range(&esw->offloads.vport_metadata_ida,
2949 MLX5_ESW_METADATA_RSVD_UPLINK + 1,
2950 vport_end_ida, GFP_KERNEL);
2953 id = (pf_num << ESW_VPORT_BITS) | id;
2957 void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2959 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2961 /* Metadata contains only 12 bits of actual ida id */
2962 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
2965 static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2966 struct mlx5_vport *vport)
2968 if (vport->vport == MLX5_VPORT_UPLINK)
2969 vport->default_metadata = mlx5_esw_match_metadata_reserved(esw);
2971 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2973 vport->metadata = vport->default_metadata;
2974 return vport->metadata ? 0 : -ENOSPC;
2977 static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2978 struct mlx5_vport *vport)
2980 if (!vport->default_metadata)
2983 if (vport->vport == MLX5_VPORT_UPLINK)
2986 WARN_ON(vport->metadata != vport->default_metadata);
2987 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2990 static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2992 struct mlx5_vport *vport;
2995 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2998 mlx5_esw_for_each_vport(esw, i, vport)
2999 esw_offloads_vport_metadata_cleanup(esw, vport);
3002 static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
3004 struct mlx5_vport *vport;
3008 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
3011 mlx5_esw_for_each_vport(esw, i, vport) {
3012 err = esw_offloads_vport_metadata_setup(esw, vport);
3020 esw_offloads_metadata_uninit(esw);
3025 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
3026 struct mlx5_vport *vport)
3030 err = esw_acl_ingress_ofld_setup(esw, vport);
3034 err = esw_acl_egress_ofld_setup(esw, vport);
3041 esw_acl_ingress_ofld_cleanup(esw, vport);
3046 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
3047 struct mlx5_vport *vport)
3049 esw_acl_egress_ofld_cleanup(vport);
3050 esw_acl_ingress_ofld_cleanup(esw, vport);
3053 static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
3055 struct mlx5_vport *vport;
3057 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
3059 return PTR_ERR(vport);
3061 return esw_vport_create_offloads_acl_tables(esw, vport);
3064 static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
3066 struct mlx5_vport *vport;
3068 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
3072 esw_vport_destroy_offloads_acl_tables(esw, vport);
3075 int mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw)
3077 struct mlx5_eswitch_rep *rep;
3081 if (!esw || esw->mode != MLX5_ESWITCH_OFFLOADS)
3084 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
3085 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
3088 ret = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
3092 mlx5_esw_for_each_rep(esw, i, rep) {
3093 if (atomic_read(&rep->rep_data[REP_ETH].state) == REP_LOADED)
3094 mlx5_esw_offloads_rep_load(esw, rep->vport);
3100 static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
3102 struct mlx5_esw_indir_table *indir;
3105 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
3106 mutex_init(&esw->fdb_table.offloads.vports.lock);
3107 hash_init(esw->fdb_table.offloads.vports.table);
3108 atomic64_set(&esw->user_count, 0);
3110 indir = mlx5_esw_indir_table_init();
3111 if (IS_ERR(indir)) {
3112 err = PTR_ERR(indir);
3113 goto create_indir_err;
3115 esw->fdb_table.offloads.indir = indir;
3117 err = esw_create_uplink_offloads_acl_tables(esw);
3119 goto create_acl_err;
3121 err = esw_create_offloads_table(esw);
3123 goto create_offloads_err;
3125 err = esw_create_restore_table(esw);
3127 goto create_restore_err;
3129 err = esw_create_offloads_fdb_tables(esw);
3131 goto create_fdb_err;
3133 err = esw_create_vport_rx_group(esw);
3137 err = esw_create_vport_rx_drop_group(esw);
3139 goto create_rx_drop_fg_err;
3141 err = esw_create_vport_rx_drop_rule(esw);
3143 goto create_rx_drop_rule_err;
3147 create_rx_drop_rule_err:
3148 esw_destroy_vport_rx_drop_group(esw);
3149 create_rx_drop_fg_err:
3150 esw_destroy_vport_rx_group(esw);
3152 esw_destroy_offloads_fdb_tables(esw);
3154 esw_destroy_restore_table(esw);
3156 esw_destroy_offloads_table(esw);
3157 create_offloads_err:
3158 esw_destroy_uplink_offloads_acl_tables(esw);
3160 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3162 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
3166 static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
3168 esw_destroy_vport_rx_drop_rule(esw);
3169 esw_destroy_vport_rx_drop_group(esw);
3170 esw_destroy_vport_rx_group(esw);
3171 esw_destroy_offloads_fdb_tables(esw);
3172 esw_destroy_restore_table(esw);
3173 esw_destroy_offloads_table(esw);
3174 esw_destroy_uplink_offloads_acl_tables(esw);
3175 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3176 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
3180 esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
3182 struct devlink *devlink;
3183 bool host_pf_disabled;
3186 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
3187 host_params_context.host_num_of_vfs);
3188 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
3189 host_params_context.host_pf_disabled);
3191 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
3194 devlink = priv_to_devlink(esw->dev);
3196 /* Number of VFs can only change from "0 to x" or "x to 0". */
3197 if (esw->esw_funcs.num_vfs > 0) {
3198 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
3202 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
3203 MLX5_VPORT_UC_ADDR_CHANGE);
3205 devl_unlock(devlink);
3209 esw->esw_funcs.num_vfs = new_num_vfs;
3210 devl_unlock(devlink);
3213 static void esw_functions_changed_event_handler(struct work_struct *work)
3215 struct mlx5_host_work *host_work;
3216 struct mlx5_eswitch *esw;
3219 host_work = container_of(work, struct mlx5_host_work, work);
3220 esw = host_work->esw;
3222 out = mlx5_esw_query_functions(esw->dev);
3226 esw_vfs_changed_event_handler(esw, out);
3232 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
3234 struct mlx5_esw_functions *esw_funcs;
3235 struct mlx5_host_work *host_work;
3236 struct mlx5_eswitch *esw;
3238 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
3242 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
3243 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
3245 host_work->esw = esw;
3247 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
3248 queue_work(esw->work_queue, &host_work->work);
3253 static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
3255 const u32 *query_host_out;
3257 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3260 query_host_out = mlx5_esw_query_functions(esw->dev);
3261 if (IS_ERR(query_host_out))
3262 return PTR_ERR(query_host_out);
3264 /* Mark non local controller with non zero controller number. */
3265 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
3266 host_params_context.host_number);
3267 kvfree(query_host_out);
3271 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
3273 /* Local controller is always valid */
3274 if (controller == 0)
3277 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3280 /* External host number starts with zero in device */
3281 return (controller == esw->offloads.host_number + 1);
3284 int esw_offloads_enable(struct mlx5_eswitch *esw)
3286 struct mapping_ctx *reg_c0_obj_pool;
3287 struct mlx5_vport *vport;
3292 mutex_init(&esw->offloads.termtbl_mutex);
3293 mlx5_rdma_enable_roce(esw->dev);
3295 err = mlx5_esw_host_number_init(esw);
3299 err = esw_offloads_metadata_init(esw);
3303 err = esw_set_passing_vport_metadata(esw, true);
3305 goto err_vport_metadata;
3307 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
3309 reg_c0_obj_pool = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
3310 sizeof(struct mlx5_mapped_obj),
3311 ESW_REG_C0_USER_DATA_METADATA_MASK,
3314 if (IS_ERR(reg_c0_obj_pool)) {
3315 err = PTR_ERR(reg_c0_obj_pool);
3318 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
3320 err = esw_offloads_steering_init(esw);
3322 goto err_steering_init;
3324 /* Representor will control the vport link state */
3325 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
3326 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3328 /* Uplink vport rep must load first. */
3329 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
3333 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
3340 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
3342 esw_offloads_steering_cleanup(esw);
3344 mapping_destroy(reg_c0_obj_pool);
3346 esw_set_passing_vport_metadata(esw, false);
3348 esw_offloads_metadata_uninit(esw);
3350 mlx5_rdma_disable_roce(esw->dev);
3351 mutex_destroy(&esw->offloads.termtbl_mutex);
3355 static int esw_offloads_stop(struct mlx5_eswitch *esw,
3356 struct netlink_ext_ack *extack)
3360 esw->mode = MLX5_ESWITCH_LEGACY;
3362 /* If changing from switchdev to legacy mode without sriov enabled,
3363 * no need to create legacy fdb.
3365 if (!mlx5_core_is_pf(esw->dev) || !mlx5_sriov_is_enabled(esw->dev))
3368 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
3370 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
3375 void esw_offloads_disable(struct mlx5_eswitch *esw)
3377 mlx5_eswitch_disable_pf_vf_vports(esw);
3378 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
3379 esw_set_passing_vport_metadata(esw, false);
3380 esw_offloads_steering_cleanup(esw);
3381 mapping_destroy(esw->offloads.reg_c0_obj_pool);
3382 esw_offloads_metadata_uninit(esw);
3383 mlx5_rdma_disable_roce(esw->dev);
3384 mutex_destroy(&esw->offloads.termtbl_mutex);
3387 static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
3390 case DEVLINK_ESWITCH_MODE_LEGACY:
3391 *mlx5_mode = MLX5_ESWITCH_LEGACY;
3393 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
3394 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
3403 static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
3405 switch (mlx5_mode) {
3406 case MLX5_ESWITCH_LEGACY:
3407 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
3409 case MLX5_ESWITCH_OFFLOADS:
3410 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
3419 static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
3422 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
3423 *mlx5_mode = MLX5_INLINE_MODE_NONE;
3425 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
3426 *mlx5_mode = MLX5_INLINE_MODE_L2;
3428 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
3429 *mlx5_mode = MLX5_INLINE_MODE_IP;
3431 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
3432 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
3441 static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
3443 switch (mlx5_mode) {
3444 case MLX5_INLINE_MODE_NONE:
3445 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
3447 case MLX5_INLINE_MODE_L2:
3448 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
3450 case MLX5_INLINE_MODE_IP:
3451 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
3453 case MLX5_INLINE_MODE_TCP_UDP:
3454 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
3463 static bool esw_offloads_devlink_ns_eq_netdev_ns(struct devlink *devlink)
3465 struct net *devl_net, *netdev_net;
3466 struct mlx5_eswitch *esw;
3468 esw = mlx5_devlink_eswitch_get(devlink);
3469 netdev_net = dev_net(esw->dev->mlx5e_res.uplink_netdev);
3470 devl_net = devlink_net(devlink);
3472 return net_eq(devl_net, netdev_net);
3475 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
3476 struct netlink_ext_ack *extack)
3478 u16 cur_mlx5_mode, mlx5_mode = 0;
3479 struct mlx5_eswitch *esw;
3482 esw = mlx5_devlink_eswitch_get(devlink);
3484 return PTR_ERR(esw);
3486 if (esw_mode_from_devlink(mode, &mlx5_mode))
3489 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV &&
3490 !esw_offloads_devlink_ns_eq_netdev_ns(devlink)) {
3491 NL_SET_ERR_MSG_MOD(extack,
3492 "Can't change E-Switch mode to switchdev when netdev net namespace has diverged from the devlink's.");
3496 mlx5_lag_disable_change(esw->dev);
3497 err = mlx5_esw_try_lock(esw);
3499 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
3502 cur_mlx5_mode = err;
3505 if (cur_mlx5_mode == mlx5_mode)
3508 mlx5_eswitch_disable_locked(esw);
3509 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) {
3510 if (mlx5_devlink_trap_get_num_active(esw->dev)) {
3511 NL_SET_ERR_MSG_MOD(extack,
3512 "Can't change mode while devlink traps are active");
3516 err = esw_offloads_start(esw, extack);
3517 } else if (mode == DEVLINK_ESWITCH_MODE_LEGACY) {
3518 err = esw_offloads_stop(esw, extack);
3519 mlx5_rescan_drivers(esw->dev);
3525 mlx5_esw_unlock(esw);
3527 mlx5_lag_enable_change(esw->dev);
3531 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
3533 struct mlx5_eswitch *esw;
3536 esw = mlx5_devlink_eswitch_get(devlink);
3538 return PTR_ERR(esw);
3540 down_read(&esw->mode_lock);
3541 err = esw_mode_to_devlink(esw->mode, mode);
3542 up_read(&esw->mode_lock);
3546 static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3547 struct netlink_ext_ack *extack)
3549 struct mlx5_core_dev *dev = esw->dev;
3550 struct mlx5_vport *vport;
3551 u16 err_vport_num = 0;
3555 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3556 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3558 err_vport_num = vport->vport;
3559 NL_SET_ERR_MSG_MOD(extack,
3560 "Failed to set min inline on vport");
3561 goto revert_inline_mode;
3567 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3568 if (vport->vport == err_vport_num)
3570 mlx5_modify_nic_vport_min_inline(dev,
3572 esw->offloads.inline_mode);
3577 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3578 struct netlink_ext_ack *extack)
3580 struct mlx5_core_dev *dev = devlink_priv(devlink);
3581 struct mlx5_eswitch *esw;
3585 esw = mlx5_devlink_eswitch_get(devlink);
3587 return PTR_ERR(esw);
3589 down_write(&esw->mode_lock);
3591 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3592 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3593 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE) {
3599 case MLX5_CAP_INLINE_MODE_L2:
3600 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
3603 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3607 if (atomic64_read(&esw->offloads.num_flows) > 0) {
3608 NL_SET_ERR_MSG_MOD(extack,
3609 "Can't set inline mode when flows are configured");
3614 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3618 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3622 esw->offloads.inline_mode = mlx5_mode;
3623 up_write(&esw->mode_lock);
3627 up_write(&esw->mode_lock);
3631 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3633 struct mlx5_eswitch *esw;
3636 esw = mlx5_devlink_eswitch_get(devlink);
3638 return PTR_ERR(esw);
3640 down_read(&esw->mode_lock);
3641 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
3642 up_read(&esw->mode_lock);
3646 bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev)
3648 struct devlink *devlink = priv_to_devlink(dev);
3649 struct mlx5_eswitch *esw;
3652 esw = mlx5_devlink_eswitch_get(devlink);
3654 devl_unlock(devlink);
3655 /* Failure means no eswitch => not possible to change encap */
3659 down_write(&esw->mode_lock);
3660 if (esw->mode != MLX5_ESWITCH_LEGACY &&
3661 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
3662 up_write(&esw->mode_lock);
3663 devl_unlock(devlink);
3667 esw->offloads.num_block_encap++;
3668 up_write(&esw->mode_lock);
3669 devl_unlock(devlink);
3673 void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev)
3675 struct devlink *devlink = priv_to_devlink(dev);
3676 struct mlx5_eswitch *esw;
3678 esw = mlx5_devlink_eswitch_get(devlink);
3682 down_write(&esw->mode_lock);
3683 esw->offloads.num_block_encap--;
3684 up_write(&esw->mode_lock);
3687 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3688 enum devlink_eswitch_encap_mode encap,
3689 struct netlink_ext_ack *extack)
3691 struct mlx5_core_dev *dev = devlink_priv(devlink);
3692 struct mlx5_eswitch *esw;
3695 esw = mlx5_devlink_eswitch_get(devlink);
3697 return PTR_ERR(esw);
3699 down_write(&esw->mode_lock);
3701 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
3702 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
3703 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3708 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3713 if (esw->mode == MLX5_ESWITCH_LEGACY) {
3714 esw->offloads.encap = encap;
3718 if (esw->offloads.encap == encap)
3721 if (atomic64_read(&esw->offloads.num_flows) > 0) {
3722 NL_SET_ERR_MSG_MOD(extack,
3723 "Can't set encapsulation when flows are configured");
3728 if (esw->offloads.num_block_encap) {
3729 NL_SET_ERR_MSG_MOD(extack,
3730 "Can't set encapsulation when IPsec SA and/or policies are configured");
3735 esw_destroy_offloads_fdb_tables(esw);
3737 esw->offloads.encap = encap;
3739 err = esw_create_offloads_fdb_tables(esw);
3742 NL_SET_ERR_MSG_MOD(extack,
3743 "Failed re-creating fast FDB table");
3744 esw->offloads.encap = !encap;
3745 (void)esw_create_offloads_fdb_tables(esw);
3749 up_write(&esw->mode_lock);
3753 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
3754 enum devlink_eswitch_encap_mode *encap)
3756 struct mlx5_eswitch *esw;
3758 esw = mlx5_devlink_eswitch_get(devlink);
3760 return PTR_ERR(esw);
3762 down_read(&esw->mode_lock);
3763 *encap = esw->offloads.encap;
3764 up_read(&esw->mode_lock);
3769 mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
3771 /* Currently, only ECPF based device has representor for host PF. */
3772 if (vport_num == MLX5_VPORT_PF &&
3773 !mlx5_core_is_ecpf_esw_manager(esw->dev))
3776 if (vport_num == MLX5_VPORT_ECPF &&
3777 !mlx5_ecpf_vport_exists(esw->dev))
3783 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
3784 const struct mlx5_eswitch_rep_ops *ops,
3787 struct mlx5_eswitch_rep_data *rep_data;
3788 struct mlx5_eswitch_rep *rep;
3791 esw->offloads.rep_ops[rep_type] = ops;
3792 mlx5_esw_for_each_rep(esw, i, rep) {
3793 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
3795 rep_data = &rep->rep_data[rep_type];
3796 atomic_set(&rep_data->state, REP_REGISTERED);
3800 EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
3802 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
3804 struct mlx5_eswitch_rep *rep;
3807 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
3808 __unload_reps_all_vport(esw, rep_type);
3810 mlx5_esw_for_each_rep(esw, i, rep)
3811 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
3813 EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
3815 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
3817 struct mlx5_eswitch_rep *rep;
3819 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
3820 return rep->rep_data[rep_type].priv;
3823 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
3827 struct mlx5_eswitch_rep *rep;
3829 rep = mlx5_eswitch_get_rep(esw, vport);
3831 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
3832 esw->offloads.rep_ops[rep_type]->get_proto_dev)
3833 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
3836 EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
3838 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
3840 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
3842 EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
3844 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
3847 return mlx5_eswitch_get_rep(esw, vport);
3849 EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
3851 bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
3853 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
3855 EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
3857 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
3859 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
3861 EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
3863 u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
3866 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
3868 if (WARN_ON_ONCE(IS_ERR(vport)))
3871 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
3873 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
3875 int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port,
3876 u16 vport_num, u32 controller, u32 sfnum)
3880 err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE);
3884 err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum);
3888 err = mlx5_esw_offloads_rep_load(esw, vport_num);
3894 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3896 mlx5_esw_vport_disable(esw, vport_num);
3900 void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num)
3902 mlx5_esw_offloads_rep_unload(esw, vport_num);
3903 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3904 mlx5_esw_vport_disable(esw, vport_num);
3907 static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
3909 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
3915 if (mlx5_esw_is_manager_vport(esw, vport_num) ||
3916 !MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
3919 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
3923 err = mlx5_vport_get_other_func_general_cap(esw->dev, vport_num, query_ctx);
3927 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
3928 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
3935 int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
3937 u16 *old_entry, *vhca_map_entry, vhca_id;
3940 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3942 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
3947 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
3948 if (!vhca_map_entry)
3951 *vhca_map_entry = vport_num;
3952 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
3953 if (xa_is_err(old_entry)) {
3954 kfree(vhca_map_entry);
3955 return xa_err(old_entry);
3961 void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
3963 u16 *vhca_map_entry, vhca_id;
3966 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3968 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
3971 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
3972 kfree(vhca_map_entry);
3975 int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
3977 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
3986 u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
3989 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
3991 if (WARN_ON_ONCE(IS_ERR(vport)))
3994 return vport->metadata;
3996 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
3999 is_port_function_supported(struct mlx5_eswitch *esw, u16 vport_num)
4001 return vport_num == MLX5_VPORT_PF ||
4002 mlx5_eswitch_is_vf_vport(esw, vport_num) ||
4003 mlx5_esw_is_sf_vport(esw, vport_num);
4006 int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port,
4007 u8 *hw_addr, int *hw_addr_len,
4008 struct netlink_ext_ack *extack)
4010 struct mlx5_eswitch *esw;
4011 struct mlx5_vport *vport;
4014 esw = mlx5_devlink_eswitch_get(port->devlink);
4016 return PTR_ERR(esw);
4018 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4019 if (!is_port_function_supported(esw, vport_num))
4022 vport = mlx5_eswitch_get_vport(esw, vport_num);
4023 if (IS_ERR(vport)) {
4024 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4025 return PTR_ERR(vport);
4028 mutex_lock(&esw->state_lock);
4029 ether_addr_copy(hw_addr, vport->info.mac);
4030 *hw_addr_len = ETH_ALEN;
4031 mutex_unlock(&esw->state_lock);
4035 int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port,
4036 const u8 *hw_addr, int hw_addr_len,
4037 struct netlink_ext_ack *extack)
4039 struct mlx5_eswitch *esw;
4042 esw = mlx5_devlink_eswitch_get(port->devlink);
4044 NL_SET_ERR_MSG_MOD(extack, "Eswitch doesn't support set hw_addr");
4045 return PTR_ERR(esw);
4048 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4049 if (!is_port_function_supported(esw, vport_num)) {
4050 NL_SET_ERR_MSG_MOD(extack, "Port doesn't support set hw_addr");
4054 return mlx5_eswitch_set_vport_mac(esw, vport_num, hw_addr);
4057 static struct mlx5_vport *
4058 mlx5_devlink_port_fn_get_vport(struct devlink_port *port, struct mlx5_eswitch *esw)
4062 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
4063 return ERR_PTR(-EOPNOTSUPP);
4065 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4066 if (!is_port_function_supported(esw, vport_num))
4067 return ERR_PTR(-EOPNOTSUPP);
4069 return mlx5_eswitch_get_vport(esw, vport_num);
4072 int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled,
4073 struct netlink_ext_ack *extack)
4075 struct mlx5_eswitch *esw;
4076 struct mlx5_vport *vport;
4077 int err = -EOPNOTSUPP;
4079 esw = mlx5_devlink_eswitch_get(port->devlink);
4081 return PTR_ERR(esw);
4083 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4084 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4088 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4089 if (IS_ERR(vport)) {
4090 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4091 return PTR_ERR(vport);
4094 mutex_lock(&esw->state_lock);
4095 if (vport->enabled) {
4096 *is_enabled = vport->info.mig_enabled;
4099 mutex_unlock(&esw->state_lock);
4103 int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable,
4104 struct netlink_ext_ack *extack)
4106 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4107 struct mlx5_eswitch *esw;
4108 struct mlx5_vport *vport;
4111 int err = -EOPNOTSUPP;
4113 esw = mlx5_devlink_eswitch_get(port->devlink);
4115 return PTR_ERR(esw);
4117 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4118 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4122 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4123 if (IS_ERR(vport)) {
4124 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4125 return PTR_ERR(vport);
4128 mutex_lock(&esw->state_lock);
4129 if (!vport->enabled) {
4130 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4134 if (vport->info.mig_enabled == enable) {
4139 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4145 err = mlx5_vport_get_other_func_cap(esw->dev, vport->vport, query_ctx,
4146 MLX5_CAP_GENERAL_2);
4148 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4152 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4153 MLX5_SET(cmd_hca_cap_2, hca_caps, migratable, 1);
4155 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport->vport,
4156 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2);
4158 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA migratable cap");
4162 vport->info.mig_enabled = enable;
4167 mutex_unlock(&esw->state_lock);
4171 int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled,
4172 struct netlink_ext_ack *extack)
4174 struct mlx5_eswitch *esw;
4175 struct mlx5_vport *vport;
4176 int err = -EOPNOTSUPP;
4178 esw = mlx5_devlink_eswitch_get(port->devlink);
4180 return PTR_ERR(esw);
4182 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4183 if (IS_ERR(vport)) {
4184 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4185 return PTR_ERR(vport);
4188 mutex_lock(&esw->state_lock);
4189 if (vport->enabled) {
4190 *is_enabled = vport->info.roce_enabled;
4193 mutex_unlock(&esw->state_lock);
4197 int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable,
4198 struct netlink_ext_ack *extack)
4200 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4201 struct mlx5_eswitch *esw;
4202 struct mlx5_vport *vport;
4203 int err = -EOPNOTSUPP;
4208 esw = mlx5_devlink_eswitch_get(port->devlink);
4210 return PTR_ERR(esw);
4212 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4213 if (IS_ERR(vport)) {
4214 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4215 return PTR_ERR(vport);
4217 vport_num = vport->vport;
4219 mutex_lock(&esw->state_lock);
4220 if (!vport->enabled) {
4221 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4225 if (vport->info.roce_enabled == enable) {
4230 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4236 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4239 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4243 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4244 MLX5_SET(cmd_hca_cap, hca_caps, roce, enable);
4246 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num,
4247 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
4249 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA roce cap");
4253 vport->info.roce_enabled = enable;
4258 mutex_unlock(&esw->state_lock);