2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/etherdevice.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/mlx5_ifc.h>
36 #include <linux/mlx5/vport.h>
37 #include <linux/mlx5/fs.h>
38 #include "mlx5_core.h"
40 #include "eswitch_offloads_chains.h"
44 #include "lib/devcom.h"
47 /* There are two match-all miss flows, one for unicast dst mac and
50 #define MLX5_ESW_MISS_FLOWS (2)
51 #define UPLINK_REP_INDEX 0
53 static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
56 int idx = mlx5_eswitch_vport_num_to_index(esw, vport_num);
58 WARN_ON(idx > esw->total_vports - 1);
59 return &esw->offloads.vport_reps[idx];
63 esw_check_ingress_prio_tag_enabled(const struct mlx5_eswitch *esw,
64 const struct mlx5_vport *vport)
66 return (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
67 mlx5_eswitch_is_vf_vport(esw, vport->vport));
71 mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
72 struct mlx5_flow_spec *spec,
73 struct mlx5_esw_flow_attr *attr)
78 /* Use metadata matching because vport is not represented by single
79 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
81 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
82 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
83 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
84 mlx5_eswitch_get_vport_metadata_for_match(attr->in_mdev->priv.eswitch,
85 attr->in_rep->vport));
87 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
88 MLX5_SET_TO_ONES(fte_match_set_misc2, misc2, metadata_reg_c_0);
90 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
91 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
92 if (memchr_inv(misc, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc)))
93 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
95 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
96 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
98 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
99 MLX5_SET(fte_match_set_misc, misc,
100 source_eswitch_owner_vhca_id,
101 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
103 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
104 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
105 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
106 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
107 source_eswitch_owner_vhca_id);
109 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
112 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
113 attr->in_rep->vport == MLX5_VPORT_UPLINK)
114 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;
117 struct mlx5_flow_handle *
118 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
119 struct mlx5_flow_spec *spec,
120 struct mlx5_esw_flow_attr *attr)
122 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
123 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
124 bool split = !!(attr->split_count);
125 struct mlx5_flow_handle *rule;
126 struct mlx5_flow_table *fdb;
129 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
130 return ERR_PTR(-EOPNOTSUPP);
132 flow_act.action = attr->action;
133 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
134 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
135 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
136 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
137 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
138 flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto[0]);
139 flow_act.vlan[0].vid = attr->vlan_vid[0];
140 flow_act.vlan[0].prio = attr->vlan_prio[0];
141 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
142 flow_act.vlan[1].ethtype = ntohs(attr->vlan_proto[1]);
143 flow_act.vlan[1].vid = attr->vlan_vid[1];
144 flow_act.vlan[1].prio = attr->vlan_prio[1];
148 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
149 struct mlx5_flow_table *ft;
151 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) {
152 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
153 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
154 dest[i].ft = mlx5_esw_chains_get_tc_end_ft(esw);
156 } else if (attr->dest_chain) {
157 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
158 ft = mlx5_esw_chains_get_table(esw, attr->dest_chain,
162 goto err_create_goto_table;
165 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
169 for (j = attr->split_count; j < attr->out_count; j++) {
170 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
171 dest[i].vport.num = attr->dests[j].rep->vport;
172 dest[i].vport.vhca_id =
173 MLX5_CAP_GEN(attr->dests[j].mdev, vhca_id);
174 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
175 dest[i].vport.flags |=
176 MLX5_FLOW_DEST_VPORT_VHCA_ID;
177 if (attr->dests[j].flags & MLX5_ESW_DEST_ENCAP) {
178 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
179 flow_act.pkt_reformat = attr->dests[j].pkt_reformat;
180 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
181 dest[i].vport.pkt_reformat =
182 attr->dests[j].pkt_reformat;
188 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
189 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
190 dest[i].counter_id = mlx5_fc_id(attr->counter);
194 mlx5_eswitch_set_rule_source_port(esw, spec, attr);
196 if (attr->outer_match_level != MLX5_MATCH_NONE)
197 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
198 if (attr->inner_match_level != MLX5_MATCH_NONE)
199 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
201 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
202 flow_act.modify_hdr = attr->modify_hdr;
204 fdb = mlx5_esw_chains_get_table(esw, attr->chain, attr->prio,
207 rule = ERR_CAST(fdb);
211 if (mlx5_eswitch_termtbl_required(esw, &flow_act, spec))
212 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, attr,
215 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
219 atomic64_inc(&esw->offloads.num_flows);
224 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio, !!split);
226 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) && attr->dest_chain)
227 mlx5_esw_chains_put_table(esw, attr->dest_chain, 1, 0);
228 err_create_goto_table:
232 struct mlx5_flow_handle *
233 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
234 struct mlx5_flow_spec *spec,
235 struct mlx5_esw_flow_attr *attr)
237 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
238 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
239 struct mlx5_flow_table *fast_fdb;
240 struct mlx5_flow_table *fwd_fdb;
241 struct mlx5_flow_handle *rule;
244 fast_fdb = mlx5_esw_chains_get_table(esw, attr->chain, attr->prio, 0);
245 if (IS_ERR(fast_fdb)) {
246 rule = ERR_CAST(fast_fdb);
250 fwd_fdb = mlx5_esw_chains_get_table(esw, attr->chain, attr->prio, 1);
251 if (IS_ERR(fwd_fdb)) {
252 rule = ERR_CAST(fwd_fdb);
256 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
257 for (i = 0; i < attr->split_count; i++) {
258 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
259 dest[i].vport.num = attr->dests[i].rep->vport;
260 dest[i].vport.vhca_id =
261 MLX5_CAP_GEN(attr->dests[i].mdev, vhca_id);
262 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
263 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
264 if (attr->dests[i].flags & MLX5_ESW_DEST_ENCAP) {
265 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
266 dest[i].vport.pkt_reformat = attr->dests[i].pkt_reformat;
269 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
270 dest[i].ft = fwd_fdb,
273 mlx5_eswitch_set_rule_source_port(esw, spec, attr);
275 if (attr->outer_match_level != MLX5_MATCH_NONE)
276 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
278 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
279 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
284 atomic64_inc(&esw->offloads.num_flows);
288 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio, 1);
290 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio, 0);
296 __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
297 struct mlx5_flow_handle *rule,
298 struct mlx5_esw_flow_attr *attr,
301 bool split = (attr->split_count > 0);
304 mlx5_del_flow_rules(rule);
306 /* unref the term table */
307 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
308 if (attr->dests[i].termtbl)
309 mlx5_eswitch_termtbl_put(esw, attr->dests[i].termtbl);
312 atomic64_dec(&esw->offloads.num_flows);
315 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio, 1);
316 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio, 0);
318 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio,
320 if (attr->dest_chain)
321 mlx5_esw_chains_put_table(esw, attr->dest_chain, 1, 0);
326 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
327 struct mlx5_flow_handle *rule,
328 struct mlx5_esw_flow_attr *attr)
330 __mlx5_eswitch_del_rule(esw, rule, attr, false);
334 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
335 struct mlx5_flow_handle *rule,
336 struct mlx5_esw_flow_attr *attr)
338 __mlx5_eswitch_del_rule(esw, rule, attr, true);
341 static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
343 struct mlx5_eswitch_rep *rep;
346 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
347 mlx5_esw_for_each_host_func_rep(esw, i, rep, esw->esw_funcs.num_vfs) {
348 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
351 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
360 static struct mlx5_eswitch_rep *
361 esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
363 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
365 in_rep = attr->in_rep;
366 out_rep = attr->dests[0].rep;
378 static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
379 bool push, bool pop, bool fwd)
381 struct mlx5_eswitch_rep *in_rep, *out_rep;
383 if ((push || pop) && !fwd)
386 in_rep = attr->in_rep;
387 out_rep = attr->dests[0].rep;
389 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
392 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
395 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
396 if (!push && !pop && fwd)
397 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
400 /* protects against (1) setting rules with different vlans to push and
401 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
403 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
412 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
413 struct mlx5_esw_flow_attr *attr)
415 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
416 struct mlx5_eswitch_rep *vport = NULL;
420 /* nop if we're on the vlan push/pop non emulation mode */
421 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
424 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
425 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
426 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
429 mutex_lock(&esw->state_lock);
431 err = esw_add_vlan_action_check(attr, push, pop, fwd);
435 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
437 vport = esw_vlan_action_get_vport(attr, push, pop);
439 if (!push && !pop && fwd) {
440 /* tracks VF --> wire rules without vlan push action */
441 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
442 vport->vlan_refcount++;
443 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
452 if (!(offloads->vlan_push_pop_refcount)) {
453 /* it's the 1st vlan rule, apply global vlan pop policy */
454 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
458 offloads->vlan_push_pop_refcount++;
461 if (vport->vlan_refcount)
464 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, attr->vlan_vid[0], 0,
465 SET_VLAN_INSERT | SET_VLAN_STRIP);
468 vport->vlan = attr->vlan_vid[0];
470 vport->vlan_refcount++;
474 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
476 mutex_unlock(&esw->state_lock);
480 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
481 struct mlx5_esw_flow_attr *attr)
483 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
484 struct mlx5_eswitch_rep *vport = NULL;
488 /* nop if we're on the vlan push/pop non emulation mode */
489 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
492 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
495 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
496 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
497 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
499 mutex_lock(&esw->state_lock);
501 vport = esw_vlan_action_get_vport(attr, push, pop);
503 if (!push && !pop && fwd) {
504 /* tracks VF --> wire rules without vlan push action */
505 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
506 vport->vlan_refcount--;
512 vport->vlan_refcount--;
513 if (vport->vlan_refcount)
514 goto skip_unset_push;
517 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
518 0, 0, SET_VLAN_STRIP);
524 offloads->vlan_push_pop_refcount--;
525 if (offloads->vlan_push_pop_refcount)
528 /* no more vlan rules, stop global vlan pop policy */
529 err = esw_set_global_vlan_pop(esw, 0);
532 mutex_unlock(&esw->state_lock);
536 struct mlx5_flow_handle *
537 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, u16 vport,
540 struct mlx5_flow_act flow_act = {0};
541 struct mlx5_flow_destination dest = {};
542 struct mlx5_flow_handle *flow_rule;
543 struct mlx5_flow_spec *spec;
546 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
548 flow_rule = ERR_PTR(-ENOMEM);
552 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
553 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
554 /* source vport is the esw manager */
555 MLX5_SET(fte_match_set_misc, misc, source_port, esw->manager_vport);
557 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
558 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
559 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
561 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
562 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
563 dest.vport.num = vport;
564 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
566 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
567 spec, &flow_act, &dest, 1);
568 if (IS_ERR(flow_rule))
569 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
574 EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
576 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
578 mlx5_del_flow_rules(rule);
581 static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
583 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
584 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
585 u8 fdb_to_vport_reg_c_id;
588 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
591 err = mlx5_eswitch_query_esw_vport_context(esw->dev, 0, false,
596 fdb_to_vport_reg_c_id = MLX5_GET(query_esw_vport_context_out, out,
597 esw_vport_context.fdb_to_vport_reg_c_id);
600 fdb_to_vport_reg_c_id |= MLX5_FDB_TO_VPORT_REG_C_0;
602 fdb_to_vport_reg_c_id &= ~MLX5_FDB_TO_VPORT_REG_C_0;
604 MLX5_SET(modify_esw_vport_context_in, in,
605 esw_vport_context.fdb_to_vport_reg_c_id, fdb_to_vport_reg_c_id);
607 MLX5_SET(modify_esw_vport_context_in, in,
608 field_select.fdb_to_vport_reg_c_id, 1);
610 return mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false,
614 static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
615 struct mlx5_core_dev *peer_dev,
616 struct mlx5_flow_spec *spec,
617 struct mlx5_flow_destination *dest)
621 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
622 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
624 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
626 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
628 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
631 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
632 MLX5_CAP_GEN(peer_dev, vhca_id));
634 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
636 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
638 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
639 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
640 source_eswitch_owner_vhca_id);
643 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
644 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
645 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
646 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
649 static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
650 struct mlx5_eswitch *peer_esw,
651 struct mlx5_flow_spec *spec,
656 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
657 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
659 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
660 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
663 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
665 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
669 static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
670 struct mlx5_core_dev *peer_dev)
672 struct mlx5_flow_destination dest = {};
673 struct mlx5_flow_act flow_act = {0};
674 struct mlx5_flow_handle **flows;
675 struct mlx5_flow_handle *flow;
676 struct mlx5_flow_spec *spec;
677 /* total vports is the same for both e-switches */
678 int nvports = esw->total_vports;
682 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
686 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
688 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
691 goto alloc_flows_err;
694 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
695 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
698 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
699 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
700 spec, MLX5_VPORT_PF);
702 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
703 spec, &flow_act, &dest, 1);
706 goto add_pf_flow_err;
708 flows[MLX5_VPORT_PF] = flow;
711 if (mlx5_ecpf_vport_exists(esw->dev)) {
712 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
713 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
714 spec, &flow_act, &dest, 1);
717 goto add_ecpf_flow_err;
719 flows[mlx5_eswitch_ecpf_idx(esw)] = flow;
722 mlx5_esw_for_each_vf_vport_num(esw, i, mlx5_core_max_vfs(esw->dev)) {
723 esw_set_peer_miss_rule_source_port(esw,
724 peer_dev->priv.eswitch,
727 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
728 spec, &flow_act, &dest, 1);
731 goto add_vf_flow_err;
736 esw->fdb_table.offloads.peer_miss_rules = flows;
743 mlx5_esw_for_each_vf_vport_num_reverse(esw, i, nvports)
744 mlx5_del_flow_rules(flows[i]);
746 if (mlx5_ecpf_vport_exists(esw->dev))
747 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
749 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
750 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
752 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
759 static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
761 struct mlx5_flow_handle **flows;
764 flows = esw->fdb_table.offloads.peer_miss_rules;
766 mlx5_esw_for_each_vf_vport_num_reverse(esw, i,
767 mlx5_core_max_vfs(esw->dev))
768 mlx5_del_flow_rules(flows[i]);
770 if (mlx5_ecpf_vport_exists(esw->dev))
771 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
773 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
774 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
779 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
781 struct mlx5_flow_act flow_act = {0};
782 struct mlx5_flow_destination dest = {};
783 struct mlx5_flow_handle *flow_rule = NULL;
784 struct mlx5_flow_spec *spec;
791 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
797 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
798 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
800 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
801 outer_headers.dmac_47_16);
804 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
805 dest.vport.num = esw->manager_vport;
806 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
808 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
809 spec, &flow_act, &dest, 1);
810 if (IS_ERR(flow_rule)) {
811 err = PTR_ERR(flow_rule);
812 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
816 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
818 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
820 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
821 outer_headers.dmac_47_16);
823 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
824 spec, &flow_act, &dest, 1);
825 if (IS_ERR(flow_rule)) {
826 err = PTR_ERR(flow_rule);
827 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
828 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
832 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
839 #define MAX_PF_SQ 256
840 #define MAX_SQ_NVPORTS 32
842 static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
845 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
849 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
850 MLX5_SET(create_flow_group_in, flow_group_in,
851 match_criteria_enable,
852 MLX5_MATCH_MISC_PARAMETERS_2);
854 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
855 misc_parameters_2.metadata_reg_c_0);
857 MLX5_SET(create_flow_group_in, flow_group_in,
858 match_criteria_enable,
859 MLX5_MATCH_MISC_PARAMETERS);
861 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
862 misc_parameters.source_port);
866 static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw, int nvports)
868 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
869 struct mlx5_flow_table_attr ft_attr = {};
870 struct mlx5_core_dev *dev = esw->dev;
871 struct mlx5_flow_namespace *root_ns;
872 struct mlx5_flow_table *fdb = NULL;
873 u32 flags = 0, *flow_group_in;
874 int table_size, ix, err = 0;
875 struct mlx5_flow_group *g;
876 void *match_criteria;
879 esw_debug(esw->dev, "Create offloads FDB Tables\n");
881 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
885 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
887 esw_warn(dev, "Failed to get FDB flow namespace\n");
891 esw->fdb_table.offloads.ns = root_ns;
892 err = mlx5_flow_namespace_set_mode(root_ns,
893 esw->dev->priv.steering->mode);
895 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
899 table_size = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ +
900 MLX5_ESW_MISS_FLOWS + esw->total_vports;
902 /* create the slow path fdb with encap set, so further table instances
903 * can be created at run time while VFs are probed if the FW allows that.
905 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
906 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
907 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
909 ft_attr.flags = flags;
910 ft_attr.max_fte = table_size;
911 ft_attr.prio = FDB_SLOW_PATH;
913 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
916 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
919 esw->fdb_table.offloads.slow_fdb = fdb;
921 err = mlx5_esw_chains_create(esw);
923 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
927 /* create send-to-vport group */
928 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
929 MLX5_MATCH_MISC_PARAMETERS);
931 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
933 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
934 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
936 ix = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ;
937 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
938 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
940 g = mlx5_create_flow_group(fdb, flow_group_in);
943 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
946 esw->fdb_table.offloads.send_to_vport_grp = g;
948 /* create peer esw miss group */
949 memset(flow_group_in, 0, inlen);
951 esw_set_flow_group_source_port(esw, flow_group_in);
953 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
954 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
958 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
959 misc_parameters.source_eswitch_owner_vhca_id);
961 MLX5_SET(create_flow_group_in, flow_group_in,
962 source_eswitch_owner_vhca_id_valid, 1);
965 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
966 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
967 ix + esw->total_vports - 1);
968 ix += esw->total_vports;
970 g = mlx5_create_flow_group(fdb, flow_group_in);
973 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
976 esw->fdb_table.offloads.peer_miss_grp = g;
978 /* create miss group */
979 memset(flow_group_in, 0, inlen);
980 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
981 MLX5_MATCH_OUTER_HEADERS);
982 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
984 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
985 outer_headers.dmac_47_16);
988 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
989 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
990 ix + MLX5_ESW_MISS_FLOWS);
992 g = mlx5_create_flow_group(fdb, flow_group_in);
995 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
998 esw->fdb_table.offloads.miss_grp = g;
1000 err = esw_add_fdb_miss_rule(esw);
1004 esw->nvports = nvports;
1005 kvfree(flow_group_in);
1009 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1011 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1013 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1015 mlx5_esw_chains_destroy(esw);
1017 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1019 /* Holds true only as long as DMFS is the default */
1020 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
1022 kvfree(flow_group_in);
1026 static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
1028 if (!esw->fdb_table.offloads.slow_fdb)
1031 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
1032 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1033 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1034 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1035 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1036 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1038 mlx5_esw_chains_destroy(esw);
1039 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1040 /* Holds true only as long as DMFS is the default */
1041 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1042 MLX5_FLOW_STEERING_MODE_DMFS);
1045 static int esw_create_offloads_table(struct mlx5_eswitch *esw, int nvports)
1047 struct mlx5_flow_table_attr ft_attr = {};
1048 struct mlx5_core_dev *dev = esw->dev;
1049 struct mlx5_flow_table *ft_offloads;
1050 struct mlx5_flow_namespace *ns;
1053 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1055 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1059 ft_attr.max_fte = nvports + MLX5_ESW_MISS_FLOWS;
1061 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
1062 if (IS_ERR(ft_offloads)) {
1063 err = PTR_ERR(ft_offloads);
1064 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1068 esw->offloads.ft_offloads = ft_offloads;
1072 static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1074 struct mlx5_esw_offload *offloads = &esw->offloads;
1076 mlx5_destroy_flow_table(offloads->ft_offloads);
1079 static int esw_create_vport_rx_group(struct mlx5_eswitch *esw, int nvports)
1081 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1082 struct mlx5_flow_group *g;
1086 nvports = nvports + MLX5_ESW_MISS_FLOWS;
1087 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1091 /* create vport rx group */
1092 esw_set_flow_group_source_port(esw, flow_group_in);
1094 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1095 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1097 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1101 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1105 esw->offloads.vport_rx_group = g;
1107 kvfree(flow_group_in);
1111 static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1113 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1116 struct mlx5_flow_handle *
1117 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
1118 struct mlx5_flow_destination *dest)
1120 struct mlx5_flow_act flow_act = {0};
1121 struct mlx5_flow_handle *flow_rule;
1122 struct mlx5_flow_spec *spec;
1125 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1127 flow_rule = ERR_PTR(-ENOMEM);
1131 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1132 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1133 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1134 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
1136 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
1137 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
1139 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1141 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1142 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1144 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1145 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1147 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1150 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1151 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
1152 &flow_act, dest, 1);
1153 if (IS_ERR(flow_rule)) {
1154 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1163 static int esw_offloads_start(struct mlx5_eswitch *esw,
1164 struct netlink_ext_ack *extack)
1168 if (esw->mode != MLX5_ESWITCH_LEGACY &&
1169 !mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1170 NL_SET_ERR_MSG_MOD(extack,
1171 "Can't set offloads mode, SRIOV legacy not enabled");
1175 mlx5_eswitch_disable(esw, false);
1176 mlx5_eswitch_update_num_of_vfs(esw, esw->dev->priv.sriov.num_vfs);
1177 err = mlx5_eswitch_enable(esw, MLX5_ESWITCH_OFFLOADS);
1179 NL_SET_ERR_MSG_MOD(extack,
1180 "Failed setting eswitch to offloads");
1181 err1 = mlx5_eswitch_enable(esw, MLX5_ESWITCH_LEGACY);
1183 NL_SET_ERR_MSG_MOD(extack,
1184 "Failed setting eswitch back to legacy");
1187 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
1188 if (mlx5_eswitch_inline_mode_get(esw,
1189 &esw->offloads.inline_mode)) {
1190 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
1191 NL_SET_ERR_MSG_MOD(extack,
1192 "Inline mode is different between vports");
1198 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
1200 kfree(esw->offloads.vport_reps);
1203 int esw_offloads_init_reps(struct mlx5_eswitch *esw)
1205 int total_vports = esw->total_vports;
1206 struct mlx5_eswitch_rep *rep;
1210 esw->offloads.vport_reps = kcalloc(total_vports,
1211 sizeof(struct mlx5_eswitch_rep),
1213 if (!esw->offloads.vport_reps)
1216 mlx5_esw_for_all_reps(esw, vport_index, rep) {
1217 rep->vport = mlx5_eswitch_index_to_vport_num(esw, vport_index);
1218 rep->vport_index = vport_index;
1220 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
1221 atomic_set(&rep->rep_data[rep_type].state,
1228 static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
1229 struct mlx5_eswitch_rep *rep, u8 rep_type)
1231 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1232 REP_LOADED, REP_REGISTERED) == REP_LOADED)
1233 esw->offloads.rep_ops[rep_type]->unload(rep);
1236 static void __unload_reps_special_vport(struct mlx5_eswitch *esw, u8 rep_type)
1238 struct mlx5_eswitch_rep *rep;
1240 if (mlx5_ecpf_vport_exists(esw->dev)) {
1241 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1242 __esw_offloads_unload_rep(esw, rep, rep_type);
1245 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1246 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1247 __esw_offloads_unload_rep(esw, rep, rep_type);
1250 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1251 __esw_offloads_unload_rep(esw, rep, rep_type);
1254 static void __unload_reps_vf_vport(struct mlx5_eswitch *esw, int nvports,
1257 struct mlx5_eswitch_rep *rep;
1260 mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvports)
1261 __esw_offloads_unload_rep(esw, rep, rep_type);
1264 static void esw_offloads_unload_vf_reps(struct mlx5_eswitch *esw, int nvports)
1266 u8 rep_type = NUM_REP_TYPES;
1268 while (rep_type-- > 0)
1269 __unload_reps_vf_vport(esw, nvports, rep_type);
1272 static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
1274 __unload_reps_vf_vport(esw, esw->esw_funcs.num_vfs, rep_type);
1276 /* Special vports must be the last to unload. */
1277 __unload_reps_special_vport(esw, rep_type);
1280 static void esw_offloads_unload_all_reps(struct mlx5_eswitch *esw)
1282 u8 rep_type = NUM_REP_TYPES;
1284 while (rep_type-- > 0)
1285 __unload_reps_all_vport(esw, rep_type);
1288 static int __esw_offloads_load_rep(struct mlx5_eswitch *esw,
1289 struct mlx5_eswitch_rep *rep, u8 rep_type)
1293 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1294 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
1295 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
1297 atomic_set(&rep->rep_data[rep_type].state,
1304 static int __load_reps_special_vport(struct mlx5_eswitch *esw, u8 rep_type)
1306 struct mlx5_eswitch_rep *rep;
1309 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1310 err = __esw_offloads_load_rep(esw, rep, rep_type);
1314 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1315 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1316 err = __esw_offloads_load_rep(esw, rep, rep_type);
1321 if (mlx5_ecpf_vport_exists(esw->dev)) {
1322 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1323 err = __esw_offloads_load_rep(esw, rep, rep_type);
1331 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1332 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1333 __esw_offloads_unload_rep(esw, rep, rep_type);
1337 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1338 __esw_offloads_unload_rep(esw, rep, rep_type);
1342 static int __load_reps_vf_vport(struct mlx5_eswitch *esw, int nvports,
1345 struct mlx5_eswitch_rep *rep;
1348 mlx5_esw_for_each_vf_rep(esw, i, rep, nvports) {
1349 err = __esw_offloads_load_rep(esw, rep, rep_type);
1357 __unload_reps_vf_vport(esw, --i, rep_type);
1361 static int __load_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
1365 /* Special vports must be loaded first, uplink rep creates mdev resource. */
1366 err = __load_reps_special_vport(esw, rep_type);
1370 err = __load_reps_vf_vport(esw, esw->esw_funcs.num_vfs, rep_type);
1377 __unload_reps_special_vport(esw, rep_type);
1381 static int esw_offloads_load_vf_reps(struct mlx5_eswitch *esw, int nvports)
1386 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
1387 err = __load_reps_vf_vport(esw, nvports, rep_type);
1395 while (rep_type-- > 0)
1396 __unload_reps_vf_vport(esw, nvports, rep_type);
1400 static int esw_offloads_load_all_reps(struct mlx5_eswitch *esw)
1405 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
1406 err = __load_reps_all_vport(esw, rep_type);
1414 while (rep_type-- > 0)
1415 __unload_reps_all_vport(esw, rep_type);
1419 #define ESW_OFFLOADS_DEVCOM_PAIR (0)
1420 #define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
1422 static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
1423 struct mlx5_eswitch *peer_esw)
1427 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
1434 static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
1436 mlx5e_tc_clean_fdb_peer_flows(esw);
1437 esw_del_fdb_peer_miss_rules(esw);
1440 static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
1441 struct mlx5_eswitch *peer_esw,
1444 struct mlx5_flow_root_namespace *peer_ns;
1445 struct mlx5_flow_root_namespace *ns;
1448 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
1449 ns = esw->dev->priv.steering->fdb_root_ns;
1452 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
1456 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
1458 mlx5_flow_namespace_set_peer(ns, NULL);
1462 mlx5_flow_namespace_set_peer(ns, NULL);
1463 mlx5_flow_namespace_set_peer(peer_ns, NULL);
1469 static int mlx5_esw_offloads_devcom_event(int event,
1473 struct mlx5_eswitch *esw = my_data;
1474 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1475 struct mlx5_eswitch *peer_esw = event_data;
1479 case ESW_OFFLOADS_DEVCOM_PAIR:
1480 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
1481 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
1484 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
1487 err = mlx5_esw_offloads_pair(esw, peer_esw);
1491 err = mlx5_esw_offloads_pair(peer_esw, esw);
1495 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
1498 case ESW_OFFLOADS_DEVCOM_UNPAIR:
1499 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
1502 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
1503 mlx5_esw_offloads_unpair(peer_esw);
1504 mlx5_esw_offloads_unpair(esw);
1505 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
1512 mlx5_esw_offloads_unpair(esw);
1514 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
1516 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
1521 static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
1523 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1525 INIT_LIST_HEAD(&esw->offloads.peer_flows);
1526 mutex_init(&esw->offloads.peer_mutex);
1528 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1531 mlx5_devcom_register_component(devcom,
1532 MLX5_DEVCOM_ESW_OFFLOADS,
1533 mlx5_esw_offloads_devcom_event,
1536 mlx5_devcom_send_event(devcom,
1537 MLX5_DEVCOM_ESW_OFFLOADS,
1538 ESW_OFFLOADS_DEVCOM_PAIR, esw);
1541 static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
1543 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1545 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1548 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
1549 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
1551 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1554 static int esw_vport_ingress_prio_tag_config(struct mlx5_eswitch *esw,
1555 struct mlx5_vport *vport)
1557 struct mlx5_flow_act flow_act = {0};
1558 struct mlx5_flow_spec *spec;
1561 /* For prio tag mode, there is only 1 FTEs:
1562 * 1) Untagged packets - push prio tag VLAN and modify metadata if
1564 * Unmatched traffic is allowed by default
1566 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1570 /* Untagged packets - push prio tag VLAN, allow */
1571 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);
1572 MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 0);
1573 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1574 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
1575 MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1576 flow_act.vlan[0].ethtype = ETH_P_8021Q;
1577 flow_act.vlan[0].vid = 0;
1578 flow_act.vlan[0].prio = 0;
1580 if (vport->ingress.offloads.modify_metadata_rule) {
1581 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1582 flow_act.modify_hdr = vport->ingress.offloads.modify_metadata;
1585 vport->ingress.allow_rule =
1586 mlx5_add_flow_rules(vport->ingress.acl, spec,
1587 &flow_act, NULL, 0);
1588 if (IS_ERR(vport->ingress.allow_rule)) {
1589 err = PTR_ERR(vport->ingress.allow_rule);
1591 "vport[%d] configure ingress untagged allow rule, err(%d)\n",
1593 vport->ingress.allow_rule = NULL;
1600 static int esw_vport_add_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
1601 struct mlx5_vport *vport)
1603 u8 action[MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)] = {};
1604 static const struct mlx5_flow_spec spec = {};
1605 struct mlx5_flow_act flow_act = {};
1608 MLX5_SET(set_action_in, action, action_type, MLX5_ACTION_TYPE_SET);
1609 MLX5_SET(set_action_in, action, field, MLX5_ACTION_IN_FIELD_METADATA_REG_C_0);
1610 MLX5_SET(set_action_in, action, data,
1611 mlx5_eswitch_get_vport_metadata_for_match(esw, vport->vport));
1613 vport->ingress.offloads.modify_metadata =
1614 mlx5_modify_header_alloc(esw->dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS,
1616 if (IS_ERR(vport->ingress.offloads.modify_metadata)) {
1617 err = PTR_ERR(vport->ingress.offloads.modify_metadata);
1619 "failed to alloc modify header for vport %d ingress acl (%d)\n",
1624 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_MOD_HDR | MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1625 flow_act.modify_hdr = vport->ingress.offloads.modify_metadata;
1626 vport->ingress.offloads.modify_metadata_rule =
1627 mlx5_add_flow_rules(vport->ingress.acl,
1628 &spec, &flow_act, NULL, 0);
1629 if (IS_ERR(vport->ingress.offloads.modify_metadata_rule)) {
1630 err = PTR_ERR(vport->ingress.offloads.modify_metadata_rule);
1632 "failed to add setting metadata rule for vport %d ingress acl, err(%d)\n",
1634 mlx5_modify_header_dealloc(esw->dev, vport->ingress.offloads.modify_metadata);
1635 vport->ingress.offloads.modify_metadata_rule = NULL;
1640 static void esw_vport_del_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
1641 struct mlx5_vport *vport)
1643 if (vport->ingress.offloads.modify_metadata_rule) {
1644 mlx5_del_flow_rules(vport->ingress.offloads.modify_metadata_rule);
1645 mlx5_modify_header_dealloc(esw->dev, vport->ingress.offloads.modify_metadata);
1647 vport->ingress.offloads.modify_metadata_rule = NULL;
1651 static int esw_vport_create_ingress_acl_group(struct mlx5_eswitch *esw,
1652 struct mlx5_vport *vport)
1654 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1655 struct mlx5_flow_group *g;
1656 void *match_criteria;
1661 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1665 if (esw_check_ingress_prio_tag_enabled(esw, vport)) {
1666 /* This group is to hold FTE to match untagged packets when prio_tag
1669 memset(flow_group_in, 0, inlen);
1671 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1672 flow_group_in, match_criteria);
1673 MLX5_SET(create_flow_group_in, flow_group_in,
1674 match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1675 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.cvlan_tag);
1676 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, flow_index);
1677 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, flow_index);
1679 g = mlx5_create_flow_group(vport->ingress.acl, flow_group_in);
1682 esw_warn(esw->dev, "vport[%d] ingress create untagged flow group, err(%d)\n",
1686 vport->ingress.offloads.metadata_prio_tag_grp = g;
1690 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1691 /* This group holds an FTE with no matches for add metadata for
1692 * tagged packets, if prio-tag is enabled (as a fallthrough),
1693 * or all traffic in case prio-tag is disabled.
1695 memset(flow_group_in, 0, inlen);
1696 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, flow_index);
1697 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, flow_index);
1699 g = mlx5_create_flow_group(vport->ingress.acl, flow_group_in);
1702 esw_warn(esw->dev, "vport[%d] ingress create drop flow group, err(%d)\n",
1706 vport->ingress.offloads.metadata_allmatch_grp = g;
1709 kvfree(flow_group_in);
1713 if (!IS_ERR_OR_NULL(vport->ingress.offloads.metadata_prio_tag_grp)) {
1714 mlx5_destroy_flow_group(vport->ingress.offloads.metadata_prio_tag_grp);
1715 vport->ingress.offloads.metadata_prio_tag_grp = NULL;
1718 kvfree(flow_group_in);
1722 static void esw_vport_destroy_ingress_acl_group(struct mlx5_vport *vport)
1724 if (vport->ingress.offloads.metadata_allmatch_grp) {
1725 mlx5_destroy_flow_group(vport->ingress.offloads.metadata_allmatch_grp);
1726 vport->ingress.offloads.metadata_allmatch_grp = NULL;
1729 if (vport->ingress.offloads.metadata_prio_tag_grp) {
1730 mlx5_destroy_flow_group(vport->ingress.offloads.metadata_prio_tag_grp);
1731 vport->ingress.offloads.metadata_prio_tag_grp = NULL;
1735 static int esw_vport_ingress_config(struct mlx5_eswitch *esw,
1736 struct mlx5_vport *vport)
1741 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
1742 !esw_check_ingress_prio_tag_enabled(esw, vport))
1745 esw_vport_cleanup_ingress_rules(esw, vport);
1747 if (mlx5_eswitch_vport_match_metadata_enabled(esw))
1749 if (esw_check_ingress_prio_tag_enabled(esw, vport))
1752 err = esw_vport_create_ingress_acl_table(esw, vport, num_ftes);
1755 "failed to enable ingress acl (%d) on vport[%d]\n",
1760 err = esw_vport_create_ingress_acl_group(esw, vport);
1765 "vport[%d] configure ingress rules\n", vport->vport);
1767 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1768 err = esw_vport_add_ingress_acl_modify_metadata(esw, vport);
1773 if (esw_check_ingress_prio_tag_enabled(esw, vport)) {
1774 err = esw_vport_ingress_prio_tag_config(esw, vport);
1781 esw_vport_del_ingress_acl_modify_metadata(esw, vport);
1783 esw_vport_destroy_ingress_acl_group(vport);
1785 esw_vport_destroy_ingress_acl_table(vport);
1789 static int esw_vport_egress_config(struct mlx5_eswitch *esw,
1790 struct mlx5_vport *vport)
1794 if (!MLX5_CAP_GEN(esw->dev, prio_tag_required))
1797 esw_vport_cleanup_egress_rules(esw, vport);
1799 err = esw_vport_enable_egress_acl(esw, vport);
1803 /* For prio tag mode, there is only 1 FTEs:
1804 * 1) prio tag packets - pop the prio tag VLAN, allow
1805 * Unmatched traffic is allowed by default
1808 "vport[%d] configure prio tag egress rules\n", vport->vport);
1810 /* prio tag vlan rule - pop it so VF receives untagged packets */
1811 err = mlx5_esw_create_vport_egress_acl_vlan(esw, vport, 0,
1812 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP |
1813 MLX5_FLOW_CONTEXT_ACTION_ALLOW);
1815 esw_vport_disable_egress_acl(esw, vport);
1821 esw_check_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
1823 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
1826 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1827 MLX5_FDB_TO_VPORT_REG_C_0))
1830 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
1833 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
1834 mlx5_ecpf_vport_exists(esw->dev))
1841 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
1842 struct mlx5_vport *vport)
1846 err = esw_vport_ingress_config(esw, vport);
1850 if (mlx5_eswitch_is_vf_vport(esw, vport->vport)) {
1851 err = esw_vport_egress_config(esw, vport);
1853 esw_vport_cleanup_ingress_rules(esw, vport);
1854 esw_vport_del_ingress_acl_modify_metadata(esw, vport);
1855 esw_vport_destroy_ingress_acl_group(vport);
1856 esw_vport_destroy_ingress_acl_table(vport);
1863 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
1864 struct mlx5_vport *vport)
1866 esw_vport_disable_egress_acl(esw, vport);
1867 esw_vport_cleanup_ingress_rules(esw, vport);
1868 esw_vport_del_ingress_acl_modify_metadata(esw, vport);
1869 esw_vport_destroy_ingress_acl_group(vport);
1870 esw_vport_destroy_ingress_acl_table(vport);
1873 static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
1875 struct mlx5_vport *vport;
1878 if (esw_check_vport_match_metadata_supported(esw))
1879 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
1881 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
1882 err = esw_vport_create_offloads_acl_tables(esw, vport);
1884 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
1888 static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
1890 struct mlx5_vport *vport;
1892 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
1893 esw_vport_destroy_offloads_acl_tables(esw, vport);
1894 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
1897 static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
1899 int num_vfs = esw->esw_funcs.num_vfs;
1903 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
1904 total_vports = esw->total_vports;
1906 total_vports = num_vfs + MLX5_SPECIAL_VPORTS(esw->dev);
1908 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
1910 err = esw_create_uplink_offloads_acl_tables(esw);
1914 err = esw_create_offloads_fdb_tables(esw, total_vports);
1916 goto create_fdb_err;
1918 err = esw_create_offloads_table(esw, total_vports);
1922 err = esw_create_vport_rx_group(esw, total_vports);
1929 esw_destroy_offloads_table(esw);
1932 esw_destroy_offloads_fdb_tables(esw);
1935 esw_destroy_uplink_offloads_acl_tables(esw);
1940 static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
1942 esw_destroy_vport_rx_group(esw);
1943 esw_destroy_offloads_table(esw);
1944 esw_destroy_offloads_fdb_tables(esw);
1945 esw_destroy_uplink_offloads_acl_tables(esw);
1949 esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
1951 bool host_pf_disabled;
1954 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
1955 host_params_context.host_num_of_vfs);
1956 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
1957 host_params_context.host_pf_disabled);
1959 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
1962 /* Number of VFs can only change from "0 to x" or "x to 0". */
1963 if (esw->esw_funcs.num_vfs > 0) {
1964 esw_offloads_unload_vf_reps(esw, esw->esw_funcs.num_vfs);
1968 err = esw_offloads_load_vf_reps(esw, new_num_vfs);
1972 esw->esw_funcs.num_vfs = new_num_vfs;
1975 static void esw_functions_changed_event_handler(struct work_struct *work)
1977 struct mlx5_host_work *host_work;
1978 struct mlx5_eswitch *esw;
1981 host_work = container_of(work, struct mlx5_host_work, work);
1982 esw = host_work->esw;
1984 out = mlx5_esw_query_functions(esw->dev);
1988 esw_vfs_changed_event_handler(esw, out);
1994 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
1996 struct mlx5_esw_functions *esw_funcs;
1997 struct mlx5_host_work *host_work;
1998 struct mlx5_eswitch *esw;
2000 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2004 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2005 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
2007 host_work->esw = esw;
2009 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
2010 queue_work(esw->work_queue, &host_work->work);
2015 int esw_offloads_enable(struct mlx5_eswitch *esw)
2017 struct mlx5_vport *vport;
2020 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2021 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2022 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2024 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2026 mlx5_rdma_enable_roce(esw->dev);
2027 err = esw_offloads_steering_init(esw);
2029 goto err_steering_init;
2031 err = esw_set_passing_vport_metadata(esw, true);
2033 goto err_vport_metadata;
2035 /* Representor will control the vport link state */
2036 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
2037 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2039 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
2043 err = esw_offloads_load_all_reps(esw);
2047 esw_offloads_devcom_init(esw);
2048 mutex_init(&esw->offloads.termtbl_mutex);
2053 mlx5_eswitch_disable_pf_vf_vports(esw);
2055 esw_set_passing_vport_metadata(esw, false);
2057 esw_offloads_steering_cleanup(esw);
2059 mlx5_rdma_disable_roce(esw->dev);
2063 static int esw_offloads_stop(struct mlx5_eswitch *esw,
2064 struct netlink_ext_ack *extack)
2068 mlx5_eswitch_disable(esw, false);
2069 err = mlx5_eswitch_enable(esw, MLX5_ESWITCH_LEGACY);
2071 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
2072 err1 = mlx5_eswitch_enable(esw, MLX5_ESWITCH_OFFLOADS);
2074 NL_SET_ERR_MSG_MOD(extack,
2075 "Failed setting eswitch back to offloads");
2082 void esw_offloads_disable(struct mlx5_eswitch *esw)
2084 esw_offloads_devcom_cleanup(esw);
2085 esw_offloads_unload_all_reps(esw);
2086 mlx5_eswitch_disable_pf_vf_vports(esw);
2087 esw_set_passing_vport_metadata(esw, false);
2088 esw_offloads_steering_cleanup(esw);
2089 mlx5_rdma_disable_roce(esw->dev);
2090 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2093 static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
2096 case DEVLINK_ESWITCH_MODE_LEGACY:
2097 *mlx5_mode = MLX5_ESWITCH_LEGACY;
2099 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
2100 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
2109 static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2111 switch (mlx5_mode) {
2112 case MLX5_ESWITCH_LEGACY:
2113 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2115 case MLX5_ESWITCH_OFFLOADS:
2116 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2125 static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2128 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2129 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2131 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2132 *mlx5_mode = MLX5_INLINE_MODE_L2;
2134 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2135 *mlx5_mode = MLX5_INLINE_MODE_IP;
2137 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2138 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2147 static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2149 switch (mlx5_mode) {
2150 case MLX5_INLINE_MODE_NONE:
2151 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2153 case MLX5_INLINE_MODE_L2:
2154 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2156 case MLX5_INLINE_MODE_IP:
2157 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2159 case MLX5_INLINE_MODE_TCP_UDP:
2160 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2169 static int mlx5_devlink_eswitch_check(struct devlink *devlink)
2171 struct mlx5_core_dev *dev = devlink_priv(devlink);
2173 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2176 if(!MLX5_ESWITCH_MANAGER(dev))
2179 if (dev->priv.eswitch->mode == MLX5_ESWITCH_NONE &&
2180 !mlx5_core_is_ecpf_esw_manager(dev))
2186 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2187 struct netlink_ext_ack *extack)
2189 struct mlx5_core_dev *dev = devlink_priv(devlink);
2190 u16 cur_mlx5_mode, mlx5_mode = 0;
2193 err = mlx5_devlink_eswitch_check(devlink);
2197 cur_mlx5_mode = dev->priv.eswitch->mode;
2199 if (esw_mode_from_devlink(mode, &mlx5_mode))
2202 if (cur_mlx5_mode == mlx5_mode)
2205 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
2206 return esw_offloads_start(dev->priv.eswitch, extack);
2207 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
2208 return esw_offloads_stop(dev->priv.eswitch, extack);
2213 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
2215 struct mlx5_core_dev *dev = devlink_priv(devlink);
2218 err = mlx5_devlink_eswitch_check(devlink);
2222 return esw_mode_to_devlink(dev->priv.eswitch->mode, mode);
2225 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
2226 struct netlink_ext_ack *extack)
2228 struct mlx5_core_dev *dev = devlink_priv(devlink);
2229 struct mlx5_eswitch *esw = dev->priv.eswitch;
2230 int err, vport, num_vport;
2233 err = mlx5_devlink_eswitch_check(devlink);
2237 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2238 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2239 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
2242 case MLX5_CAP_INLINE_MODE_L2:
2243 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
2245 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2249 if (atomic64_read(&esw->offloads.num_flows) > 0) {
2250 NL_SET_ERR_MSG_MOD(extack,
2251 "Can't set inline mode when flows are configured");
2255 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
2259 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
2260 err = mlx5_modify_nic_vport_min_inline(dev, vport, mlx5_mode);
2262 NL_SET_ERR_MSG_MOD(extack,
2263 "Failed to set min inline on vport");
2264 goto revert_inline_mode;
2268 esw->offloads.inline_mode = mlx5_mode;
2272 num_vport = --vport;
2273 mlx5_esw_for_each_host_func_vport_reverse(esw, vport, num_vport)
2274 mlx5_modify_nic_vport_min_inline(dev,
2276 esw->offloads.inline_mode);
2281 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
2283 struct mlx5_core_dev *dev = devlink_priv(devlink);
2284 struct mlx5_eswitch *esw = dev->priv.eswitch;
2287 err = mlx5_devlink_eswitch_check(devlink);
2291 return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
2294 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
2296 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2297 struct mlx5_core_dev *dev = esw->dev;
2300 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2303 if (esw->mode == MLX5_ESWITCH_NONE)
2306 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2307 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2308 mlx5_mode = MLX5_INLINE_MODE_NONE;
2310 case MLX5_CAP_INLINE_MODE_L2:
2311 mlx5_mode = MLX5_INLINE_MODE_L2;
2313 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2318 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
2319 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
2320 mlx5_query_nic_vport_min_inline(dev, vport, &mlx5_mode);
2321 if (prev_mlx5_mode != mlx5_mode)
2323 prev_mlx5_mode = mlx5_mode;
2331 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
2332 enum devlink_eswitch_encap_mode encap,
2333 struct netlink_ext_ack *extack)
2335 struct mlx5_core_dev *dev = devlink_priv(devlink);
2336 struct mlx5_eswitch *esw = dev->priv.eswitch;
2339 err = mlx5_devlink_eswitch_check(devlink);
2343 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
2344 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
2345 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap)))
2348 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC)
2351 if (esw->mode == MLX5_ESWITCH_LEGACY) {
2352 esw->offloads.encap = encap;
2356 if (esw->offloads.encap == encap)
2359 if (atomic64_read(&esw->offloads.num_flows) > 0) {
2360 NL_SET_ERR_MSG_MOD(extack,
2361 "Can't set encapsulation when flows are configured");
2365 esw_destroy_offloads_fdb_tables(esw);
2367 esw->offloads.encap = encap;
2369 err = esw_create_offloads_fdb_tables(esw, esw->nvports);
2372 NL_SET_ERR_MSG_MOD(extack,
2373 "Failed re-creating fast FDB table");
2374 esw->offloads.encap = !encap;
2375 (void)esw_create_offloads_fdb_tables(esw, esw->nvports);
2381 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
2382 enum devlink_eswitch_encap_mode *encap)
2384 struct mlx5_core_dev *dev = devlink_priv(devlink);
2385 struct mlx5_eswitch *esw = dev->priv.eswitch;
2388 err = mlx5_devlink_eswitch_check(devlink);
2392 *encap = esw->offloads.encap;
2396 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
2397 const struct mlx5_eswitch_rep_ops *ops,
2400 struct mlx5_eswitch_rep_data *rep_data;
2401 struct mlx5_eswitch_rep *rep;
2404 esw->offloads.rep_ops[rep_type] = ops;
2405 mlx5_esw_for_all_reps(esw, i, rep) {
2406 rep_data = &rep->rep_data[rep_type];
2407 atomic_set(&rep_data->state, REP_REGISTERED);
2410 EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
2412 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
2414 struct mlx5_eswitch_rep *rep;
2417 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
2418 __unload_reps_all_vport(esw, rep_type);
2420 mlx5_esw_for_all_reps(esw, i, rep)
2421 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
2423 EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
2425 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
2427 struct mlx5_eswitch_rep *rep;
2429 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
2430 return rep->rep_data[rep_type].priv;
2433 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
2437 struct mlx5_eswitch_rep *rep;
2439 rep = mlx5_eswitch_get_rep(esw, vport);
2441 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2442 esw->offloads.rep_ops[rep_type]->get_proto_dev)
2443 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
2446 EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
2448 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
2450 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
2452 EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
2454 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
2457 return mlx5_eswitch_get_rep(esw, vport);
2459 EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
2461 bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num)
2463 return vport_num >= MLX5_VPORT_FIRST_VF &&
2464 vport_num <= esw->dev->priv.sriov.max_vfs;
2467 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
2469 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
2471 EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
2473 u32 mlx5_eswitch_get_vport_metadata_for_match(const struct mlx5_eswitch *esw,
2476 return ((MLX5_CAP_GEN(esw->dev, vhca_id) & 0xffff) << 16) | vport_num;
2478 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);