2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_ESWITCH_H__
34 #define __MLX5_ESWITCH_H__
36 #include <linux/if_ether.h>
37 #include <linux/if_link.h>
38 #include <net/devlink.h>
39 #include <linux/mlx5/device.h>
40 #include <linux/mlx5/eswitch.h>
41 #include <linux/mlx5/vport.h>
42 #include <linux/mlx5/fs.h>
45 #ifdef CONFIG_MLX5_ESWITCH
47 #define MLX5_MAX_UC_PER_VPORT(dev) \
48 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
50 #define MLX5_MAX_MC_PER_VPORT(dev) \
51 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
53 #define MLX5_MIN_BW_SHARE 1
55 #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
56 min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
58 #define mlx5_esw_has_fwd_fdb(dev) \
59 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
61 #define FDB_MAX_CHAIN 3
62 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
63 #define FDB_MAX_PRIO 16
65 struct vport_ingress {
66 struct mlx5_flow_table *acl;
67 struct mlx5_flow_group *allow_untagged_spoofchk_grp;
68 struct mlx5_flow_group *allow_spoofchk_only_grp;
69 struct mlx5_flow_group *allow_untagged_only_grp;
70 struct mlx5_flow_group *drop_grp;
71 int modify_metadata_id;
72 struct mlx5_flow_handle *modify_metadata_rule;
73 struct mlx5_flow_handle *allow_rule;
74 struct mlx5_flow_handle *drop_rule;
75 struct mlx5_fc *drop_counter;
79 struct mlx5_flow_table *acl;
80 struct mlx5_flow_group *allowed_vlans_grp;
81 struct mlx5_flow_group *drop_grp;
82 struct mlx5_flow_handle *allowed_vlan;
83 struct mlx5_flow_handle *drop_rule;
84 struct mlx5_fc *drop_counter;
87 struct mlx5_vport_drop_stats {
92 struct mlx5_vport_info {
105 struct mlx5_core_dev *dev;
107 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
108 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
109 struct mlx5_flow_handle *promisc_rule;
110 struct mlx5_flow_handle *allmulti_rule;
111 struct work_struct vport_change_handler;
113 struct vport_ingress ingress;
114 struct vport_egress egress;
116 struct mlx5_vport_info info;
128 enum offloads_fdb_flags {
129 ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
132 extern const unsigned int ESW_POOLS[4];
134 #define PRIO_LEVELS 2
135 struct mlx5_eswitch_fdb {
138 struct mlx5_flow_table *fdb;
139 struct mlx5_flow_group *addr_grp;
140 struct mlx5_flow_group *allmulti_grp;
141 struct mlx5_flow_group *promisc_grp;
142 struct mlx5_flow_table *vepa_fdb;
143 struct mlx5_flow_handle *vepa_uplink_rule;
144 struct mlx5_flow_handle *vepa_star_rule;
147 struct offloads_fdb {
148 struct mlx5_flow_table *slow_fdb;
149 struct mlx5_flow_group *send_to_vport_grp;
150 struct mlx5_flow_group *peer_miss_grp;
151 struct mlx5_flow_handle **peer_miss_rules;
152 struct mlx5_flow_group *miss_grp;
153 struct mlx5_flow_handle *miss_rule_uni;
154 struct mlx5_flow_handle *miss_rule_multi;
155 int vlan_push_pop_refcount;
158 struct mlx5_flow_table *fdb;
160 } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS];
161 /* Protects fdb_prio table */
162 struct mutex fdb_prio_lock;
164 int fdb_left[ARRAY_SIZE(ESW_POOLS)];
170 struct mlx5_esw_offload {
171 struct mlx5_flow_table *ft_offloads;
172 struct mlx5_flow_group *vport_rx_group;
173 struct mlx5_eswitch_rep *vport_reps;
174 struct list_head peer_flows;
175 struct mutex peer_mutex;
176 DECLARE_HASHTABLE(encap_tbl, 8);
177 DECLARE_HASHTABLE(mod_hdr_tbl, 8);
178 const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES];
181 enum devlink_eswitch_encap_mode encap;
184 /* E-Switch MC FDB table hash node */
185 struct esw_mc_addr { /* SRIOV only */
186 struct l2addr_node node;
187 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
191 struct mlx5_host_work {
192 struct work_struct work;
193 struct mlx5_eswitch *esw;
196 struct mlx5_esw_functions {
202 MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0),
205 struct mlx5_eswitch {
206 struct mlx5_core_dev *dev;
208 struct mlx5_eswitch_fdb fdb_table;
209 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
210 struct workqueue_struct *work_queue;
211 struct mlx5_vport *vports;
215 /* Synchronize between vport change events
216 * and async SRIOV admin state changes
218 struct mutex state_lock;
219 struct esw_mc_addr mc_promisc;
226 struct mlx5_esw_offload offloads;
230 u16 first_host_vport;
231 struct mlx5_esw_functions esw_funcs;
234 void esw_offloads_cleanup(struct mlx5_eswitch *esw);
235 int esw_offloads_init(struct mlx5_eswitch *esw);
236 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
237 int esw_offloads_init_reps(struct mlx5_eswitch *esw);
238 void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
239 struct mlx5_vport *vport);
240 int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
241 struct mlx5_vport *vport);
242 void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
243 struct mlx5_vport *vport);
244 int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
245 struct mlx5_vport *vport);
246 void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
247 struct mlx5_vport *vport);
248 void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
249 struct mlx5_vport *vport);
250 void esw_vport_del_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
251 struct mlx5_vport *vport);
254 int mlx5_eswitch_init(struct mlx5_core_dev *dev);
255 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
256 int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode);
257 void mlx5_eswitch_disable(struct mlx5_eswitch *esw);
258 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
259 u16 vport, u8 mac[ETH_ALEN]);
260 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
261 u16 vport, int link_state);
262 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
263 u16 vport, u16 vlan, u8 qos);
264 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
265 u16 vport, bool spoofchk);
266 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
267 u16 vport_num, bool setting);
268 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport,
269 u32 max_rate, u32 min_rate);
270 int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
271 int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting);
272 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
273 u16 vport, struct ifla_vf_info *ivi);
274 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
276 struct ifla_vf_stats *vf_stats);
277 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
279 int mlx5_eswitch_modify_esw_vport_context(struct mlx5_eswitch *esw, u16 vport,
280 void *in, int inlen);
281 int mlx5_eswitch_query_esw_vport_context(struct mlx5_eswitch *esw, u16 vport,
282 void *out, int outlen);
284 struct mlx5_flow_spec;
285 struct mlx5_esw_flow_attr;
287 struct mlx5_flow_handle *
288 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
289 struct mlx5_flow_spec *spec,
290 struct mlx5_esw_flow_attr *attr);
291 struct mlx5_flow_handle *
292 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
293 struct mlx5_flow_spec *spec,
294 struct mlx5_esw_flow_attr *attr);
296 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
297 struct mlx5_flow_handle *rule,
298 struct mlx5_esw_flow_attr *attr);
300 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
301 struct mlx5_flow_handle *rule,
302 struct mlx5_esw_flow_attr *attr);
305 mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw);
308 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw);
311 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw);
313 struct mlx5_flow_handle *
314 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
315 struct mlx5_flow_destination *dest);
318 SET_VLAN_STRIP = BIT(0),
319 SET_VLAN_INSERT = BIT(1)
322 enum mlx5_flow_match_level {
323 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
324 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
325 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
326 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
329 /* current maximum for flow based vport multicasting */
330 #define MLX5_MAX_FLOW_FWD_VPORTS 2
333 MLX5_ESW_DEST_ENCAP = BIT(0),
334 MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
337 struct mlx5_esw_flow_attr {
338 struct mlx5_eswitch_rep *in_rep;
339 struct mlx5_core_dev *in_mdev;
340 struct mlx5_core_dev *counter_dev;
346 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
347 u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
348 u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
353 struct mlx5_eswitch_rep *rep;
354 struct mlx5_core_dev *mdev;
356 } dests[MLX5_MAX_FLOW_FWD_VPORTS];
359 u8 tunnel_match_level;
360 struct mlx5_fc *counter;
364 struct mlx5e_tc_flow_parse_attr *parse_attr;
367 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
368 struct netlink_ext_ack *extack);
369 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
370 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
371 struct netlink_ext_ack *extack);
372 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
373 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode);
374 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
375 enum devlink_eswitch_encap_mode encap,
376 struct netlink_ext_ack *extack);
377 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
378 enum devlink_eswitch_encap_mode *encap);
379 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
381 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
382 struct mlx5_esw_flow_attr *attr);
383 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
384 struct mlx5_esw_flow_attr *attr);
385 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
386 u16 vport, u16 vlan, u8 qos, u8 set_flags);
388 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
391 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
392 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
397 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
398 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
401 bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
402 struct mlx5_core_dev *dev1);
403 bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
404 struct mlx5_core_dev *dev1);
406 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev);
408 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
410 #define esw_info(__dev, format, ...) \
411 dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
413 #define esw_warn(__dev, format, ...) \
414 dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
416 #define esw_debug(dev, format, ...) \
417 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
419 /* The returned number is valid only when the dev is eswitch manager. */
420 static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
422 return mlx5_core_is_ecpf_esw_manager(dev) ?
423 MLX5_VPORT_ECPF : MLX5_VPORT_PF;
426 static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev)
428 return mlx5_core_is_ecpf_esw_manager(dev) ?
429 MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF;
432 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev)
434 /* Ideally device should have the functions changed supported
435 * capability regardless of it being ECPF or PF wherever such
436 * event should be processed such as on eswitch manager device.
437 * However, some ECPF based device might not have this capability
438 * set. Hence OR for ECPF check to cover such device.
440 return MLX5_CAP_ESW(dev, esw_functions_changed) ||
441 mlx5_core_is_ecpf_esw_manager(dev);
444 static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
446 /* Uplink always locate at the last element of the array.*/
447 return esw->total_vports - 1;
450 static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
452 return esw->total_vports - 2;
455 static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
458 if (vport_num == MLX5_VPORT_ECPF) {
459 if (!mlx5_ecpf_vport_exists(esw->dev))
460 esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
461 return mlx5_eswitch_ecpf_idx(esw);
464 if (vport_num == MLX5_VPORT_UPLINK)
465 return mlx5_eswitch_uplink_idx(esw);
470 static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
473 if (index == mlx5_eswitch_ecpf_idx(esw) &&
474 mlx5_ecpf_vport_exists(esw->dev))
475 return MLX5_VPORT_ECPF;
477 if (index == mlx5_eswitch_uplink_idx(esw))
478 return MLX5_VPORT_UPLINK;
483 /* TODO: This mlx5e_tc function shouldn't be called by eswitch */
484 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);
486 /* The vport getter/iterator are only valid after esw->total_vports
487 * and vport->vport are initialized in mlx5_eswitch_init.
489 #define mlx5_esw_for_all_vports(esw, i, vport) \
490 for ((i) = MLX5_VPORT_PF; \
491 (vport) = &(esw)->vports[i], \
492 (i) < (esw)->total_vports; (i)++)
494 #define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \
495 for ((i) = MLX5_VPORT_FIRST_VF; \
496 (vport) = &(esw)->vports[(i)], \
497 (i) <= (nvfs); (i)++)
499 #define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \
501 (vport) = &(esw)->vports[(i)], \
502 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
504 /* The rep getter/iterator are only valid after esw->total_vports
505 * and vport->vport are initialized in mlx5_eswitch_init.
507 #define mlx5_esw_for_all_reps(esw, i, rep) \
508 for ((i) = MLX5_VPORT_PF; \
509 (rep) = &(esw)->offloads.vport_reps[i], \
510 (i) < (esw)->total_vports; (i)++)
512 #define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \
513 for ((i) = MLX5_VPORT_FIRST_VF; \
514 (rep) = &(esw)->offloads.vport_reps[i], \
515 (i) <= (nvfs); (i)++)
517 #define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \
519 (rep) = &(esw)->offloads.vport_reps[i], \
520 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
522 #define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \
523 for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++)
525 #define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \
526 for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--)
528 /* Includes host PF (vport 0) if it's not esw manager. */
529 #define mlx5_esw_for_each_host_func_rep(esw, i, rep, nvfs) \
530 for ((i) = (esw)->first_host_vport; \
531 (rep) = &(esw)->offloads.vport_reps[i], \
532 (i) <= (nvfs); (i)++)
534 #define mlx5_esw_for_each_host_func_rep_reverse(esw, i, rep, nvfs) \
536 (rep) = &(esw)->offloads.vport_reps[i], \
537 (i) >= (esw)->first_host_vport; (i)--)
539 #define mlx5_esw_for_each_host_func_vport(esw, vport, nvfs) \
540 for ((vport) = (esw)->first_host_vport; \
541 (vport) <= (nvfs); (vport)++)
543 #define mlx5_esw_for_each_host_func_vport_reverse(esw, vport, nvfs) \
544 for ((vport) = (nvfs); \
545 (vport) >= (esw)->first_host_vport; (vport)--)
547 struct mlx5_vport *__must_check
548 mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num);
550 bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num);
552 void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs);
553 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data);
555 #else /* CONFIG_MLX5_ESWITCH */
556 /* eswitch API stubs */
557 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
558 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
559 static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode) { return 0; }
560 static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {}
561 static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; }
562 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; }
563 static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev)
565 return ERR_PTR(-EOPNOTSUPP);
568 static inline void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs) {}
570 #define FDB_MAX_CHAIN 1
571 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
572 #define FDB_MAX_PRIO 1
574 #endif /* CONFIG_MLX5_ESWITCH */
576 #endif /* __MLX5_ESWITCH_H__ */