2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_ESWITCH_H__
34 #define __MLX5_ESWITCH_H__
36 #include <linux/if_ether.h>
37 #include <linux/if_link.h>
38 #include <linux/atomic.h>
39 #include <net/devlink.h>
40 #include <linux/mlx5/device.h>
41 #include <linux/mlx5/eswitch.h>
42 #include <linux/mlx5/vport.h>
43 #include <linux/mlx5/fs.h>
47 #define FDB_TC_MAX_CHAIN 3
48 #define FDB_FT_CHAIN (FDB_TC_MAX_CHAIN + 1)
49 #define FDB_TC_SLOW_PATH_CHAIN (FDB_FT_CHAIN + 1)
51 /* The index of the last real chain (FT) + 1 as chain zero is valid as well */
52 #define FDB_NUM_CHAINS (FDB_FT_CHAIN + 1)
54 #define FDB_TC_MAX_PRIO 16
55 #define FDB_TC_LEVELS_PER_PRIO 2
57 #ifdef CONFIG_MLX5_ESWITCH
59 #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15
61 #define MLX5_MAX_UC_PER_VPORT(dev) \
62 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
64 #define MLX5_MAX_MC_PER_VPORT(dev) \
65 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
67 #define MLX5_MIN_BW_SHARE 1
69 #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
70 min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
72 #define mlx5_esw_has_fwd_fdb(dev) \
73 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
75 struct vport_ingress {
76 struct mlx5_flow_table *acl;
77 struct mlx5_flow_handle *allow_rule;
79 struct mlx5_flow_group *allow_spoofchk_only_grp;
80 struct mlx5_flow_group *allow_untagged_spoofchk_grp;
81 struct mlx5_flow_group *allow_untagged_only_grp;
82 struct mlx5_flow_group *drop_grp;
83 struct mlx5_flow_handle *drop_rule;
84 struct mlx5_fc *drop_counter;
87 /* Optional group to add an FTE to do internal priority
88 * tagging on ingress packets.
90 struct mlx5_flow_group *metadata_prio_tag_grp;
91 /* Group to add default match-all FTE entry to tag ingress
92 * packet with metadata.
94 struct mlx5_flow_group *metadata_allmatch_grp;
95 struct mlx5_modify_hdr *modify_metadata;
96 struct mlx5_flow_handle *modify_metadata_rule;
100 struct vport_egress {
101 struct mlx5_flow_table *acl;
102 struct mlx5_flow_group *allowed_vlans_grp;
103 struct mlx5_flow_group *drop_grp;
104 struct mlx5_flow_handle *allowed_vlan;
106 struct mlx5_flow_handle *drop_rule;
107 struct mlx5_fc *drop_counter;
111 struct mlx5_vport_drop_stats {
116 struct mlx5_vport_info {
128 /* Vport context events */
129 enum mlx5_eswitch_vport_event {
130 MLX5_VPORT_UC_ADDR_CHANGE = BIT(0),
131 MLX5_VPORT_MC_ADDR_CHANGE = BIT(1),
132 MLX5_VPORT_PROMISC_CHANGE = BIT(3),
136 struct mlx5_core_dev *dev;
138 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
139 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
140 struct mlx5_flow_handle *promisc_rule;
141 struct mlx5_flow_handle *allmulti_rule;
142 struct work_struct vport_change_handler;
144 struct vport_ingress ingress;
145 struct vport_egress egress;
147 struct mlx5_vport_info info;
156 enum mlx5_eswitch_vport_event enabled_events;
159 enum offloads_fdb_flags {
160 ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
163 struct mlx5_esw_chains_priv;
165 struct mlx5_eswitch_fdb {
168 struct mlx5_flow_table *fdb;
169 struct mlx5_flow_group *addr_grp;
170 struct mlx5_flow_group *allmulti_grp;
171 struct mlx5_flow_group *promisc_grp;
172 struct mlx5_flow_table *vepa_fdb;
173 struct mlx5_flow_handle *vepa_uplink_rule;
174 struct mlx5_flow_handle *vepa_star_rule;
177 struct offloads_fdb {
178 struct mlx5_flow_namespace *ns;
179 struct mlx5_flow_table *slow_fdb;
180 struct mlx5_flow_group *send_to_vport_grp;
181 struct mlx5_flow_group *peer_miss_grp;
182 struct mlx5_flow_handle **peer_miss_rules;
183 struct mlx5_flow_group *miss_grp;
184 struct mlx5_flow_handle *miss_rule_uni;
185 struct mlx5_flow_handle *miss_rule_multi;
186 int vlan_push_pop_refcount;
188 struct mlx5_esw_chains_priv *esw_chains_priv;
190 DECLARE_HASHTABLE(table, 8);
191 /* Protects vports.table */
200 struct mlx5_esw_offload {
201 struct mlx5_flow_table *ft_offloads_restore;
202 struct mlx5_flow_group *restore_group;
203 struct mlx5_modify_hdr *restore_copy_hdr_id;
205 struct mlx5_flow_table *ft_offloads;
206 struct mlx5_flow_group *vport_rx_group;
207 struct mlx5_eswitch_rep *vport_reps;
208 struct list_head peer_flows;
209 struct mutex peer_mutex;
210 struct mutex encap_tbl_lock; /* protects encap_tbl */
211 DECLARE_HASHTABLE(encap_tbl, 8);
212 struct mod_hdr_tbl mod_hdr;
213 DECLARE_HASHTABLE(termtbl_tbl, 8);
214 struct mutex termtbl_mutex; /* protects termtbl hash */
215 const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES];
217 atomic64_t num_flows;
218 enum devlink_eswitch_encap_mode encap;
221 /* E-Switch MC FDB table hash node */
222 struct esw_mc_addr { /* SRIOV only */
223 struct l2addr_node node;
224 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
228 struct mlx5_host_work {
229 struct work_struct work;
230 struct mlx5_eswitch *esw;
233 struct mlx5_esw_functions {
239 MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0),
240 MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED = BIT(1),
243 struct mlx5_eswitch {
244 struct mlx5_core_dev *dev;
246 struct mlx5_eswitch_fdb fdb_table;
247 /* legacy data structures */
248 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
249 struct esw_mc_addr mc_promisc;
251 struct workqueue_struct *work_queue;
252 struct mlx5_vport *vports;
256 /* Synchronize between vport change events
257 * and async SRIOV admin state changes
259 struct mutex state_lock;
261 /* Protects eswitch mode change that occurs via one or more
262 * user commands, i.e. sriov state change, devlink commands.
264 struct mutex mode_lock;
271 struct mlx5_esw_offload offloads;
275 u16 first_host_vport;
276 struct mlx5_esw_functions esw_funcs;
282 void esw_offloads_disable(struct mlx5_eswitch *esw);
283 int esw_offloads_enable(struct mlx5_eswitch *esw);
284 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
285 int esw_offloads_init_reps(struct mlx5_eswitch *esw);
286 void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
287 struct mlx5_vport *vport);
288 int esw_vport_create_ingress_acl_table(struct mlx5_eswitch *esw,
289 struct mlx5_vport *vport,
291 void esw_vport_destroy_ingress_acl_table(struct mlx5_vport *vport);
292 void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
293 struct mlx5_vport *vport);
294 int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
295 struct mlx5_vport *vport);
296 void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
297 struct mlx5_vport *vport);
298 int mlx5_esw_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num,
302 int mlx5_eswitch_init(struct mlx5_core_dev *dev);
303 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
305 #define MLX5_ESWITCH_IGNORE_NUM_VFS (-1)
306 int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int mode, int num_vfs);
307 int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs);
308 void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw, bool clear_vf);
309 void mlx5_eswitch_disable(struct mlx5_eswitch *esw, bool clear_vf);
310 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
311 u16 vport, u8 mac[ETH_ALEN]);
312 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
313 u16 vport, int link_state);
314 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
315 u16 vport, u16 vlan, u8 qos);
316 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
317 u16 vport, bool spoofchk);
318 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
319 u16 vport_num, bool setting);
320 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport,
321 u32 max_rate, u32 min_rate);
322 int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
323 int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting);
324 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
325 u16 vport, struct ifla_vf_info *ivi);
326 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
328 struct ifla_vf_stats *vf_stats);
329 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
331 int mlx5_eswitch_modify_esw_vport_context(struct mlx5_core_dev *dev, u16 vport,
332 bool other_vport, void *in);
334 struct mlx5_flow_spec;
335 struct mlx5_esw_flow_attr;
336 struct mlx5_termtbl_handle;
339 mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw,
340 struct mlx5_esw_flow_attr *attr,
341 struct mlx5_flow_act *flow_act,
342 struct mlx5_flow_spec *spec);
344 struct mlx5_flow_handle *
345 mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw,
346 struct mlx5_flow_table *ft,
347 struct mlx5_flow_spec *spec,
348 struct mlx5_esw_flow_attr *attr,
349 struct mlx5_flow_act *flow_act,
350 struct mlx5_flow_destination *dest,
354 mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw,
355 struct mlx5_termtbl_handle *tt);
357 struct mlx5_flow_handle *
358 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
359 struct mlx5_flow_spec *spec,
360 struct mlx5_esw_flow_attr *attr);
361 struct mlx5_flow_handle *
362 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
363 struct mlx5_flow_spec *spec,
364 struct mlx5_esw_flow_attr *attr);
366 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
367 struct mlx5_flow_handle *rule,
368 struct mlx5_esw_flow_attr *attr);
370 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
371 struct mlx5_flow_handle *rule,
372 struct mlx5_esw_flow_attr *attr);
374 struct mlx5_flow_handle *
375 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
376 struct mlx5_flow_destination *dest);
379 SET_VLAN_STRIP = BIT(0),
380 SET_VLAN_INSERT = BIT(1)
383 enum mlx5_flow_match_level {
384 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
385 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
386 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
387 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
390 /* current maximum for flow based vport multicasting */
391 #define MLX5_MAX_FLOW_FWD_VPORTS 2
394 MLX5_ESW_DEST_ENCAP = BIT(0),
395 MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
399 MLX5_ESW_ATTR_FLAG_VLAN_HANDLED = BIT(0),
400 MLX5_ESW_ATTR_FLAG_SLOW_PATH = BIT(1),
401 MLX5_ESW_ATTR_FLAG_NO_IN_PORT = BIT(2),
404 struct mlx5_esw_flow_attr {
405 struct mlx5_eswitch_rep *in_rep;
406 struct mlx5_core_dev *in_mdev;
407 struct mlx5_core_dev *counter_dev;
413 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
414 u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
415 u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
419 struct mlx5_eswitch_rep *rep;
420 struct mlx5_pkt_reformat *pkt_reformat;
421 struct mlx5_core_dev *mdev;
422 struct mlx5_termtbl_handle *termtbl;
423 } dests[MLX5_MAX_FLOW_FWD_VPORTS];
424 struct mlx5_modify_hdr *modify_hdr;
425 u8 inner_match_level;
426 u8 outer_match_level;
427 struct mlx5_fc *counter;
432 struct mlx5_flow_table *fdb;
433 struct mlx5_flow_table *dest_ft;
434 struct mlx5_ct_attr ct_attr;
435 struct mlx5e_tc_flow_parse_attr *parse_attr;
438 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
439 struct netlink_ext_ack *extack);
440 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
441 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
442 struct netlink_ext_ack *extack);
443 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
444 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
445 enum devlink_eswitch_encap_mode encap,
446 struct netlink_ext_ack *extack);
447 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
448 enum devlink_eswitch_encap_mode *encap);
449 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
451 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
452 struct mlx5_esw_flow_attr *attr);
453 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
454 struct mlx5_esw_flow_attr *attr);
455 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
456 u16 vport, u16 vlan, u8 qos, u8 set_flags);
458 int mlx5_esw_create_vport_egress_acl_vlan(struct mlx5_eswitch *esw,
459 struct mlx5_vport *vport,
460 u16 vlan_id, u32 flow_action);
462 static inline bool mlx5_esw_qos_enabled(struct mlx5_eswitch *esw)
464 return esw->qos.enabled;
467 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
470 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
471 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
476 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
477 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
480 bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
481 struct mlx5_core_dev *dev1);
482 bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
483 struct mlx5_core_dev *dev1);
485 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev);
487 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
489 #define esw_info(__dev, format, ...) \
490 dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
492 #define esw_warn(__dev, format, ...) \
493 dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
495 #define esw_debug(dev, format, ...) \
496 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
498 /* The returned number is valid only when the dev is eswitch manager. */
499 static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
501 return mlx5_core_is_ecpf_esw_manager(dev) ?
502 MLX5_VPORT_ECPF : MLX5_VPORT_PF;
506 mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num)
508 return esw->manager_vport == vport_num;
511 static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev)
513 return mlx5_core_is_ecpf_esw_manager(dev) ?
514 MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF;
517 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev)
519 /* Ideally device should have the functions changed supported
520 * capability regardless of it being ECPF or PF wherever such
521 * event should be processed such as on eswitch manager device.
522 * However, some ECPF based device might not have this capability
523 * set. Hence OR for ECPF check to cover such device.
525 return MLX5_CAP_ESW(dev, esw_functions_changed) ||
526 mlx5_core_is_ecpf_esw_manager(dev);
529 static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
531 /* Uplink always locate at the last element of the array.*/
532 return esw->total_vports - 1;
535 static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
537 return esw->total_vports - 2;
540 static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
543 if (vport_num == MLX5_VPORT_ECPF) {
544 if (!mlx5_ecpf_vport_exists(esw->dev))
545 esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
546 return mlx5_eswitch_ecpf_idx(esw);
549 if (vport_num == MLX5_VPORT_UPLINK)
550 return mlx5_eswitch_uplink_idx(esw);
555 static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
558 if (index == mlx5_eswitch_ecpf_idx(esw) &&
559 mlx5_ecpf_vport_exists(esw->dev))
560 return MLX5_VPORT_ECPF;
562 if (index == mlx5_eswitch_uplink_idx(esw))
563 return MLX5_VPORT_UPLINK;
568 /* TODO: This mlx5e_tc function shouldn't be called by eswitch */
569 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);
571 /* The vport getter/iterator are only valid after esw->total_vports
572 * and vport->vport are initialized in mlx5_eswitch_init.
574 #define mlx5_esw_for_all_vports(esw, i, vport) \
575 for ((i) = MLX5_VPORT_PF; \
576 (vport) = &(esw)->vports[i], \
577 (i) < (esw)->total_vports; (i)++)
579 #define mlx5_esw_for_all_vports_reverse(esw, i, vport) \
580 for ((i) = (esw)->total_vports - 1; \
581 (vport) = &(esw)->vports[i], \
582 (i) >= MLX5_VPORT_PF; (i)--)
584 #define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \
585 for ((i) = MLX5_VPORT_FIRST_VF; \
586 (vport) = &(esw)->vports[(i)], \
587 (i) <= (nvfs); (i)++)
589 #define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \
591 (vport) = &(esw)->vports[(i)], \
592 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
594 /* The rep getter/iterator are only valid after esw->total_vports
595 * and vport->vport are initialized in mlx5_eswitch_init.
597 #define mlx5_esw_for_all_reps(esw, i, rep) \
598 for ((i) = MLX5_VPORT_PF; \
599 (rep) = &(esw)->offloads.vport_reps[i], \
600 (i) < (esw)->total_vports; (i)++)
602 #define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \
603 for ((i) = MLX5_VPORT_FIRST_VF; \
604 (rep) = &(esw)->offloads.vport_reps[i], \
605 (i) <= (nvfs); (i)++)
607 #define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \
609 (rep) = &(esw)->offloads.vport_reps[i], \
610 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
612 #define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \
613 for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++)
615 #define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \
616 for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--)
618 /* Includes host PF (vport 0) if it's not esw manager. */
619 #define mlx5_esw_for_each_host_func_rep(esw, i, rep, nvfs) \
620 for ((i) = (esw)->first_host_vport; \
621 (rep) = &(esw)->offloads.vport_reps[i], \
622 (i) <= (nvfs); (i)++)
624 #define mlx5_esw_for_each_host_func_rep_reverse(esw, i, rep, nvfs) \
626 (rep) = &(esw)->offloads.vport_reps[i], \
627 (i) >= (esw)->first_host_vport; (i)--)
629 #define mlx5_esw_for_each_host_func_vport(esw, vport, nvfs) \
630 for ((vport) = (esw)->first_host_vport; \
631 (vport) <= (nvfs); (vport)++)
633 #define mlx5_esw_for_each_host_func_vport_reverse(esw, vport, nvfs) \
634 for ((vport) = (nvfs); \
635 (vport) >= (esw)->first_host_vport; (vport)--)
637 struct mlx5_vport *__must_check
638 mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num);
640 bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num);
642 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data);
645 mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw,
646 enum mlx5_eswitch_vport_event enabled_events);
647 void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw);
650 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
651 struct mlx5_vport *vport);
653 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
654 struct mlx5_vport *vport);
656 int mlx5_esw_vport_tbl_get(struct mlx5_eswitch *esw);
657 void mlx5_esw_vport_tbl_put(struct mlx5_eswitch *esw);
659 struct mlx5_flow_handle *
660 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag);
662 esw_get_max_restore_tag(struct mlx5_eswitch *esw);
664 int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num);
665 void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num);
667 int mlx5_eswitch_load_vport(struct mlx5_eswitch *esw, u16 vport_num,
668 enum mlx5_eswitch_vport_event enabled_events);
669 void mlx5_eswitch_unload_vport(struct mlx5_eswitch *esw, u16 vport_num);
671 int mlx5_eswitch_load_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs,
672 enum mlx5_eswitch_vport_event enabled_events);
673 void mlx5_eswitch_unload_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs);
675 #else /* CONFIG_MLX5_ESWITCH */
676 /* eswitch API stubs */
677 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
678 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
679 static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs) { return 0; }
680 static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw, bool clear_vf) {}
681 static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; }
682 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; }
683 static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev)
685 return ERR_PTR(-EOPNOTSUPP);
688 static inline struct mlx5_flow_handle *
689 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
691 return ERR_PTR(-EOPNOTSUPP);
693 #endif /* CONFIG_MLX5_ESWITCH */
695 #endif /* __MLX5_ESWITCH_H__ */