2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/interrupt.h>
34 #include <linux/notifier.h>
35 #include <linux/module.h>
36 #include <linux/mlx5/driver.h>
37 #include <linux/mlx5/vport.h>
38 #include <linux/mlx5/eq.h>
39 #ifdef CONFIG_RFS_ACCEL
40 #include <linux/cpu_rmap.h>
42 #include "mlx5_core.h"
44 #include "fpga/core.h"
46 #include "lib/clock.h"
47 #include "diag/fw_tracer.h"
50 MLX5_EQE_OWNER_INIT_VAL = 0x1,
54 MLX5_EQ_STATE_ARMED = 0x9,
55 MLX5_EQ_STATE_FIRED = 0xa,
56 MLX5_EQ_STATE_ALWAYS_ARMED = 0xb,
60 MLX5_EQ_DOORBEL_OFFSET = 0x40,
63 /* budget must be smaller than MLX5_NUM_SPARE_EQE to guarantee that we update
64 * the ci before we polled all the entries in the EQ. MLX5_NUM_SPARE_EQE is
65 * used to set the EQ size, budget must be smaller than the EQ size.
68 MLX5_EQ_POLLING_BUDGET = 128,
71 static_assert(MLX5_EQ_POLLING_BUDGET <= MLX5_NUM_SPARE_EQE);
73 struct mlx5_eq_table {
74 struct list_head comp_eqs_list;
75 struct mlx5_eq_async pages_eq;
76 struct mlx5_eq_async cmd_eq;
77 struct mlx5_eq_async async_eq;
79 struct atomic_notifier_head nh[MLX5_EVENT_TYPE_MAX];
81 /* Since CQ DB is stored in async_eq */
82 struct mlx5_nb cq_err_nb;
84 struct mutex lock; /* sync async eqs creations */
86 struct mlx5_irq_table *irq_table;
89 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
90 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
91 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
92 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
93 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
94 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
95 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
96 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
97 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
98 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
99 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
100 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
102 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
104 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {};
106 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
107 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
108 return mlx5_cmd_exec_in(dev, destroy_eq, in);
111 /* caller must eventually call mlx5_cq_put on the returned cq */
112 static struct mlx5_core_cq *mlx5_eq_cq_get(struct mlx5_eq *eq, u32 cqn)
114 struct mlx5_cq_table *table = &eq->cq_table;
115 struct mlx5_core_cq *cq = NULL;
118 cq = radix_tree_lookup(&table->tree, cqn);
126 static int mlx5_eq_comp_int(struct notifier_block *nb,
127 __always_unused unsigned long action,
128 __always_unused void *data)
130 struct mlx5_eq_comp *eq_comp =
131 container_of(nb, struct mlx5_eq_comp, irq_nb);
132 struct mlx5_eq *eq = &eq_comp->core;
133 struct mlx5_eqe *eqe;
137 eqe = next_eqe_sw(eq);
142 struct mlx5_core_cq *cq;
144 /* Make sure we read EQ entry contents after we've
145 * checked the ownership bit.
148 /* Assume (eqe->type) is always MLX5_EVENT_TYPE_COMP */
149 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
151 cq = mlx5_eq_cq_get(eq, cqn);
157 dev_dbg_ratelimited(eq->dev->device,
158 "Completion event for bogus CQ 0x%x\n", cqn);
163 } while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq)));
167 tasklet_schedule(&eq_comp->tasklet_ctx.task);
172 /* Some architectures don't latch interrupts when they are disabled, so using
173 * mlx5_eq_poll_irq_disabled could end up losing interrupts while trying to
174 * avoid losing them. It is not recommended to use it, unless this is the last
177 u32 mlx5_eq_poll_irq_disabled(struct mlx5_eq_comp *eq)
181 disable_irq(eq->core.irqn);
182 count_eqe = eq->core.cons_index;
183 mlx5_eq_comp_int(&eq->irq_nb, 0, NULL);
184 count_eqe = eq->core.cons_index - count_eqe;
185 enable_irq(eq->core.irqn);
190 static void mlx5_eq_async_int_lock(struct mlx5_eq_async *eq, bool recovery,
191 unsigned long *flags)
192 __acquires(&eq->lock)
195 spin_lock(&eq->lock);
197 spin_lock_irqsave(&eq->lock, *flags);
200 static void mlx5_eq_async_int_unlock(struct mlx5_eq_async *eq, bool recovery,
201 unsigned long *flags)
202 __releases(&eq->lock)
205 spin_unlock(&eq->lock);
207 spin_unlock_irqrestore(&eq->lock, *flags);
210 enum async_eq_nb_action {
211 ASYNC_EQ_IRQ_HANDLER = 0,
212 ASYNC_EQ_RECOVER = 1,
215 static int mlx5_eq_async_int(struct notifier_block *nb,
216 unsigned long action, void *data)
218 struct mlx5_eq_async *eq_async =
219 container_of(nb, struct mlx5_eq_async, irq_nb);
220 struct mlx5_eq *eq = &eq_async->core;
221 struct mlx5_eq_table *eqt;
222 struct mlx5_core_dev *dev;
223 struct mlx5_eqe *eqe;
229 eqt = dev->priv.eq_table;
231 recovery = action == ASYNC_EQ_RECOVER;
232 mlx5_eq_async_int_lock(eq_async, recovery, &flags);
234 eqe = next_eqe_sw(eq);
240 * Make sure we read EQ entry contents after we've
241 * checked the ownership bit.
245 atomic_notifier_call_chain(&eqt->nh[eqe->type], eqe->type, eqe);
246 atomic_notifier_call_chain(&eqt->nh[MLX5_EVENT_TYPE_NOTIFY_ANY], eqe->type, eqe);
250 } while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq)));
254 mlx5_eq_async_int_unlock(eq_async, recovery, &flags);
256 return unlikely(recovery) ? num_eqes : 0;
259 void mlx5_cmd_eq_recover(struct mlx5_core_dev *dev)
261 struct mlx5_eq_async *eq = &dev->priv.eq_table->cmd_eq;
264 eqes = mlx5_eq_async_int(&eq->irq_nb, ASYNC_EQ_RECOVER, NULL);
266 mlx5_core_warn(dev, "Recovered %d EQEs on cmd_eq\n", eqes);
269 static void init_eq_buf(struct mlx5_eq *eq)
271 struct mlx5_eqe *eqe;
274 for (i = 0; i < eq->nent; i++) {
275 eqe = get_eqe(eq, i);
276 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
281 create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
282 struct mlx5_eq_param *param)
284 struct mlx5_cq_table *cq_table = &eq->cq_table;
285 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
286 struct mlx5_priv *priv = &dev->priv;
287 u8 vecidx = param->irq_index;
296 memset(cq_table, 0, sizeof(*cq_table));
297 spin_lock_init(&cq_table->lock);
298 INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
300 eq->nent = roundup_pow_of_two(param->nent + MLX5_NUM_SPARE_EQE);
302 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
308 inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
309 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
311 in = kvzalloc(inlen, GFP_KERNEL);
317 pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
318 mlx5_fill_page_array(&eq->buf, pas);
320 MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
321 if (!param->mask[0] && MLX5_CAP_GEN(dev, log_max_uctx))
322 MLX5_SET(create_eq_in, in, uid, MLX5_SHARED_RESOURCE_UID);
324 for (i = 0; i < 4; i++)
325 MLX5_ARRAY_SET64(create_eq_in, in, event_bitmask, i,
328 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
329 MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
330 MLX5_SET(eqc, eqc, uar_page, priv->uar->index);
331 MLX5_SET(eqc, eqc, intr, vecidx);
332 MLX5_SET(eqc, eqc, log_page_size,
333 eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
335 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
340 eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
341 eq->irqn = pci_irq_vector(dev->pdev, vecidx);
343 eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
345 err = mlx5_debug_eq_add(dev, eq);
353 mlx5_cmd_destroy_eq(dev, eq->eqn);
359 mlx5_buf_free(dev, &eq->buf);
364 * mlx5_eq_enable - Enable EQ for receiving EQEs
365 * @dev : Device which owns the eq
367 * @nb : Notifier call block
369 * Must be called after EQ is created in device.
371 * @return: 0 if no error
373 int mlx5_eq_enable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
374 struct notifier_block *nb)
376 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
379 err = mlx5_irq_attach_nb(eq_table->irq_table, eq->vecidx, nb);
385 EXPORT_SYMBOL(mlx5_eq_enable);
388 * mlx5_eq_disable - Disable EQ for receiving EQEs
389 * @dev : Device which owns the eq
390 * @eq : EQ to disable
391 * @nb : Notifier call block
393 * Must be called before EQ is destroyed.
395 void mlx5_eq_disable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
396 struct notifier_block *nb)
398 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
400 mlx5_irq_detach_nb(eq_table->irq_table, eq->vecidx, nb);
402 EXPORT_SYMBOL(mlx5_eq_disable);
404 static int destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
408 mlx5_debug_eq_remove(dev, eq);
410 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
412 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
414 synchronize_irq(eq->irqn);
416 mlx5_buf_free(dev, &eq->buf);
421 int mlx5_eq_add_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq)
423 struct mlx5_cq_table *table = &eq->cq_table;
426 spin_lock(&table->lock);
427 err = radix_tree_insert(&table->tree, cq->cqn, cq);
428 spin_unlock(&table->lock);
433 void mlx5_eq_del_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq)
435 struct mlx5_cq_table *table = &eq->cq_table;
436 struct mlx5_core_cq *tmp;
438 spin_lock(&table->lock);
439 tmp = radix_tree_delete(&table->tree, cq->cqn);
440 spin_unlock(&table->lock);
443 mlx5_core_dbg(eq->dev, "cq 0x%x not found in eq 0x%x tree\n",
449 mlx5_core_dbg(eq->dev, "corruption on cqn 0x%x in eq 0x%x\n",
453 int mlx5_eq_table_init(struct mlx5_core_dev *dev)
455 struct mlx5_eq_table *eq_table;
458 eq_table = kvzalloc(sizeof(*eq_table), GFP_KERNEL);
462 dev->priv.eq_table = eq_table;
464 mlx5_eq_debugfs_init(dev);
466 mutex_init(&eq_table->lock);
467 for (i = 0; i < MLX5_EVENT_TYPE_MAX; i++)
468 ATOMIC_INIT_NOTIFIER_HEAD(&eq_table->nh[i]);
470 eq_table->irq_table = mlx5_irq_table_get(dev);
474 void mlx5_eq_table_cleanup(struct mlx5_core_dev *dev)
476 mlx5_eq_debugfs_cleanup(dev);
477 kvfree(dev->priv.eq_table);
482 static int create_async_eq(struct mlx5_core_dev *dev,
483 struct mlx5_eq *eq, struct mlx5_eq_param *param)
485 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
488 mutex_lock(&eq_table->lock);
489 /* Async EQs must share irq index 0 */
490 if (param->irq_index != 0) {
495 err = create_map_eq(dev, eq, param);
497 mutex_unlock(&eq_table->lock);
501 static int destroy_async_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
503 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
506 mutex_lock(&eq_table->lock);
507 err = destroy_unmap_eq(dev, eq);
508 mutex_unlock(&eq_table->lock);
512 static int cq_err_event_notifier(struct notifier_block *nb,
513 unsigned long type, void *data)
515 struct mlx5_eq_table *eqt;
516 struct mlx5_core_cq *cq;
517 struct mlx5_eqe *eqe;
521 /* type == MLX5_EVENT_TYPE_CQ_ERROR */
523 eqt = mlx5_nb_cof(nb, struct mlx5_eq_table, cq_err_nb);
524 eq = &eqt->async_eq.core;
527 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
528 mlx5_core_warn(eq->dev, "CQ error on CQN 0x%x, syndrome 0x%x\n",
529 cqn, eqe->data.cq_err.syndrome);
531 cq = mlx5_eq_cq_get(eq, cqn);
533 mlx5_core_warn(eq->dev, "Async event for bogus CQ 0x%x\n", cqn);
545 static void gather_user_async_events(struct mlx5_core_dev *dev, u64 mask[4])
547 __be64 *user_unaffiliated_events;
548 __be64 *user_affiliated_events;
551 user_affiliated_events =
552 MLX5_CAP_DEV_EVENT(dev, user_affiliated_events);
553 user_unaffiliated_events =
554 MLX5_CAP_DEV_EVENT(dev, user_unaffiliated_events);
556 for (i = 0; i < 4; i++)
557 mask[i] |= be64_to_cpu(user_affiliated_events[i] |
558 user_unaffiliated_events[i]);
561 static void gather_async_events_mask(struct mlx5_core_dev *dev, u64 mask[4])
563 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
565 if (MLX5_VPORT_MANAGER(dev))
566 async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
568 if (MLX5_CAP_GEN(dev, general_notification_event))
569 async_event_mask |= (1ull << MLX5_EVENT_TYPE_GENERAL_EVENT);
571 if (MLX5_CAP_GEN(dev, port_module_event))
572 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PORT_MODULE_EVENT);
574 mlx5_core_dbg(dev, "port_module_event is not set\n");
576 if (MLX5_PPS_CAP(dev))
577 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);
579 if (MLX5_CAP_GEN(dev, fpga))
580 async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) |
581 (1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR);
582 if (MLX5_CAP_GEN_MAX(dev, dct))
583 async_event_mask |= (1ull << MLX5_EVENT_TYPE_DCT_DRAINED);
585 if (MLX5_CAP_GEN(dev, temp_warn_event))
586 async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT);
588 if (MLX5_CAP_MCAM_REG(dev, tracer_registers))
589 async_event_mask |= (1ull << MLX5_EVENT_TYPE_DEVICE_TRACER);
591 if (MLX5_CAP_GEN(dev, max_num_of_monitor_counters))
592 async_event_mask |= (1ull << MLX5_EVENT_TYPE_MONITOR_COUNTER);
594 if (mlx5_eswitch_is_funcs_handler(dev))
596 (1ull << MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED);
598 if (MLX5_CAP_GEN_MAX(dev, vhca_state))
599 async_event_mask |= (1ull << MLX5_EVENT_TYPE_VHCA_STATE_CHANGE);
601 mask[0] = async_event_mask;
603 if (MLX5_CAP_GEN(dev, event_cap))
604 gather_user_async_events(dev, mask);
608 setup_async_eq(struct mlx5_core_dev *dev, struct mlx5_eq_async *eq,
609 struct mlx5_eq_param *param, const char *name)
613 eq->irq_nb.notifier_call = mlx5_eq_async_int;
614 spin_lock_init(&eq->lock);
616 err = create_async_eq(dev, &eq->core, param);
618 mlx5_core_warn(dev, "failed to create %s EQ %d\n", name, err);
621 err = mlx5_eq_enable(dev, &eq->core, &eq->irq_nb);
623 mlx5_core_warn(dev, "failed to enable %s EQ %d\n", name, err);
624 destroy_async_eq(dev, &eq->core);
629 static void cleanup_async_eq(struct mlx5_core_dev *dev,
630 struct mlx5_eq_async *eq, const char *name)
634 mlx5_eq_disable(dev, &eq->core, &eq->irq_nb);
635 err = destroy_async_eq(dev, &eq->core);
637 mlx5_core_err(dev, "failed to destroy %s eq, err(%d)\n",
641 static int create_async_eqs(struct mlx5_core_dev *dev)
643 struct mlx5_eq_table *table = dev->priv.eq_table;
644 struct mlx5_eq_param param = {};
647 MLX5_NB_INIT(&table->cq_err_nb, cq_err_event_notifier, CQ_ERROR);
648 mlx5_eq_notifier_register(dev, &table->cq_err_nb);
650 param = (struct mlx5_eq_param) {
652 .nent = MLX5_NUM_CMD_EQE,
653 .mask[0] = 1ull << MLX5_EVENT_TYPE_CMD,
655 mlx5_cmd_allowed_opcode(dev, MLX5_CMD_OP_CREATE_EQ);
656 err = setup_async_eq(dev, &table->cmd_eq, ¶m, "cmd");
660 mlx5_cmd_use_events(dev);
661 mlx5_cmd_allowed_opcode(dev, CMD_ALLOWED_OPCODE_ALL);
663 param = (struct mlx5_eq_param) {
665 .nent = MLX5_NUM_ASYNC_EQE,
668 gather_async_events_mask(dev, param.mask);
669 err = setup_async_eq(dev, &table->async_eq, ¶m, "async");
673 param = (struct mlx5_eq_param) {
675 .nent = /* TODO: sriov max_vf + */ 1,
676 .mask[0] = 1ull << MLX5_EVENT_TYPE_PAGE_REQUEST,
679 err = setup_async_eq(dev, &table->pages_eq, ¶m, "pages");
686 cleanup_async_eq(dev, &table->async_eq, "async");
688 mlx5_cmd_use_polling(dev);
689 cleanup_async_eq(dev, &table->cmd_eq, "cmd");
691 mlx5_cmd_allowed_opcode(dev, CMD_ALLOWED_OPCODE_ALL);
692 mlx5_eq_notifier_unregister(dev, &table->cq_err_nb);
696 static void destroy_async_eqs(struct mlx5_core_dev *dev)
698 struct mlx5_eq_table *table = dev->priv.eq_table;
700 cleanup_async_eq(dev, &table->pages_eq, "pages");
701 cleanup_async_eq(dev, &table->async_eq, "async");
702 mlx5_cmd_allowed_opcode(dev, MLX5_CMD_OP_DESTROY_EQ);
703 mlx5_cmd_use_polling(dev);
704 cleanup_async_eq(dev, &table->cmd_eq, "cmd");
705 mlx5_cmd_allowed_opcode(dev, CMD_ALLOWED_OPCODE_ALL);
706 mlx5_eq_notifier_unregister(dev, &table->cq_err_nb);
709 struct mlx5_eq *mlx5_get_async_eq(struct mlx5_core_dev *dev)
711 return &dev->priv.eq_table->async_eq.core;
714 void mlx5_eq_synchronize_async_irq(struct mlx5_core_dev *dev)
716 synchronize_irq(dev->priv.eq_table->async_eq.core.irqn);
719 void mlx5_eq_synchronize_cmd_irq(struct mlx5_core_dev *dev)
721 synchronize_irq(dev->priv.eq_table->cmd_eq.core.irqn);
724 /* Generic EQ API for mlx5_core consumers
725 * Needed For RDMA ODP EQ for now
728 mlx5_eq_create_generic(struct mlx5_core_dev *dev,
729 struct mlx5_eq_param *param)
731 struct mlx5_eq *eq = kvzalloc(sizeof(*eq), GFP_KERNEL);
735 return ERR_PTR(-ENOMEM);
737 err = create_async_eq(dev, eq, param);
745 EXPORT_SYMBOL(mlx5_eq_create_generic);
747 int mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
754 err = destroy_async_eq(dev, eq);
762 EXPORT_SYMBOL(mlx5_eq_destroy_generic);
764 struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc)
766 u32 ci = eq->cons_index + cc;
767 struct mlx5_eqe *eqe;
769 eqe = get_eqe(eq, ci & (eq->nent - 1));
770 eqe = ((eqe->owner & 1) ^ !!(ci & eq->nent)) ? NULL : eqe;
771 /* Make sure we read EQ entry contents after we've
772 * checked the ownership bit.
779 EXPORT_SYMBOL(mlx5_eq_get_eqe);
781 void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm)
783 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
786 eq->cons_index += cc;
787 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
789 __raw_writel((__force u32)cpu_to_be32(val), addr);
790 /* We still want ordering, just not swabbing, so add a barrier */
793 EXPORT_SYMBOL(mlx5_eq_update_ci);
795 static void destroy_comp_eqs(struct mlx5_core_dev *dev)
797 struct mlx5_eq_table *table = dev->priv.eq_table;
798 struct mlx5_eq_comp *eq, *n;
800 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
802 mlx5_eq_disable(dev, &eq->core, &eq->irq_nb);
803 if (destroy_unmap_eq(dev, &eq->core))
804 mlx5_core_warn(dev, "failed to destroy comp EQ 0x%x\n",
806 tasklet_disable(&eq->tasklet_ctx.task);
811 static int create_comp_eqs(struct mlx5_core_dev *dev)
813 struct mlx5_eq_table *table = dev->priv.eq_table;
814 struct mlx5_eq_comp *eq;
820 INIT_LIST_HEAD(&table->comp_eqs_list);
821 ncomp_eqs = table->num_comp_eqs;
822 nent = MLX5_COMP_EQ_SIZE;
823 for (i = 0; i < ncomp_eqs; i++) {
824 int vecidx = i + MLX5_IRQ_VEC_COMP_BASE;
825 struct mlx5_eq_param param = {};
827 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
833 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
834 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
835 spin_lock_init(&eq->tasklet_ctx.lock);
836 tasklet_setup(&eq->tasklet_ctx.task, mlx5_cq_tasklet_cb);
838 eq->irq_nb.notifier_call = mlx5_eq_comp_int;
839 param = (struct mlx5_eq_param) {
843 err = create_map_eq(dev, &eq->core, ¶m);
848 err = mlx5_eq_enable(dev, &eq->core, &eq->irq_nb);
850 destroy_unmap_eq(dev, &eq->core);
855 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->core.eqn);
856 /* add tail, to keep the list ordered, for mlx5_vector2eqn to work */
857 list_add_tail(&eq->list, &table->comp_eqs_list);
863 destroy_comp_eqs(dev);
867 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
870 struct mlx5_eq_table *table = dev->priv.eq_table;
871 struct mlx5_eq_comp *eq, *n;
875 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
878 *irqn = eq->core.irqn;
886 EXPORT_SYMBOL(mlx5_vector2eqn);
888 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev)
890 return dev->priv.eq_table->num_comp_eqs;
892 EXPORT_SYMBOL(mlx5_comp_vectors_count);
895 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector)
897 int vecidx = vector + MLX5_IRQ_VEC_COMP_BASE;
899 return mlx5_irq_get_affinity_mask(dev->priv.eq_table->irq_table,
902 EXPORT_SYMBOL(mlx5_comp_irq_get_affinity_mask);
904 #ifdef CONFIG_RFS_ACCEL
905 struct cpu_rmap *mlx5_eq_table_get_rmap(struct mlx5_core_dev *dev)
907 return mlx5_irq_get_rmap(dev->priv.eq_table->irq_table);
911 struct mlx5_eq_comp *mlx5_eqn2comp_eq(struct mlx5_core_dev *dev, int eqn)
913 struct mlx5_eq_table *table = dev->priv.eq_table;
914 struct mlx5_eq_comp *eq;
916 list_for_each_entry(eq, &table->comp_eqs_list, list) {
917 if (eq->core.eqn == eqn)
921 return ERR_PTR(-ENOENT);
924 /* This function should only be called after mlx5_cmd_force_teardown_hca */
925 void mlx5_core_eq_free_irqs(struct mlx5_core_dev *dev)
927 struct mlx5_eq_table *table = dev->priv.eq_table;
929 mutex_lock(&table->lock); /* sync with create/destroy_async_eq */
930 mlx5_irq_table_destroy(dev);
931 mutex_unlock(&table->lock);
934 int mlx5_eq_table_create(struct mlx5_core_dev *dev)
936 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
939 eq_table->num_comp_eqs =
940 mlx5_irq_get_num_comp(eq_table->irq_table);
942 err = create_async_eqs(dev);
944 mlx5_core_err(dev, "Failed to create async EQs\n");
948 err = create_comp_eqs(dev);
950 mlx5_core_err(dev, "Failed to create completion EQs\n");
956 destroy_async_eqs(dev);
961 void mlx5_eq_table_destroy(struct mlx5_core_dev *dev)
963 destroy_comp_eqs(dev);
964 destroy_async_eqs(dev);
967 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb)
969 struct mlx5_eq_table *eqt = dev->priv.eq_table;
971 return atomic_notifier_chain_register(&eqt->nh[nb->event_type], &nb->nb);
973 EXPORT_SYMBOL(mlx5_eq_notifier_register);
975 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb)
977 struct mlx5_eq_table *eqt = dev->priv.eq_table;
979 return atomic_notifier_chain_unregister(&eqt->nh[nb->event_type], &nb->nb);
981 EXPORT_SYMBOL(mlx5_eq_notifier_unregister);