2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
35 #include <net/geneve.h>
36 #include <net/dsfield.h>
39 #include "ipoib/ipoib.h"
40 #include "en_accel/en_accel.h"
43 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma)
47 for (i = 0; i < num_dma; i++) {
48 struct mlx5e_sq_dma *last_pushed_dma =
49 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
51 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
55 #ifdef CONFIG_MLX5_CORE_EN_DCB
56 static inline int mlx5e_get_dscp_up(struct mlx5e_priv *priv, struct sk_buff *skb)
60 if (skb->protocol == htons(ETH_P_IP))
61 dscp_cp = ipv4_get_dsfield(ip_hdr(skb)) >> 2;
62 else if (skb->protocol == htons(ETH_P_IPV6))
63 dscp_cp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2;
65 return priv->dcbx_dp.dscp2prio[dscp_cp];
69 static u16 mlx5e_select_ptpsq(struct net_device *dev, struct sk_buff *skb)
71 struct mlx5e_priv *priv = netdev_priv(dev);
74 if (!netdev_get_num_tc(dev))
77 #ifdef CONFIG_MLX5_CORE_EN_DCB
78 if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP)
79 up = mlx5e_get_dscp_up(priv, skb);
82 if (skb_vlan_tag_present(skb))
83 up = skb_vlan_tag_get_prio(skb);
86 return priv->port_ptp_tc2realtxq[up];
89 static int mlx5e_select_htb_queue(struct mlx5e_priv *priv, struct sk_buff *skb,
94 if ((TC_H_MAJ(skb->priority) >> 16) == htb_maj_id)
95 classid = TC_H_MIN(skb->priority);
97 classid = READ_ONCE(priv->htb.defcls);
102 return mlx5e_get_txq_by_classid(priv, classid);
105 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
106 struct net_device *sb_dev)
108 struct mlx5e_priv *priv = netdev_priv(dev);
114 /* Sync with mlx5e_update_num_tc_x_num_ch - avoid refetching. */
115 num_tc_x_num_ch = READ_ONCE(priv->num_tc_x_num_ch);
116 if (unlikely(dev->real_num_tx_queues > num_tc_x_num_ch)) {
117 struct mlx5e_ptp *ptp_channel;
119 /* Order maj_id before defcls - pairs with mlx5e_htb_root_add. */
120 u16 htb_maj_id = smp_load_acquire(&priv->htb.maj_id);
122 if (unlikely(htb_maj_id)) {
123 txq_ix = mlx5e_select_htb_queue(priv, skb, htb_maj_id);
128 ptp_channel = READ_ONCE(priv->channels.ptp);
129 if (unlikely(ptp_channel &&
130 test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state) &&
131 mlx5e_use_ptpsq(skb)))
132 return mlx5e_select_ptpsq(dev, skb);
134 txq_ix = netdev_pick_tx(dev, skb, NULL);
135 /* Fix netdev_pick_tx() not to choose ptp_channel and HTB txqs.
136 * If they are selected, switch to regular queues.
137 * Driver to select these queues only at mlx5e_select_ptpsq()
138 * and mlx5e_select_htb_queue().
140 if (unlikely(txq_ix >= num_tc_x_num_ch))
141 txq_ix %= num_tc_x_num_ch;
143 txq_ix = netdev_pick_tx(dev, skb, NULL);
146 if (!netdev_get_num_tc(dev))
149 #ifdef CONFIG_MLX5_CORE_EN_DCB
150 if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP)
151 up = mlx5e_get_dscp_up(priv, skb);
154 if (skb_vlan_tag_present(skb))
155 up = skb_vlan_tag_get_prio(skb);
157 /* Normalize any picked txq_ix to [0, num_channels),
158 * So we can return a txq_ix that matches the channel and
161 ch_ix = priv->txq2sq[txq_ix]->ch_ix;
163 return priv->channel_tc2realtxq[ch_ix][up];
166 static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb)
168 #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
170 return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
173 static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb)
175 if (skb_transport_header_was_set(skb))
176 return skb_transport_offset(skb);
178 return mlx5e_skb_l2_header_offset(skb);
181 static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
187 case MLX5_INLINE_MODE_NONE:
189 case MLX5_INLINE_MODE_TCP_UDP:
190 hlen = eth_get_headlen(skb->dev, skb->data, skb_headlen(skb));
191 if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb))
194 case MLX5_INLINE_MODE_IP:
195 hlen = mlx5e_skb_l3_header_offset(skb);
197 case MLX5_INLINE_MODE_L2:
199 hlen = mlx5e_skb_l2_header_offset(skb);
201 return min_t(u16, hlen, skb_headlen(skb));
204 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs)
206 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
207 int cpy1_sz = 2 * ETH_ALEN;
208 int cpy2_sz = ihs - cpy1_sz;
210 memcpy(vhdr, skb->data, cpy1_sz);
211 vhdr->h_vlan_proto = skb->vlan_proto;
212 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
213 memcpy(&vhdr->h_vlan_encapsulated_proto, skb->data + cpy1_sz, cpy2_sz);
216 /* If packet is not IP's CHECKSUM_PARTIAL (e.g. icmd packet),
217 * need to set L3 checksum flag for IPsec
220 ipsec_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb,
221 struct mlx5_wqe_eth_seg *eseg)
223 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
224 if (skb->encapsulation) {
225 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM;
226 sq->stats->csum_partial_inner++;
228 sq->stats->csum_partial++;
233 mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb,
234 struct mlx5e_accel_tx_state *accel,
235 struct mlx5_wqe_eth_seg *eseg)
237 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
238 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
239 if (skb->encapsulation) {
240 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
241 MLX5_ETH_WQE_L4_INNER_CSUM;
242 sq->stats->csum_partial_inner++;
244 eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
245 sq->stats->csum_partial++;
247 #ifdef CONFIG_MLX5_EN_TLS
248 } else if (unlikely(accel && accel->tls.tls_tisn)) {
249 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
250 sq->stats->csum_partial++;
252 } else if (unlikely(mlx5e_ipsec_eseg_meta(eseg))) {
253 ipsec_txwqe_build_eseg_csum(sq, skb, eseg);
255 sq->stats->csum_none++;
259 mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq *sq, struct sk_buff *skb)
261 struct mlx5e_sq_stats *stats = sq->stats;
264 if (skb->encapsulation) {
265 ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
266 stats->tso_inner_packets++;
267 stats->tso_inner_bytes += skb->len - ihs;
269 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4)
270 ihs = skb_transport_offset(skb) + sizeof(struct udphdr);
272 ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
273 stats->tso_packets++;
274 stats->tso_bytes += skb->len - ihs;
281 mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb,
282 unsigned char *skb_data, u16 headlen,
283 struct mlx5_wqe_data_seg *dseg)
285 dma_addr_t dma_addr = 0;
290 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
292 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
293 goto dma_unmap_wqe_err;
295 dseg->addr = cpu_to_be64(dma_addr);
296 dseg->lkey = sq->mkey_be;
297 dseg->byte_count = cpu_to_be32(headlen);
299 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
304 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
305 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
306 int fsz = skb_frag_size(frag);
308 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
310 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
311 goto dma_unmap_wqe_err;
313 dseg->addr = cpu_to_be64(dma_addr);
314 dseg->lkey = sq->mkey_be;
315 dseg->byte_count = cpu_to_be32(fsz);
317 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
325 mlx5e_dma_unmap_wqe_err(sq, num_dma);
329 struct mlx5e_tx_attr {
338 struct mlx5e_tx_wqe_attr {
346 mlx5e_tx_wqe_inline_mode(struct mlx5e_txqsq *sq, struct sk_buff *skb,
347 struct mlx5e_accel_tx_state *accel)
351 #ifdef CONFIG_MLX5_EN_TLS
352 if (accel && accel->tls.tls_tisn)
353 return MLX5_INLINE_MODE_TCP_UDP;
356 mode = sq->min_inline_mode;
358 if (skb_vlan_tag_present(skb) &&
359 test_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state))
360 mode = max_t(u8, MLX5_INLINE_MODE_L2, mode);
365 static void mlx5e_sq_xmit_prepare(struct mlx5e_txqsq *sq, struct sk_buff *skb,
366 struct mlx5e_accel_tx_state *accel,
367 struct mlx5e_tx_attr *attr)
369 struct mlx5e_sq_stats *stats = sq->stats;
371 if (skb_is_gso(skb)) {
372 u16 ihs = mlx5e_tx_get_gso_ihs(sq, skb);
374 *attr = (struct mlx5e_tx_attr) {
375 .opcode = MLX5_OPCODE_LSO,
376 .mss = cpu_to_be16(skb_shinfo(skb)->gso_size),
378 .num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs,
379 .headlen = skb_headlen(skb) - ihs,
382 stats->packets += skb_shinfo(skb)->gso_segs;
384 u8 mode = mlx5e_tx_wqe_inline_mode(sq, skb, accel);
385 u16 ihs = mlx5e_calc_min_inline(mode, skb);
387 *attr = (struct mlx5e_tx_attr) {
388 .opcode = MLX5_OPCODE_SEND,
389 .mss = cpu_to_be16(0),
391 .num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN),
392 .headlen = skb_headlen(skb) - ihs,
398 attr->insz = mlx5e_accel_tx_ids_len(sq, accel);
399 stats->bytes += attr->num_bytes;
402 static void mlx5e_sq_calc_wqe_attr(struct sk_buff *skb, const struct mlx5e_tx_attr *attr,
403 struct mlx5e_tx_wqe_attr *wqe_attr)
405 u16 ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT;
410 ds_cnt_ids = DIV_ROUND_UP(sizeof(struct mlx5_wqe_inline_seg) + attr->insz,
413 ds_cnt += !!attr->headlen + skb_shinfo(skb)->nr_frags + ds_cnt_ids;
415 u16 inl = attr->ihs - INL_HDR_START_SZ;
417 if (skb_vlan_tag_present(skb))
420 ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS);
421 ds_cnt += ds_cnt_inl;
424 *wqe_attr = (struct mlx5e_tx_wqe_attr) {
426 .ds_cnt_inl = ds_cnt_inl,
427 .ds_cnt_ids = ds_cnt_ids,
428 .num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS),
432 static void mlx5e_tx_skb_update_hwts_flags(struct sk_buff *skb)
434 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
435 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
438 static void mlx5e_tx_check_stop(struct mlx5e_txqsq *sq)
440 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room))) {
441 netif_tx_stop_queue(sq->txq);
442 sq->stats->stopped++;
447 mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
448 const struct mlx5e_tx_attr *attr,
449 const struct mlx5e_tx_wqe_attr *wqe_attr, u8 num_dma,
450 struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg,
453 struct mlx5_wq_cyc *wq = &sq->wq;
456 *wi = (struct mlx5e_tx_wqe_info) {
458 .num_bytes = attr->num_bytes,
460 .num_wqebbs = wqe_attr->num_wqebbs,
464 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | attr->opcode);
465 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | wqe_attr->ds_cnt);
467 mlx5e_tx_skb_update_hwts_flags(skb);
469 sq->pc += wi->num_wqebbs;
471 mlx5e_tx_check_stop(sq);
473 if (unlikely(sq->ptpsq)) {
474 mlx5e_skb_cb_hwtstamp_init(skb);
475 mlx5e_skb_fifo_push(&sq->ptpsq->skb_fifo, skb);
479 send_doorbell = __netdev_tx_sent_queue(sq->txq, attr->num_bytes, xmit_more);
481 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg);
485 mlx5e_sq_xmit_wqe(struct mlx5e_txqsq *sq, struct sk_buff *skb,
486 const struct mlx5e_tx_attr *attr, const struct mlx5e_tx_wqe_attr *wqe_attr,
487 struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more)
489 struct mlx5_wqe_ctrl_seg *cseg;
490 struct mlx5_wqe_eth_seg *eseg;
491 struct mlx5_wqe_data_seg *dseg;
492 struct mlx5e_tx_wqe_info *wi;
494 struct mlx5e_sq_stats *stats = sq->stats;
497 stats->xmit_more += xmit_more;
500 wi = &sq->db.wqe_info[pi];
505 eseg->mss = attr->mss;
508 if (skb_vlan_tag_present(skb)) {
509 eseg->inline_hdr.sz |= cpu_to_be16(attr->ihs + VLAN_HLEN);
510 mlx5e_insert_vlan(eseg->inline_hdr.start, skb, attr->ihs);
511 stats->added_vlan_packets++;
513 eseg->inline_hdr.sz |= cpu_to_be16(attr->ihs);
514 memcpy(eseg->inline_hdr.start, skb->data, attr->ihs);
516 dseg += wqe_attr->ds_cnt_inl;
517 } else if (skb_vlan_tag_present(skb)) {
518 eseg->insert.type = cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN);
519 if (skb->vlan_proto == cpu_to_be16(ETH_P_8021AD))
520 eseg->insert.type |= cpu_to_be16(MLX5_ETH_WQE_SVLAN);
521 eseg->insert.vlan_tci = cpu_to_be16(skb_vlan_tag_get(skb));
522 stats->added_vlan_packets++;
525 dseg += wqe_attr->ds_cnt_ids;
526 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + attr->ihs,
527 attr->headlen, dseg);
528 if (unlikely(num_dma < 0))
531 mlx5e_txwqe_complete(sq, skb, attr, wqe_attr, num_dma, wi, cseg, xmit_more);
537 dev_kfree_skb_any(skb);
540 static bool mlx5e_tx_skb_supports_mpwqe(struct sk_buff *skb, struct mlx5e_tx_attr *attr)
542 return !skb_is_nonlinear(skb) && !skb_vlan_tag_present(skb) && !attr->ihs &&
546 static bool mlx5e_tx_mpwqe_same_eseg(struct mlx5e_txqsq *sq, struct mlx5_wqe_eth_seg *eseg)
548 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
550 /* Assumes the session is already running and has at least one packet. */
551 return !memcmp(&session->wqe->eth, eseg, MLX5E_ACCEL_ESEG_LEN);
554 static void mlx5e_tx_mpwqe_session_start(struct mlx5e_txqsq *sq,
555 struct mlx5_wqe_eth_seg *eseg)
557 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
558 struct mlx5e_tx_wqe *wqe;
561 pi = mlx5e_txqsq_get_next_pi(sq, MLX5E_TX_MPW_MAX_WQEBBS);
562 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
563 net_prefetchw(wqe->data);
565 *session = (struct mlx5e_tx_mpwqe) {
568 .ds_count = MLX5E_TX_WQE_EMPTY_DS_COUNT,
573 memcpy(&session->wqe->eth, eseg, MLX5E_ACCEL_ESEG_LEN);
575 sq->stats->mpwqe_blks++;
578 static bool mlx5e_tx_mpwqe_session_is_active(struct mlx5e_txqsq *sq)
580 return sq->mpwqe.wqe;
583 static void mlx5e_tx_mpwqe_add_dseg(struct mlx5e_txqsq *sq, struct mlx5e_xmit_data *txd)
585 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
586 struct mlx5_wqe_data_seg *dseg;
588 dseg = (struct mlx5_wqe_data_seg *)session->wqe + session->ds_count;
590 session->pkt_count++;
591 session->bytes_count += txd->len;
593 dseg->addr = cpu_to_be64(txd->dma_addr);
594 dseg->byte_count = cpu_to_be32(txd->len);
595 dseg->lkey = sq->mkey_be;
598 sq->stats->mpwqe_pkts++;
601 static struct mlx5_wqe_ctrl_seg *mlx5e_tx_mpwqe_session_complete(struct mlx5e_txqsq *sq)
603 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
604 u8 ds_count = session->ds_count;
605 struct mlx5_wqe_ctrl_seg *cseg;
606 struct mlx5e_tx_wqe_info *wi;
609 cseg = &session->wqe->ctrl;
610 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_ENHANCED_MPSW);
611 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_count);
613 pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc);
614 wi = &sq->db.wqe_info[pi];
615 *wi = (struct mlx5e_tx_wqe_info) {
617 .num_bytes = session->bytes_count,
618 .num_wqebbs = DIV_ROUND_UP(ds_count, MLX5_SEND_WQEBB_NUM_DS),
619 .num_dma = session->pkt_count,
620 .num_fifo_pkts = session->pkt_count,
623 sq->pc += wi->num_wqebbs;
627 mlx5e_tx_check_stop(sq);
633 mlx5e_sq_xmit_mpwqe(struct mlx5e_txqsq *sq, struct sk_buff *skb,
634 struct mlx5_wqe_eth_seg *eseg, bool xmit_more)
636 struct mlx5_wqe_ctrl_seg *cseg;
637 struct mlx5e_xmit_data txd;
639 if (!mlx5e_tx_mpwqe_session_is_active(sq)) {
640 mlx5e_tx_mpwqe_session_start(sq, eseg);
641 } else if (!mlx5e_tx_mpwqe_same_eseg(sq, eseg)) {
642 mlx5e_tx_mpwqe_session_complete(sq);
643 mlx5e_tx_mpwqe_session_start(sq, eseg);
646 sq->stats->xmit_more += xmit_more;
648 txd.data = skb->data;
651 txd.dma_addr = dma_map_single(sq->pdev, txd.data, txd.len, DMA_TO_DEVICE);
652 if (unlikely(dma_mapping_error(sq->pdev, txd.dma_addr)))
654 mlx5e_dma_push(sq, txd.dma_addr, txd.len, MLX5E_DMA_MAP_SINGLE);
656 mlx5e_skb_fifo_push(&sq->db.skb_fifo, skb);
658 mlx5e_tx_mpwqe_add_dseg(sq, &txd);
660 mlx5e_tx_skb_update_hwts_flags(skb);
662 if (unlikely(mlx5e_tx_mpwqe_is_full(&sq->mpwqe))) {
663 /* Might stop the queue and affect the retval of __netdev_tx_sent_queue. */
664 cseg = mlx5e_tx_mpwqe_session_complete(sq);
666 if (__netdev_tx_sent_queue(sq->txq, txd.len, xmit_more))
667 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg);
668 } else if (__netdev_tx_sent_queue(sq->txq, txd.len, xmit_more)) {
669 /* Might stop the queue, but we were asked to ring the doorbell anyway. */
670 cseg = mlx5e_tx_mpwqe_session_complete(sq);
672 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg);
678 mlx5e_dma_unmap_wqe_err(sq, 1);
679 sq->stats->dropped++;
680 dev_kfree_skb_any(skb);
683 void mlx5e_tx_mpwqe_ensure_complete(struct mlx5e_txqsq *sq)
685 /* Unlikely in non-MPWQE workloads; not important in MPWQE workloads. */
686 if (unlikely(mlx5e_tx_mpwqe_session_is_active(sq)))
687 mlx5e_tx_mpwqe_session_complete(sq);
690 static void mlx5e_txwqe_build_eseg(struct mlx5e_priv *priv, struct mlx5e_txqsq *sq,
691 struct sk_buff *skb, struct mlx5e_accel_tx_state *accel,
692 struct mlx5_wqe_eth_seg *eseg, u16 ihs)
694 mlx5e_accel_tx_eseg(priv, skb, eseg, ihs);
695 mlx5e_txwqe_build_eseg_csum(sq, skb, accel, eseg);
698 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
700 struct mlx5e_priv *priv = netdev_priv(dev);
701 struct mlx5e_accel_tx_state accel = {};
702 struct mlx5e_tx_wqe_attr wqe_attr;
703 struct mlx5e_tx_attr attr;
704 struct mlx5e_tx_wqe *wqe;
705 struct mlx5e_txqsq *sq;
708 sq = priv->txq2sq[skb_get_queue_mapping(skb)];
710 dev_kfree_skb_any(skb);
714 /* May send SKBs and WQEs. */
715 if (unlikely(!mlx5e_accel_tx_begin(dev, sq, skb, &accel)))
718 mlx5e_sq_xmit_prepare(sq, skb, &accel, &attr);
720 if (test_bit(MLX5E_SQ_STATE_MPWQE, &sq->state)) {
721 if (mlx5e_tx_skb_supports_mpwqe(skb, &attr)) {
722 struct mlx5_wqe_eth_seg eseg = {};
724 mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &eseg, attr.ihs);
725 mlx5e_sq_xmit_mpwqe(sq, skb, &eseg, netdev_xmit_more());
729 mlx5e_tx_mpwqe_ensure_complete(sq);
732 mlx5e_sq_calc_wqe_attr(skb, &attr, &wqe_attr);
733 pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs);
734 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
736 /* May update the WQE, but may not post other WQEs. */
737 mlx5e_accel_tx_finish(sq, wqe, &accel,
738 (struct mlx5_wqe_inline_seg *)(wqe->data + wqe_attr.ds_cnt_inl));
739 mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &wqe->eth, attr.ihs);
740 mlx5e_sq_xmit_wqe(sq, skb, &attr, &wqe_attr, wqe, pi, netdev_xmit_more());
745 void mlx5e_sq_xmit_simple(struct mlx5e_txqsq *sq, struct sk_buff *skb, bool xmit_more)
747 struct mlx5e_tx_wqe_attr wqe_attr;
748 struct mlx5e_tx_attr attr;
749 struct mlx5e_tx_wqe *wqe;
752 mlx5e_sq_xmit_prepare(sq, skb, NULL, &attr);
753 mlx5e_sq_calc_wqe_attr(skb, &attr, &wqe_attr);
754 pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs);
755 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
756 mlx5e_txwqe_build_eseg_csum(sq, skb, NULL, &wqe->eth);
757 mlx5e_sq_xmit_wqe(sq, skb, &attr, &wqe_attr, wqe, pi, xmit_more);
760 static void mlx5e_tx_wi_dma_unmap(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi,
765 for (i = 0; i < wi->num_dma; i++) {
766 struct mlx5e_sq_dma *dma = mlx5e_dma_get(sq, (*dma_fifo_cc)++);
768 mlx5e_tx_dma_unmap(sq->pdev, dma);
772 static void mlx5e_consume_skb(struct mlx5e_txqsq *sq, struct sk_buff *skb,
773 struct mlx5_cqe64 *cqe, int napi_budget)
775 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
776 struct skb_shared_hwtstamps hwts = {};
777 u64 ts = get_cqe_ts(cqe);
779 hwts.hwtstamp = mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, ts);
781 mlx5e_skb_cb_hwtstamp_handler(skb, MLX5E_SKB_CB_CQE_HWTSTAMP,
782 hwts.hwtstamp, sq->ptpsq->cq_stats);
784 skb_tstamp_tx(skb, &hwts);
787 napi_consume_skb(skb, napi_budget);
790 static void mlx5e_tx_wi_consume_fifo_skbs(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi,
791 struct mlx5_cqe64 *cqe, int napi_budget)
795 for (i = 0; i < wi->num_fifo_pkts; i++) {
796 struct sk_buff *skb = mlx5e_skb_fifo_pop(&sq->db.skb_fifo);
798 mlx5e_consume_skb(sq, skb, cqe, napi_budget);
802 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
804 struct mlx5e_sq_stats *stats;
805 struct mlx5e_txqsq *sq;
806 struct mlx5_cqe64 *cqe;
813 sq = container_of(cq, struct mlx5e_txqsq, cq);
815 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
818 cqe = mlx5_cqwq_get_cqe(&cq->wq);
827 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
828 * otherwise a cq overrun may occur
832 /* avoid dirtying sq cache line every cqe */
833 dma_fifo_cc = sq->dma_fifo_cc;
837 struct mlx5e_tx_wqe_info *wi;
842 mlx5_cqwq_pop(&cq->wq);
844 wqe_counter = be16_to_cpu(cqe->wqe_counter);
847 last_wqe = (sqcc == wqe_counter);
849 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
850 wi = &sq->db.wqe_info[ci];
852 sqcc += wi->num_wqebbs;
854 if (likely(wi->skb)) {
855 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
856 mlx5e_consume_skb(sq, wi->skb, cqe, napi_budget);
859 nbytes += wi->num_bytes;
863 if (unlikely(mlx5e_ktls_tx_try_handle_resync_dump_comp(sq, wi,
867 if (wi->num_fifo_pkts) {
868 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
869 mlx5e_tx_wi_consume_fifo_skbs(sq, wi, cqe, napi_budget);
871 npkts += wi->num_fifo_pkts;
872 nbytes += wi->num_bytes;
876 if (unlikely(get_cqe_opcode(cqe) == MLX5_CQE_REQ_ERR)) {
877 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING,
879 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
880 (struct mlx5_err_cqe *)cqe);
881 mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs);
882 queue_work(cq->priv->wq, &sq->recover_work);
887 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
891 mlx5_cqwq_update_db_record(&cq->wq);
893 /* ensure cq space is freed before enabling more cqes */
896 sq->dma_fifo_cc = dma_fifo_cc;
899 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
901 if (netif_tx_queue_stopped(sq->txq) &&
902 mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room) &&
903 !test_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) {
904 netif_tx_wake_queue(sq->txq);
908 return (i == MLX5E_TX_CQ_POLL_BUDGET);
911 static void mlx5e_tx_wi_kfree_fifo_skbs(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi)
915 for (i = 0; i < wi->num_fifo_pkts; i++)
916 dev_kfree_skb_any(mlx5e_skb_fifo_pop(&sq->db.skb_fifo));
919 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq)
921 struct mlx5e_tx_wqe_info *wi;
922 u32 dma_fifo_cc, nbytes = 0;
923 u16 ci, sqcc, npkts = 0;
926 dma_fifo_cc = sq->dma_fifo_cc;
928 while (sqcc != sq->pc) {
929 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
930 wi = &sq->db.wqe_info[ci];
932 sqcc += wi->num_wqebbs;
934 if (likely(wi->skb)) {
935 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
936 dev_kfree_skb_any(wi->skb);
939 nbytes += wi->num_bytes;
943 if (unlikely(mlx5e_ktls_tx_try_handle_resync_dump_comp(sq, wi, &dma_fifo_cc)))
946 if (wi->num_fifo_pkts) {
947 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
948 mlx5e_tx_wi_kfree_fifo_skbs(sq, wi);
950 npkts += wi->num_fifo_pkts;
951 nbytes += wi->num_bytes;
955 sq->dma_fifo_cc = dma_fifo_cc;
958 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
961 #ifdef CONFIG_MLX5_CORE_IPOIB
963 mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey,
964 struct mlx5_wqe_datagram_seg *dseg)
966 memcpy(&dseg->av, av, sizeof(struct mlx5_av));
967 dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV);
968 dseg->av.key.qkey.qkey = cpu_to_be32(dqkey);
971 static void mlx5i_sq_calc_wqe_attr(struct sk_buff *skb,
972 const struct mlx5e_tx_attr *attr,
973 struct mlx5e_tx_wqe_attr *wqe_attr)
975 u16 ds_cnt = sizeof(struct mlx5i_tx_wqe) / MLX5_SEND_WQE_DS;
978 ds_cnt += !!attr->headlen + skb_shinfo(skb)->nr_frags;
981 u16 inl = attr->ihs - INL_HDR_START_SZ;
983 ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS);
984 ds_cnt += ds_cnt_inl;
987 *wqe_attr = (struct mlx5e_tx_wqe_attr) {
989 .ds_cnt_inl = ds_cnt_inl,
990 .num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS),
994 void mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
995 struct mlx5_av *av, u32 dqpn, u32 dqkey, bool xmit_more)
997 struct mlx5e_tx_wqe_attr wqe_attr;
998 struct mlx5e_tx_attr attr;
999 struct mlx5i_tx_wqe *wqe;
1001 struct mlx5_wqe_datagram_seg *datagram;
1002 struct mlx5_wqe_ctrl_seg *cseg;
1003 struct mlx5_wqe_eth_seg *eseg;
1004 struct mlx5_wqe_data_seg *dseg;
1005 struct mlx5e_tx_wqe_info *wi;
1007 struct mlx5e_sq_stats *stats = sq->stats;
1011 mlx5e_sq_xmit_prepare(sq, skb, NULL, &attr);
1012 mlx5i_sq_calc_wqe_attr(skb, &attr, &wqe_attr);
1014 pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs);
1015 wqe = MLX5I_SQ_FETCH_WQE(sq, pi);
1017 stats->xmit_more += xmit_more;
1020 wi = &sq->db.wqe_info[pi];
1022 datagram = &wqe->datagram;
1026 mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram);
1028 mlx5e_txwqe_build_eseg_csum(sq, skb, NULL, eseg);
1030 eseg->mss = attr.mss;
1033 memcpy(eseg->inline_hdr.start, skb->data, attr.ihs);
1034 eseg->inline_hdr.sz = cpu_to_be16(attr.ihs);
1035 dseg += wqe_attr.ds_cnt_inl;
1038 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + attr.ihs,
1039 attr.headlen, dseg);
1040 if (unlikely(num_dma < 0))
1043 mlx5e_txwqe_complete(sq, skb, &attr, &wqe_attr, num_dma, wi, cseg, xmit_more);
1049 dev_kfree_skb_any(skb);