2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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33 #ifndef __MLX5_EN_TC_H__
34 #define __MLX5_EN_TC_H__
36 #include <net/pkt_cls.h>
39 #define MLX5E_TC_FLOW_ID_MASK 0x0000ffff
41 #ifdef CONFIG_MLX5_ESWITCH
43 struct tunnel_match_key {
44 struct flow_dissector_key_control enc_control;
45 struct flow_dissector_key_keyid enc_key_id;
46 struct flow_dissector_key_ports enc_tp;
47 struct flow_dissector_key_ip enc_ip;
49 struct flow_dissector_key_ipv4_addrs enc_ipv4;
50 struct flow_dissector_key_ipv6_addrs enc_ipv6;
56 struct tunnel_match_enc_opts {
57 struct flow_dissector_key_enc_opts key;
58 struct flow_dissector_key_enc_opts mask;
61 /* Tunnel_id mapping is TUNNEL_INFO_BITS + ENC_OPTS_BITS.
62 * Upper TUNNEL_INFO_BITS for general tunnel info.
63 * Lower ENC_OPTS_BITS bits for enc_opts.
65 #define TUNNEL_INFO_BITS 6
66 #define TUNNEL_INFO_BITS_MASK GENMASK(TUNNEL_INFO_BITS - 1, 0)
67 #define ENC_OPTS_BITS 2
68 #define ENC_OPTS_BITS_MASK GENMASK(ENC_OPTS_BITS - 1, 0)
69 #define TUNNEL_ID_BITS (TUNNEL_INFO_BITS + ENC_OPTS_BITS)
70 #define TUNNEL_ID_MASK GENMASK(TUNNEL_ID_BITS - 1, 0)
73 MLX5E_TC_FLAG_INGRESS_BIT,
74 MLX5E_TC_FLAG_EGRESS_BIT,
75 MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
76 MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
77 MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
78 MLX5E_TC_FLAG_LAST_EXPORTED_BIT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
81 #define MLX5_TC_FLAG(flag) BIT(MLX5E_TC_FLAG_##flag##_BIT)
83 int mlx5e_tc_esw_init(struct rhashtable *tc_ht);
84 void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht);
86 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
87 struct flow_cls_offload *f, unsigned long flags);
88 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
89 struct flow_cls_offload *f, unsigned long flags);
91 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
92 struct flow_cls_offload *f, unsigned long flags);
94 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
95 struct tc_cls_matchall_offload *f);
96 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
97 struct tc_cls_matchall_offload *f);
98 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
99 struct tc_cls_matchall_offload *ma);
101 struct mlx5e_encap_entry;
102 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
103 struct mlx5e_encap_entry *e,
104 struct list_head *flow_list);
105 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
106 struct mlx5e_encap_entry *e,
107 struct list_head *flow_list);
108 bool mlx5e_encap_take(struct mlx5e_encap_entry *e);
109 void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e);
111 void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list);
112 void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list);
114 struct mlx5e_neigh_hash_entry;
115 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe);
117 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags);
119 void mlx5e_tc_reoffload_flows_work(struct work_struct *work);
121 enum mlx5e_tc_attr_to_reg {
132 struct mlx5e_tc_attr_to_reg_mapping {
133 int mfield; /* rewrite field */
134 int moffset; /* offset of mfield */
135 int mlen; /* bytes to rewrite/match */
137 int soffset; /* offset of spec for match */
140 extern struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[];
142 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
143 struct net_device *out_dev);
145 struct mlx5e_tc_update_priv {
146 struct net_device *tun_dev;
149 struct mlx5e_tc_mod_hdr_acts {
155 int mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
156 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
157 enum mlx5e_tc_attr_to_reg type,
160 void mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
161 enum mlx5e_tc_attr_to_reg type,
165 int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
167 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts);
168 void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts);
170 struct mlx5e_tc_flow;
171 u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow);
173 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
175 int mlx5e_tc_nic_init(struct mlx5e_priv *priv);
176 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv);
178 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
181 #else /* CONFIG_MLX5_CLS_ACT */
182 static inline int mlx5e_tc_nic_init(struct mlx5e_priv *priv) { return 0; }
183 static inline void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) {}
185 mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv)
186 { return -EOPNOTSUPP; }
187 #endif /* CONFIG_MLX5_CLS_ACT */
189 #else /* CONFIG_MLX5_ESWITCH */
190 static inline int mlx5e_tc_nic_init(struct mlx5e_priv *priv) { return 0; }
191 static inline void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) {}
192 static inline int mlx5e_tc_num_filters(struct mlx5e_priv *priv,
199 mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv)
200 { return -EOPNOTSUPP; }
203 #endif /* __MLX5_EN_TC_H__ */