2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/flow_dissector.h>
34 #include <net/flow_offload.h>
35 #include <net/sch_generic.h>
36 #include <net/pkt_cls.h>
37 #include <net/tc_act/tc_gact.h>
38 #include <net/tc_act/tc_skbedit.h>
39 #include <linux/mlx5/fs.h>
40 #include <linux/mlx5/device.h>
41 #include <linux/rhashtable.h>
42 #include <linux/refcount.h>
43 #include <linux/completion.h>
44 #include <net/tc_act/tc_mirred.h>
45 #include <net/tc_act/tc_vlan.h>
46 #include <net/tc_act/tc_tunnel_key.h>
47 #include <net/tc_act/tc_pedit.h>
48 #include <net/tc_act/tc_csum.h>
49 #include <net/tc_act/tc_mpls.h>
51 #include <net/ipv6_stubs.h>
52 #include <net/bareudp.h>
53 #include <net/bonding.h>
56 #include "en/rep/tc.h"
57 #include "en/rep/neigh.h"
62 #include "en/tc_tun.h"
63 #include "en/mapping.h"
65 #include "en/mod_hdr.h"
66 #include "en/tc_priv.h"
67 #include "en/tc_tun_encap.h"
68 #include "lib/devcom.h"
69 #include "lib/geneve.h"
70 #include "lib/fs_chains.h"
71 #include "diag/en_tc_tracepoint.h"
72 #include <asm/div64.h>
74 #define nic_chains(priv) ((priv)->fs.tc.chains)
75 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
77 #define MLX5E_TC_TABLE_NUM_GROUPS 4
78 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
80 struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
82 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
87 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
92 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
94 .mlen = ((ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS) / 8),
95 .soffset = MLX5_BYTE_OFF(fte_match_param,
96 misc_parameters_2.metadata_reg_c_1),
98 [ZONE_TO_REG] = zone_to_reg_ct,
99 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
100 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
101 [MARK_TO_REG] = mark_to_reg_ct,
102 [LABELS_TO_REG] = labels_to_reg_ct,
103 [FTEID_TO_REG] = fteid_to_reg_ct,
104 /* For NIC rules we store the retore metadata directly
105 * into reg_b that is passed to SW since we don't
106 * jump between steering domains.
108 [NIC_CHAIN_TO_REG] = {
109 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
113 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
116 /* To avoid false lock dependency warning set the tc_ht lock
117 * class different than the lock class of the ht being used when deleting
118 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
119 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
120 * it's different than the ht->mutex here.
122 static struct lock_class_key tc_ht_lock_key;
124 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
127 mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
128 enum mlx5e_tc_attr_to_reg type,
132 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
133 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
134 void *headers_c = spec->match_criteria;
135 void *headers_v = spec->match_value;
138 fmask = headers_c + soffset;
139 fval = headers_v + soffset;
141 mask = (__force u32)(cpu_to_be32(mask)) >> (32 - (match_len * 8));
142 data = (__force u32)(cpu_to_be32(data)) >> (32 - (match_len * 8));
144 memcpy(fmask, &mask, match_len);
145 memcpy(fval, &data, match_len);
147 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
151 mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
152 enum mlx5e_tc_attr_to_reg type,
156 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
157 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
158 void *headers_c = spec->match_criteria;
159 void *headers_v = spec->match_value;
162 fmask = headers_c + soffset;
163 fval = headers_v + soffset;
165 memcpy(mask, fmask, match_len);
166 memcpy(data, fval, match_len);
168 *mask = be32_to_cpu((__force __be32)(*mask << (32 - (match_len * 8))));
169 *data = be32_to_cpu((__force __be32)(*data << (32 - (match_len * 8))));
173 mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
174 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
175 enum mlx5_flow_namespace_type ns,
176 enum mlx5e_tc_attr_to_reg type,
179 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
180 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
181 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
185 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
189 modact = mod_hdr_acts->actions +
190 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
192 /* Firmware has 5bit length field and 0 means 32bits */
196 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
197 MLX5_SET(set_action_in, modact, field, mfield);
198 MLX5_SET(set_action_in, modact, offset, moffset * 8);
199 MLX5_SET(set_action_in, modact, length, mlen * 8);
200 MLX5_SET(set_action_in, modact, data, data);
201 err = mod_hdr_acts->num_actions;
202 mod_hdr_acts->num_actions++;
207 static struct mlx5_tc_ct_priv *
208 get_ct_priv(struct mlx5e_priv *priv)
210 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
211 struct mlx5_rep_uplink_priv *uplink_priv;
212 struct mlx5e_rep_priv *uplink_rpriv;
214 if (is_mdev_switchdev_mode(priv->mdev)) {
215 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
216 uplink_priv = &uplink_rpriv->uplink_priv;
218 return uplink_priv->ct_priv;
221 return priv->fs.tc.ct;
224 struct mlx5_flow_handle *
225 mlx5_tc_rule_insert(struct mlx5e_priv *priv,
226 struct mlx5_flow_spec *spec,
227 struct mlx5_flow_attr *attr)
229 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
231 if (is_mdev_switchdev_mode(priv->mdev))
232 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
234 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
238 mlx5_tc_rule_delete(struct mlx5e_priv *priv,
239 struct mlx5_flow_handle *rule,
240 struct mlx5_flow_attr *attr)
242 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
244 if (is_mdev_switchdev_mode(priv->mdev)) {
245 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
250 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
254 mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
255 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
256 enum mlx5_flow_namespace_type ns,
257 enum mlx5e_tc_attr_to_reg type,
260 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
262 return ret < 0 ? ret : 0;
265 void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
266 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
267 enum mlx5e_tc_attr_to_reg type,
268 int act_id, u32 data)
270 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
271 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
272 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
275 modact = mod_hdr_acts->actions + (act_id * MLX5_MH_ACT_SZ);
277 /* Firmware has 5bit length field and 0 means 32bits */
281 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
282 MLX5_SET(set_action_in, modact, field, mfield);
283 MLX5_SET(set_action_in, modact, offset, moffset * 8);
284 MLX5_SET(set_action_in, modact, length, mlen * 8);
285 MLX5_SET(set_action_in, modact, data, data);
288 struct mlx5e_hairpin {
289 struct mlx5_hairpin *pair;
291 struct mlx5_core_dev *func_mdev;
292 struct mlx5e_priv *func_priv;
297 struct mlx5e_rqt indir_rqt;
298 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
299 struct mlx5e_ttc_table ttc;
302 struct mlx5e_hairpin_entry {
303 /* a node of a hash table which keeps all the hairpin entries */
304 struct hlist_node hairpin_hlist;
306 /* protects flows list */
307 spinlock_t flows_lock;
308 /* flows sharing the same hairpin */
309 struct list_head flows;
310 /* hpe's that were not fully initialized when dead peer update event
311 * function traversed them.
313 struct list_head dead_peer_wait_list;
317 struct mlx5e_hairpin *hp;
319 struct completion res_ready;
322 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
323 struct mlx5e_tc_flow *flow);
325 struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
327 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
328 return ERR_PTR(-EINVAL);
332 void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
334 if (refcount_dec_and_test(&flow->refcnt)) {
335 mlx5e_tc_del_flow(priv, flow);
336 kfree_rcu(flow, rcu_head);
340 bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
342 return flow_flag_test(flow, ESWITCH);
345 static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
347 return flow_flag_test(flow, FT);
350 bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
352 return flow_flag_test(flow, OFFLOADED);
355 static int get_flow_name_space(struct mlx5e_tc_flow *flow)
357 return mlx5e_is_eswitch_flow(flow) ?
358 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
361 static struct mod_hdr_tbl *
362 get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
364 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
366 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
367 &esw->offloads.mod_hdr :
368 &priv->fs.tc.mod_hdr;
371 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
372 struct mlx5e_tc_flow *flow,
373 struct mlx5e_tc_flow_parse_attr *parse_attr)
375 struct mlx5_modify_hdr *modify_hdr;
376 struct mlx5e_mod_hdr_handle *mh;
378 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
379 get_flow_name_space(flow),
380 &parse_attr->mod_hdr_acts);
384 modify_hdr = mlx5e_mod_hdr_get(mh);
385 flow->attr->modify_hdr = modify_hdr;
391 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
392 struct mlx5e_tc_flow *flow)
394 /* flow wasn't fully initialized */
398 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
404 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
406 struct net_device *netdev;
407 struct mlx5e_priv *priv;
409 netdev = __dev_get_by_index(net, ifindex);
410 priv = netdev_priv(netdev);
414 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
416 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
420 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
424 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
426 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
427 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
428 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
430 err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn);
437 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
442 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
444 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
445 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
448 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
450 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
451 struct mlx5e_priv *priv = hp->func_priv;
452 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
454 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
457 for (i = 0; i < sz; i++) {
459 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
460 ix = mlx5e_bits_invert(i, ilog2(sz));
461 ix = indirection_rqt[ix];
462 rqn = hp->pair->rqn[ix];
463 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
467 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
469 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
470 struct mlx5e_priv *priv = hp->func_priv;
471 struct mlx5_core_dev *mdev = priv->mdev;
475 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
476 in = kvzalloc(inlen, GFP_KERNEL);
480 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
482 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
483 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
485 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
487 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
489 hp->indir_rqt.enabled = true;
495 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
497 struct mlx5e_priv *priv = hp->func_priv;
498 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
502 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
503 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
505 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
506 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
508 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
509 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
510 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
511 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
513 err = mlx5_core_create_tir(hp->func_mdev, in,
514 &hp->indir_tirn[tt]);
516 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
517 goto err_destroy_tirs;
523 for (i = 0; i < tt; i++)
524 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
528 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
532 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
533 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
536 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
537 struct ttc_params *ttc_params)
539 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
542 memset(ttc_params, 0, sizeof(*ttc_params));
544 ttc_params->any_tt_tirn = hp->tirn;
546 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
547 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
549 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
550 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
551 ft_attr->prio = MLX5E_TC_PRIO;
554 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
556 struct mlx5e_priv *priv = hp->func_priv;
557 struct ttc_params ttc_params;
560 err = mlx5e_hairpin_create_indirect_rqt(hp);
564 err = mlx5e_hairpin_create_indirect_tirs(hp);
566 goto err_create_indirect_tirs;
568 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
569 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
571 goto err_create_ttc_table;
573 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
574 hp->num_channels, hp->ttc.ft.t->id);
578 err_create_ttc_table:
579 mlx5e_hairpin_destroy_indirect_tirs(hp);
580 err_create_indirect_tirs:
581 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
586 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
588 struct mlx5e_priv *priv = hp->func_priv;
590 mlx5e_destroy_ttc_table(priv, &hp->ttc);
591 mlx5e_hairpin_destroy_indirect_tirs(hp);
592 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
595 static struct mlx5e_hairpin *
596 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
599 struct mlx5_core_dev *func_mdev, *peer_mdev;
600 struct mlx5e_hairpin *hp;
601 struct mlx5_hairpin *pair;
604 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
606 return ERR_PTR(-ENOMEM);
608 func_mdev = priv->mdev;
609 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
611 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
614 goto create_pair_err;
617 hp->func_mdev = func_mdev;
618 hp->func_priv = priv;
619 hp->num_channels = params->num_channels;
621 err = mlx5e_hairpin_create_transport(hp);
623 goto create_transport_err;
625 if (hp->num_channels > 1) {
626 err = mlx5e_hairpin_rss_init(hp);
634 mlx5e_hairpin_destroy_transport(hp);
635 create_transport_err:
636 mlx5_core_hairpin_destroy(hp->pair);
642 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
644 if (hp->num_channels > 1)
645 mlx5e_hairpin_rss_cleanup(hp);
646 mlx5e_hairpin_destroy_transport(hp);
647 mlx5_core_hairpin_destroy(hp->pair);
651 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
653 return (peer_vhca_id << 16 | prio);
656 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
657 u16 peer_vhca_id, u8 prio)
659 struct mlx5e_hairpin_entry *hpe;
660 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
662 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
663 hairpin_hlist, hash_key) {
664 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
665 refcount_inc(&hpe->refcnt);
673 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
674 struct mlx5e_hairpin_entry *hpe)
676 /* no more hairpin flows for us, release the hairpin pair */
677 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
679 hash_del(&hpe->hairpin_hlist);
680 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
682 if (!IS_ERR_OR_NULL(hpe->hp)) {
683 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
684 dev_name(hpe->hp->pair->peer_mdev->device));
686 mlx5e_hairpin_destroy(hpe->hp);
689 WARN_ON(!list_empty(&hpe->flows));
693 #define UNKNOWN_MATCH_PRIO 8
695 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
696 struct mlx5_flow_spec *spec, u8 *match_prio,
697 struct netlink_ext_ack *extack)
699 void *headers_c, *headers_v;
700 u8 prio_val, prio_mask = 0;
703 #ifdef CONFIG_MLX5_CORE_EN_DCB
704 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
705 NL_SET_ERR_MSG_MOD(extack,
706 "only PCP trust state supported for hairpin");
710 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
711 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
713 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
715 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
716 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
719 if (!vlan_present || !prio_mask) {
720 prio_val = UNKNOWN_MATCH_PRIO;
721 } else if (prio_mask != 0x7) {
722 NL_SET_ERR_MSG_MOD(extack,
723 "masked priority match not supported for hairpin");
727 *match_prio = prio_val;
731 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
732 struct mlx5e_tc_flow *flow,
733 struct mlx5e_tc_flow_parse_attr *parse_attr,
734 struct netlink_ext_ack *extack)
736 int peer_ifindex = parse_attr->mirred_ifindex[0];
737 struct mlx5_hairpin_params params;
738 struct mlx5_core_dev *peer_mdev;
739 struct mlx5e_hairpin_entry *hpe;
740 struct mlx5e_hairpin *hp;
747 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
748 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
749 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
753 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
754 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
759 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
760 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
762 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
763 wait_for_completion(&hpe->res_ready);
765 if (IS_ERR(hpe->hp)) {
772 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
774 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
778 spin_lock_init(&hpe->flows_lock);
779 INIT_LIST_HEAD(&hpe->flows);
780 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
781 hpe->peer_vhca_id = peer_id;
782 hpe->prio = match_prio;
783 refcount_set(&hpe->refcnt, 1);
784 init_completion(&hpe->res_ready);
786 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
787 hash_hairpin_info(peer_id, match_prio));
788 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
790 params.log_data_size = 15;
791 params.log_data_size = min_t(u8, params.log_data_size,
792 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
793 params.log_data_size = max_t(u8, params.log_data_size,
794 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
796 params.log_num_packets = params.log_data_size -
797 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
798 params.log_num_packets = min_t(u8, params.log_num_packets,
799 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
801 params.q_counter = priv->q_counter;
802 /* set hairpin pair per each 50Gbs share of the link */
803 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
804 link_speed = max_t(u32, link_speed, 50000);
805 link_speed64 = link_speed;
806 do_div(link_speed64, 50000);
807 params.num_channels = link_speed64;
809 hp = mlx5e_hairpin_create(priv, ¶ms, peer_ifindex);
811 complete_all(&hpe->res_ready);
817 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
818 hp->tirn, hp->pair->rqn[0],
819 dev_name(hp->pair->peer_mdev->device),
820 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
823 if (hpe->hp->num_channels > 1) {
824 flow_flag_set(flow, HAIRPIN_RSS);
825 flow->attr->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
827 flow->attr->nic_attr->hairpin_tirn = hpe->hp->tirn;
831 spin_lock(&hpe->flows_lock);
832 list_add(&flow->hairpin, &hpe->flows);
833 spin_unlock(&hpe->flows_lock);
838 mlx5e_hairpin_put(priv, hpe);
842 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
843 struct mlx5e_tc_flow *flow)
845 /* flow wasn't fully initialized */
849 spin_lock(&flow->hpe->flows_lock);
850 list_del(&flow->hairpin);
851 spin_unlock(&flow->hpe->flows_lock);
853 mlx5e_hairpin_put(priv, flow->hpe);
857 struct mlx5_flow_handle *
858 mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
859 struct mlx5_flow_spec *spec,
860 struct mlx5_flow_attr *attr)
862 struct mlx5_flow_context *flow_context = &spec->flow_context;
863 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
864 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
865 struct mlx5e_tc_table *tc = &priv->fs.tc;
866 struct mlx5_flow_destination dest[2] = {};
867 struct mlx5_flow_act flow_act = {
868 .action = attr->action,
869 .flags = FLOW_ACT_NO_APPEND,
871 struct mlx5_flow_handle *rule;
872 struct mlx5_flow_table *ft;
875 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
876 flow_context->flow_tag = nic_attr->flow_tag;
879 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
880 dest[dest_ix].ft = attr->dest_ft;
882 } else if (nic_attr->hairpin_ft) {
883 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
884 dest[dest_ix].ft = nic_attr->hairpin_ft;
886 } else if (nic_attr->hairpin_tirn) {
887 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
888 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
890 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
891 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
892 if (attr->dest_chain) {
893 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
896 if (IS_ERR(dest[dest_ix].ft))
897 return ERR_CAST(dest[dest_ix].ft);
899 dest[dest_ix].ft = priv->fs.vlan.ft.t;
904 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
905 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
906 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
908 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
909 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
910 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
914 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
915 flow_act.modify_hdr = attr->modify_hdr;
917 mutex_lock(&tc->t_lock);
918 if (IS_ERR_OR_NULL(tc->t)) {
919 /* Create the root table here if doesn't exist yet */
921 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
924 mutex_unlock(&tc->t_lock);
925 netdev_err(priv->netdev,
926 "Failed to create tc offload table\n");
927 rule = ERR_CAST(priv->fs.tc.t);
931 mutex_unlock(&tc->t_lock);
933 if (attr->chain || attr->prio)
934 ft = mlx5_chains_get_table(nic_chains,
935 attr->chain, attr->prio,
945 if (attr->outer_match_level != MLX5_MATCH_NONE)
946 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
948 rule = mlx5_add_flow_rules(ft, spec,
949 &flow_act, dest, dest_ix);
956 if (attr->chain || attr->prio)
957 mlx5_chains_put_table(nic_chains,
958 attr->chain, attr->prio,
961 if (attr->dest_chain)
962 mlx5_chains_put_table(nic_chains,
966 return ERR_CAST(rule);
970 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
971 struct mlx5e_tc_flow_parse_attr *parse_attr,
972 struct mlx5e_tc_flow *flow,
973 struct netlink_ext_ack *extack)
975 struct mlx5_flow_attr *attr = flow->attr;
976 struct mlx5_core_dev *dev = priv->mdev;
977 struct mlx5_fc *counter = NULL;
980 if (flow_flag_test(flow, HAIRPIN)) {
981 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
986 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
987 counter = mlx5_fc_create(dev, true);
989 return PTR_ERR(counter);
991 attr->counter = counter;
994 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
995 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
996 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1001 if (flow_flag_test(flow, CT))
1002 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1003 attr, &parse_attr->mod_hdr_acts);
1005 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1008 return PTR_ERR_OR_ZERO(flow->rule[0]);
1011 void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
1012 struct mlx5_flow_handle *rule,
1013 struct mlx5_flow_attr *attr)
1015 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1017 mlx5_del_flow_rules(rule);
1019 if (attr->chain || attr->prio)
1020 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1023 if (attr->dest_chain)
1024 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1028 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1029 struct mlx5e_tc_flow *flow)
1031 struct mlx5_flow_attr *attr = flow->attr;
1032 struct mlx5e_tc_table *tc = &priv->fs.tc;
1034 flow_flag_clear(flow, OFFLOADED);
1036 if (flow_flag_test(flow, CT))
1037 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1038 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1039 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1041 /* Remove root table if no rules are left to avoid
1042 * extra steering hops.
1044 mutex_lock(&priv->fs.tc.t_lock);
1045 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1046 !IS_ERR_OR_NULL(tc->t)) {
1047 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
1048 priv->fs.tc.t = NULL;
1050 mutex_unlock(&priv->fs.tc.t_lock);
1052 kvfree(attr->parse_attr);
1054 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1055 mlx5e_detach_mod_hdr(priv, flow);
1057 mlx5_fc_destroy(priv->mdev, attr->counter);
1059 if (flow_flag_test(flow, HAIRPIN))
1060 mlx5e_hairpin_flow_del(priv, flow);
1065 struct mlx5_flow_handle *
1066 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1067 struct mlx5e_tc_flow *flow,
1068 struct mlx5_flow_spec *spec,
1069 struct mlx5_flow_attr *attr)
1071 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1072 struct mlx5_flow_handle *rule;
1074 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1075 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1077 if (flow_flag_test(flow, CT)) {
1078 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1080 return mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
1085 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1089 if (attr->esw_attr->split_count) {
1090 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1091 if (IS_ERR(flow->rule[1])) {
1092 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1093 return flow->rule[1];
1100 void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1101 struct mlx5e_tc_flow *flow,
1102 struct mlx5_flow_attr *attr)
1104 flow_flag_clear(flow, OFFLOADED);
1106 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1107 goto offload_rule_0;
1109 if (flow_flag_test(flow, CT)) {
1110 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1114 if (attr->esw_attr->split_count)
1115 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1118 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1121 struct mlx5_flow_handle *
1122 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1123 struct mlx5e_tc_flow *flow,
1124 struct mlx5_flow_spec *spec)
1126 struct mlx5_flow_attr *slow_attr;
1127 struct mlx5_flow_handle *rule;
1129 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1131 return ERR_PTR(-ENOMEM);
1133 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1134 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1135 slow_attr->esw_attr->split_count = 0;
1136 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1138 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1140 flow_flag_set(flow, SLOW);
1147 void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1148 struct mlx5e_tc_flow *flow)
1150 struct mlx5_flow_attr *slow_attr;
1152 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1154 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1158 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1159 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1160 slow_attr->esw_attr->split_count = 0;
1161 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1162 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
1163 flow_flag_clear(flow, SLOW);
1167 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1170 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1171 struct list_head *unready_flows)
1173 flow_flag_set(flow, NOT_READY);
1174 list_add_tail(&flow->unready, unready_flows);
1177 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1180 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1182 list_del(&flow->unready);
1183 flow_flag_clear(flow, NOT_READY);
1186 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1188 struct mlx5_rep_uplink_priv *uplink_priv;
1189 struct mlx5e_rep_priv *rpriv;
1190 struct mlx5_eswitch *esw;
1192 esw = flow->priv->mdev->priv.eswitch;
1193 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1194 uplink_priv = &rpriv->uplink_priv;
1196 mutex_lock(&uplink_priv->unready_flows_lock);
1197 unready_flow_add(flow, &uplink_priv->unready_flows);
1198 mutex_unlock(&uplink_priv->unready_flows_lock);
1201 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1203 struct mlx5_rep_uplink_priv *uplink_priv;
1204 struct mlx5e_rep_priv *rpriv;
1205 struct mlx5_eswitch *esw;
1207 esw = flow->priv->mdev->priv.eswitch;
1208 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1209 uplink_priv = &rpriv->uplink_priv;
1211 mutex_lock(&uplink_priv->unready_flows_lock);
1212 unready_flow_del(flow);
1213 mutex_unlock(&uplink_priv->unready_flows_lock);
1216 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1218 bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
1220 struct mlx5_core_dev *out_mdev, *route_mdev;
1221 struct mlx5e_priv *out_priv, *route_priv;
1223 out_priv = netdev_priv(out_dev);
1224 out_mdev = out_priv->mdev;
1225 route_priv = netdev_priv(route_dev);
1226 route_mdev = route_priv->mdev;
1228 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1229 route_mdev->coredev_type != MLX5_COREDEV_VF)
1232 return same_hw_devs(out_priv, route_priv);
1235 int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
1237 struct mlx5e_priv *out_priv, *route_priv;
1238 struct mlx5_core_dev *route_mdev;
1239 struct mlx5_eswitch *esw;
1243 out_priv = netdev_priv(out_dev);
1244 esw = out_priv->mdev->priv.eswitch;
1245 route_priv = netdev_priv(route_dev);
1246 route_mdev = route_priv->mdev;
1248 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1249 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1253 int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1254 struct mlx5e_tc_flow_parse_attr *parse_attr,
1255 struct mlx5e_tc_flow *flow)
1257 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1258 struct mlx5_modify_hdr *mod_hdr;
1260 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
1261 get_flow_name_space(flow),
1262 mod_hdr_acts->num_actions,
1263 mod_hdr_acts->actions);
1264 if (IS_ERR(mod_hdr))
1265 return PTR_ERR(mod_hdr);
1267 WARN_ON(flow->attr->modify_hdr);
1268 flow->attr->modify_hdr = mod_hdr;
1274 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1275 struct mlx5e_tc_flow *flow,
1276 struct netlink_ext_ack *extack)
1278 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1279 struct net_device *out_dev, *encap_dev = NULL;
1280 struct mlx5e_tc_flow_parse_attr *parse_attr;
1281 struct mlx5_flow_attr *attr = flow->attr;
1282 bool vf_tun = false, encap_valid = true;
1283 struct mlx5_esw_flow_attr *esw_attr;
1284 struct mlx5_fc *counter = NULL;
1285 struct mlx5e_rep_priv *rpriv;
1286 struct mlx5e_priv *out_priv;
1287 u32 max_prio, max_chain;
1291 /* We check chain range only for tc flows.
1292 * For ft flows, we checked attr->chain was originally 0 and set it to
1293 * FDB_FT_CHAIN which is outside tc range.
1294 * See mlx5e_rep_setup_ft_cb().
1296 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
1297 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
1298 NL_SET_ERR_MSG_MOD(extack,
1299 "Requested chain is out of supported range");
1304 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
1305 if (attr->prio > max_prio) {
1306 NL_SET_ERR_MSG_MOD(extack,
1307 "Requested priority is out of supported range");
1312 if (flow_flag_test(flow, TUN_RX)) {
1313 err = mlx5e_attach_decap_route(priv, flow);
1318 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1319 err = mlx5e_attach_decap(priv, flow, extack);
1324 parse_attr = attr->parse_attr;
1325 esw_attr = attr->esw_attr;
1327 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1330 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1333 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
1334 out_dev = __dev_get_by_index(dev_net(priv->netdev),
1336 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
1337 extack, &encap_dev, &encap_valid);
1341 if (esw_attr->dests[out_index].flags &
1342 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1344 out_priv = netdev_priv(encap_dev);
1345 rpriv = out_priv->ppriv;
1346 esw_attr->dests[out_index].rep = rpriv->rep;
1347 esw_attr->dests[out_index].mdev = out_priv->mdev;
1350 err = mlx5_eswitch_add_vlan_action(esw, attr);
1354 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1355 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
1357 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1361 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1367 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1368 counter = mlx5_fc_create(esw_attr->counter_dev, true);
1369 if (IS_ERR(counter)) {
1370 err = PTR_ERR(counter);
1374 attr->counter = counter;
1377 /* we get here if one of the following takes place:
1378 * (1) there's no error
1379 * (2) there's an encap action and we don't have valid neigh
1382 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
1384 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
1386 if (IS_ERR(flow->rule[0])) {
1387 err = PTR_ERR(flow->rule[0]);
1390 flow_flag_set(flow, OFFLOADED);
1395 flow_flag_set(flow, FAILED);
1399 static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1401 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
1402 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1405 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1407 geneve_tlv_option_0_data);
1409 return !!geneve_tlv_opt_0_data;
1412 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1413 struct mlx5e_tc_flow *flow)
1415 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1416 struct mlx5_flow_attr *attr = flow->attr;
1417 struct mlx5_esw_flow_attr *esw_attr;
1418 bool vf_tun = false;
1421 esw_attr = attr->esw_attr;
1422 mlx5e_put_flow_tunnel_id(flow);
1424 if (flow_flag_test(flow, NOT_READY))
1425 remove_unready_flow(flow);
1427 if (mlx5e_is_offloaded_flow(flow)) {
1428 if (flow_flag_test(flow, SLOW))
1429 mlx5e_tc_unoffload_from_slow_path(esw, flow);
1431 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1434 if (mlx5_flow_has_geneve_opt(flow))
1435 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1437 mlx5_eswitch_del_vlan_action(esw, attr);
1439 if (flow->decap_route)
1440 mlx5e_detach_decap_route(priv, flow);
1442 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1443 if (esw_attr->dests[out_index].flags &
1444 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1446 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
1447 mlx5e_detach_encap(priv, flow, out_index);
1448 kfree(attr->parse_attr->tun_info[out_index]);
1452 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
1454 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1455 dealloc_mod_hdr_actions(&attr->parse_attr->mod_hdr_acts);
1456 if (vf_tun && attr->modify_hdr)
1457 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1459 mlx5e_detach_mod_hdr(priv, flow);
1461 kvfree(attr->parse_attr);
1462 kvfree(attr->esw_attr->rx_tun_attr);
1464 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1465 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
1467 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1468 mlx5e_detach_decap(priv, flow);
1473 struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1475 return flow->attr->counter;
1478 /* Iterate over tmp_list of flows attached to flow_list head. */
1479 void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
1481 struct mlx5e_tc_flow *flow, *tmp;
1483 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1484 mlx5e_flow_put(priv, flow);
1487 static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1489 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1491 if (!flow_flag_test(flow, ESWITCH) ||
1492 !flow_flag_test(flow, DUP))
1495 mutex_lock(&esw->offloads.peer_mutex);
1496 list_del(&flow->peer);
1497 mutex_unlock(&esw->offloads.peer_mutex);
1499 flow_flag_clear(flow, DUP);
1501 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1502 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1503 kfree(flow->peer_flow);
1506 flow->peer_flow = NULL;
1509 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1511 struct mlx5_core_dev *dev = flow->priv->mdev;
1512 struct mlx5_devcom *devcom = dev->priv.devcom;
1513 struct mlx5_eswitch *peer_esw;
1515 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1519 __mlx5e_tc_del_fdb_peer_flow(flow);
1520 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1523 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1524 struct mlx5e_tc_flow *flow)
1526 if (mlx5e_is_eswitch_flow(flow)) {
1527 mlx5e_tc_del_fdb_peer_flow(flow);
1528 mlx5e_tc_del_fdb_flow(priv, flow);
1530 mlx5e_tc_del_nic_flow(priv, flow);
1534 static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1536 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1537 struct flow_action *flow_action = &rule->action;
1538 const struct flow_action_entry *act;
1541 flow_action_for_each(i, act, flow_action) {
1543 case FLOW_ACTION_GOTO:
1554 enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1555 struct flow_dissector_key_enc_opts *opts,
1556 struct netlink_ext_ack *extack,
1559 struct geneve_opt *opt;
1564 while (opts->len > off) {
1565 opt = (struct geneve_opt *)&opts->data[off];
1567 if (!(*dont_care) || opt->opt_class || opt->type ||
1568 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1571 if (opt->opt_class != htons(U16_MAX) ||
1572 opt->type != U8_MAX) {
1573 NL_SET_ERR_MSG(extack,
1574 "Partial match of tunnel options in chain > 0 isn't supported");
1575 netdev_warn(priv->netdev,
1576 "Partial match of tunnel options in chain > 0 isn't supported");
1581 off += sizeof(struct geneve_opt) + opt->length * 4;
1587 #define COPY_DISSECTOR(rule, diss_key, dst)\
1589 struct flow_rule *__rule = (rule);\
1590 typeof(dst) __dst = dst;\
1593 skb_flow_dissector_target(__rule->match.dissector,\
1595 __rule->match.key),\
1599 static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1600 struct mlx5e_tc_flow *flow,
1601 struct flow_cls_offload *f,
1602 struct net_device *filter_dev)
1604 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1605 struct netlink_ext_ack *extack = f->common.extack;
1606 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1607 struct flow_match_enc_opts enc_opts_match;
1608 struct tunnel_match_enc_opts tun_enc_opts;
1609 struct mlx5_rep_uplink_priv *uplink_priv;
1610 struct mlx5_flow_attr *attr = flow->attr;
1611 struct mlx5e_rep_priv *uplink_rpriv;
1612 struct tunnel_match_key tunnel_key;
1613 bool enc_opts_is_dont_care = true;
1614 u32 tun_id, enc_opts_id = 0;
1615 struct mlx5_eswitch *esw;
1619 esw = priv->mdev->priv.eswitch;
1620 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1621 uplink_priv = &uplink_rpriv->uplink_priv;
1623 memset(&tunnel_key, 0, sizeof(tunnel_key));
1624 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1625 &tunnel_key.enc_control);
1626 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1627 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1628 &tunnel_key.enc_ipv4);
1630 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1631 &tunnel_key.enc_ipv6);
1632 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1633 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1634 &tunnel_key.enc_tp);
1635 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1636 &tunnel_key.enc_key_id);
1637 tunnel_key.filter_ifindex = filter_dev->ifindex;
1639 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1643 flow_rule_match_enc_opts(rule, &enc_opts_match);
1644 err = enc_opts_is_dont_care_or_full_match(priv,
1645 enc_opts_match.mask,
1647 &enc_opts_is_dont_care);
1651 if (!enc_opts_is_dont_care) {
1652 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1653 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1654 sizeof(*enc_opts_match.key));
1655 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1656 sizeof(*enc_opts_match.mask));
1658 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
1659 &tun_enc_opts, &enc_opts_id);
1664 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1665 mask = enc_opts_id ? TUNNEL_ID_MASK :
1666 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
1669 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1670 TUNNEL_TO_REG, value, mask);
1672 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1673 err = mlx5e_tc_match_to_reg_set(priv->mdev,
1674 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
1675 TUNNEL_TO_REG, value);
1679 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1682 flow->tunnel_id = value;
1687 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1690 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1694 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1696 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1697 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1698 struct mlx5_rep_uplink_priv *uplink_priv;
1699 struct mlx5e_rep_priv *uplink_rpriv;
1700 struct mlx5_eswitch *esw;
1702 esw = flow->priv->mdev->priv.eswitch;
1703 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1704 uplink_priv = &uplink_rpriv->uplink_priv;
1707 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1709 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1713 u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1715 return flow->tunnel_id;
1718 void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1719 struct flow_match_basic *match, bool outer,
1720 void *headers_c, void *headers_v)
1722 bool ip_version_cap;
1724 ip_version_cap = outer ?
1725 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1726 ft_field_support.outer_ip_version) :
1727 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1728 ft_field_support.inner_ip_version);
1730 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1731 (match->key->n_proto == htons(ETH_P_IP) ||
1732 match->key->n_proto == htons(ETH_P_IPV6))) {
1733 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1734 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1735 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1737 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1738 ntohs(match->mask->n_proto));
1739 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1740 ntohs(match->key->n_proto));
1744 u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
1751 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1753 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1755 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1756 /* Return ip_version converted from ethertype anyway */
1758 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1759 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1761 else if (ethertype == ETH_P_IPV6)
1767 static int parse_tunnel_attr(struct mlx5e_priv *priv,
1768 struct mlx5e_tc_flow *flow,
1769 struct mlx5_flow_spec *spec,
1770 struct flow_cls_offload *f,
1771 struct net_device *filter_dev,
1775 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
1776 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1777 struct netlink_ext_ack *extack = f->common.extack;
1778 bool needs_mapping, sets_mapping;
1781 if (!mlx5e_is_eswitch_flow(flow))
1784 needs_mapping = !!flow->attr->chain;
1785 sets_mapping = !flow->attr->chain && flow_has_tc_fwd_action(f);
1786 *match_inner = !needs_mapping;
1788 if ((needs_mapping || sets_mapping) &&
1789 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1790 NL_SET_ERR_MSG(extack,
1791 "Chains on tunnel devices isn't supported without register loopback support");
1792 netdev_warn(priv->netdev,
1793 "Chains on tunnel devices isn't supported without register loopback support");
1797 if (!flow->attr->chain) {
1798 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1801 NL_SET_ERR_MSG_MOD(extack,
1802 "Failed to parse tunnel attributes");
1803 netdev_warn(priv->netdev,
1804 "Failed to parse tunnel attributes");
1808 /* With mpls over udp we decapsulate using packet reformat
1811 if (!netif_is_bareudp(filter_dev))
1812 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
1813 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
1816 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
1817 struct mlx5_flow_spec *tmp_spec;
1819 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
1821 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
1822 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
1825 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
1827 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
1830 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
1831 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
1834 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
1840 if (!needs_mapping && !sets_mapping)
1843 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
1846 static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
1848 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1852 static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
1854 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1858 static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
1860 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1864 static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
1866 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1870 static void *get_match_headers_value(u32 flags,
1871 struct mlx5_flow_spec *spec)
1873 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1874 get_match_inner_headers_value(spec) :
1875 get_match_outer_headers_value(spec);
1878 static void *get_match_headers_criteria(u32 flags,
1879 struct mlx5_flow_spec *spec)
1881 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1882 get_match_inner_headers_criteria(spec) :
1883 get_match_outer_headers_criteria(spec);
1886 static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
1887 struct flow_cls_offload *f)
1889 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1890 struct netlink_ext_ack *extack = f->common.extack;
1891 struct net_device *ingress_dev;
1892 struct flow_match_meta match;
1894 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
1897 flow_rule_match_meta(rule, &match);
1898 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
1899 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
1903 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
1904 match.key->ingress_ifindex);
1906 NL_SET_ERR_MSG_MOD(extack,
1907 "Can't find the ingress port to match on");
1911 if (ingress_dev != filter_dev) {
1912 NL_SET_ERR_MSG_MOD(extack,
1913 "Can't match on the ingress filter port");
1920 static bool skip_key_basic(struct net_device *filter_dev,
1921 struct flow_cls_offload *f)
1923 /* When doing mpls over udp decap, the user needs to provide
1924 * MPLS_UC as the protocol in order to be able to match on mpls
1925 * label fields. However, the actual ethertype is IP so we want to
1926 * avoid matching on this, otherwise we'll fail the match.
1928 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
1934 static int __parse_cls_flower(struct mlx5e_priv *priv,
1935 struct mlx5e_tc_flow *flow,
1936 struct mlx5_flow_spec *spec,
1937 struct flow_cls_offload *f,
1938 struct net_device *filter_dev,
1939 u8 *inner_match_level, u8 *outer_match_level)
1941 struct netlink_ext_ack *extack = f->common.extack;
1942 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1944 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1946 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1948 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1950 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1951 struct flow_dissector *dissector = rule->match.dissector;
1957 match_level = outer_match_level;
1959 if (dissector->used_keys &
1960 ~(BIT(FLOW_DISSECTOR_KEY_META) |
1961 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1962 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1963 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
1964 BIT(FLOW_DISSECTOR_KEY_VLAN) |
1965 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
1966 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1967 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
1968 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1969 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1970 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1971 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1972 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
1973 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
1974 BIT(FLOW_DISSECTOR_KEY_TCP) |
1975 BIT(FLOW_DISSECTOR_KEY_IP) |
1976 BIT(FLOW_DISSECTOR_KEY_CT) |
1977 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1978 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
1979 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
1980 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
1981 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
1982 dissector->used_keys);
1986 if (mlx5e_get_tc_tun(filter_dev)) {
1987 bool match_inner = false;
1989 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
1990 outer_match_level, &match_inner);
1995 /* header pointers should point to the inner headers
1996 * if the packet was decapsulated already.
1997 * outer headers are set by parse_tunnel_attr.
1999 match_level = inner_match_level;
2000 headers_c = get_match_inner_headers_criteria(spec);
2001 headers_v = get_match_inner_headers_value(spec);
2005 err = mlx5e_flower_parse_meta(filter_dev, f);
2009 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2010 !skip_key_basic(filter_dev, f)) {
2011 struct flow_match_basic match;
2013 flow_rule_match_basic(rule, &match);
2014 mlx5e_tc_set_ethertype(priv->mdev, &match,
2015 match_level == outer_match_level,
2016 headers_c, headers_v);
2018 if (match.mask->n_proto)
2019 *match_level = MLX5_MATCH_L2;
2021 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2022 is_vlan_dev(filter_dev)) {
2023 struct flow_dissector_key_vlan filter_dev_mask;
2024 struct flow_dissector_key_vlan filter_dev_key;
2025 struct flow_match_vlan match;
2027 if (is_vlan_dev(filter_dev)) {
2028 match.key = &filter_dev_key;
2029 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2030 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2031 match.key->vlan_priority = 0;
2032 match.mask = &filter_dev_mask;
2033 memset(match.mask, 0xff, sizeof(*match.mask));
2034 match.mask->vlan_priority = 0;
2036 flow_rule_match_vlan(rule, &match);
2038 if (match.mask->vlan_id ||
2039 match.mask->vlan_priority ||
2040 match.mask->vlan_tpid) {
2041 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2042 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2044 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2047 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2049 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2053 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2054 match.mask->vlan_id);
2055 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2056 match.key->vlan_id);
2058 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2059 match.mask->vlan_priority);
2060 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2061 match.key->vlan_priority);
2063 *match_level = MLX5_MATCH_L2;
2065 } else if (*match_level != MLX5_MATCH_NONE) {
2066 /* cvlan_tag enabled in match criteria and
2067 * disabled in match value means both S & C tags
2068 * don't exist (untagged of both)
2070 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
2071 *match_level = MLX5_MATCH_L2;
2074 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2075 struct flow_match_vlan match;
2077 flow_rule_match_cvlan(rule, &match);
2078 if (match.mask->vlan_id ||
2079 match.mask->vlan_priority ||
2080 match.mask->vlan_tpid) {
2081 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2082 MLX5_SET(fte_match_set_misc, misc_c,
2083 outer_second_svlan_tag, 1);
2084 MLX5_SET(fte_match_set_misc, misc_v,
2085 outer_second_svlan_tag, 1);
2087 MLX5_SET(fte_match_set_misc, misc_c,
2088 outer_second_cvlan_tag, 1);
2089 MLX5_SET(fte_match_set_misc, misc_v,
2090 outer_second_cvlan_tag, 1);
2093 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
2094 match.mask->vlan_id);
2095 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
2096 match.key->vlan_id);
2097 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
2098 match.mask->vlan_priority);
2099 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
2100 match.key->vlan_priority);
2102 *match_level = MLX5_MATCH_L2;
2103 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
2107 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2108 struct flow_match_eth_addrs match;
2110 flow_rule_match_eth_addrs(rule, &match);
2111 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2114 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2118 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2121 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2125 if (!is_zero_ether_addr(match.mask->src) ||
2126 !is_zero_ether_addr(match.mask->dst))
2127 *match_level = MLX5_MATCH_L2;
2130 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2131 struct flow_match_control match;
2133 flow_rule_match_control(rule, &match);
2134 addr_type = match.key->addr_type;
2136 /* the HW doesn't support frag first/later */
2137 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
2140 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
2141 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2142 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
2143 match.key->flags & FLOW_DIS_IS_FRAGMENT);
2145 /* the HW doesn't need L3 inline to match on frag=no */
2146 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
2147 *match_level = MLX5_MATCH_L2;
2148 /* *** L2 attributes parsing up to here *** */
2150 *match_level = MLX5_MATCH_L3;
2154 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2155 struct flow_match_basic match;
2157 flow_rule_match_basic(rule, &match);
2158 ip_proto = match.key->ip_proto;
2160 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2161 match.mask->ip_proto);
2162 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2163 match.key->ip_proto);
2165 if (match.mask->ip_proto)
2166 *match_level = MLX5_MATCH_L3;
2169 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
2170 struct flow_match_ipv4_addrs match;
2172 flow_rule_match_ipv4_addrs(rule, &match);
2173 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2174 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2175 &match.mask->src, sizeof(match.mask->src));
2176 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2177 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2178 &match.key->src, sizeof(match.key->src));
2179 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2180 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2181 &match.mask->dst, sizeof(match.mask->dst));
2182 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2183 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2184 &match.key->dst, sizeof(match.key->dst));
2186 if (match.mask->src || match.mask->dst)
2187 *match_level = MLX5_MATCH_L3;
2190 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
2191 struct flow_match_ipv6_addrs match;
2193 flow_rule_match_ipv6_addrs(rule, &match);
2194 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2195 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2196 &match.mask->src, sizeof(match.mask->src));
2197 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2198 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2199 &match.key->src, sizeof(match.key->src));
2201 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2202 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2203 &match.mask->dst, sizeof(match.mask->dst));
2204 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2205 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2206 &match.key->dst, sizeof(match.key->dst));
2208 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2209 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
2210 *match_level = MLX5_MATCH_L3;
2213 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2214 struct flow_match_ip match;
2216 flow_rule_match_ip(rule, &match);
2217 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2218 match.mask->tos & 0x3);
2219 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2220 match.key->tos & 0x3);
2222 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2223 match.mask->tos >> 2);
2224 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2225 match.key->tos >> 2);
2227 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2229 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2232 if (match.mask->ttl &&
2233 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
2234 ft_field_support.outer_ipv4_ttl)) {
2235 NL_SET_ERR_MSG_MOD(extack,
2236 "Matching on TTL is not supported");
2240 if (match.mask->tos || match.mask->ttl)
2241 *match_level = MLX5_MATCH_L3;
2244 /* *** L3 attributes parsing up to here *** */
2246 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2247 struct flow_match_ports match;
2249 flow_rule_match_ports(rule, &match);
2252 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2253 tcp_sport, ntohs(match.mask->src));
2254 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2255 tcp_sport, ntohs(match.key->src));
2257 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2258 tcp_dport, ntohs(match.mask->dst));
2259 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2260 tcp_dport, ntohs(match.key->dst));
2264 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2265 udp_sport, ntohs(match.mask->src));
2266 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2267 udp_sport, ntohs(match.key->src));
2269 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2270 udp_dport, ntohs(match.mask->dst));
2271 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2272 udp_dport, ntohs(match.key->dst));
2275 NL_SET_ERR_MSG_MOD(extack,
2276 "Only UDP and TCP transports are supported for L4 matching");
2277 netdev_err(priv->netdev,
2278 "Only UDP and TCP transport are supported\n");
2282 if (match.mask->src || match.mask->dst)
2283 *match_level = MLX5_MATCH_L4;
2286 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2287 struct flow_match_tcp match;
2289 flow_rule_match_tcp(rule, &match);
2290 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
2291 ntohs(match.mask->flags));
2292 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
2293 ntohs(match.key->flags));
2295 if (match.mask->flags)
2296 *match_level = MLX5_MATCH_L4;
2302 static int parse_cls_flower(struct mlx5e_priv *priv,
2303 struct mlx5e_tc_flow *flow,
2304 struct mlx5_flow_spec *spec,
2305 struct flow_cls_offload *f,
2306 struct net_device *filter_dev)
2308 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
2309 struct netlink_ext_ack *extack = f->common.extack;
2310 struct mlx5_core_dev *dev = priv->mdev;
2311 struct mlx5_eswitch *esw = dev->priv.eswitch;
2312 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2313 struct mlx5_eswitch_rep *rep;
2314 bool is_eswitch_flow;
2317 inner_match_level = MLX5_MATCH_NONE;
2318 outer_match_level = MLX5_MATCH_NONE;
2320 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2321 &inner_match_level, &outer_match_level);
2322 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2323 outer_match_level : inner_match_level;
2325 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2326 if (!err && is_eswitch_flow) {
2328 if (rep->vport != MLX5_VPORT_UPLINK &&
2329 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
2330 esw->offloads.inline_mode < non_tunnel_match_level)) {
2331 NL_SET_ERR_MSG_MOD(extack,
2332 "Flow is not offloaded due to min inline setting");
2333 netdev_warn(priv->netdev,
2334 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
2335 non_tunnel_match_level, esw->offloads.inline_mode);
2340 flow->attr->inner_match_level = inner_match_level;
2341 flow->attr->outer_match_level = outer_match_level;
2347 struct pedit_headers {
2349 struct vlan_hdr vlan;
2356 struct pedit_headers_action {
2357 struct pedit_headers vals;
2358 struct pedit_headers masks;
2362 static int pedit_header_offsets[] = {
2363 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2364 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2365 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2366 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2367 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
2370 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2372 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
2373 struct pedit_headers_action *hdrs)
2375 u32 *curr_pmask, *curr_pval;
2377 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2378 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
2380 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2383 *curr_pmask |= mask;
2384 *curr_pval |= (val & mask);
2392 struct mlx5_fields {
2400 #define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2401 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
2402 offsetof(struct pedit_headers, field) + (off), \
2403 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2405 /* masked values are the same and there are no rewrites that do not have a
2408 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2409 type matchmaskx = *(type *)(matchmaskp); \
2410 type matchvalx = *(type *)(matchvalp); \
2411 type maskx = *(type *)(maskp); \
2412 type valx = *(type *)(valp); \
2414 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2418 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
2419 void *matchmaskp, u8 bsize)
2425 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
2428 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
2431 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
2438 static struct mlx5_fields fields[] = {
2439 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2440 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2441 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2442 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2443 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2444 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2446 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
2447 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2448 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2449 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2451 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
2452 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
2453 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
2454 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
2455 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
2456 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
2457 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
2458 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
2459 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
2460 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
2461 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
2462 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
2463 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
2464 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
2465 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
2466 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
2467 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
2468 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
2470 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2471 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2472 /* in linux iphdr tcp_flags is 8 bits long */
2473 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
2475 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2476 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
2479 static unsigned long mask_to_le(unsigned long mask, int size)
2485 mask_be32 = (__force __be32)(mask);
2486 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2487 } else if (size == 16) {
2488 mask_be32 = (__force __be32)(mask);
2489 mask_be16 = *(__be16 *)&mask_be32;
2490 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2495 static int offload_pedit_fields(struct mlx5e_priv *priv,
2497 struct pedit_headers_action *hdrs,
2498 struct mlx5e_tc_flow_parse_attr *parse_attr,
2500 struct netlink_ext_ack *extack)
2502 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2503 int i, action_size, first, last, next_z;
2504 void *headers_c, *headers_v, *action, *vals_p;
2505 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
2506 struct mlx5e_tc_mod_hdr_acts *mod_acts;
2507 struct mlx5_fields *f;
2508 unsigned long mask, field_mask;
2512 mod_acts = &parse_attr->mod_hdr_acts;
2513 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2514 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
2516 set_masks = &hdrs[0].masks;
2517 add_masks = &hdrs[1].masks;
2518 set_vals = &hdrs[0].vals;
2519 add_vals = &hdrs[1].vals;
2521 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
2523 for (i = 0; i < ARRAY_SIZE(fields); i++) {
2527 /* avoid seeing bits set from previous iterations */
2531 s_masks_p = (void *)set_masks + f->offset;
2532 a_masks_p = (void *)add_masks + f->offset;
2534 s_mask = *s_masks_p & f->field_mask;
2535 a_mask = *a_masks_p & f->field_mask;
2537 if (!s_mask && !a_mask) /* nothing to offload here */
2540 if (s_mask && a_mask) {
2541 NL_SET_ERR_MSG_MOD(extack,
2542 "can't set and add to the same HW field");
2543 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2549 void *match_mask = headers_c + f->match_offset;
2550 void *match_val = headers_v + f->match_offset;
2552 cmd = MLX5_ACTION_TYPE_SET;
2554 vals_p = (void *)set_vals + f->offset;
2555 /* don't rewrite if we have a match on the same value */
2556 if (cmp_val_mask(vals_p, s_masks_p, match_val,
2557 match_mask, f->field_bsize))
2559 /* clear to denote we consumed this field */
2560 *s_masks_p &= ~f->field_mask;
2562 cmd = MLX5_ACTION_TYPE_ADD;
2564 vals_p = (void *)add_vals + f->offset;
2565 /* add 0 is no change */
2566 if ((*(u32 *)vals_p & f->field_mask) == 0)
2568 /* clear to denote we consumed this field */
2569 *a_masks_p &= ~f->field_mask;
2574 mask = mask_to_le(mask, f->field_bsize);
2576 first = find_first_bit(&mask, f->field_bsize);
2577 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2578 last = find_last_bit(&mask, f->field_bsize);
2579 if (first < next_z && next_z < last) {
2580 NL_SET_ERR_MSG_MOD(extack,
2581 "rewrite of few sub-fields isn't supported");
2582 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2587 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2589 NL_SET_ERR_MSG_MOD(extack,
2590 "too many pedit actions, can't offload");
2591 mlx5_core_warn(priv->mdev,
2592 "mlx5: parsed %d pedit actions, can't do more\n",
2593 mod_acts->num_actions);
2597 action = mod_acts->actions +
2598 (mod_acts->num_actions * action_size);
2599 MLX5_SET(set_action_in, action, action_type, cmd);
2600 MLX5_SET(set_action_in, action, field, f->field);
2602 if (cmd == MLX5_ACTION_TYPE_SET) {
2605 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2607 /* if field is bit sized it can start not from first bit */
2608 start = find_first_bit(&field_mask, f->field_bsize);
2610 MLX5_SET(set_action_in, action, offset, first - start);
2611 /* length is num of bits to be written, zero means length of 32 */
2612 MLX5_SET(set_action_in, action, length, (last - first + 1));
2615 if (f->field_bsize == 32)
2616 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
2617 else if (f->field_bsize == 16)
2618 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
2619 else if (f->field_bsize == 8)
2620 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
2622 ++mod_acts->num_actions;
2628 static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2631 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2632 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2633 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2634 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2637 int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2639 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2641 int action_size, new_num_actions, max_hw_actions;
2642 size_t new_sz, old_sz;
2645 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2648 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
2650 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2652 new_num_actions = min(max_hw_actions,
2653 mod_hdr_acts->actions ?
2654 mod_hdr_acts->max_actions * 2 : 1);
2655 if (mod_hdr_acts->max_actions == new_num_actions)
2658 new_sz = action_size * new_num_actions;
2659 old_sz = mod_hdr_acts->max_actions * action_size;
2660 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2664 memset(ret + old_sz, 0, new_sz - old_sz);
2665 mod_hdr_acts->actions = ret;
2666 mod_hdr_acts->max_actions = new_num_actions;
2671 void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2673 kfree(mod_hdr_acts->actions);
2674 mod_hdr_acts->actions = NULL;
2675 mod_hdr_acts->num_actions = 0;
2676 mod_hdr_acts->max_actions = 0;
2679 static const struct pedit_headers zero_masks = {};
2682 parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2683 const struct flow_action_entry *act, int namespace,
2684 struct mlx5e_tc_flow_parse_attr *parse_attr,
2685 struct pedit_headers_action *hdrs,
2686 struct netlink_ext_ack *extack)
2688 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2689 int err = -EOPNOTSUPP;
2690 u32 mask, val, offset;
2693 htype = act->mangle.htype;
2694 err = -EOPNOTSUPP; /* can't be all optimistic */
2696 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2697 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2701 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2702 NL_SET_ERR_MSG_MOD(extack,
2703 "The pedit offload action is not supported");
2707 mask = act->mangle.mask;
2708 val = act->mangle.val;
2709 offset = act->mangle.offset;
2711 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2723 parse_pedit_to_reformat(struct mlx5e_priv *priv,
2724 const struct flow_action_entry *act,
2725 struct mlx5e_tc_flow_parse_attr *parse_attr,
2726 struct netlink_ext_ack *extack)
2728 u32 mask, val, offset;
2731 if (act->id != FLOW_ACTION_MANGLE)
2734 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
2735 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
2739 mask = ~act->mangle.mask;
2740 val = act->mangle.val;
2741 offset = act->mangle.offset;
2742 p = (u32 *)&parse_attr->eth;
2743 *(p + (offset >> 2)) |= (val & mask);
2748 static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2749 const struct flow_action_entry *act, int namespace,
2750 struct mlx5e_tc_flow_parse_attr *parse_attr,
2751 struct pedit_headers_action *hdrs,
2752 struct mlx5e_tc_flow *flow,
2753 struct netlink_ext_ack *extack)
2755 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
2756 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
2758 return parse_pedit_to_modify_hdr(priv, act, namespace,
2759 parse_attr, hdrs, extack);
2762 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2763 struct mlx5e_tc_flow_parse_attr *parse_attr,
2764 struct pedit_headers_action *hdrs,
2766 struct netlink_ext_ack *extack)
2768 struct pedit_headers *cmd_masks;
2772 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2773 action_flags, extack);
2775 goto out_dealloc_parsed_actions;
2777 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2778 cmd_masks = &hdrs[cmd].masks;
2779 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
2780 NL_SET_ERR_MSG_MOD(extack,
2781 "attempt to offload an unsupported field");
2782 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
2783 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2784 16, 1, cmd_masks, sizeof(zero_masks), true);
2786 goto out_dealloc_parsed_actions;
2792 out_dealloc_parsed_actions:
2793 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
2797 static bool csum_offload_supported(struct mlx5e_priv *priv,
2800 struct netlink_ext_ack *extack)
2802 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2803 TCA_CSUM_UPDATE_FLAG_UDP;
2805 /* The HW recalcs checksums only if re-writing headers */
2806 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
2807 NL_SET_ERR_MSG_MOD(extack,
2808 "TC csum action is only offloaded with pedit");
2809 netdev_warn(priv->netdev,
2810 "TC csum action is only offloaded with pedit\n");
2814 if (update_flags & ~prot_flags) {
2815 NL_SET_ERR_MSG_MOD(extack,
2816 "can't offload TC csum action for some header/s");
2817 netdev_warn(priv->netdev,
2818 "can't offload TC csum action for some header/s - flags %#x\n",
2826 struct ip_ttl_word {
2832 struct ipv6_hoplimit_word {
2838 static int is_action_keys_supported(const struct flow_action_entry *act,
2839 bool ct_flow, bool *modify_ip_header,
2841 struct netlink_ext_ack *extack)
2846 htype = act->mangle.htype;
2847 offset = act->mangle.offset;
2848 mask = ~act->mangle.mask;
2849 /* For IPv4 & IPv6 header check 4 byte word,
2850 * to determine that modified fields
2851 * are NOT ttl & hop_limit only.
2853 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2854 struct ip_ttl_word *ttl_word =
2855 (struct ip_ttl_word *)&mask;
2857 if (offset != offsetof(struct iphdr, ttl) ||
2858 ttl_word->protocol ||
2860 *modify_ip_header = true;
2863 if (offset >= offsetof(struct iphdr, saddr))
2864 *modify_tuple = true;
2866 if (ct_flow && *modify_tuple) {
2867 NL_SET_ERR_MSG_MOD(extack,
2868 "can't offload re-write of ipv4 address with action ct");
2871 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2872 struct ipv6_hoplimit_word *hoplimit_word =
2873 (struct ipv6_hoplimit_word *)&mask;
2875 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2876 hoplimit_word->payload_len ||
2877 hoplimit_word->nexthdr) {
2878 *modify_ip_header = true;
2881 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
2882 *modify_tuple = true;
2884 if (ct_flow && *modify_tuple) {
2885 NL_SET_ERR_MSG_MOD(extack,
2886 "can't offload re-write of ipv6 address with action ct");
2889 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
2890 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
2891 *modify_tuple = true;
2893 NL_SET_ERR_MSG_MOD(extack,
2894 "can't offload re-write of transport header ports with action ct");
2902 static bool modify_header_match_supported(struct mlx5e_priv *priv,
2903 struct mlx5_flow_spec *spec,
2904 struct flow_action *flow_action,
2905 u32 actions, bool ct_flow,
2907 struct netlink_ext_ack *extack)
2909 const struct flow_action_entry *act;
2910 bool modify_ip_header, modify_tuple;
2917 headers_c = get_match_headers_criteria(actions, spec);
2918 headers_v = get_match_headers_value(actions, spec);
2919 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2921 /* for non-IP we only re-write MACs, so we're okay */
2922 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
2923 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2926 modify_ip_header = false;
2927 modify_tuple = false;
2928 flow_action_for_each(i, act, flow_action) {
2929 if (act->id != FLOW_ACTION_MANGLE &&
2930 act->id != FLOW_ACTION_ADD)
2933 err = is_action_keys_supported(act, ct_flow,
2935 &modify_tuple, extack);
2940 /* Add ct_state=-trk match so it will be offloaded for non ct flows
2941 * (or after clear action), as otherwise, since the tuple is changed,
2942 * we can't restore ct state
2944 if (!ct_clear && modify_tuple &&
2945 mlx5_tc_ct_add_no_trk_match(spec)) {
2946 NL_SET_ERR_MSG_MOD(extack,
2947 "can't offload tuple modify header with ct matches");
2948 netdev_info(priv->netdev,
2949 "can't offload tuple modify header with ct matches");
2953 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
2954 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2955 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
2956 NL_SET_ERR_MSG_MOD(extack,
2957 "can't offload re-write of non TCP/UDP");
2958 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
2967 static bool actions_match_supported(struct mlx5e_priv *priv,
2968 struct flow_action *flow_action,
2969 struct mlx5e_tc_flow_parse_attr *parse_attr,
2970 struct mlx5e_tc_flow *flow,
2971 struct netlink_ext_ack *extack)
2973 bool ct_flow = false, ct_clear = false;
2976 ct_clear = flow->attr->ct_attr.ct_action &
2978 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
2979 actions = flow->attr->action;
2981 if (mlx5e_is_eswitch_flow(flow)) {
2982 if (flow->attr->esw_attr->split_count && ct_flow) {
2983 /* All registers used by ct are cleared when using
2986 NL_SET_ERR_MSG_MOD(extack,
2987 "Can't offload mirroring with action ct");
2992 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2993 return modify_header_match_supported(priv, &parse_attr->spec,
2994 flow_action, actions,
3001 static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3003 return priv->mdev == peer_priv->mdev;
3006 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3008 struct mlx5_core_dev *fmdev, *pmdev;
3009 u64 fsystem_guid, psystem_guid;
3012 pmdev = peer_priv->mdev;
3014 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3015 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
3017 return (fsystem_guid == psystem_guid);
3020 static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3021 const struct flow_action_entry *act,
3022 struct mlx5e_tc_flow_parse_attr *parse_attr,
3023 struct pedit_headers_action *hdrs,
3024 u32 *action, struct netlink_ext_ack *extack)
3026 u16 mask16 = VLAN_VID_MASK;
3027 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3028 const struct flow_action_entry pedit_act = {
3029 .id = FLOW_ACTION_MANGLE,
3030 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3031 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3032 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3033 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3035 u8 match_prio_mask, match_prio_val;
3036 void *headers_c, *headers_v;
3039 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3040 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3042 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3043 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3044 NL_SET_ERR_MSG_MOD(extack,
3045 "VLAN rewrite action must have VLAN protocol match");
3049 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3050 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3051 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3052 NL_SET_ERR_MSG_MOD(extack,
3053 "Changing VLAN prio is not supported");
3057 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
3058 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3064 add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3065 struct mlx5e_tc_flow_parse_attr *parse_attr,
3066 struct pedit_headers_action *hdrs,
3067 u32 *action, struct netlink_ext_ack *extack)
3069 const struct flow_action_entry prio_tag_act = {
3072 MLX5_GET(fte_match_set_lyr_2_4,
3073 get_match_headers_value(*action,
3076 MLX5_GET(fte_match_set_lyr_2_4,
3077 get_match_headers_criteria(*action,
3082 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3083 &prio_tag_act, parse_attr, hdrs, action,
3087 static int validate_goto_chain(struct mlx5e_priv *priv,
3088 struct mlx5e_tc_flow *flow,
3089 const struct flow_action_entry *act,
3091 struct netlink_ext_ack *extack)
3093 bool is_esw = mlx5e_is_eswitch_flow(flow);
3094 struct mlx5_flow_attr *attr = flow->attr;
3095 bool ft_flow = mlx5e_is_ft_flow(flow);
3096 u32 dest_chain = act->chain_index;
3097 struct mlx5_fs_chains *chains;
3098 struct mlx5_eswitch *esw;
3099 u32 reformat_and_fwd;
3102 esw = priv->mdev->priv.eswitch;
3103 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3104 max_chain = mlx5_chains_get_chain_range(chains);
3105 reformat_and_fwd = is_esw ?
3106 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3107 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3110 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3114 if (!mlx5_chains_backwards_supported(chains) &&
3115 dest_chain <= attr->chain) {
3116 NL_SET_ERR_MSG_MOD(extack,
3117 "Goto lower numbered chain isn't supported");
3121 if (dest_chain > max_chain) {
3122 NL_SET_ERR_MSG_MOD(extack,
3123 "Requested destination chain is out of supported range");
3127 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3128 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3129 !reformat_and_fwd) {
3130 NL_SET_ERR_MSG_MOD(extack,
3131 "Goto chain is not allowed if action has reformat or decap");
3138 static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3139 struct flow_action *flow_action,
3140 struct mlx5e_tc_flow_parse_attr *parse_attr,
3141 struct mlx5e_tc_flow *flow,
3142 struct netlink_ext_ack *extack)
3144 struct mlx5_flow_attr *attr = flow->attr;
3145 struct pedit_headers_action hdrs[2] = {};
3146 const struct flow_action_entry *act;
3147 struct mlx5_nic_flow_attr *nic_attr;
3151 if (!flow_action_has_entries(flow_action))
3154 if (!flow_action_hw_stats_check(flow_action, extack,
3155 FLOW_ACTION_HW_STATS_DELAYED_BIT))
3158 nic_attr = attr->nic_attr;
3160 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
3162 flow_action_for_each(i, act, flow_action) {
3164 case FLOW_ACTION_ACCEPT:
3165 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3166 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3168 case FLOW_ACTION_DROP:
3169 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3170 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3171 flow_table_properties_nic_receive.flow_counter))
3172 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3174 case FLOW_ACTION_MANGLE:
3175 case FLOW_ACTION_ADD:
3176 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
3177 parse_attr, hdrs, NULL, extack);
3181 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3183 case FLOW_ACTION_VLAN_MANGLE:
3184 err = add_vlan_rewrite_action(priv,
3185 MLX5_FLOW_NAMESPACE_KERNEL,
3186 act, parse_attr, hdrs,
3192 case FLOW_ACTION_CSUM:
3193 if (csum_offload_supported(priv, action,
3199 case FLOW_ACTION_REDIRECT: {
3200 struct net_device *peer_dev = act->dev;
3202 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3203 same_hw_devs(priv, netdev_priv(peer_dev))) {
3204 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
3205 flow_flag_set(flow, HAIRPIN);
3206 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3207 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3209 NL_SET_ERR_MSG_MOD(extack,
3210 "device is not on same HW, can't offload");
3211 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3217 case FLOW_ACTION_MARK: {
3218 u32 mark = act->mark;
3220 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
3221 NL_SET_ERR_MSG_MOD(extack,
3222 "Bad flow mark - only 16 bit is supported");
3226 nic_attr->flow_tag = mark;
3227 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3230 case FLOW_ACTION_GOTO:
3231 err = validate_goto_chain(priv, flow, act, action,
3236 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3237 attr->dest_chain = act->chain_index;
3239 case FLOW_ACTION_CT:
3240 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3244 flow_flag_set(flow, CT);
3247 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3252 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3253 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3254 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
3255 parse_attr, hdrs, &action, extack);
3258 /* in case all pedit actions are skipped, remove the MOD_HDR
3261 if (parse_attr->mod_hdr_acts.num_actions == 0) {
3262 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3263 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
3267 attr->action = action;
3269 if (attr->dest_chain) {
3270 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3271 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3274 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3277 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3278 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3280 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
3286 static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
3287 struct net_device *peer_netdev)
3289 struct mlx5e_priv *peer_priv;
3291 peer_priv = netdev_priv(peer_netdev);
3293 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
3294 mlx5e_eswitch_vf_rep(priv->netdev) &&
3295 mlx5e_eswitch_vf_rep(peer_netdev) &&
3296 same_hw_devs(priv, peer_priv));
3299 static int parse_tc_vlan_action(struct mlx5e_priv *priv,
3300 const struct flow_action_entry *act,
3301 struct mlx5_esw_flow_attr *attr,
3304 u8 vlan_idx = attr->total_vlan;
3306 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3310 case FLOW_ACTION_VLAN_POP:
3312 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3313 MLX5_FS_VLAN_DEPTH))
3316 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3318 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3321 case FLOW_ACTION_VLAN_PUSH:
3322 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3323 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3324 attr->vlan_proto[vlan_idx] = act->vlan.proto;
3325 if (!attr->vlan_proto[vlan_idx])
3326 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3329 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3330 MLX5_FS_VLAN_DEPTH))
3333 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3335 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
3336 (act->vlan.proto != htons(ETH_P_8021Q) ||
3340 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
3347 attr->total_vlan = vlan_idx + 1;
3352 static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3353 struct net_device *out_dev)
3355 struct net_device *fdb_out_dev = out_dev;
3356 struct net_device *uplink_upper;
3359 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3360 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3361 uplink_upper == out_dev) {
3362 fdb_out_dev = uplink_dev;
3363 } else if (netif_is_lag_master(out_dev)) {
3364 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3366 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3367 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3374 static int add_vlan_push_action(struct mlx5e_priv *priv,
3375 struct mlx5_flow_attr *attr,
3376 struct net_device **out_dev,
3379 struct net_device *vlan_dev = *out_dev;
3380 struct flow_action_entry vlan_act = {
3381 .id = FLOW_ACTION_VLAN_PUSH,
3382 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3383 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3388 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
3392 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3393 dev_get_iflink(vlan_dev));
3394 if (is_vlan_dev(*out_dev))
3395 err = add_vlan_push_action(priv, attr, out_dev, action);
3400 static int add_vlan_pop_action(struct mlx5e_priv *priv,
3401 struct mlx5_flow_attr *attr,
3404 struct flow_action_entry vlan_act = {
3405 .id = FLOW_ACTION_VLAN_POP,
3407 int nest_level, err = 0;
3409 nest_level = attr->parse_attr->filter_dev->lower_level -
3410 priv->netdev->lower_level;
3411 while (nest_level--) {
3412 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
3420 static bool same_hw_reps(struct mlx5e_priv *priv,
3421 struct net_device *peer_netdev)
3423 struct mlx5e_priv *peer_priv;
3425 peer_priv = netdev_priv(peer_netdev);
3427 return mlx5e_eswitch_rep(priv->netdev) &&
3428 mlx5e_eswitch_rep(peer_netdev) &&
3429 same_hw_devs(priv, peer_priv);
3432 static bool is_lag_dev(struct mlx5e_priv *priv,
3433 struct net_device *peer_netdev)
3435 return ((mlx5_lag_is_sriov(priv->mdev) ||
3436 mlx5_lag_is_multipath(priv->mdev)) &&
3437 same_hw_reps(priv, peer_netdev));
3440 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3441 struct net_device *out_dev)
3443 if (is_merged_eswitch_vfs(priv, out_dev))
3446 if (is_lag_dev(priv, out_dev))
3449 return mlx5e_eswitch_rep(out_dev) &&
3450 same_port_devs(priv, netdev_priv(out_dev));
3453 static bool is_duplicated_output_device(struct net_device *dev,
3454 struct net_device *out_dev,
3455 int *ifindexes, int if_count,
3456 struct netlink_ext_ack *extack)
3460 for (i = 0; i < if_count; i++) {
3461 if (ifindexes[i] == out_dev->ifindex) {
3462 NL_SET_ERR_MSG_MOD(extack,
3463 "can't duplicate output to same device");
3464 netdev_err(dev, "can't duplicate output to same device: %s\n",
3473 static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3474 struct mlx5e_tc_flow *flow,
3475 struct net_device *out_dev,
3476 struct netlink_ext_ack *extack)
3478 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
3479 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3480 struct mlx5e_rep_priv *rep_priv;
3482 /* Forwarding non encapsulated traffic between
3483 * uplink ports is allowed only if
3484 * termination_table_raw_traffic cap is set.
3486 * Input vport was stored attr->in_rep.
3487 * In LAG case, *priv* is the private data of
3488 * uplink which may be not the input vport.
3490 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3492 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3493 mlx5e_eswitch_uplink_rep(out_dev)))
3496 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3497 termination_table_raw_traffic)) {
3498 NL_SET_ERR_MSG_MOD(extack,
3499 "devices are both uplink, can't offload forwarding");
3500 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3501 priv->netdev->name, out_dev->name);
3503 } else if (out_dev != rep_priv->netdev) {
3504 NL_SET_ERR_MSG_MOD(extack,
3505 "devices are not the same uplink, can't offload forwarding");
3506 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3507 priv->netdev->name, out_dev->name);
3513 static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3514 struct flow_action *flow_action,
3515 struct mlx5e_tc_flow *flow,
3516 struct netlink_ext_ack *extack,
3517 struct net_device *filter_dev)
3519 struct pedit_headers_action hdrs[2] = {};
3520 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3521 struct mlx5e_tc_flow_parse_attr *parse_attr;
3522 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3523 const struct ip_tunnel_info *info = NULL;
3524 struct mlx5_flow_attr *attr = flow->attr;
3525 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
3526 bool ft_flow = mlx5e_is_ft_flow(flow);
3527 const struct flow_action_entry *act;
3528 struct mlx5_esw_flow_attr *esw_attr;
3529 bool encap = false, decap = false;
3530 u32 action = attr->action;
3531 int err, i, if_count = 0;
3532 bool mpls_push = false;
3534 if (!flow_action_has_entries(flow_action))
3537 if (!flow_action_hw_stats_check(flow_action, extack,
3538 FLOW_ACTION_HW_STATS_DELAYED_BIT))
3541 esw_attr = attr->esw_attr;
3542 parse_attr = attr->parse_attr;
3544 flow_action_for_each(i, act, flow_action) {
3546 case FLOW_ACTION_DROP:
3547 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3548 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3550 case FLOW_ACTION_TRAP:
3551 if (!flow_offload_has_one_action(flow_action)) {
3552 NL_SET_ERR_MSG_MOD(extack,
3553 "action trap is supported as a sole action only");
3556 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3557 MLX5_FLOW_CONTEXT_ACTION_COUNT);
3558 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
3560 case FLOW_ACTION_MPLS_PUSH:
3561 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3562 reformat_l2_to_l3_tunnel) ||
3563 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
3564 NL_SET_ERR_MSG_MOD(extack,
3565 "mpls push is supported only for mpls_uc protocol");
3570 case FLOW_ACTION_MPLS_POP:
3571 /* we only support mpls pop if it is the first action
3572 * and the filter net device is bareudp. Subsequent
3573 * actions can be pedit and the last can be mirred
3577 NL_SET_ERR_MSG_MOD(extack,
3578 "mpls pop supported only as first action");
3581 if (!netif_is_bareudp(filter_dev)) {
3582 NL_SET_ERR_MSG_MOD(extack,
3583 "mpls pop supported only on bareudp devices");
3587 parse_attr->eth.h_proto = act->mpls_pop.proto;
3588 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
3589 flow_flag_set(flow, L3_TO_L2_DECAP);
3591 case FLOW_ACTION_MANGLE:
3592 case FLOW_ACTION_ADD:
3593 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
3594 parse_attr, hdrs, flow, extack);
3598 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
3599 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3600 esw_attr->split_count = esw_attr->out_count;
3603 case FLOW_ACTION_CSUM:
3604 if (csum_offload_supported(priv, action,
3605 act->csum_flags, extack))
3609 case FLOW_ACTION_REDIRECT:
3610 case FLOW_ACTION_MIRRED: {
3611 struct mlx5e_priv *out_priv;
3612 struct net_device *out_dev;
3616 /* out_dev is NULL when filters with
3617 * non-existing mirred device are replayed to
3623 if (mpls_push && !netif_is_bareudp(out_dev)) {
3624 NL_SET_ERR_MSG_MOD(extack,
3625 "mpls is supported only through a bareudp device");
3629 if (ft_flow && out_dev == priv->netdev) {
3630 /* Ignore forward to self rules generated
3631 * by adding both mlx5 devs to the flow table
3632 * block on a normal nft offload setup.
3637 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
3638 NL_SET_ERR_MSG_MOD(extack,
3639 "can't support more output ports, can't offload forwarding");
3640 netdev_warn(priv->netdev,
3641 "can't support more than %d output ports, can't offload forwarding\n",
3642 esw_attr->out_count);
3646 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3647 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3649 parse_attr->mirred_ifindex[esw_attr->out_count] =
3651 parse_attr->tun_info[esw_attr->out_count] =
3652 mlx5e_dup_tun_info(info);
3653 if (!parse_attr->tun_info[esw_attr->out_count])
3656 esw_attr->dests[esw_attr->out_count].flags |=
3657 MLX5_ESW_DEST_ENCAP;
3658 esw_attr->out_count++;
3659 /* attr->dests[].rep is resolved when we
3662 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
3663 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3664 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
3666 if (is_duplicated_output_device(priv->netdev,
3673 ifindexes[if_count] = out_dev->ifindex;
3676 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
3680 if (is_vlan_dev(out_dev)) {
3681 err = add_vlan_push_action(priv, attr,
3688 if (is_vlan_dev(parse_attr->filter_dev)) {
3689 err = add_vlan_pop_action(priv, attr,
3695 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
3699 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3700 NL_SET_ERR_MSG_MOD(extack,
3701 "devices are not on same switch HW, can't offload forwarding");
3705 out_priv = netdev_priv(out_dev);
3706 rpriv = out_priv->ppriv;
3707 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
3708 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
3709 esw_attr->out_count++;
3710 } else if (parse_attr->filter_dev != priv->netdev) {
3711 /* All mlx5 devices are called to configure
3712 * high level device filters. Therefore, the
3713 * *attempt* to install a filter on invalid
3714 * eswitch should not trigger an explicit error
3718 NL_SET_ERR_MSG_MOD(extack,
3719 "devices are not on same switch HW, can't offload forwarding");
3720 netdev_warn(priv->netdev,
3721 "devices %s %s not on same switch HW, can't offload forwarding\n",
3728 case FLOW_ACTION_TUNNEL_ENCAP:
3736 case FLOW_ACTION_VLAN_PUSH:
3737 case FLOW_ACTION_VLAN_POP:
3738 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3739 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3740 /* Replace vlan pop+push with vlan modify */
3741 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3742 err = add_vlan_rewrite_action(priv,
3743 MLX5_FLOW_NAMESPACE_FDB,
3744 act, parse_attr, hdrs,
3747 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
3752 esw_attr->split_count = esw_attr->out_count;
3754 case FLOW_ACTION_VLAN_MANGLE:
3755 err = add_vlan_rewrite_action(priv,
3756 MLX5_FLOW_NAMESPACE_FDB,
3757 act, parse_attr, hdrs,
3762 esw_attr->split_count = esw_attr->out_count;
3764 case FLOW_ACTION_TUNNEL_DECAP:
3767 case FLOW_ACTION_GOTO:
3768 err = validate_goto_chain(priv, flow, act, action,
3773 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3774 attr->dest_chain = act->chain_index;
3776 case FLOW_ACTION_CT:
3777 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3781 flow_flag_set(flow, CT);
3784 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3789 /* always set IP version for indirect table handling */
3790 attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
3792 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3793 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3794 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3797 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3798 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3804 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3805 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3806 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3807 parse_attr, hdrs, &action, extack);
3810 /* in case all pedit actions are skipped, remove the MOD_HDR
3811 * flag. we might have set split_count either by pedit or
3812 * pop/push. if there is no pop/push either, reset it too.
3814 if (parse_attr->mod_hdr_acts.num_actions == 0) {
3815 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3816 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
3817 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3818 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3819 esw_attr->split_count = 0;
3823 attr->action = action;
3824 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
3827 if (attr->dest_chain) {
3829 /* It can be supported if we'll create a mapping for
3830 * the tunnel device only (without tunnel), and set
3831 * this tunnel id with this decap flow.
3833 * On restore (miss), we'll just set this saved tunnel
3837 NL_SET_ERR_MSG(extack,
3838 "Decap with goto isn't supported");
3839 netdev_warn(priv->netdev,
3840 "Decap with goto isn't supported");
3844 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3845 NL_SET_ERR_MSG_MOD(extack,
3846 "Mirroring goto chain rules isn't supported");
3849 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3852 if (!(attr->action &
3853 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3854 NL_SET_ERR_MSG_MOD(extack,
3855 "Rule must have at least one forward/drop action");
3859 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3860 NL_SET_ERR_MSG_MOD(extack,
3861 "current firmware doesn't support split rule for port mirroring");
3862 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3869 static void get_flags(int flags, unsigned long *flow_flags)
3871 unsigned long __flow_flags = 0;
3873 if (flags & MLX5_TC_FLAG(INGRESS))
3874 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3875 if (flags & MLX5_TC_FLAG(EGRESS))
3876 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
3878 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3879 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3880 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3881 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
3882 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
3883 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
3885 *flow_flags = __flow_flags;
3888 static const struct rhashtable_params tc_ht_params = {
3889 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3890 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3891 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3892 .automatic_shrinking = true,
3895 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3896 unsigned long flags)
3898 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3899 struct mlx5e_rep_priv *uplink_rpriv;
3901 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
3902 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3903 return &uplink_rpriv->uplink_priv.tc_ht;
3904 } else /* NIC offload */
3905 return &priv->fs.tc.ht;
3908 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3910 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
3911 struct mlx5_flow_attr *attr = flow->attr;
3912 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
3913 flow_flag_test(flow, INGRESS);
3914 bool act_is_encap = !!(attr->action &
3915 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3916 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
3917 MLX5_DEVCOM_ESW_OFFLOADS);
3922 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
3923 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
3924 (is_rep_ingress || act_is_encap))
3930 struct mlx5_flow_attr *
3931 mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
3933 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
3934 sizeof(struct mlx5_esw_flow_attr) :
3935 sizeof(struct mlx5_nic_flow_attr);
3936 struct mlx5_flow_attr *attr;
3938 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
3942 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
3943 struct flow_cls_offload *f, unsigned long flow_flags,
3944 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3945 struct mlx5e_tc_flow **__flow)
3947 struct mlx5e_tc_flow_parse_attr *parse_attr;
3948 struct mlx5_flow_attr *attr;
3949 struct mlx5e_tc_flow *flow;
3953 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
3954 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
3955 if (!parse_attr || !flow)
3958 flow->flags = flow_flags;
3959 flow->cookie = f->cookie;
3962 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
3968 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3969 INIT_LIST_HEAD(&flow->encaps[out_index].list);
3970 INIT_LIST_HEAD(&flow->hairpin);
3971 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
3972 refcount_set(&flow->refcnt, 1);
3973 init_completion(&flow->init_done);
3976 *__parse_attr = parse_attr;
3987 mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
3988 struct mlx5e_tc_flow_parse_attr *parse_attr,
3989 struct flow_cls_offload *f)
3991 attr->parse_attr = parse_attr;
3992 attr->chain = f->common.chain_index;
3993 attr->prio = f->common.prio;
3997 mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
3998 struct mlx5e_priv *priv,
3999 struct mlx5e_tc_flow_parse_attr *parse_attr,
4000 struct flow_cls_offload *f,
4001 struct mlx5_eswitch_rep *in_rep,
4002 struct mlx5_core_dev *in_mdev)
4004 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4005 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4007 mlx5e_flow_attr_init(attr, parse_attr, f);
4009 esw_attr->in_rep = in_rep;
4010 esw_attr->in_mdev = in_mdev;
4012 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4013 MLX5_COUNTER_SOURCE_ESWITCH)
4014 esw_attr->counter_dev = in_mdev;
4016 esw_attr->counter_dev = priv->mdev;
4019 static struct mlx5e_tc_flow *
4020 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4021 struct flow_cls_offload *f,
4022 unsigned long flow_flags,
4023 struct net_device *filter_dev,
4024 struct mlx5_eswitch_rep *in_rep,
4025 struct mlx5_core_dev *in_mdev)
4027 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4028 struct netlink_ext_ack *extack = f->common.extack;
4029 struct mlx5e_tc_flow_parse_attr *parse_attr;
4030 struct mlx5e_tc_flow *flow;
4033 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4034 attr_size = sizeof(struct mlx5_esw_flow_attr);
4035 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4036 &parse_attr, &flow);
4040 parse_attr->filter_dev = filter_dev;
4041 mlx5e_flow_esw_attr_init(flow->attr,
4043 f, in_rep, in_mdev);
4045 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4050 /* actions validation depends on parsing the ct matches first */
4051 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4052 &flow->attr->ct_attr, extack);
4056 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack, filter_dev);
4060 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
4061 complete_all(&flow->init_done);
4063 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4066 add_unready_flow(flow);
4072 mlx5e_flow_put(priv, flow);
4074 return ERR_PTR(err);
4077 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
4078 struct mlx5e_tc_flow *flow,
4079 unsigned long flow_flags)
4081 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4082 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
4083 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
4084 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4085 struct mlx5e_tc_flow_parse_attr *parse_attr;
4086 struct mlx5e_rep_priv *peer_urpriv;
4087 struct mlx5e_tc_flow *peer_flow;
4088 struct mlx5_core_dev *in_mdev;
4091 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4095 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4096 peer_priv = netdev_priv(peer_urpriv->netdev);
4098 /* in_mdev is assigned of which the packet originated from.
4099 * So packets redirected to uplink use the same mdev of the
4100 * original flow and packets redirected from uplink use the
4103 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
4104 in_mdev = peer_priv->mdev;
4106 in_mdev = priv->mdev;
4108 parse_attr = flow->attr->parse_attr;
4109 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
4110 parse_attr->filter_dev,
4111 attr->in_rep, in_mdev);
4112 if (IS_ERR(peer_flow)) {
4113 err = PTR_ERR(peer_flow);
4117 flow->peer_flow = peer_flow;
4118 flow_flag_set(flow, DUP);
4119 mutex_lock(&esw->offloads.peer_mutex);
4120 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4121 mutex_unlock(&esw->offloads.peer_mutex);
4124 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4129 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4130 struct flow_cls_offload *f,
4131 unsigned long flow_flags,
4132 struct net_device *filter_dev,
4133 struct mlx5e_tc_flow **__flow)
4135 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4136 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4137 struct mlx5_core_dev *in_mdev = priv->mdev;
4138 struct mlx5e_tc_flow *flow;
4141 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4144 return PTR_ERR(flow);
4146 if (is_peer_flow_needed(flow)) {
4147 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
4149 mlx5e_tc_del_fdb_flow(priv, flow);
4163 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
4164 struct flow_cls_offload *f,
4165 unsigned long flow_flags,
4166 struct net_device *filter_dev,
4167 struct mlx5e_tc_flow **__flow)
4169 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4170 struct netlink_ext_ack *extack = f->common.extack;
4171 struct mlx5e_tc_flow_parse_attr *parse_attr;
4172 struct mlx5e_tc_flow *flow;
4175 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4176 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4178 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
4182 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4183 attr_size = sizeof(struct mlx5_nic_flow_attr);
4184 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4185 &parse_attr, &flow);
4189 parse_attr->filter_dev = filter_dev;
4190 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4192 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4197 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4198 &flow->attr->ct_attr, extack);
4202 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
4206 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4210 flow_flag_set(flow, OFFLOADED);
4216 flow_flag_set(flow, FAILED);
4217 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
4218 mlx5e_flow_put(priv, flow);
4224 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
4225 struct flow_cls_offload *f,
4226 unsigned long flags,
4227 struct net_device *filter_dev,
4228 struct mlx5e_tc_flow **flow)
4230 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4231 unsigned long flow_flags;
4234 get_flags(flags, &flow_flags);
4236 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4239 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
4240 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4243 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4249 static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4250 struct mlx5e_rep_priv *rpriv)
4252 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
4253 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4254 * function is called from NIC mode.
4256 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
4259 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
4260 struct flow_cls_offload *f, unsigned long flags)
4262 struct netlink_ext_ack *extack = f->common.extack;
4263 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4264 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4265 struct mlx5e_tc_flow *flow;
4269 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4271 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4274 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
4277 NL_SET_ERR_MSG_MOD(extack,
4278 "flow cookie already exists, ignoring");
4279 netdev_warn_once(priv->netdev,
4280 "flow cookie %lx already exists, ignoring\n",
4290 trace_mlx5e_configure_flower(f);
4291 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
4295 /* Flow rule offloaded to non-uplink representor sharing tc block,
4296 * set the flow's owner dev.
4298 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4299 flow->orig_dev = dev;
4301 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
4308 mlx5e_flow_put(priv, flow);
4313 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4315 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4316 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
4318 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4319 flow_flag_test(flow, EGRESS) == dir_egress;
4322 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
4323 struct flow_cls_offload *f, unsigned long flags)
4325 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4326 struct mlx5e_tc_flow *flow;
4330 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4331 if (!flow || !same_flow_direction(flow, flags)) {
4336 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4339 if (flow_flag_test_and_set(flow, DELETED)) {
4343 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
4346 trace_mlx5e_delete_flower(f);
4347 mlx5e_flow_put(priv, flow);
4356 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
4357 struct flow_cls_offload *f, unsigned long flags)
4359 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4360 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4361 struct mlx5_eswitch *peer_esw;
4362 struct mlx5e_tc_flow *flow;
4363 struct mlx5_fc *counter;
4370 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4374 return PTR_ERR(flow);
4376 if (!same_flow_direction(flow, flags)) {
4381 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
4382 counter = mlx5e_tc_get_counter(flow);
4386 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4389 /* Under multipath it's possible for one rule to be currently
4390 * un-offloaded while the other rule is offloaded.
4392 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4396 if (flow_flag_test(flow, DUP) &&
4397 flow_flag_test(flow->peer_flow, OFFLOADED)) {
4402 counter = mlx5e_tc_get_counter(flow->peer_flow);
4404 goto no_peer_counter;
4405 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4408 packets += packets2;
4409 lastuse = max_t(u64, lastuse, lastuse2);
4413 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4415 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
4416 FLOW_ACTION_HW_STATS_DELAYED);
4417 trace_mlx5e_stats_flower(f);
4419 mlx5e_flow_put(priv, flow);
4423 static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
4424 struct netlink_ext_ack *extack)
4426 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4427 struct mlx5_eswitch *esw;
4432 vport_num = rpriv->rep->vport;
4433 if (vport_num >= MLX5_VPORT_ECPF) {
4434 NL_SET_ERR_MSG_MOD(extack,
4435 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4439 esw = priv->mdev->priv.eswitch;
4440 /* rate is given in bytes/sec.
4441 * First convert to bits/sec and then round to the nearest mbit/secs.
4442 * mbit means million bits.
4443 * Moreover, if rate is non zero we choose to configure to a minimum of
4447 rate = (rate * BITS_PER_BYTE) + 500000;
4448 rate_mbps = max_t(u64, do_div(rate, 1000000), 1);
4451 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4453 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4458 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4459 struct flow_action *flow_action,
4460 struct netlink_ext_ack *extack)
4462 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4463 const struct flow_action_entry *act;
4467 if (!flow_action_has_entries(flow_action)) {
4468 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4472 if (!flow_offload_has_one_action(flow_action)) {
4473 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4477 if (!flow_action_basic_hw_stats_check(flow_action, extack))
4480 flow_action_for_each(i, act, flow_action) {
4482 case FLOW_ACTION_POLICE:
4483 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4487 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4490 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4498 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4499 struct tc_cls_matchall_offload *ma)
4501 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4502 struct netlink_ext_ack *extack = ma->common.extack;
4504 if (!mlx5_esw_qos_enabled(esw)) {
4505 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4509 if (ma->common.prio != 1) {
4510 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4514 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4517 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4518 struct tc_cls_matchall_offload *ma)
4520 struct netlink_ext_ack *extack = ma->common.extack;
4522 return apply_police_params(priv, 0, extack);
4525 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4526 struct tc_cls_matchall_offload *ma)
4528 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4529 struct rtnl_link_stats64 cur_stats;
4533 cur_stats = priv->stats.vf_vport;
4534 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4535 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4536 rpriv->prev_vf_vport_stats = cur_stats;
4537 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
4538 FLOW_ACTION_HW_STATS_DELAYED);
4541 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4542 struct mlx5e_priv *peer_priv)
4544 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
4545 struct mlx5e_hairpin_entry *hpe, *tmp;
4546 LIST_HEAD(init_wait_list);
4550 if (!same_hw_devs(priv, peer_priv))
4553 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4555 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
4556 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4557 if (refcount_inc_not_zero(&hpe->refcnt))
4558 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4559 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4561 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4562 wait_for_completion(&hpe->res_ready);
4563 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4564 hpe->hp->pair->peer_gone = true;
4566 mlx5e_hairpin_put(priv, hpe);
4570 static int mlx5e_tc_netdev_event(struct notifier_block *this,
4571 unsigned long event, void *ptr)
4573 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4574 struct mlx5e_flow_steering *fs;
4575 struct mlx5e_priv *peer_priv;
4576 struct mlx5e_tc_table *tc;
4577 struct mlx5e_priv *priv;
4579 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4580 event != NETDEV_UNREGISTER ||
4581 ndev->reg_state == NETREG_REGISTERED)
4584 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4585 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4586 priv = container_of(fs, struct mlx5e_priv, fs);
4587 peer_priv = netdev_priv(ndev);
4588 if (priv == peer_priv ||
4589 !(priv->netdev->features & NETIF_F_HW_TC))
4592 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4597 static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4599 int tc_grp_size, tc_tbl_size;
4600 u32 max_flow_counter;
4602 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4603 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4605 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4607 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4608 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4613 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
4615 struct mlx5e_tc_table *tc = &priv->fs.tc;
4616 struct mlx5_core_dev *dev = priv->mdev;
4617 struct mlx5_chains_attr attr = {};
4620 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
4621 mutex_init(&tc->t_lock);
4622 mutex_init(&tc->hairpin_tbl_lock);
4623 hash_init(tc->hairpin_tbl);
4625 err = rhashtable_init(&tc->ht, &tc_ht_params);
4629 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4631 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4632 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4633 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
4634 attr.max_restore_tag = MLX5E_TC_TABLE_CHAIN_TAG_MASK;
4636 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4637 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4638 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
4639 attr.default_ft = priv->fs.vlan.ft.t;
4641 tc->chains = mlx5_chains_create(dev, &attr);
4642 if (IS_ERR(tc->chains)) {
4643 err = PTR_ERR(tc->chains);
4647 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
4648 MLX5_FLOW_NAMESPACE_KERNEL);
4649 if (IS_ERR(tc->ct)) {
4650 err = PTR_ERR(tc->ct);
4654 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
4655 err = register_netdevice_notifier_dev_net(priv->netdev,
4659 tc->netdevice_nb.notifier_call = NULL;
4660 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4667 mlx5_tc_ct_clean(tc->ct);
4669 mlx5_chains_destroy(tc->chains);
4671 rhashtable_destroy(&tc->ht);
4675 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4677 struct mlx5e_tc_flow *flow = ptr;
4678 struct mlx5e_priv *priv = flow->priv;
4680 mlx5e_tc_del_flow(priv, flow);
4684 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
4686 struct mlx5e_tc_table *tc = &priv->fs.tc;
4688 if (tc->netdevice_nb.notifier_call)
4689 unregister_netdevice_notifier_dev_net(priv->netdev,
4693 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
4694 mutex_destroy(&tc->hairpin_tbl_lock);
4696 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
4698 if (!IS_ERR_OR_NULL(tc->t)) {
4699 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
4702 mutex_destroy(&tc->t_lock);
4704 mlx5_tc_ct_clean(tc->ct);
4705 mlx5_chains_destroy(tc->chains);
4708 int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4710 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
4711 struct mlx5_rep_uplink_priv *uplink_priv;
4712 struct mlx5e_rep_priv *rpriv;
4713 struct mapping_ctx *mapping;
4714 struct mlx5_eswitch *esw;
4715 struct mlx5e_priv *priv;
4718 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
4719 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4720 priv = netdev_priv(rpriv->netdev);
4721 esw = priv->mdev->priv.eswitch;
4723 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
4725 &esw->offloads.mod_hdr,
4726 MLX5_FLOW_NAMESPACE_FDB);
4727 if (IS_ERR(uplink_priv->ct_priv))
4730 mapping = mapping_create(sizeof(struct tunnel_match_key),
4731 TUNNEL_INFO_BITS_MASK, true);
4732 if (IS_ERR(mapping)) {
4733 err = PTR_ERR(mapping);
4734 goto err_tun_mapping;
4736 uplink_priv->tunnel_mapping = mapping;
4738 /* 0xFFF is reserved for stack devices slow path table mark */
4739 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK - 1, true);
4740 if (IS_ERR(mapping)) {
4741 err = PTR_ERR(mapping);
4742 goto err_enc_opts_mapping;
4744 uplink_priv->tunnel_enc_opts_mapping = mapping;
4746 err = rhashtable_init(tc_ht, &tc_ht_params);
4750 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
4752 uplink_priv->encap = mlx5e_tc_tun_init(priv);
4753 if (IS_ERR(uplink_priv->encap)) {
4754 err = PTR_ERR(uplink_priv->encap);
4755 goto err_register_fib_notifier;
4760 err_register_fib_notifier:
4761 rhashtable_destroy(tc_ht);
4763 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4764 err_enc_opts_mapping:
4765 mapping_destroy(uplink_priv->tunnel_mapping);
4767 mlx5_tc_ct_clean(uplink_priv->ct_priv);
4769 netdev_warn(priv->netdev,
4770 "Failed to initialize tc (eswitch), err: %d", err);
4774 void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4776 struct mlx5_rep_uplink_priv *uplink_priv;
4778 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
4780 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4781 mlx5e_tc_tun_cleanup(uplink_priv->encap);
4783 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4784 mapping_destroy(uplink_priv->tunnel_mapping);
4786 mlx5_tc_ct_clean(uplink_priv->ct_priv);
4789 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
4791 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4793 return atomic_read(&tc_ht->nelems);
4796 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4798 struct mlx5e_tc_flow *flow, *tmp;
4800 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4801 __mlx5e_tc_del_fdb_peer_flow(flow);
4804 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4806 struct mlx5_rep_uplink_priv *rpriv =
4807 container_of(work, struct mlx5_rep_uplink_priv,
4808 reoffload_flows_work);
4809 struct mlx5e_tc_flow *flow, *tmp;
4811 mutex_lock(&rpriv->unready_flows_lock);
4812 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4813 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
4814 unready_flow_del(flow);
4816 mutex_unlock(&rpriv->unready_flows_lock);
4819 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
4820 struct flow_cls_offload *cls_flower,
4821 unsigned long flags)
4823 switch (cls_flower->command) {
4824 case FLOW_CLS_REPLACE:
4825 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
4827 case FLOW_CLS_DESTROY:
4828 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
4830 case FLOW_CLS_STATS:
4831 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
4838 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
4841 unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
4842 struct mlx5e_priv *priv = cb_priv;
4845 case TC_SETUP_CLSFLOWER:
4846 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
4852 bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
4853 struct sk_buff *skb)
4855 #if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
4856 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
4857 struct mlx5e_priv *priv = netdev_priv(skb->dev);
4858 struct mlx5e_tc_table *tc = &priv->fs.tc;
4859 struct tc_skb_ext *tc_skb_ext;
4862 reg_b = be32_to_cpu(cqe->ft_metadata);
4864 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
4866 err = mlx5_get_chain_for_tag(nic_chains(priv), chain_tag, &chain);
4868 netdev_dbg(priv->netdev,
4869 "Couldn't find chain for chain tag: %d, err: %d\n",
4875 tc_skb_ext = skb_ext_add(skb, TC_SKB_EXT);
4876 if (WARN_ON(!tc_skb_ext))
4879 tc_skb_ext->chain = chain;
4881 zone_restore_id = (reg_b >> REG_MAPPING_SHIFT(NIC_ZONE_RESTORE_TO_REG)) &
4884 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
4888 #endif /* CONFIG_NET_TC_SKB_EXT */