drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

   1 /*
   2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/flow_dissector.h>
  34 #include <net/flow_offload.h>
  35 #include <net/sch_generic.h>
  36 #include <net/pkt_cls.h>
  37 #include <linux/mlx5/fs.h>
  38 #include <linux/mlx5/device.h>
  39 #include <linux/rhashtable.h>
  40 #include <linux/refcount.h>
  41 #include <linux/completion.h>
  42 #include <net/arp.h>
  43 #include <net/ipv6_stubs.h>
  44 #include <net/bareudp.h>
  45 #include <net/bonding.h>
  46 #include <net/dst_metadata.h>
  47 #include "devlink.h"
  48 #include "en.h"
  49 #include "en/tc/post_act.h"
  50 #include "en/tc/act_stats.h"
  51 #include "en_rep.h"
  52 #include "en/rep/tc.h"
  53 #include "en/rep/neigh.h"
  54 #include "en_tc.h"
  55 #include "eswitch.h"
  56 #include "fs_core.h"
  57 #include "en/port.h"
  58 #include "en/tc_tun.h"
  59 #include "en/mapping.h"
  60 #include "en/tc_ct.h"
  61 #include "en/mod_hdr.h"
  62 #include "en/tc_tun_encap.h"
  63 #include "en/tc/sample.h"
  64 #include "en/tc/act/act.h"
  65 #include "en/tc/post_meter.h"
  66 #include "lib/devcom.h"
  67 #include "lib/geneve.h"
  68 #include "lib/fs_chains.h"
  69 #include "diag/en_tc_tracepoint.h"
  70 #include <asm/div64.h>
  71 #include "lag/lag.h"
  72 #include "lag/mp.h"
  73
  74 #define MLX5E_TC_TABLE_NUM_GROUPS 4
  75 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
  76
  77 struct mlx5e_tc_table {
  78         /* Protects the dynamic assignment of the t parameter
  79          * which is the nic tc root table.
  80          */
  81         struct mutex                    t_lock;
  82         struct mlx5e_priv               *priv;
  83         struct mlx5_flow_table          *t;
  84         struct mlx5_flow_table          *miss_t;
  85         struct mlx5_fs_chains           *chains;
  86         struct mlx5e_post_act           *post_act;
  87
  88         struct rhashtable               ht;
  89
  90         struct mod_hdr_tbl mod_hdr;
  91         struct mutex hairpin_tbl_lock; /* protects hairpin_tbl */
  92         DECLARE_HASHTABLE(hairpin_tbl, 8);
  93
  94         struct notifier_block     netdevice_nb;
  95         struct netdev_net_notifier      netdevice_nn;
  96
  97         struct mlx5_tc_ct_priv         *ct;
  98         struct mapping_ctx             *mapping;
  99         struct dentry                  *dfs_root;
 100
 101         /* tc action stats */
 102         struct mlx5e_tc_act_stats_handle *action_stats_handle;
 103 };
 104
 105 struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
 106         [MAPPED_OBJ_TO_REG] = {
 107                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
 108                 .moffset = 0,
 109                 .mlen = 16,
 110         },
 111         [VPORT_TO_REG] = {
 112                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
 113                 .moffset = 16,
 114                 .mlen = 16,
 115         },
 116         [TUNNEL_TO_REG] = {
 117                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
 118                 .moffset = 8,
 119                 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
 120                 .soffset = MLX5_BYTE_OFF(fte_match_param,
 121                                          misc_parameters_2.metadata_reg_c_1),
 122         },
 123         [ZONE_TO_REG] = zone_to_reg_ct,
 124         [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
 125         [CTSTATE_TO_REG] = ctstate_to_reg_ct,
 126         [MARK_TO_REG] = mark_to_reg_ct,
 127         [LABELS_TO_REG] = labels_to_reg_ct,
 128         [FTEID_TO_REG] = fteid_to_reg_ct,
 129         /* For NIC rules we store the restore metadata directly
 130          * into reg_b that is passed to SW since we don't
 131          * jump between steering domains.
 132          */
 133         [NIC_MAPPED_OBJ_TO_REG] = {
 134                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
 135                 .moffset = 0,
 136                 .mlen = 16,
 137         },
 138         [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
 139         [PACKET_COLOR_TO_REG] = packet_color_to_reg,
 140 };
 141
 142 struct mlx5e_tc_jump_state {
 143         u32 jump_count;
 144         bool jump_target;
 145         struct mlx5_flow_attr *jumping_attr;
 146
 147         enum flow_action_id last_id;
 148         u32 last_index;
 149 };
 150
 151 struct mlx5e_tc_table *mlx5e_tc_table_alloc(void)
 152 {
 153         struct mlx5e_tc_table *tc;
 154
 155         tc = kvzalloc(sizeof(*tc), GFP_KERNEL);
 156         return tc ? tc : ERR_PTR(-ENOMEM);
 157 }
 158
 159 void mlx5e_tc_table_free(struct mlx5e_tc_table *tc)
 160 {
 161         kvfree(tc);
 162 }
 163
 164 struct mlx5_fs_chains *mlx5e_nic_chains(struct mlx5e_tc_table *tc)
 165 {
 166         return tc->chains;
 167 }
 168
 169 /* To avoid false lock dependency warning set the tc_ht lock
 170  * class different than the lock class of the ht being used when deleting
 171  * last flow from a group and then deleting a group, we get into del_sw_flow_group()
 172  * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
 173  * it's different than the ht->mutex here.
 174  */
 175 static struct lock_class_key tc_ht_lock_key;
 176 static struct lock_class_key tc_ht_wq_key;
 177
 178 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
 179 static void free_flow_post_acts(struct mlx5e_tc_flow *flow);
 180 static void mlx5_free_flow_attr_actions(struct mlx5e_tc_flow *flow,
 181                                         struct mlx5_flow_attr *attr);
 182
 183 void
 184 mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
 185                             enum mlx5e_tc_attr_to_reg type,
 186                             u32 val,
 187                             u32 mask)
 188 {
 189         void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
 190         int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
 191         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 192         int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 193         u32 max_mask = GENMASK(match_len - 1, 0);
 194         __be32 curr_mask_be, curr_val_be;
 195         u32 curr_mask, curr_val;
 196
 197         fmask = headers_c + soffset;
 198         fval = headers_v + soffset;
 199
 200         memcpy(&curr_mask_be, fmask, 4);
 201         memcpy(&curr_val_be, fval, 4);
 202
 203         curr_mask = be32_to_cpu(curr_mask_be);
 204         curr_val = be32_to_cpu(curr_val_be);
 205
 206         //move to correct offset
 207         WARN_ON(mask > max_mask);
 208         mask <<= moffset;
 209         val <<= moffset;
 210         max_mask <<= moffset;
 211
 212         //zero val and mask
 213         curr_mask &= ~max_mask;
 214         curr_val &= ~max_mask;
 215
 216         //add current to mask
 217         curr_mask |= mask;
 218         curr_val |= val;
 219
 220         //back to be32 and write
 221         curr_mask_be = cpu_to_be32(curr_mask);
 222         curr_val_be = cpu_to_be32(curr_val);
 223
 224         memcpy(fmask, &curr_mask_be, 4);
 225         memcpy(fval, &curr_val_be, 4);
 226
 227         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
 228 }
 229
 230 void
 231 mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
 232                                 enum mlx5e_tc_attr_to_reg type,
 233                                 u32 *val,
 234                                 u32 *mask)
 235 {
 236         void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
 237         int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
 238         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 239         int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 240         u32 max_mask = GENMASK(match_len - 1, 0);
 241         __be32 curr_mask_be, curr_val_be;
 242         u32 curr_mask, curr_val;
 243
 244         fmask = headers_c + soffset;
 245         fval = headers_v + soffset;
 246
 247         memcpy(&curr_mask_be, fmask, 4);
 248         memcpy(&curr_val_be, fval, 4);
 249
 250         curr_mask = be32_to_cpu(curr_mask_be);
 251         curr_val = be32_to_cpu(curr_val_be);
 252
 253         *mask = (curr_mask >> moffset) & max_mask;
 254         *val = (curr_val >> moffset) & max_mask;
 255 }
 256
 257 int
 258 mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
 259                                      struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 260                                      enum mlx5_flow_namespace_type ns,
 261                                      enum mlx5e_tc_attr_to_reg type,
 262                                      u32 data)
 263 {
 264         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 265         int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
 266         int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 267         char *modact;
 268         int err;
 269
 270         modact = mlx5e_mod_hdr_alloc(mdev, ns, mod_hdr_acts);
 271         if (IS_ERR(modact))
 272                 return PTR_ERR(modact);
 273
 274         /* Firmware has 5bit length field and 0 means 32bits */
 275         if (mlen == 32)
 276                 mlen = 0;
 277
 278         MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
 279         MLX5_SET(set_action_in, modact, field, mfield);
 280         MLX5_SET(set_action_in, modact, offset, moffset);
 281         MLX5_SET(set_action_in, modact, length, mlen);
 282         MLX5_SET(set_action_in, modact, data, data);
 283         err = mod_hdr_acts->num_actions;
 284         mod_hdr_acts->num_actions++;
 285
 286         return err;
 287 }
 288
 289 static struct mlx5e_tc_act_stats_handle  *
 290 get_act_stats_handle(struct mlx5e_priv *priv)
 291 {
 292         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 293         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 294         struct mlx5_rep_uplink_priv *uplink_priv;
 295         struct mlx5e_rep_priv *uplink_rpriv;
 296
 297         if (is_mdev_switchdev_mode(priv->mdev)) {
 298                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 299                 uplink_priv = &uplink_rpriv->uplink_priv;
 300
 301                 return uplink_priv->action_stats_handle;
 302         }
 303
 304         return tc->action_stats_handle;
 305 }
 306
 307 struct mlx5e_tc_int_port_priv *
 308 mlx5e_get_int_port_priv(struct mlx5e_priv *priv)
 309 {
 310         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 311         struct mlx5_rep_uplink_priv *uplink_priv;
 312         struct mlx5e_rep_priv *uplink_rpriv;
 313
 314         if (is_mdev_switchdev_mode(priv->mdev)) {
 315                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 316                 uplink_priv = &uplink_rpriv->uplink_priv;
 317
 318                 return uplink_priv->int_port_priv;
 319         }
 320
 321         return NULL;
 322 }
 323
 324 struct mlx5e_flow_meters *
 325 mlx5e_get_flow_meters(struct mlx5_core_dev *dev)
 326 {
 327         struct mlx5_eswitch *esw = dev->priv.eswitch;
 328         struct mlx5_rep_uplink_priv *uplink_priv;
 329         struct mlx5e_rep_priv *uplink_rpriv;
 330         struct mlx5e_priv *priv;
 331
 332         if (is_mdev_switchdev_mode(dev)) {
 333                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 334                 uplink_priv = &uplink_rpriv->uplink_priv;
 335                 priv = netdev_priv(uplink_rpriv->netdev);
 336                 if (!uplink_priv->flow_meters)
 337                         uplink_priv->flow_meters =
 338                                 mlx5e_flow_meters_init(priv,
 339                                                        MLX5_FLOW_NAMESPACE_FDB,
 340                                                        uplink_priv->post_act);
 341                 if (!IS_ERR(uplink_priv->flow_meters))
 342                         return uplink_priv->flow_meters;
 343         }
 344
 345         return NULL;
 346 }
 347
 348 static struct mlx5_tc_ct_priv *
 349 get_ct_priv(struct mlx5e_priv *priv)
 350 {
 351         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 352         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 353         struct mlx5_rep_uplink_priv *uplink_priv;
 354         struct mlx5e_rep_priv *uplink_rpriv;
 355
 356         if (is_mdev_switchdev_mode(priv->mdev)) {
 357                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 358                 uplink_priv = &uplink_rpriv->uplink_priv;
 359
 360                 return uplink_priv->ct_priv;
 361         }
 362
 363         return tc->ct;
 364 }
 365
 366 static struct mlx5e_tc_psample *
 367 get_sample_priv(struct mlx5e_priv *priv)
 368 {
 369         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 370         struct mlx5_rep_uplink_priv *uplink_priv;
 371         struct mlx5e_rep_priv *uplink_rpriv;
 372
 373         if (is_mdev_switchdev_mode(priv->mdev)) {
 374                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 375                 uplink_priv = &uplink_rpriv->uplink_priv;
 376
 377                 return uplink_priv->tc_psample;
 378         }
 379
 380         return NULL;
 381 }
 382
 383 static struct mlx5e_post_act *
 384 get_post_action(struct mlx5e_priv *priv)
 385 {
 386         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 387         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 388         struct mlx5_rep_uplink_priv *uplink_priv;
 389         struct mlx5e_rep_priv *uplink_rpriv;
 390
 391         if (is_mdev_switchdev_mode(priv->mdev)) {
 392                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 393                 uplink_priv = &uplink_rpriv->uplink_priv;
 394
 395                 return uplink_priv->post_act;
 396         }
 397
 398         return tc->post_act;
 399 }
 400
 401 struct mlx5_flow_handle *
 402 mlx5_tc_rule_insert(struct mlx5e_priv *priv,
 403                     struct mlx5_flow_spec *spec,
 404                     struct mlx5_flow_attr *attr)
 405 {
 406         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 407
 408         if (is_mdev_switchdev_mode(priv->mdev))
 409                 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
 410
 411         return  mlx5e_add_offloaded_nic_rule(priv, spec, attr);
 412 }
 413
 414 void
 415 mlx5_tc_rule_delete(struct mlx5e_priv *priv,
 416                     struct mlx5_flow_handle *rule,
 417                     struct mlx5_flow_attr *attr)
 418 {
 419         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 420
 421         if (is_mdev_switchdev_mode(priv->mdev)) {
 422                 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
 423                 return;
 424         }
 425
 426         mlx5e_del_offloaded_nic_rule(priv, rule, attr);
 427 }
 428
 429 static bool
 430 is_flow_meter_action(struct mlx5_flow_attr *attr)
 431 {
 432         return (((attr->action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
 433                  (attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)) ||
 434                 attr->flags & MLX5_ATTR_FLAG_MTU);
 435 }
 436
 437 static int
 438 mlx5e_tc_add_flow_meter(struct mlx5e_priv *priv,
 439                         struct mlx5_flow_attr *attr)
 440 {
 441         struct mlx5e_post_act *post_act = get_post_action(priv);
 442         struct mlx5e_post_meter_priv *post_meter;
 443         enum mlx5_flow_namespace_type ns_type;
 444         struct mlx5e_flow_meter_handle *meter;
 445         enum mlx5e_post_meter_type type;
 446
 447         if (IS_ERR(post_act))
 448                 return PTR_ERR(post_act);
 449
 450         meter = mlx5e_tc_meter_replace(priv->mdev, &attr->meter_attr.params);
 451         if (IS_ERR(meter)) {
 452                 mlx5_core_err(priv->mdev, "Failed to get flow meter\n");
 453                 return PTR_ERR(meter);
 454         }
 455
 456         ns_type = mlx5e_tc_meter_get_namespace(meter->flow_meters);
 457         type = meter->params.mtu ? MLX5E_POST_METER_MTU : MLX5E_POST_METER_RATE;
 458         post_meter = mlx5e_post_meter_init(priv, ns_type, post_act,
 459                                            type,
 460                                            meter->act_counter, meter->drop_counter,
 461                                            attr->branch_true, attr->branch_false);
 462         if (IS_ERR(post_meter)) {
 463                 mlx5_core_err(priv->mdev, "Failed to init post meter\n");
 464                 goto err_meter_init;
 465         }
 466
 467         attr->meter_attr.meter = meter;
 468         attr->meter_attr.post_meter = post_meter;
 469         attr->dest_ft = mlx5e_post_meter_get_ft(post_meter);
 470         attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
 471
 472         return 0;
 473
 474 err_meter_init:
 475         mlx5e_tc_meter_put(meter);
 476         return PTR_ERR(post_meter);
 477 }
 478
 479 static void
 480 mlx5e_tc_del_flow_meter(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
 481 {
 482         mlx5e_post_meter_cleanup(esw, attr->meter_attr.post_meter);
 483         mlx5e_tc_meter_put(attr->meter_attr.meter);
 484 }
 485
 486 struct mlx5_flow_handle *
 487 mlx5e_tc_rule_offload(struct mlx5e_priv *priv,
 488                       struct mlx5_flow_spec *spec,
 489                       struct mlx5_flow_attr *attr)
 490 {
 491         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 492         int err;
 493
 494         if (!is_mdev_switchdev_mode(priv->mdev))
 495                 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
 496
 497         if (attr->flags & MLX5_ATTR_FLAG_SAMPLE)
 498                 return mlx5e_tc_sample_offload(get_sample_priv(priv), spec, attr);
 499
 500         if (is_flow_meter_action(attr)) {
 501                 err = mlx5e_tc_add_flow_meter(priv, attr);
 502                 if (err)
 503                         return ERR_PTR(err);
 504         }
 505
 506         return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
 507 }
 508
 509 void
 510 mlx5e_tc_rule_unoffload(struct mlx5e_priv *priv,
 511                         struct mlx5_flow_handle *rule,
 512                         struct mlx5_flow_attr *attr)
 513 {
 514         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 515
 516         if (!is_mdev_switchdev_mode(priv->mdev)) {
 517                 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
 518                 return;
 519         }
 520
 521         if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
 522                 mlx5e_tc_sample_unoffload(get_sample_priv(priv), rule, attr);
 523                 return;
 524         }
 525
 526         mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
 527
 528         if (attr->meter_attr.meter)
 529                 mlx5e_tc_del_flow_meter(esw, attr);
 530 }
 531
 532 int
 533 mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
 534                           struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 535                           enum mlx5_flow_namespace_type ns,
 536                           enum mlx5e_tc_attr_to_reg type,
 537                           u32 data)
 538 {
 539         int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
 540
 541         return ret < 0 ? ret : 0;
 542 }
 543
 544 void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
 545                                           struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 546                                           enum mlx5e_tc_attr_to_reg type,
 547                                           int act_id, u32 data)
 548 {
 549         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 550         int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
 551         int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 552         char *modact;
 553
 554         modact = mlx5e_mod_hdr_get_item(mod_hdr_acts, act_id);
 555
 556         /* Firmware has 5bit length field and 0 means 32bits */
 557         if (mlen == 32)
 558                 mlen = 0;
 559
 560         MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
 561         MLX5_SET(set_action_in, modact, field, mfield);
 562         MLX5_SET(set_action_in, modact, offset, moffset);
 563         MLX5_SET(set_action_in, modact, length, mlen);
 564         MLX5_SET(set_action_in, modact, data, data);
 565 }
 566
 567 struct mlx5e_hairpin {
 568         struct mlx5_hairpin *pair;
 569
 570         struct mlx5_core_dev *func_mdev;
 571         struct mlx5e_priv *func_priv;
 572         u32 tdn;
 573         struct mlx5e_tir direct_tir;
 574
 575         int num_channels;
 576         u8 log_num_packets;
 577         struct mlx5e_rqt indir_rqt;
 578         struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
 579         struct mlx5_ttc_table *ttc;
 580 };
 581
 582 struct mlx5e_hairpin_entry {
 583         /* a node of a hash table which keeps all the  hairpin entries */
 584         struct hlist_node hairpin_hlist;
 585
 586         /* protects flows list */
 587         spinlock_t flows_lock;
 588         /* flows sharing the same hairpin */
 589         struct list_head flows;
 590         /* hpe's that were not fully initialized when dead peer update event
 591          * function traversed them.
 592          */
 593         struct list_head dead_peer_wait_list;
 594
 595         u16 peer_vhca_id;
 596         u8 prio;
 597         struct mlx5e_hairpin *hp;
 598         refcount_t refcnt;
 599         struct completion res_ready;
 600 };
 601
 602 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
 603                               struct mlx5e_tc_flow *flow);
 604
 605 struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
 606 {
 607         if (!flow || !refcount_inc_not_zero(&flow->refcnt))
 608                 return ERR_PTR(-EINVAL);
 609         return flow;
 610 }
 611
 612 void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
 613 {
 614         if (refcount_dec_and_test(&flow->refcnt)) {
 615                 mlx5e_tc_del_flow(priv, flow);
 616                 kfree_rcu(flow, rcu_head);
 617         }
 618 }
 619
 620 bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
 621 {
 622         return flow_flag_test(flow, ESWITCH);
 623 }
 624
 625 bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
 626 {
 627         return flow_flag_test(flow, FT);
 628 }
 629
 630 bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
 631 {
 632         return flow_flag_test(flow, OFFLOADED);
 633 }
 634
 635 int mlx5e_get_flow_namespace(struct mlx5e_tc_flow *flow)
 636 {
 637         return mlx5e_is_eswitch_flow(flow) ?
 638                 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
 639 }
 640
 641 static struct mlx5_core_dev *
 642 get_flow_counter_dev(struct mlx5e_tc_flow *flow)
 643 {
 644         return mlx5e_is_eswitch_flow(flow) ? flow->attr->esw_attr->counter_dev : flow->priv->mdev;
 645 }
 646
 647 static struct mod_hdr_tbl *
 648 get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
 649 {
 650         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 651         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 652
 653         return mlx5e_get_flow_namespace(flow) == MLX5_FLOW_NAMESPACE_FDB ?
 654                 &esw->offloads.mod_hdr :
 655                 &tc->mod_hdr;
 656 }
 657
 658 int mlx5e_tc_attach_mod_hdr(struct mlx5e_priv *priv,
 659                             struct mlx5e_tc_flow *flow,
 660                             struct mlx5_flow_attr *attr)
 661 {
 662         struct mlx5e_mod_hdr_handle *mh;
 663
 664         mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
 665                                   mlx5e_get_flow_namespace(flow),
 666                                   &attr->parse_attr->mod_hdr_acts);
 667         if (IS_ERR(mh))
 668                 return PTR_ERR(mh);
 669
 670         WARN_ON(attr->modify_hdr);
 671         attr->modify_hdr = mlx5e_mod_hdr_get(mh);
 672         attr->mh = mh;
 673
 674         return 0;
 675 }
 676
 677 void mlx5e_tc_detach_mod_hdr(struct mlx5e_priv *priv,
 678                              struct mlx5e_tc_flow *flow,
 679                              struct mlx5_flow_attr *attr)
 680 {
 681         /* flow wasn't fully initialized */
 682         if (!attr->mh)
 683                 return;
 684
 685         mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
 686                              attr->mh);
 687         attr->mh = NULL;
 688 }
 689
 690 static
 691 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
 692 {
 693         struct mlx5_core_dev *mdev;
 694         struct net_device *netdev;
 695         struct mlx5e_priv *priv;
 696
 697         netdev = dev_get_by_index(net, ifindex);
 698         if (!netdev)
 699                 return ERR_PTR(-ENODEV);
 700
 701         priv = netdev_priv(netdev);
 702         mdev = priv->mdev;
 703         dev_put(netdev);
 704
 705         /* Mirred tc action holds a refcount on the ifindex net_device (see
 706          * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
 707          * after dev_put(netdev), while we're in the context of adding a tc flow.
 708          *
 709          * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
 710          * stored in a hairpin object, which exists until all flows, that refer to it, get
 711          * removed.
 712          *
 713          * On the other hand, after a hairpin object has been created, the peer net_device may
 714          * be removed/unbound while there are still some hairpin flows that are using it. This
 715          * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
 716          * NETDEV_UNREGISTER event of the peer net_device.
 717          */
 718         return mdev;
 719 }
 720
 721 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
 722 {
 723         struct mlx5e_tir_builder *builder;
 724         int err;
 725
 726         builder = mlx5e_tir_builder_alloc(false);
 727         if (!builder)
 728                 return -ENOMEM;
 729
 730         err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
 731         if (err)
 732                 goto out;
 733
 734         mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
 735         err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
 736         if (err)
 737                 goto create_tir_err;
 738
 739 out:
 740         mlx5e_tir_builder_free(builder);
 741         return err;
 742
 743 create_tir_err:
 744         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 745
 746         goto out;
 747 }
 748
 749 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
 750 {
 751         mlx5e_tir_destroy(&hp->direct_tir);
 752         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 753 }
 754
 755 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
 756 {
 757         struct mlx5e_priv *priv = hp->func_priv;
 758         struct mlx5_core_dev *mdev = priv->mdev;
 759         struct mlx5e_rss_params_indir indir;
 760         int err;
 761
 762         err = mlx5e_rss_params_indir_init(&indir, mdev,
 763                                           mlx5e_rqt_size(mdev, hp->num_channels),
 764                                           mlx5e_rqt_size(mdev, priv->max_nch));
 765         if (err)
 766                 return err;
 767
 768         mlx5e_rss_params_indir_init_uniform(&indir, hp->num_channels);
 769         err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
 770                                    mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
 771                                    &indir);
 772
 773         mlx5e_rss_params_indir_cleanup(&indir);
 774         return err;
 775 }
 776
 777 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
 778 {
 779         struct mlx5e_priv *priv = hp->func_priv;
 780         struct mlx5e_rss_params_hash rss_hash;
 781         enum mlx5_traffic_types tt, max_tt;
 782         struct mlx5e_tir_builder *builder;
 783         int err = 0;
 784
 785         builder = mlx5e_tir_builder_alloc(false);
 786         if (!builder)
 787                 return -ENOMEM;
 788
 789         rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
 790
 791         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
 792                 struct mlx5e_rss_params_traffic_type rss_tt;
 793
 794                 rss_tt = mlx5e_rss_get_default_tt_config(tt);
 795
 796                 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
 797                                             mlx5e_rqt_get_rqtn(&hp->indir_rqt),
 798                                             false);
 799                 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
 800
 801                 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
 802                 if (err) {
 803                         mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
 804                         goto err_destroy_tirs;
 805                 }
 806
 807                 mlx5e_tir_builder_clear(builder);
 808         }
 809
 810 out:
 811         mlx5e_tir_builder_free(builder);
 812         return err;
 813
 814 err_destroy_tirs:
 815         max_tt = tt;
 816         for (tt = 0; tt < max_tt; tt++)
 817                 mlx5e_tir_destroy(&hp->indir_tir[tt]);
 818
 819         goto out;
 820 }
 821
 822 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
 823 {
 824         int tt;
 825
 826         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 827                 mlx5e_tir_destroy(&hp->indir_tir[tt]);
 828 }
 829
 830 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
 831                                          struct ttc_params *ttc_params)
 832 {
 833         struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
 834         int tt;
 835
 836         memset(ttc_params, 0, sizeof(*ttc_params));
 837
 838         ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
 839                                                  MLX5_FLOW_NAMESPACE_KERNEL);
 840         for (tt = 0; tt < MLX5_NUM_TT; tt++) {
 841                 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
 842                 ttc_params->dests[tt].tir_num =
 843                         tt == MLX5_TT_ANY ?
 844                                 mlx5e_tir_get_tirn(&hp->direct_tir) :
 845                                 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
 846         }
 847
 848         ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
 849         ft_attr->prio = MLX5E_TC_PRIO;
 850 }
 851
 852 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
 853 {
 854         struct mlx5e_priv *priv = hp->func_priv;
 855         struct ttc_params ttc_params;
 856         struct mlx5_ttc_table *ttc;
 857         int err;
 858
 859         err = mlx5e_hairpin_create_indirect_rqt(hp);
 860         if (err)
 861                 return err;
 862
 863         err = mlx5e_hairpin_create_indirect_tirs(hp);
 864         if (err)
 865                 goto err_create_indirect_tirs;
 866
 867         mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
 868         hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
 869         if (IS_ERR(hp->ttc)) {
 870                 err = PTR_ERR(hp->ttc);
 871                 goto err_create_ttc_table;
 872         }
 873
 874         ttc = mlx5e_fs_get_ttc(priv->fs, false);
 875         netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
 876                    hp->num_channels,
 877                    mlx5_get_ttc_flow_table(ttc)->id);
 878
 879         return 0;
 880
 881 err_create_ttc_table:
 882         mlx5e_hairpin_destroy_indirect_tirs(hp);
 883 err_create_indirect_tirs:
 884         mlx5e_rqt_destroy(&hp->indir_rqt);
 885
 886         return err;
 887 }
 888
 889 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
 890 {
 891         mlx5_destroy_ttc_table(hp->ttc);
 892         mlx5e_hairpin_destroy_indirect_tirs(hp);
 893         mlx5e_rqt_destroy(&hp->indir_rqt);
 894 }
 895
 896 static struct mlx5e_hairpin *
 897 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
 898                      int peer_ifindex)
 899 {
 900         struct mlx5_core_dev *func_mdev, *peer_mdev;
 901         struct mlx5e_hairpin *hp;
 902         struct mlx5_hairpin *pair;
 903         int err;
 904
 905         hp = kzalloc(sizeof(*hp), GFP_KERNEL);
 906         if (!hp)
 907                 return ERR_PTR(-ENOMEM);
 908
 909         func_mdev = priv->mdev;
 910         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 911         if (IS_ERR(peer_mdev)) {
 912                 err = PTR_ERR(peer_mdev);
 913                 goto create_pair_err;
 914         }
 915
 916         pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
 917         if (IS_ERR(pair)) {
 918                 err = PTR_ERR(pair);
 919                 goto create_pair_err;
 920         }
 921         hp->pair = pair;
 922         hp->func_mdev = func_mdev;
 923         hp->func_priv = priv;
 924         hp->num_channels = params->num_channels;
 925         hp->log_num_packets = params->log_num_packets;
 926
 927         err = mlx5e_hairpin_create_transport(hp);
 928         if (err)
 929                 goto create_transport_err;
 930
 931         if (hp->num_channels > 1) {
 932                 err = mlx5e_hairpin_rss_init(hp);
 933                 if (err)
 934                         goto rss_init_err;
 935         }
 936
 937         return hp;
 938
 939 rss_init_err:
 940         mlx5e_hairpin_destroy_transport(hp);
 941 create_transport_err:
 942         mlx5_core_hairpin_destroy(hp->pair);
 943 create_pair_err:
 944         kfree(hp);
 945         return ERR_PTR(err);
 946 }
 947
 948 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
 949 {
 950         if (hp->num_channels > 1)
 951                 mlx5e_hairpin_rss_cleanup(hp);
 952         mlx5e_hairpin_destroy_transport(hp);
 953         mlx5_core_hairpin_destroy(hp->pair);
 954         kvfree(hp);
 955 }
 956
 957 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
 958 {
 959         return (peer_vhca_id << 16 | prio);
 960 }
 961
 962 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
 963                                                      u16 peer_vhca_id, u8 prio)
 964 {
 965         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 966         struct mlx5e_hairpin_entry *hpe;
 967         u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
 968
 969         hash_for_each_possible(tc->hairpin_tbl, hpe,
 970                                hairpin_hlist, hash_key) {
 971                 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
 972                         refcount_inc(&hpe->refcnt);
 973                         return hpe;
 974                 }
 975         }
 976
 977         return NULL;
 978 }
 979
 980 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
 981                               struct mlx5e_hairpin_entry *hpe)
 982 {
 983         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 984         /* no more hairpin flows for us, release the hairpin pair */
 985         if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &tc->hairpin_tbl_lock))
 986                 return;
 987         hash_del(&hpe->hairpin_hlist);
 988         mutex_unlock(&tc->hairpin_tbl_lock);
 989
 990         if (!IS_ERR_OR_NULL(hpe->hp)) {
 991                 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
 992                            dev_name(hpe->hp->pair->peer_mdev->device));
 993
 994                 mlx5e_hairpin_destroy(hpe->hp);
 995         }
 996
 997         WARN_ON(!list_empty(&hpe->flows));
 998         kfree(hpe);
 999 }
1000
1001 #define UNKNOWN_MATCH_PRIO 8
1002
1003 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
1004                                   struct mlx5_flow_spec *spec, u8 *match_prio,
1005                                   struct netlink_ext_ack *extack)
1006 {
1007         void *headers_c, *headers_v;
1008         u8 prio_val, prio_mask = 0;
1009         bool vlan_present;
1010
1011 #ifdef CONFIG_MLX5_CORE_EN_DCB
1012         if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
1013                 NL_SET_ERR_MSG_MOD(extack,
1014                                    "only PCP trust state supported for hairpin");
1015                 return -EOPNOTSUPP;
1016         }
1017 #endif
1018         headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
1019         headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1020
1021         vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
1022         if (vlan_present) {
1023                 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
1024                 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
1025         }
1026
1027         if (!vlan_present || !prio_mask) {
1028                 prio_val = UNKNOWN_MATCH_PRIO;
1029         } else if (prio_mask != 0x7) {
1030                 NL_SET_ERR_MSG_MOD(extack,
1031                                    "masked priority match not supported for hairpin");
1032                 return -EOPNOTSUPP;
1033         }
1034
1035         *match_prio = prio_val;
1036         return 0;
1037 }
1038
1039 static int debugfs_hairpin_num_active_get(void *data, u64 *val)
1040 {
1041         struct mlx5e_tc_table *tc = data;
1042         struct mlx5e_hairpin_entry *hpe;
1043         u32 cnt = 0;
1044         u32 bkt;
1045
1046         mutex_lock(&tc->hairpin_tbl_lock);
1047         hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
1048                 cnt++;
1049         mutex_unlock(&tc->hairpin_tbl_lock);
1050
1051         *val = cnt;
1052
1053         return 0;
1054 }
1055 DEFINE_DEBUGFS_ATTRIBUTE(fops_hairpin_num_active,
1056                          debugfs_hairpin_num_active_get, NULL, "%llu\n");
1057
1058 static int debugfs_hairpin_table_dump_show(struct seq_file *file, void *priv)
1059
1060 {
1061         struct mlx5e_tc_table *tc = file->private;
1062         struct mlx5e_hairpin_entry *hpe;
1063         u32 bkt;
1064
1065         mutex_lock(&tc->hairpin_tbl_lock);
1066         hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
1067                 seq_printf(file,
1068                            "Hairpin peer_vhca_id %u prio %u refcnt %u num_channels %u num_packets %lu\n",
1069                            hpe->peer_vhca_id, hpe->prio,
1070                            refcount_read(&hpe->refcnt), hpe->hp->num_channels,
1071                            BIT(hpe->hp->log_num_packets));
1072         mutex_unlock(&tc->hairpin_tbl_lock);
1073
1074         return 0;
1075 }
1076 DEFINE_SHOW_ATTRIBUTE(debugfs_hairpin_table_dump);
1077
1078 static void mlx5e_tc_debugfs_init(struct mlx5e_tc_table *tc,
1079                                   struct dentry *dfs_root)
1080 {
1081         if (IS_ERR_OR_NULL(dfs_root))
1082                 return;
1083
1084         tc->dfs_root = debugfs_create_dir("tc", dfs_root);
1085
1086         debugfs_create_file("hairpin_num_active", 0444, tc->dfs_root, tc,
1087                             &fops_hairpin_num_active);
1088         debugfs_create_file("hairpin_table_dump", 0444, tc->dfs_root, tc,
1089                             &debugfs_hairpin_table_dump_fops);
1090 }
1091
1092 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
1093                                   struct mlx5e_tc_flow *flow,
1094                                   struct mlx5e_tc_flow_parse_attr *parse_attr,
1095                                   struct netlink_ext_ack *extack)
1096 {
1097         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1098         struct devlink *devlink = priv_to_devlink(priv->mdev);
1099         int peer_ifindex = parse_attr->mirred_ifindex[0];
1100         union devlink_param_value val = {};
1101         struct mlx5_hairpin_params params;
1102         struct mlx5_core_dev *peer_mdev;
1103         struct mlx5e_hairpin_entry *hpe;
1104         struct mlx5e_hairpin *hp;
1105         u8 match_prio;
1106         u16 peer_id;
1107         int err;
1108
1109         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
1110         if (IS_ERR(peer_mdev)) {
1111                 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
1112                 return PTR_ERR(peer_mdev);
1113         }
1114
1115         if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
1116                 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
1117                 return -EOPNOTSUPP;
1118         }
1119
1120         peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
1121         err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
1122                                      extack);
1123         if (err)
1124                 return err;
1125
1126         mutex_lock(&tc->hairpin_tbl_lock);
1127         hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
1128         if (hpe) {
1129                 mutex_unlock(&tc->hairpin_tbl_lock);
1130                 wait_for_completion(&hpe->res_ready);
1131
1132                 if (IS_ERR(hpe->hp)) {
1133                         err = -EREMOTEIO;
1134                         goto out_err;
1135                 }
1136                 goto attach_flow;
1137         }
1138
1139         hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
1140         if (!hpe) {
1141                 mutex_unlock(&tc->hairpin_tbl_lock);
1142                 return -ENOMEM;
1143         }
1144
1145         spin_lock_init(&hpe->flows_lock);
1146         INIT_LIST_HEAD(&hpe->flows);
1147         INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
1148         hpe->peer_vhca_id = peer_id;
1149         hpe->prio = match_prio;
1150         refcount_set(&hpe->refcnt, 1);
1151         init_completion(&hpe->res_ready);
1152
1153         hash_add(tc->hairpin_tbl, &hpe->hairpin_hlist,
1154                  hash_hairpin_info(peer_id, match_prio));
1155         mutex_unlock(&tc->hairpin_tbl_lock);
1156
1157         err = devl_param_driverinit_value_get(
1158                 devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE, &val);
1159         if (err) {
1160                 err = -ENOMEM;
1161                 goto out_err;
1162         }
1163
1164         params.log_num_packets = ilog2(val.vu32);
1165         params.log_data_size =
1166                 clamp_t(u32,
1167                         params.log_num_packets +
1168                                 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev),
1169                         MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz),
1170                         MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
1171
1172         params.q_counter = priv->q_counter;
1173         err = devl_param_driverinit_value_get(
1174                 devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES, &val);
1175         if (err) {
1176                 err = -ENOMEM;
1177                 goto out_err;
1178         }
1179
1180         params.num_channels = val.vu32;
1181
1182         hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
1183         hpe->hp = hp;
1184         complete_all(&hpe->res_ready);
1185         if (IS_ERR(hp)) {
1186                 err = PTR_ERR(hp);
1187                 goto out_err;
1188         }
1189
1190         netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
1191                    mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
1192                    dev_name(hp->pair->peer_mdev->device),
1193                    hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
1194
1195 attach_flow:
1196         if (hpe->hp->num_channels > 1) {
1197                 flow_flag_set(flow, HAIRPIN_RSS);
1198                 flow->attr->nic_attr->hairpin_ft =
1199                         mlx5_get_ttc_flow_table(hpe->hp->ttc);
1200         } else {
1201                 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
1202         }
1203
1204         flow->hpe = hpe;
1205         spin_lock(&hpe->flows_lock);
1206         list_add(&flow->hairpin, &hpe->flows);
1207         spin_unlock(&hpe->flows_lock);
1208
1209         return 0;
1210
1211 out_err:
1212         mlx5e_hairpin_put(priv, hpe);
1213         return err;
1214 }
1215
1216 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
1217                                    struct mlx5e_tc_flow *flow)
1218 {
1219         /* flow wasn't fully initialized */
1220         if (!flow->hpe)
1221                 return;
1222
1223         spin_lock(&flow->hpe->flows_lock);
1224         list_del(&flow->hairpin);
1225         spin_unlock(&flow->hpe->flows_lock);
1226
1227         mlx5e_hairpin_put(priv, flow->hpe);
1228         flow->hpe = NULL;
1229 }
1230
1231 struct mlx5_flow_handle *
1232 mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
1233                              struct mlx5_flow_spec *spec,
1234                              struct mlx5_flow_attr *attr)
1235 {
1236         struct mlx5_flow_context *flow_context = &spec->flow_context;
1237         struct mlx5e_vlan_table *vlan = mlx5e_fs_get_vlan(priv->fs);
1238         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1239         struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
1240         struct mlx5_flow_destination dest[2] = {};
1241         struct mlx5_fs_chains *nic_chains;
1242         struct mlx5_flow_act flow_act = {
1243                 .action = attr->action,
1244                 .flags    = FLOW_ACT_NO_APPEND,
1245         };
1246         struct mlx5_flow_handle *rule;
1247         struct mlx5_flow_table *ft;
1248         int dest_ix = 0;
1249
1250         nic_chains = mlx5e_nic_chains(tc);
1251         flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1252         flow_context->flow_tag = nic_attr->flow_tag;
1253
1254         if (attr->dest_ft) {
1255                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1256                 dest[dest_ix].ft = attr->dest_ft;
1257                 dest_ix++;
1258         } else if (nic_attr->hairpin_ft) {
1259                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1260                 dest[dest_ix].ft = nic_attr->hairpin_ft;
1261                 dest_ix++;
1262         } else if (nic_attr->hairpin_tirn) {
1263                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1264                 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
1265                 dest_ix++;
1266         } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1267                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1268                 if (attr->dest_chain) {
1269                         dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
1270                                                                  attr->dest_chain, 1,
1271                                                                  MLX5E_TC_FT_LEVEL);
1272                         if (IS_ERR(dest[dest_ix].ft))
1273                                 return ERR_CAST(dest[dest_ix].ft);
1274                 } else {
1275                         dest[dest_ix].ft = mlx5e_vlan_get_flowtable(vlan);
1276                 }
1277                 dest_ix++;
1278         }
1279
1280         if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
1281             MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
1282                 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
1283
1284         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1285                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
1286                 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
1287                 dest_ix++;
1288         }
1289
1290         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1291                 flow_act.modify_hdr = attr->modify_hdr;
1292
1293         mutex_lock(&tc->t_lock);
1294         if (IS_ERR_OR_NULL(tc->t)) {
1295                 /* Create the root table here if doesn't exist yet */
1296                 tc->t =
1297                         mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
1298
1299                 if (IS_ERR(tc->t)) {
1300                         mutex_unlock(&tc->t_lock);
1301                         netdev_err(priv->netdev,
1302                                    "Failed to create tc offload table\n");
1303                         rule = ERR_CAST(tc->t);
1304                         goto err_ft_get;
1305                 }
1306         }
1307         mutex_unlock(&tc->t_lock);
1308
1309         if (attr->chain || attr->prio)
1310                 ft = mlx5_chains_get_table(nic_chains,
1311                                            attr->chain, attr->prio,
1312                                            MLX5E_TC_FT_LEVEL);
1313         else
1314                 ft = attr->ft;
1315
1316         if (IS_ERR(ft)) {
1317                 rule = ERR_CAST(ft);
1318                 goto err_ft_get;
1319         }
1320
1321         if (attr->outer_match_level != MLX5_MATCH_NONE)
1322                 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
1323
1324         rule = mlx5_add_flow_rules(ft, spec,
1325                                    &flow_act, dest, dest_ix);
1326         if (IS_ERR(rule))
1327                 goto err_rule;
1328
1329         return rule;
1330
1331 err_rule:
1332         if (attr->chain || attr->prio)
1333                 mlx5_chains_put_table(nic_chains,
1334                                       attr->chain, attr->prio,
1335                                       MLX5E_TC_FT_LEVEL);
1336 err_ft_get:
1337         if (attr->dest_chain)
1338                 mlx5_chains_put_table(nic_chains,
1339                                       attr->dest_chain, 1,
1340                                       MLX5E_TC_FT_LEVEL);
1341
1342         return ERR_CAST(rule);
1343 }
1344
1345 static int
1346 alloc_flow_attr_counter(struct mlx5_core_dev *counter_dev,
1347                         struct mlx5_flow_attr *attr)
1348
1349 {
1350         struct mlx5_fc *counter;
1351
1352         counter = mlx5_fc_create(counter_dev, true);
1353         if (IS_ERR(counter))
1354                 return PTR_ERR(counter);
1355
1356         attr->counter = counter;
1357         return 0;
1358 }
1359
1360 static int
1361 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1362                       struct mlx5e_tc_flow *flow,
1363                       struct netlink_ext_ack *extack)
1364 {
1365         struct mlx5e_tc_flow_parse_attr *parse_attr;
1366         struct mlx5_flow_attr *attr = flow->attr;
1367         struct mlx5_core_dev *dev = priv->mdev;
1368         int err;
1369
1370         parse_attr = attr->parse_attr;
1371
1372         if (flow_flag_test(flow, HAIRPIN)) {
1373                 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1374                 if (err)
1375                         return err;
1376         }
1377
1378         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1379                 err = alloc_flow_attr_counter(dev, attr);
1380                 if (err)
1381                         return err;
1382         }
1383
1384         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1385                 err = mlx5e_tc_attach_mod_hdr(priv, flow, attr);
1386                 if (err)
1387                         return err;
1388         }
1389
1390         flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec, attr);
1391         return PTR_ERR_OR_ZERO(flow->rule[0]);
1392 }
1393
1394 void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
1395                                   struct mlx5_flow_handle *rule,
1396                                   struct mlx5_flow_attr *attr)
1397 {
1398         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1399         struct mlx5_fs_chains *nic_chains;
1400
1401         nic_chains = mlx5e_nic_chains(tc);
1402         mlx5_del_flow_rules(rule);
1403
1404         if (attr->chain || attr->prio)
1405                 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1406                                       MLX5E_TC_FT_LEVEL);
1407
1408         if (attr->dest_chain)
1409                 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1410                                       MLX5E_TC_FT_LEVEL);
1411 }
1412
1413 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1414                                   struct mlx5e_tc_flow *flow)
1415 {
1416         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1417         struct mlx5_flow_attr *attr = flow->attr;
1418
1419         flow_flag_clear(flow, OFFLOADED);
1420
1421         if (!IS_ERR_OR_NULL(flow->rule[0]))
1422                 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1423
1424         /* Remove root table if no rules are left to avoid
1425          * extra steering hops.
1426          */
1427         mutex_lock(&tc->t_lock);
1428         if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1429             !IS_ERR_OR_NULL(tc->t)) {
1430                 mlx5_chains_put_table(mlx5e_nic_chains(tc), 0, 1, MLX5E_TC_FT_LEVEL);
1431                 tc->t = NULL;
1432         }
1433         mutex_unlock(&tc->t_lock);
1434
1435         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1436                 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
1437                 mlx5e_tc_detach_mod_hdr(priv, flow, attr);
1438         }
1439
1440         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1441                 mlx5_fc_destroy(priv->mdev, attr->counter);
1442
1443         if (flow_flag_test(flow, HAIRPIN))
1444                 mlx5e_hairpin_flow_del(priv, flow);
1445
1446         free_flow_post_acts(flow);
1447         mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), attr);
1448
1449         kvfree(attr->parse_attr);
1450         kfree(flow->attr);
1451 }
1452
1453 struct mlx5_flow_handle *
1454 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1455                            struct mlx5e_tc_flow *flow,
1456                            struct mlx5_flow_spec *spec,
1457                            struct mlx5_flow_attr *attr)
1458 {
1459         struct mlx5_flow_handle *rule;
1460
1461         if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
1462                 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1463
1464         rule = mlx5e_tc_rule_offload(flow->priv, spec, attr);
1465
1466         if (IS_ERR(rule))
1467                 return rule;
1468
1469         if (attr->esw_attr->split_count) {
1470                 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1471                 if (IS_ERR(flow->rule[1]))
1472                         goto err_rule1;
1473         }
1474
1475         return rule;
1476
1477 err_rule1:
1478         mlx5e_tc_rule_unoffload(flow->priv, rule, attr);
1479         return flow->rule[1];
1480 }
1481
1482 void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1483                                   struct mlx5e_tc_flow *flow,
1484                                   struct mlx5_flow_attr *attr)
1485 {
1486         flow_flag_clear(flow, OFFLOADED);
1487
1488         if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
1489                 return mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1490
1491         if (attr->esw_attr->split_count)
1492                 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1493
1494         mlx5e_tc_rule_unoffload(flow->priv, flow->rule[0], attr);
1495 }
1496
1497 struct mlx5_flow_handle *
1498 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1499                               struct mlx5e_tc_flow *flow,
1500                               struct mlx5_flow_spec *spec)
1501 {
1502         struct mlx5e_tc_mod_hdr_acts mod_acts = {};
1503         struct mlx5e_mod_hdr_handle *mh = NULL;
1504         struct mlx5_flow_attr *slow_attr;
1505         struct mlx5_flow_handle *rule;
1506         bool fwd_and_modify_cap;
1507         u32 chain_mapping = 0;
1508         int err;
1509
1510         slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1511         if (!slow_attr)
1512                 return ERR_PTR(-ENOMEM);
1513
1514         memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1515         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1516         slow_attr->esw_attr->split_count = 0;
1517         slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
1518
1519         fwd_and_modify_cap = MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table);
1520         if (!fwd_and_modify_cap)
1521                 goto skip_restore;
1522
1523         err = mlx5_chains_get_chain_mapping(esw_chains(esw), flow->attr->chain, &chain_mapping);
1524         if (err)
1525                 goto err_get_chain;
1526
1527         err = mlx5e_tc_match_to_reg_set(esw->dev, &mod_acts, MLX5_FLOW_NAMESPACE_FDB,
1528                                         MAPPED_OBJ_TO_REG, chain_mapping);
1529         if (err)
1530                 goto err_reg_set;
1531
1532         mh = mlx5e_mod_hdr_attach(esw->dev, get_mod_hdr_table(flow->priv, flow),
1533                                   MLX5_FLOW_NAMESPACE_FDB, &mod_acts);
1534         if (IS_ERR(mh)) {
1535                 err = PTR_ERR(mh);
1536                 goto err_attach;
1537         }
1538
1539         slow_attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1540         slow_attr->modify_hdr = mlx5e_mod_hdr_get(mh);
1541
1542 skip_restore:
1543         rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1544         if (IS_ERR(rule)) {
1545                 err = PTR_ERR(rule);
1546                 goto err_offload;
1547         }
1548
1549         flow->attr->slow_mh = mh;
1550         flow->chain_mapping = chain_mapping;
1551         flow_flag_set(flow, SLOW);
1552
1553         mlx5e_mod_hdr_dealloc(&mod_acts);
1554         kfree(slow_attr);
1555
1556         return rule;
1557
1558 err_offload:
1559         if (fwd_and_modify_cap)
1560                 mlx5e_mod_hdr_detach(esw->dev, get_mod_hdr_table(flow->priv, flow), mh);
1561 err_attach:
1562 err_reg_set:
1563         if (fwd_and_modify_cap)
1564                 mlx5_chains_put_chain_mapping(esw_chains(esw), chain_mapping);
1565 err_get_chain:
1566         mlx5e_mod_hdr_dealloc(&mod_acts);
1567         kfree(slow_attr);
1568         return ERR_PTR(err);
1569 }
1570
1571 void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1572                                        struct mlx5e_tc_flow *flow)
1573 {
1574         struct mlx5e_mod_hdr_handle *slow_mh = flow->attr->slow_mh;
1575         struct mlx5_flow_attr *slow_attr;
1576
1577         slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1578         if (!slow_attr) {
1579                 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1580                 return;
1581         }
1582
1583         memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1584         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1585         slow_attr->esw_attr->split_count = 0;
1586         slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
1587         if (slow_mh) {
1588                 slow_attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1589                 slow_attr->modify_hdr = mlx5e_mod_hdr_get(slow_mh);
1590         }
1591         mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
1592         if (slow_mh) {
1593                 mlx5e_mod_hdr_detach(esw->dev, get_mod_hdr_table(flow->priv, flow), slow_mh);
1594                 mlx5_chains_put_chain_mapping(esw_chains(esw), flow->chain_mapping);
1595                 flow->chain_mapping = 0;
1596                 flow->attr->slow_mh = NULL;
1597         }
1598         flow_flag_clear(flow, SLOW);
1599         kfree(slow_attr);
1600 }
1601
1602 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1603  * function.
1604  */
1605 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1606                              struct list_head *unready_flows)
1607 {
1608         flow_flag_set(flow, NOT_READY);
1609         list_add_tail(&flow->unready, unready_flows);
1610 }
1611
1612 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1613  * function.
1614  */
1615 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1616 {
1617         list_del(&flow->unready);
1618         flow_flag_clear(flow, NOT_READY);
1619 }
1620
1621 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1622 {
1623         struct mlx5_rep_uplink_priv *uplink_priv;
1624         struct mlx5e_rep_priv *rpriv;
1625         struct mlx5_eswitch *esw;
1626
1627         esw = flow->priv->mdev->priv.eswitch;
1628         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1629         uplink_priv = &rpriv->uplink_priv;
1630
1631         mutex_lock(&uplink_priv->unready_flows_lock);
1632         unready_flow_add(flow, &uplink_priv->unready_flows);
1633         mutex_unlock(&uplink_priv->unready_flows_lock);
1634 }
1635
1636 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1637 {
1638         struct mlx5_rep_uplink_priv *uplink_priv;
1639         struct mlx5e_rep_priv *rpriv;
1640         struct mlx5_eswitch *esw;
1641
1642         esw = flow->priv->mdev->priv.eswitch;
1643         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1644         uplink_priv = &rpriv->uplink_priv;
1645
1646         mutex_lock(&uplink_priv->unready_flows_lock);
1647         if (flow_flag_test(flow, NOT_READY))
1648                 unready_flow_del(flow);
1649         mutex_unlock(&uplink_priv->unready_flows_lock);
1650 }
1651
1652 bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
1653 {
1654         struct mlx5_core_dev *out_mdev, *route_mdev;
1655         struct mlx5e_priv *out_priv, *route_priv;
1656
1657         out_priv = netdev_priv(out_dev);
1658         out_mdev = out_priv->mdev;
1659         route_priv = netdev_priv(route_dev);
1660         route_mdev = route_priv->mdev;
1661
1662         if (out_mdev->coredev_type != MLX5_COREDEV_PF)
1663                 return false;
1664
1665         if (route_mdev->coredev_type != MLX5_COREDEV_VF &&
1666             route_mdev->coredev_type != MLX5_COREDEV_SF)
1667                 return false;
1668
1669         return mlx5e_same_hw_devs(out_priv, route_priv);
1670 }
1671
1672 int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
1673 {
1674         struct mlx5e_priv *out_priv, *route_priv;
1675         struct mlx5_core_dev *route_mdev;
1676         struct mlx5_devcom_comp_dev *pos;
1677         struct mlx5_eswitch *esw;
1678         u16 vhca_id;
1679         int err;
1680
1681         out_priv = netdev_priv(out_dev);
1682         esw = out_priv->mdev->priv.eswitch;
1683         route_priv = netdev_priv(route_dev);
1684         route_mdev = route_priv->mdev;
1685
1686         vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1687         err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1688         if (!err)
1689                 return err;
1690
1691         if (!mlx5_lag_is_active(out_priv->mdev))
1692                 return err;
1693
1694         rcu_read_lock();
1695         err = -ENODEV;
1696         mlx5_devcom_for_each_peer_entry_rcu(esw->devcom, esw, pos) {
1697                 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1698                 if (!err)
1699                         break;
1700         }
1701         rcu_read_unlock();
1702
1703         return err;
1704 }
1705
1706 static int
1707 verify_attr_actions(u32 actions, struct netlink_ext_ack *extack)
1708 {
1709         if (!(actions &
1710               (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
1711                 NL_SET_ERR_MSG_MOD(extack, "Rule must have at least one forward/drop action");
1712                 return -EOPNOTSUPP;
1713         }
1714
1715         if (!(~actions &
1716               (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
1717                 NL_SET_ERR_MSG_MOD(extack, "Rule cannot support forward+drop action");
1718                 return -EOPNOTSUPP;
1719         }
1720
1721         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1722             actions & MLX5_FLOW_CONTEXT_ACTION_DROP) {
1723                 NL_SET_ERR_MSG_MOD(extack, "Drop with modify header action is not supported");
1724                 return -EOPNOTSUPP;
1725         }
1726
1727         return 0;
1728 }
1729
1730 static bool
1731 has_encap_dests(struct mlx5_flow_attr *attr)
1732 {
1733         struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
1734         int out_index;
1735
1736         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1737                 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1738                         return true;
1739
1740         return false;
1741 }
1742
1743 static int
1744 post_process_attr(struct mlx5e_tc_flow *flow,
1745                   struct mlx5_flow_attr *attr,
1746                   struct netlink_ext_ack *extack)
1747 {
1748         bool vf_tun;
1749         int err = 0;
1750
1751         err = verify_attr_actions(attr->action, extack);
1752         if (err)
1753                 goto err_out;
1754
1755         if (mlx5e_is_eswitch_flow(flow) && has_encap_dests(attr)) {
1756                 err = mlx5e_tc_tun_encap_dests_set(flow->priv, flow, attr, extack, &vf_tun);
1757                 if (err)
1758                         goto err_out;
1759         }
1760
1761         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1762                 err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr);
1763                 if (err)
1764                         goto err_out;
1765         }
1766
1767         if (attr->branch_true &&
1768             attr->branch_true->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1769                 err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr->branch_true);
1770                 if (err)
1771                         goto err_out;
1772         }
1773
1774         if (attr->branch_false &&
1775             attr->branch_false->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1776                 err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr->branch_false);
1777                 if (err)
1778                         goto err_out;
1779         }
1780
1781         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1782                 err = alloc_flow_attr_counter(get_flow_counter_dev(flow), attr);
1783                 if (err)
1784                         goto err_out;
1785         }
1786
1787 err_out:
1788         return err;
1789 }
1790
1791 static int
1792 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1793                       struct mlx5e_tc_flow *flow,
1794                       struct netlink_ext_ack *extack)
1795 {
1796         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1797         struct mlx5e_tc_flow_parse_attr *parse_attr;
1798         struct mlx5_flow_attr *attr = flow->attr;
1799         struct mlx5_esw_flow_attr *esw_attr;
1800         u32 max_prio, max_chain;
1801         int err = 0;
1802
1803         parse_attr = attr->parse_attr;
1804         esw_attr = attr->esw_attr;
1805
1806         /* We check chain range only for tc flows.
1807          * For ft flows, we checked attr->chain was originally 0 and set it to
1808          * FDB_FT_CHAIN which is outside tc range.
1809          * See mlx5e_rep_setup_ft_cb().
1810          */
1811         max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
1812         if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
1813                 NL_SET_ERR_MSG_MOD(extack,
1814                                    "Requested chain is out of supported range");
1815                 err = -EOPNOTSUPP;
1816                 goto err_out;
1817         }
1818
1819         max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
1820         if (attr->prio > max_prio) {
1821                 NL_SET_ERR_MSG_MOD(extack,
1822                                    "Requested priority is out of supported range");
1823                 err = -EOPNOTSUPP;
1824                 goto err_out;
1825         }
1826
1827         if (flow_flag_test(flow, TUN_RX)) {
1828                 err = mlx5e_attach_decap_route(priv, flow);
1829                 if (err)
1830                         goto err_out;
1831
1832                 if (!attr->chain && esw_attr->int_port &&
1833                     attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1834                         /* If decap route device is internal port, change the
1835                          * source vport value in reg_c0 back to uplink just in
1836                          * case the rule performs goto chain > 0. If we have a miss
1837                          * on chain > 0 we want the metadata regs to hold the
1838                          * chain id so SW will resume handling of this packet
1839                          * from the proper chain.
1840                          */
1841                         u32 metadata = mlx5_eswitch_get_vport_metadata_for_set(esw,
1842                                                                         esw_attr->in_rep->vport);
1843
1844                         err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
1845                                                         MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
1846                                                         metadata);
1847                         if (err)
1848                                 goto err_out;
1849
1850                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1851                 }
1852         }
1853
1854         if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1855                 err = mlx5e_attach_decap(priv, flow, extack);
1856                 if (err)
1857                         goto err_out;
1858         }
1859
1860         if (netif_is_ovs_master(parse_attr->filter_dev)) {
1861                 struct mlx5e_tc_int_port *int_port;
1862
1863                 if (attr->chain) {
1864                         NL_SET_ERR_MSG_MOD(extack,
1865                                            "Internal port rule is only supported on chain 0");
1866                         err = -EOPNOTSUPP;
1867                         goto err_out;
1868                 }
1869
1870                 if (attr->dest_chain) {
1871                         NL_SET_ERR_MSG_MOD(extack,
1872                                            "Internal port rule offload doesn't support goto action");
1873                         err = -EOPNOTSUPP;
1874                         goto err_out;
1875                 }
1876
1877                 int_port = mlx5e_tc_int_port_get(mlx5e_get_int_port_priv(priv),
1878                                                  parse_attr->filter_dev->ifindex,
1879                                                  flow_flag_test(flow, EGRESS) ?
1880                                                  MLX5E_TC_INT_PORT_EGRESS :
1881                                                  MLX5E_TC_INT_PORT_INGRESS);
1882                 if (IS_ERR(int_port)) {
1883                         err = PTR_ERR(int_port);
1884                         goto err_out;
1885                 }
1886
1887                 esw_attr->int_port = int_port;
1888         }
1889
1890         err = post_process_attr(flow, attr, extack);
1891         if (err)
1892                 goto err_out;
1893
1894         err = mlx5e_tc_act_stats_add_flow(get_act_stats_handle(priv), flow);
1895         if (err)
1896                 goto err_out;
1897
1898         /* we get here if one of the following takes place:
1899          * (1) there's no error
1900          * (2) there's an encap action and we don't have valid neigh
1901          */
1902         if (flow_flag_test(flow, SLOW))
1903                 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
1904         else
1905                 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
1906
1907         if (IS_ERR(flow->rule[0])) {
1908                 err = PTR_ERR(flow->rule[0]);
1909                 goto err_out;
1910         }
1911         flow_flag_set(flow, OFFLOADED);
1912
1913         return 0;
1914
1915 err_out:
1916         flow_flag_set(flow, FAILED);
1917         return err;
1918 }
1919
1920 static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1921 {
1922         struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
1923         void *headers_v = MLX5_ADDR_OF(fte_match_param,
1924                                        spec->match_value,
1925                                        misc_parameters_3);
1926         u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1927                                              headers_v,
1928                                              geneve_tlv_option_0_data);
1929
1930         return !!geneve_tlv_opt_0_data;
1931 }
1932
1933 static void free_branch_attr(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
1934 {
1935         if (!attr)
1936                 return;
1937
1938         mlx5_free_flow_attr_actions(flow, attr);
1939         kvfree(attr->parse_attr);
1940         kfree(attr);
1941 }
1942
1943 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1944                                   struct mlx5e_tc_flow *flow)
1945 {
1946         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1947         struct mlx5_flow_attr *attr = flow->attr;
1948
1949         mlx5e_put_flow_tunnel_id(flow);
1950
1951         remove_unready_flow(flow);
1952
1953         if (mlx5e_is_offloaded_flow(flow)) {
1954                 if (flow_flag_test(flow, SLOW))
1955                         mlx5e_tc_unoffload_from_slow_path(esw, flow);
1956                 else
1957                         mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1958         }
1959         complete_all(&flow->del_hw_done);
1960
1961         if (mlx5_flow_has_geneve_opt(flow))
1962                 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1963
1964         if (flow->decap_route)
1965                 mlx5e_detach_decap_route(priv, flow);
1966
1967         mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
1968
1969         if (flow_flag_test(flow, L3_TO_L2_DECAP))
1970                 mlx5e_detach_decap(priv, flow);
1971
1972         mlx5e_tc_act_stats_del_flow(get_act_stats_handle(priv), flow);
1973
1974         free_flow_post_acts(flow);
1975         mlx5_free_flow_attr_actions(flow, attr);
1976
1977         kvfree(attr->esw_attr->rx_tun_attr);
1978         kvfree(attr->parse_attr);
1979         kfree(flow->attr);
1980 }
1981
1982 struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1983 {
1984         struct mlx5_flow_attr *attr;
1985
1986         attr = list_first_entry(&flow->attrs, struct mlx5_flow_attr, list);
1987         return attr->counter;
1988 }
1989
1990 /* Iterate over tmp_list of flows attached to flow_list head. */
1991 void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
1992 {
1993         struct mlx5e_tc_flow *flow, *tmp;
1994
1995         list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1996                 mlx5e_flow_put(priv, flow);
1997 }
1998
1999 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow,
2000                                        int peer_index)
2001 {
2002         struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
2003         struct mlx5e_tc_flow *peer_flow;
2004         struct mlx5e_tc_flow *tmp;
2005
2006         if (!flow_flag_test(flow, ESWITCH) ||
2007             !flow_flag_test(flow, DUP))
2008                 return;
2009
2010         mutex_lock(&esw->offloads.peer_mutex);
2011         list_del(&flow->peer[peer_index]);
2012         mutex_unlock(&esw->offloads.peer_mutex);
2013
2014         list_for_each_entry_safe(peer_flow, tmp, &flow->peer_flows, peer_flows) {
2015                 if (peer_index != mlx5_get_dev_index(peer_flow->priv->mdev))
2016                         continue;
2017                 if (refcount_dec_and_test(&peer_flow->refcnt)) {
2018                         mlx5e_tc_del_fdb_flow(peer_flow->priv, peer_flow);
2019                         list_del(&peer_flow->peer_flows);
2020                         kfree(peer_flow);
2021                 }
2022         }
2023
2024         if (list_empty(&flow->peer_flows))
2025                 flow_flag_clear(flow, DUP);
2026 }
2027
2028 static void mlx5e_tc_del_fdb_peers_flow(struct mlx5e_tc_flow *flow)
2029 {
2030         int i;
2031
2032         for (i = 0; i < MLX5_MAX_PORTS; i++) {
2033                 if (i == mlx5_get_dev_index(flow->priv->mdev))
2034                         continue;
2035                 mlx5e_tc_del_fdb_peer_flow(flow, i);
2036         }
2037 }
2038
2039 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
2040                               struct mlx5e_tc_flow *flow)
2041 {
2042         if (mlx5e_is_eswitch_flow(flow)) {
2043                 struct mlx5_devcom_comp_dev *devcom = flow->priv->mdev->priv.eswitch->devcom;
2044
2045                 if (!mlx5_devcom_for_each_peer_begin(devcom)) {
2046                         mlx5e_tc_del_fdb_flow(priv, flow);
2047                         return;
2048                 }
2049
2050                 mlx5e_tc_del_fdb_peers_flow(flow);
2051                 mlx5_devcom_for_each_peer_end(devcom);
2052                 mlx5e_tc_del_fdb_flow(priv, flow);
2053         } else {
2054                 mlx5e_tc_del_nic_flow(priv, flow);
2055         }
2056 }
2057
2058 static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
2059 {
2060         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2061         struct flow_action *flow_action = &rule->action;
2062         const struct flow_action_entry *act;
2063         int i;
2064
2065         if (chain)
2066                 return false;
2067
2068         flow_action_for_each(i, act, flow_action) {
2069                 switch (act->id) {
2070                 case FLOW_ACTION_GOTO:
2071                         return true;
2072                 case FLOW_ACTION_SAMPLE:
2073                         return true;
2074                 default:
2075                         continue;
2076                 }
2077         }
2078
2079         return false;
2080 }
2081
2082 static int
2083 enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
2084                                     struct flow_dissector_key_enc_opts *opts,
2085                                     struct netlink_ext_ack *extack,
2086                                     bool *dont_care)
2087 {
2088         struct geneve_opt *opt;
2089         int off = 0;
2090
2091         *dont_care = true;
2092
2093         while (opts->len > off) {
2094                 opt = (struct geneve_opt *)&opts->data[off];
2095
2096                 if (!(*dont_care) || opt->opt_class || opt->type ||
2097                     memchr_inv(opt->opt_data, 0, opt->length * 4)) {
2098                         *dont_care = false;
2099
2100                         if (opt->opt_class != htons(U16_MAX) ||
2101                             opt->type != U8_MAX) {
2102                                 NL_SET_ERR_MSG_MOD(extack,
2103                                                    "Partial match of tunnel options in chain > 0 isn't supported");
2104                                 netdev_warn(priv->netdev,
2105                                             "Partial match of tunnel options in chain > 0 isn't supported");
2106                                 return -EOPNOTSUPP;
2107                         }
2108                 }
2109
2110                 off += sizeof(struct geneve_opt) + opt->length * 4;
2111         }
2112
2113         return 0;
2114 }
2115
2116 #define COPY_DISSECTOR(rule, diss_key, dst)\
2117 ({ \
2118         struct flow_rule *__rule = (rule);\
2119         typeof(dst) __dst = dst;\
2120 \
2121         memcpy(__dst,\
2122                skb_flow_dissector_target(__rule->match.dissector,\
2123                                          diss_key,\
2124                                          __rule->match.key),\
2125                sizeof(*__dst));\
2126 })
2127
2128 static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
2129                                     struct mlx5e_tc_flow *flow,
2130                                     struct flow_cls_offload *f,
2131                                     struct net_device *filter_dev)
2132 {
2133         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2134         struct netlink_ext_ack *extack = f->common.extack;
2135         struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
2136         struct flow_match_enc_opts enc_opts_match;
2137         struct tunnel_match_enc_opts tun_enc_opts;
2138         struct mlx5_rep_uplink_priv *uplink_priv;
2139         struct mlx5_flow_attr *attr = flow->attr;
2140         struct mlx5e_rep_priv *uplink_rpriv;
2141         struct tunnel_match_key tunnel_key;
2142         bool enc_opts_is_dont_care = true;
2143         u32 tun_id, enc_opts_id = 0;
2144         struct mlx5_eswitch *esw;
2145         u32 value, mask;
2146         int err;
2147
2148         esw = priv->mdev->priv.eswitch;
2149         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2150         uplink_priv = &uplink_rpriv->uplink_priv;
2151
2152         memset(&tunnel_key, 0, sizeof(tunnel_key));
2153         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
2154                        &tunnel_key.enc_control);
2155         if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
2156                 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
2157                                &tunnel_key.enc_ipv4);
2158         else
2159                 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
2160                                &tunnel_key.enc_ipv6);
2161         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
2162         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
2163                        &tunnel_key.enc_tp);
2164         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
2165                        &tunnel_key.enc_key_id);
2166         tunnel_key.filter_ifindex = filter_dev->ifindex;
2167
2168         err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
2169         if (err)
2170                 return err;
2171
2172         flow_rule_match_enc_opts(rule, &enc_opts_match);
2173         err = enc_opts_is_dont_care_or_full_match(priv,
2174                                                   enc_opts_match.mask,
2175                                                   extack,
2176                                                   &enc_opts_is_dont_care);
2177         if (err)
2178                 goto err_enc_opts;
2179
2180         if (!enc_opts_is_dont_care) {
2181                 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
2182                 memcpy(&tun_enc_opts.key, enc_opts_match.key,
2183                        sizeof(*enc_opts_match.key));
2184                 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
2185                        sizeof(*enc_opts_match.mask));
2186
2187                 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
2188                                   &tun_enc_opts, &enc_opts_id);
2189                 if (err)
2190                         goto err_enc_opts;
2191         }
2192
2193         value = tun_id << ENC_OPTS_BITS | enc_opts_id;
2194         mask = enc_opts_id ? TUNNEL_ID_MASK :
2195                              (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
2196
2197         if (attr->chain) {
2198                 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
2199                                             TUNNEL_TO_REG, value, mask);
2200         } else {
2201                 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
2202                 err = mlx5e_tc_match_to_reg_set(priv->mdev,
2203                                                 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
2204                                                 TUNNEL_TO_REG, value);
2205                 if (err)
2206                         goto err_set;
2207
2208                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2209         }
2210
2211         flow->attr->tunnel_id = value;
2212         return 0;
2213
2214 err_set:
2215         if (enc_opts_id)
2216                 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2217                                enc_opts_id);
2218 err_enc_opts:
2219         mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2220         return err;
2221 }
2222
2223 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
2224 {
2225         u32 enc_opts_id = flow->attr->tunnel_id & ENC_OPTS_BITS_MASK;
2226         u32 tun_id = flow->attr->tunnel_id >> ENC_OPTS_BITS;
2227         struct mlx5_rep_uplink_priv *uplink_priv;
2228         struct mlx5e_rep_priv *uplink_rpriv;
2229         struct mlx5_eswitch *esw;
2230
2231         esw = flow->priv->mdev->priv.eswitch;
2232         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2233         uplink_priv = &uplink_rpriv->uplink_priv;
2234
2235         if (tun_id)
2236                 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2237         if (enc_opts_id)
2238                 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2239                                enc_opts_id);
2240 }
2241
2242 void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
2243                             struct flow_match_basic *match, bool outer,
2244                             void *headers_c, void *headers_v)
2245 {
2246         bool ip_version_cap;
2247
2248         ip_version_cap = outer ?
2249                 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2250                                           ft_field_support.outer_ip_version) :
2251                 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2252                                           ft_field_support.inner_ip_version);
2253
2254         if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
2255             (match->key->n_proto == htons(ETH_P_IP) ||
2256              match->key->n_proto == htons(ETH_P_IPV6))) {
2257                 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
2258                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
2259                          match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
2260         } else {
2261                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
2262                          ntohs(match->mask->n_proto));
2263                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
2264                          ntohs(match->key->n_proto));
2265         }
2266 }
2267
2268 u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
2269 {
2270         void *headers_v;
2271         u16 ethertype;
2272         u8 ip_version;
2273
2274         if (outer)
2275                 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2276         else
2277                 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
2278
2279         ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
2280         /* Return ip_version converted from ethertype anyway */
2281         if (!ip_version) {
2282                 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2283                 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
2284                         ip_version = 4;
2285                 else if (ethertype == ETH_P_IPV6)
2286                         ip_version = 6;
2287         }
2288         return ip_version;
2289 }
2290
2291 /* Tunnel device follows RFC 6040, see include/net/inet_ecn.h.
2292  * And changes inner ip_ecn depending on inner and outer ip_ecn as follows:
2293  *      +---------+----------------------------------------+
2294  *      |Arriving |         Arriving Outer Header          |
2295  *      |   Inner +---------+---------+---------+----------+
2296  *      |  Header | Not-ECT | ECT(0)  | ECT(1)  |   CE     |
2297  *      +---------+---------+---------+---------+----------+
2298  *      | Not-ECT | Not-ECT | Not-ECT | Not-ECT | <drop>   |
2299  *      |  ECT(0) |  ECT(0) | ECT(0)  | ECT(1)  |   CE*    |
2300  *      |  ECT(1) |  ECT(1) | ECT(1)  | ECT(1)* |   CE*    |
2301  *      |    CE   |   CE    |  CE     | CE      |   CE     |
2302  *      +---------+---------+---------+---------+----------+
2303  *
2304  * Tc matches on inner after decapsulation on tunnel device, but hw offload matches
2305  * the inner ip_ecn value before hardware decap action.
2306  *
2307  * Cells marked are changed from original inner packet ip_ecn value during decap, and
2308  * so matching those values on inner ip_ecn before decap will fail.
2309  *
2310  * The following helper allows offload when inner ip_ecn won't be changed by outer ip_ecn,
2311  * except for the outer ip_ecn = CE, where in all cases inner ip_ecn will be changed to CE,
2312  * and such we can drop the inner ip_ecn=CE match.
2313  */
2314
2315 static int mlx5e_tc_verify_tunnel_ecn(struct mlx5e_priv *priv,
2316                                       struct flow_cls_offload *f,
2317                                       bool *match_inner_ecn)
2318 {
2319         u8 outer_ecn_mask = 0, outer_ecn_key = 0, inner_ecn_mask = 0, inner_ecn_key = 0;
2320         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2321         struct netlink_ext_ack *extack = f->common.extack;
2322         struct flow_match_ip match;
2323
2324         *match_inner_ecn = true;
2325
2326         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
2327                 flow_rule_match_enc_ip(rule, &match);
2328                 outer_ecn_key = match.key->tos & INET_ECN_MASK;
2329                 outer_ecn_mask = match.mask->tos & INET_ECN_MASK;
2330         }
2331
2332         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2333                 flow_rule_match_ip(rule, &match);
2334                 inner_ecn_key = match.key->tos & INET_ECN_MASK;
2335                 inner_ecn_mask = match.mask->tos & INET_ECN_MASK;
2336         }
2337
2338         if (outer_ecn_mask != 0 && outer_ecn_mask != INET_ECN_MASK) {
2339                 NL_SET_ERR_MSG_MOD(extack, "Partial match on enc_tos ecn bits isn't supported");
2340                 netdev_warn(priv->netdev, "Partial match on enc_tos ecn bits isn't supported");
2341                 return -EOPNOTSUPP;
2342         }
2343
2344         if (!outer_ecn_mask) {
2345                 if (!inner_ecn_mask)
2346                         return 0;
2347
2348                 NL_SET_ERR_MSG_MOD(extack,
2349                                    "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2350                 netdev_warn(priv->netdev,
2351                             "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2352                 return -EOPNOTSUPP;
2353         }
2354
2355         if (inner_ecn_mask && inner_ecn_mask != INET_ECN_MASK) {
2356                 NL_SET_ERR_MSG_MOD(extack,
2357                                    "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2358                 netdev_warn(priv->netdev,
2359                             "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2360                 return -EOPNOTSUPP;
2361         }
2362
2363         if (!inner_ecn_mask)
2364                 return 0;
2365
2366         /* Both inner and outer have full mask on ecn */
2367
2368         if (outer_ecn_key == INET_ECN_ECT_1) {
2369                 /* inner ecn might change by DECAP action */
2370
2371                 NL_SET_ERR_MSG_MOD(extack, "Match on enc_tos ecn = ECT(1) isn't supported");
2372                 netdev_warn(priv->netdev, "Match on enc_tos ecn = ECT(1) isn't supported");
2373                 return -EOPNOTSUPP;
2374         }
2375
2376         if (outer_ecn_key != INET_ECN_CE)
2377                 return 0;
2378
2379         if (inner_ecn_key != INET_ECN_CE) {
2380                 /* Can't happen in software, as packet ecn will be changed to CE after decap */
2381                 NL_SET_ERR_MSG_MOD(extack,
2382                                    "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2383                 netdev_warn(priv->netdev,
2384                             "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2385                 return -EOPNOTSUPP;
2386         }
2387
2388         /* outer ecn = CE, inner ecn = CE, as decap will change inner ecn to CE in anycase,
2389          * drop match on inner ecn
2390          */
2391         *match_inner_ecn = false;
2392
2393         return 0;
2394 }
2395
2396 static int parse_tunnel_attr(struct mlx5e_priv *priv,
2397                              struct mlx5e_tc_flow *flow,
2398                              struct mlx5_flow_spec *spec,
2399                              struct flow_cls_offload *f,
2400                              struct net_device *filter_dev,
2401                              u8 *match_level,
2402                              bool *match_inner)
2403 {
2404         struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
2405         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2406         struct netlink_ext_ack *extack = f->common.extack;
2407         bool needs_mapping, sets_mapping;
2408         int err;
2409
2410         if (!mlx5e_is_eswitch_flow(flow)) {
2411                 NL_SET_ERR_MSG_MOD(extack, "Match on tunnel is not supported");
2412                 return -EOPNOTSUPP;
2413         }
2414
2415         needs_mapping = !!flow->attr->chain;
2416         sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
2417         *match_inner = !needs_mapping;
2418
2419         if ((needs_mapping || sets_mapping) &&
2420             !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
2421                 NL_SET_ERR_MSG_MOD(extack,
2422                                    "Chains on tunnel devices isn't supported without register loopback support");
2423                 netdev_warn(priv->netdev,
2424                             "Chains on tunnel devices isn't supported without register loopback support");
2425                 return -EOPNOTSUPP;
2426         }
2427
2428         if (!flow->attr->chain) {
2429                 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2430                                          match_level);
2431                 if (err) {
2432                         NL_SET_ERR_MSG_MOD(extack,
2433                                            "Failed to parse tunnel attributes");
2434                         netdev_warn(priv->netdev,
2435                                     "Failed to parse tunnel attributes");
2436                         return err;
2437                 }
2438
2439                 /* With mpls over udp we decapsulate using packet reformat
2440                  * object
2441                  */
2442                 if (!netif_is_bareudp(filter_dev))
2443                         flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2444                 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
2445                 if (err)
2446                         return err;
2447         } else if (tunnel) {
2448                 struct mlx5_flow_spec *tmp_spec;
2449
2450                 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
2451                 if (!tmp_spec) {
2452                         NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for tunnel tmp spec");
2453                         netdev_warn(priv->netdev, "Failed to allocate memory for tunnel tmp spec");
2454                         return -ENOMEM;
2455                 }
2456                 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
2457
2458                 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
2459                 if (err) {
2460                         kvfree(tmp_spec);
2461                         NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
2462                         netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
2463                         return err;
2464                 }
2465                 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
2466                 kvfree(tmp_spec);
2467                 if (err)
2468                         return err;
2469         }
2470
2471         if (!needs_mapping && !sets_mapping)
2472                 return 0;
2473
2474         return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
2475 }
2476
2477 static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
2478 {
2479         return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2480                             inner_headers);
2481 }
2482
2483 static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
2484 {
2485         return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2486                             inner_headers);
2487 }
2488
2489 static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2490 {
2491         return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2492                             outer_headers);
2493 }
2494
2495 static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2496 {
2497         return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2498                             outer_headers);
2499 }
2500
2501 void *mlx5e_get_match_headers_value(u32 flags, struct mlx5_flow_spec *spec)
2502 {
2503         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2504                 get_match_inner_headers_value(spec) :
2505                 get_match_outer_headers_value(spec);
2506 }
2507
2508 void *mlx5e_get_match_headers_criteria(u32 flags, struct mlx5_flow_spec *spec)
2509 {
2510         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2511                 get_match_inner_headers_criteria(spec) :
2512                 get_match_outer_headers_criteria(spec);
2513 }
2514
2515 static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2516                                    struct flow_cls_offload *f)
2517 {
2518         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2519         struct netlink_ext_ack *extack = f->common.extack;
2520         struct net_device *ingress_dev;
2521         struct flow_match_meta match;
2522
2523         if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2524                 return 0;
2525
2526         flow_rule_match_meta(rule, &match);
2527
2528         if (match.mask->l2_miss) {
2529                 NL_SET_ERR_MSG_MOD(f->common.extack, "Can't match on \"l2_miss\"");
2530                 return -EOPNOTSUPP;
2531         }
2532
2533         if (!match.mask->ingress_ifindex)
2534                 return 0;
2535
2536         if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2537                 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
2538                 return -EOPNOTSUPP;
2539         }
2540
2541         ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2542                                          match.key->ingress_ifindex);
2543         if (!ingress_dev) {
2544                 NL_SET_ERR_MSG_MOD(extack,
2545                                    "Can't find the ingress port to match on");
2546                 return -ENOENT;
2547         }
2548
2549         if (ingress_dev != filter_dev) {
2550                 NL_SET_ERR_MSG_MOD(extack,
2551                                    "Can't match on the ingress filter port");
2552                 return -EOPNOTSUPP;
2553         }
2554
2555         return 0;
2556 }
2557
2558 static bool skip_key_basic(struct net_device *filter_dev,
2559                            struct flow_cls_offload *f)
2560 {
2561         /* When doing mpls over udp decap, the user needs to provide
2562          * MPLS_UC as the protocol in order to be able to match on mpls
2563          * label fields.  However, the actual ethertype is IP so we want to
2564          * avoid matching on this, otherwise we'll fail the match.
2565          */
2566         if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2567                 return true;
2568
2569         return false;
2570 }
2571
2572 static int __parse_cls_flower(struct mlx5e_priv *priv,
2573                               struct mlx5e_tc_flow *flow,
2574                               struct mlx5_flow_spec *spec,
2575                               struct flow_cls_offload *f,
2576                               struct net_device *filter_dev,
2577                               u8 *inner_match_level, u8 *outer_match_level)
2578 {
2579         struct netlink_ext_ack *extack = f->common.extack;
2580         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2581                                        outer_headers);
2582         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2583                                        outer_headers);
2584         void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2585                                     misc_parameters);
2586         void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2587                                     misc_parameters);
2588         void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2589                                     misc_parameters_3);
2590         void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2591                                     misc_parameters_3);
2592         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2593         struct flow_dissector *dissector = rule->match.dissector;
2594         enum fs_flow_table_type fs_type;
2595         bool match_inner_ecn = true;
2596         u16 addr_type = 0;
2597         u8 ip_proto = 0;
2598         u8 *match_level;
2599         int err;
2600
2601         fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
2602         match_level = outer_match_level;
2603
2604         if (dissector->used_keys &
2605             ~(BIT_ULL(FLOW_DISSECTOR_KEY_META) |
2606               BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
2607               BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
2608               BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2609               BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
2610               BIT_ULL(FLOW_DISSECTOR_KEY_CVLAN) |
2611               BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2612               BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
2613               BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
2614               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2615               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2616               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2617               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_PORTS)     |
2618               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
2619               BIT_ULL(FLOW_DISSECTOR_KEY_TCP) |
2620               BIT_ULL(FLOW_DISSECTOR_KEY_IP)  |
2621               BIT_ULL(FLOW_DISSECTOR_KEY_CT) |
2622               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IP) |
2623               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_OPTS) |
2624               BIT_ULL(FLOW_DISSECTOR_KEY_ICMP) |
2625               BIT_ULL(FLOW_DISSECTOR_KEY_MPLS))) {
2626                 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
2627                 netdev_dbg(priv->netdev, "Unsupported key used: 0x%llx\n",
2628                            dissector->used_keys);
2629                 return -EOPNOTSUPP;
2630         }
2631
2632         if (mlx5e_get_tc_tun(filter_dev)) {
2633                 bool match_inner = false;
2634
2635                 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2636                                         outer_match_level, &match_inner);
2637                 if (err)
2638                         return err;
2639
2640                 if (match_inner) {
2641                         /* header pointers should point to the inner headers
2642                          * if the packet was decapsulated already.
2643                          * outer headers are set by parse_tunnel_attr.
2644                          */
2645                         match_level = inner_match_level;
2646                         headers_c = get_match_inner_headers_criteria(spec);
2647                         headers_v = get_match_inner_headers_value(spec);
2648                 }
2649
2650                 err = mlx5e_tc_verify_tunnel_ecn(priv, f, &match_inner_ecn);
2651                 if (err)
2652                         return err;
2653         }
2654
2655         err = mlx5e_flower_parse_meta(filter_dev, f);
2656         if (err)
2657                 return err;
2658
2659         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2660             !skip_key_basic(filter_dev, f)) {
2661                 struct flow_match_basic match;
2662
2663                 flow_rule_match_basic(rule, &match);
2664                 mlx5e_tc_set_ethertype(priv->mdev, &match,
2665                                        match_level == outer_match_level,
2666                                        headers_c, headers_v);
2667
2668                 if (match.mask->n_proto)
2669                         *match_level = MLX5_MATCH_L2;
2670         }
2671         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2672             is_vlan_dev(filter_dev)) {
2673                 struct flow_dissector_key_vlan filter_dev_mask;
2674                 struct flow_dissector_key_vlan filter_dev_key;
2675                 struct flow_match_vlan match;
2676
2677                 if (is_vlan_dev(filter_dev)) {
2678                         match.key = &filter_dev_key;
2679                         match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2680                         match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2681                         match.key->vlan_priority = 0;
2682                         match.mask = &filter_dev_mask;
2683                         memset(match.mask, 0xff, sizeof(*match.mask));
2684                         match.mask->vlan_priority = 0;
2685                 } else {
2686                         flow_rule_match_vlan(rule, &match);
2687                 }
2688                 if (match.mask->vlan_id ||
2689                     match.mask->vlan_priority ||
2690                     match.mask->vlan_tpid) {
2691                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2692                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2693                                          svlan_tag, 1);
2694                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2695                                          svlan_tag, 1);
2696                         } else {
2697                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2698                                          cvlan_tag, 1);
2699                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2700                                          cvlan_tag, 1);
2701                         }
2702
2703                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2704                                  match.mask->vlan_id);
2705                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2706                                  match.key->vlan_id);
2707
2708                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2709                                  match.mask->vlan_priority);
2710                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2711                                  match.key->vlan_priority);
2712
2713                         *match_level = MLX5_MATCH_L2;
2714
2715                         if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN) &&
2716                             match.mask->vlan_eth_type &&
2717                             MLX5_CAP_FLOWTABLE_TYPE(priv->mdev,
2718                                                     ft_field_support.outer_second_vid,
2719                                                     fs_type)) {
2720                                 MLX5_SET(fte_match_set_misc, misc_c,
2721                                          outer_second_cvlan_tag, 1);
2722                                 spec->match_criteria_enable |=
2723                                         MLX5_MATCH_MISC_PARAMETERS;
2724                         }
2725                 }
2726         } else if (*match_level != MLX5_MATCH_NONE) {
2727                 /* cvlan_tag enabled in match criteria and
2728                  * disabled in match value means both S & C tags
2729                  * don't exist (untagged of both)
2730                  */
2731                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
2732                 *match_level = MLX5_MATCH_L2;
2733         }
2734
2735         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2736                 struct flow_match_vlan match;
2737
2738                 flow_rule_match_cvlan(rule, &match);
2739                 if (match.mask->vlan_id ||
2740                     match.mask->vlan_priority ||
2741                     match.mask->vlan_tpid) {
2742                         if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2743                                                      fs_type)) {
2744                                 NL_SET_ERR_MSG_MOD(extack,
2745                                                    "Matching on CVLAN is not supported");
2746                                 return -EOPNOTSUPP;
2747                         }
2748
2749                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2750                                 MLX5_SET(fte_match_set_misc, misc_c,
2751                                          outer_second_svlan_tag, 1);
2752                                 MLX5_SET(fte_match_set_misc, misc_v,
2753                                          outer_second_svlan_tag, 1);
2754                         } else {
2755                                 MLX5_SET(fte_match_set_misc, misc_c,
2756                                          outer_second_cvlan_tag, 1);
2757                                 MLX5_SET(fte_match_set_misc, misc_v,
2758                                          outer_second_cvlan_tag, 1);
2759                         }
2760
2761                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
2762                                  match.mask->vlan_id);
2763                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
2764                                  match.key->vlan_id);
2765                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
2766                                  match.mask->vlan_priority);
2767                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
2768                                  match.key->vlan_priority);
2769
2770                         *match_level = MLX5_MATCH_L2;
2771                         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
2772                 }
2773         }
2774
2775         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2776                 struct flow_match_eth_addrs match;
2777
2778                 flow_rule_match_eth_addrs(rule, &match);
2779                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2780                                              dmac_47_16),
2781                                 match.mask->dst);
2782                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2783                                              dmac_47_16),
2784                                 match.key->dst);
2785
2786                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2787                                              smac_47_16),
2788                                 match.mask->src);
2789                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2790                                              smac_47_16),
2791                                 match.key->src);
2792
2793                 if (!is_zero_ether_addr(match.mask->src) ||
2794                     !is_zero_ether_addr(match.mask->dst))
2795                         *match_level = MLX5_MATCH_L2;
2796         }
2797
2798         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2799                 struct flow_match_control match;
2800
2801                 flow_rule_match_control(rule, &match);
2802                 addr_type = match.key->addr_type;
2803
2804                 /* the HW doesn't support frag first/later */
2805                 if (match.mask->flags & FLOW_DIS_FIRST_FRAG) {
2806                         NL_SET_ERR_MSG_MOD(extack, "Match on frag first/later is not supported");
2807                         return -EOPNOTSUPP;
2808                 }
2809
2810                 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
2811                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2812                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
2813                                  match.key->flags & FLOW_DIS_IS_FRAGMENT);
2814
2815                         /* the HW doesn't need L3 inline to match on frag=no */
2816                         if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
2817                                 *match_level = MLX5_MATCH_L2;
2818         /* ***  L2 attributes parsing up to here *** */
2819                         else
2820                                 *match_level = MLX5_MATCH_L3;
2821                 }
2822         }
2823
2824         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2825                 struct flow_match_basic match;
2826
2827                 flow_rule_match_basic(rule, &match);
2828                 ip_proto = match.key->ip_proto;
2829
2830                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2831                          match.mask->ip_proto);
2832                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2833                          match.key->ip_proto);
2834
2835                 if (match.mask->ip_proto)
2836                         *match_level = MLX5_MATCH_L3;
2837         }
2838
2839         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
2840                 struct flow_match_ipv4_addrs match;
2841
2842                 flow_rule_match_ipv4_addrs(rule, &match);
2843                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2844                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2845                        &match.mask->src, sizeof(match.mask->src));
2846                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2847                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2848                        &match.key->src, sizeof(match.key->src));
2849                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2850                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2851                        &match.mask->dst, sizeof(match.mask->dst));
2852                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2853                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2854                        &match.key->dst, sizeof(match.key->dst));
2855
2856                 if (match.mask->src || match.mask->dst)
2857                         *match_level = MLX5_MATCH_L3;
2858         }
2859
2860         if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
2861                 struct flow_match_ipv6_addrs match;
2862
2863                 flow_rule_match_ipv6_addrs(rule, &match);
2864                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2865                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2866                        &match.mask->src, sizeof(match.mask->src));
2867                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2868                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2869                        &match.key->src, sizeof(match.key->src));
2870
2871                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2872                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2873                        &match.mask->dst, sizeof(match.mask->dst));
2874                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2875                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2876                        &match.key->dst, sizeof(match.key->dst));
2877
2878                 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2879                     ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
2880                         *match_level = MLX5_MATCH_L3;
2881         }
2882
2883         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2884                 struct flow_match_ip match;
2885
2886                 flow_rule_match_ip(rule, &match);
2887                 if (match_inner_ecn) {
2888                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2889                                  match.mask->tos & 0x3);
2890                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2891                                  match.key->tos & 0x3);
2892                 }
2893
2894                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2895                          match.mask->tos >> 2);
2896                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2897                          match.key->tos  >> 2);
2898
2899                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2900                          match.mask->ttl);
2901                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2902                          match.key->ttl);
2903
2904                 if (match.mask->ttl &&
2905                     !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
2906                                                 ft_field_support.outer_ipv4_ttl)) {
2907                         NL_SET_ERR_MSG_MOD(extack,
2908                                            "Matching on TTL is not supported");
2909                         return -EOPNOTSUPP;
2910                 }
2911
2912                 if (match.mask->tos || match.mask->ttl)
2913                         *match_level = MLX5_MATCH_L3;
2914         }
2915
2916         /* ***  L3 attributes parsing up to here *** */
2917
2918         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2919                 struct flow_match_ports match;
2920
2921                 flow_rule_match_ports(rule, &match);
2922                 switch (ip_proto) {
2923                 case IPPROTO_TCP:
2924                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2925                                  tcp_sport, ntohs(match.mask->src));
2926                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2927                                  tcp_sport, ntohs(match.key->src));
2928
2929                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2930                                  tcp_dport, ntohs(match.mask->dst));
2931                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2932                                  tcp_dport, ntohs(match.key->dst));
2933                         break;
2934
2935                 case IPPROTO_UDP:
2936                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2937                                  udp_sport, ntohs(match.mask->src));
2938                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2939                                  udp_sport, ntohs(match.key->src));
2940
2941                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2942                                  udp_dport, ntohs(match.mask->dst));
2943                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2944                                  udp_dport, ntohs(match.key->dst));
2945                         break;
2946                 default:
2947                         NL_SET_ERR_MSG_MOD(extack,
2948                                            "Only UDP and TCP transports are supported for L4 matching");
2949                         netdev_err(priv->netdev,
2950                                    "Only UDP and TCP transport are supported\n");
2951                         return -EINVAL;
2952                 }
2953
2954                 if (match.mask->src || match.mask->dst)
2955                         *match_level = MLX5_MATCH_L4;
2956         }
2957
2958         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2959                 struct flow_match_tcp match;
2960
2961                 flow_rule_match_tcp(rule, &match);
2962                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
2963                          ntohs(match.mask->flags));
2964                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
2965                          ntohs(match.key->flags));
2966
2967                 if (match.mask->flags)
2968                         *match_level = MLX5_MATCH_L4;
2969         }
2970         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2971                 struct flow_match_icmp match;
2972
2973                 flow_rule_match_icmp(rule, &match);
2974                 switch (ip_proto) {
2975                 case IPPROTO_ICMP:
2976                         if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2977                               MLX5_FLEX_PROTO_ICMP)) {
2978                                 NL_SET_ERR_MSG_MOD(extack,
2979                                                    "Match on Flex protocols for ICMP is not supported");
2980                                 return -EOPNOTSUPP;
2981                         }
2982                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2983                                  match.mask->type);
2984                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2985                                  match.key->type);
2986                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2987                                  match.mask->code);
2988                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2989                                  match.key->code);
2990                         break;
2991                 case IPPROTO_ICMPV6:
2992                         if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2993                               MLX5_FLEX_PROTO_ICMPV6)) {
2994                                 NL_SET_ERR_MSG_MOD(extack,
2995                                                    "Match on Flex protocols for ICMPV6 is not supported");
2996                                 return -EOPNOTSUPP;
2997                         }
2998                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2999                                  match.mask->type);
3000                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
3001                                  match.key->type);
3002                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
3003                                  match.mask->code);
3004                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
3005                                  match.key->code);
3006                         break;
3007                 default:
3008                         NL_SET_ERR_MSG_MOD(extack,
3009                                            "Code and type matching only with ICMP and ICMPv6");
3010                         netdev_err(priv->netdev,
3011                                    "Code and type matching only with ICMP and ICMPv6\n");
3012                         return -EINVAL;
3013                 }
3014                 if (match.mask->code || match.mask->type) {
3015                         *match_level = MLX5_MATCH_L4;
3016                         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
3017                 }
3018         }
3019         /* Currently supported only for MPLS over UDP */
3020         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
3021             !netif_is_bareudp(filter_dev)) {
3022                 NL_SET_ERR_MSG_MOD(extack,
3023                                    "Matching on MPLS is supported only for MPLS over UDP");
3024                 netdev_err(priv->netdev,
3025                            "Matching on MPLS is supported only for MPLS over UDP\n");
3026                 return -EOPNOTSUPP;
3027         }
3028
3029         return 0;
3030 }
3031
3032 static int parse_cls_flower(struct mlx5e_priv *priv,
3033                             struct mlx5e_tc_flow *flow,
3034                             struct mlx5_flow_spec *spec,
3035                             struct flow_cls_offload *f,
3036                             struct net_device *filter_dev)
3037 {
3038         u8 inner_match_level, outer_match_level, non_tunnel_match_level;
3039         struct netlink_ext_ack *extack = f->common.extack;
3040         struct mlx5_core_dev *dev = priv->mdev;
3041         struct mlx5_eswitch *esw = dev->priv.eswitch;
3042         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3043         struct mlx5_eswitch_rep *rep;
3044         bool is_eswitch_flow;
3045         int err;
3046
3047         inner_match_level = MLX5_MATCH_NONE;
3048         outer_match_level = MLX5_MATCH_NONE;
3049
3050         err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
3051                                  &inner_match_level, &outer_match_level);
3052         non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
3053                                  outer_match_level : inner_match_level;
3054
3055         is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
3056         if (!err && is_eswitch_flow) {
3057                 rep = rpriv->rep;
3058                 if (rep->vport != MLX5_VPORT_UPLINK &&
3059                     (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
3060                     esw->offloads.inline_mode < non_tunnel_match_level)) {
3061                         NL_SET_ERR_MSG_MOD(extack,
3062                                            "Flow is not offloaded due to min inline setting");
3063                         netdev_warn(priv->netdev,
3064                                     "Flow is not offloaded due to min inline setting, required %d actual %d\n",
3065                                     non_tunnel_match_level, esw->offloads.inline_mode);
3066                         return -EOPNOTSUPP;
3067                 }
3068         }
3069
3070         flow->attr->inner_match_level = inner_match_level;
3071         flow->attr->outer_match_level = outer_match_level;
3072
3073
3074         return err;
3075 }
3076
3077 struct mlx5_fields {
3078         u8  field;
3079         u8  field_bsize;
3080         u32 field_mask;
3081         u32 offset;
3082         u32 match_offset;
3083 };
3084
3085 #define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
3086                 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
3087                  offsetof(struct pedit_headers, field) + (off), \
3088                  MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
3089
3090 /* masked values are the same and there are no rewrites that do not have a
3091  * match.
3092  */
3093 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
3094         type matchmaskx = *(type *)(matchmaskp); \
3095         type matchvalx = *(type *)(matchvalp); \
3096         type maskx = *(type *)(maskp); \
3097         type valx = *(type *)(valp); \
3098         \
3099         (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
3100                                                                  matchmaskx)); \
3101 })
3102
3103 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
3104                          void *matchmaskp, u8 bsize)
3105 {
3106         bool same = false;
3107
3108         switch (bsize) {
3109         case 8:
3110                 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
3111                 break;
3112         case 16:
3113                 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
3114                 break;
3115         case 32:
3116                 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
3117                 break;
3118         }
3119
3120         return same;
3121 }
3122
3123 static struct mlx5_fields fields[] = {
3124         OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
3125         OFFLOAD(DMAC_15_0,  16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
3126         OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
3127         OFFLOAD(SMAC_15_0,  16, U16_MAX, eth.h_source[4], 0, smac_15_0),
3128         OFFLOAD(ETHERTYPE,  16, U16_MAX, eth.h_proto, 0, ethertype),
3129         OFFLOAD(FIRST_VID,  16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
3130
3131         OFFLOAD(IP_DSCP, 8,    0xfc, ip4.tos,   0, ip_dscp),
3132         OFFLOAD(IP_TTL,  8,  U8_MAX, ip4.ttl,   0, ttl_hoplimit),
3133         OFFLOAD(SIPV4,  32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
3134         OFFLOAD(DIPV4,  32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
3135
3136         OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
3137                 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
3138         OFFLOAD(SIPV6_95_64,  32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
3139                 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
3140         OFFLOAD(SIPV6_63_32,  32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
3141                 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
3142         OFFLOAD(SIPV6_31_0,   32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
3143                 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
3144         OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
3145                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
3146         OFFLOAD(DIPV6_95_64,  32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
3147                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
3148         OFFLOAD(DIPV6_63_32,  32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
3149                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
3150         OFFLOAD(DIPV6_31_0,   32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
3151                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
3152         OFFLOAD(IPV6_HOPLIMIT, 8,  U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
3153         OFFLOAD(IP_DSCP, 16,  0x0fc0, ip6, 0, ip_dscp),
3154
3155         OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source,  0, tcp_sport),
3156         OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest,    0, tcp_dport),
3157         /* in linux iphdr tcp_flags is 8 bits long */
3158         OFFLOAD(TCP_FLAGS,  8,  U8_MAX, tcp.ack_seq, 5, tcp_flags),
3159
3160         OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
3161         OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest,   0, udp_dport),
3162 };
3163
3164 static u32 mask_field_get(void *mask, struct mlx5_fields *f)
3165 {
3166         switch (f->field_bsize) {
3167         case 32:
3168                 return be32_to_cpu(*(__be32 *)mask) & f->field_mask;
3169         case 16:
3170                 return be16_to_cpu(*(__be16 *)mask) & (u16)f->field_mask;
3171         default:
3172                 return *(u8 *)mask & (u8)f->field_mask;
3173         }
3174 }
3175
3176 static void mask_field_clear(void *mask, struct mlx5_fields *f)
3177 {
3178         switch (f->field_bsize) {
3179         case 32:
3180                 *(__be32 *)mask &= ~cpu_to_be32(f->field_mask);
3181                 break;
3182         case 16:
3183                 *(__be16 *)mask &= ~cpu_to_be16((u16)f->field_mask);
3184                 break;
3185         default:
3186                 *(u8 *)mask &= ~(u8)f->field_mask;
3187                 break;
3188         }
3189 }
3190
3191 static int offload_pedit_fields(struct mlx5e_priv *priv,
3192                                 int namespace,
3193                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
3194                                 u32 *action_flags,
3195                                 struct netlink_ext_ack *extack)
3196 {
3197         struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
3198         struct pedit_headers_action *hdrs = parse_attr->hdrs;
3199         void *headers_c, *headers_v, *action, *vals_p;
3200         struct mlx5e_tc_mod_hdr_acts *mod_acts;
3201         void *s_masks_p, *a_masks_p;
3202         int i, first, last, next_z;
3203         struct mlx5_fields *f;
3204         unsigned long mask;
3205         u32 s_mask, a_mask;
3206         u8 cmd;
3207
3208         mod_acts = &parse_attr->mod_hdr_acts;
3209         headers_c = mlx5e_get_match_headers_criteria(*action_flags, &parse_attr->spec);
3210         headers_v = mlx5e_get_match_headers_value(*action_flags, &parse_attr->spec);
3211
3212         set_masks = &hdrs[0].masks;
3213         add_masks = &hdrs[1].masks;
3214         set_vals = &hdrs[0].vals;
3215         add_vals = &hdrs[1].vals;
3216
3217         for (i = 0; i < ARRAY_SIZE(fields); i++) {
3218                 bool skip;
3219
3220                 f = &fields[i];
3221                 s_masks_p = (void *)set_masks + f->offset;
3222                 a_masks_p = (void *)add_masks + f->offset;
3223
3224                 s_mask = mask_field_get(s_masks_p, f);
3225                 a_mask = mask_field_get(a_masks_p, f);
3226
3227                 if (!s_mask && !a_mask) /* nothing to offload here */
3228                         continue;
3229
3230                 if (s_mask && a_mask) {
3231                         NL_SET_ERR_MSG_MOD(extack,
3232                                            "can't set and add to the same HW field");
3233                         netdev_warn(priv->netdev,
3234                                     "mlx5: can't set and add to the same HW field (%x)\n",
3235                                     f->field);
3236                         return -EOPNOTSUPP;
3237                 }
3238
3239                 skip = false;
3240                 if (s_mask) {
3241                         void *match_mask = headers_c + f->match_offset;
3242                         void *match_val = headers_v + f->match_offset;
3243
3244                         cmd  = MLX5_ACTION_TYPE_SET;
3245                         mask = s_mask;
3246                         vals_p = (void *)set_vals + f->offset;
3247                         /* don't rewrite if we have a match on the same value */
3248                         if (cmp_val_mask(vals_p, s_masks_p, match_val,
3249                                          match_mask, f->field_bsize))
3250                                 skip = true;
3251                         /* clear to denote we consumed this field */
3252                         mask_field_clear(s_masks_p, f);
3253                 } else {
3254                         cmd  = MLX5_ACTION_TYPE_ADD;
3255                         mask = a_mask;
3256                         vals_p = (void *)add_vals + f->offset;
3257                         /* add 0 is no change */
3258                         if (!mask_field_get(vals_p, f))
3259                                 skip = true;
3260                         /* clear to denote we consumed this field */
3261                         mask_field_clear(a_masks_p, f);
3262                 }
3263                 if (skip)
3264                         continue;
3265
3266                 first = find_first_bit(&mask, f->field_bsize);
3267                 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
3268                 last  = find_last_bit(&mask, f->field_bsize);
3269                 if (first < next_z && next_z < last) {
3270                         NL_SET_ERR_MSG_MOD(extack,
3271                                            "rewrite of few sub-fields isn't supported");
3272                         netdev_warn(priv->netdev,
3273                                     "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
3274                                     mask);
3275                         return -EOPNOTSUPP;
3276                 }
3277
3278                 action = mlx5e_mod_hdr_alloc(priv->mdev, namespace, mod_acts);
3279                 if (IS_ERR(action)) {
3280                         NL_SET_ERR_MSG_MOD(extack,
3281                                            "too many pedit actions, can't offload");
3282                         mlx5_core_warn(priv->mdev,
3283                                        "mlx5: parsed %d pedit actions, can't do more\n",
3284                                        mod_acts->num_actions);
3285                         return PTR_ERR(action);
3286                 }
3287
3288                 MLX5_SET(set_action_in, action, action_type, cmd);
3289                 MLX5_SET(set_action_in, action, field, f->field);
3290
3291                 if (cmd == MLX5_ACTION_TYPE_SET) {
3292                         unsigned long field_mask = f->field_mask;
3293                         int start;
3294
3295                         /* if field is bit sized it can start not from first bit */
3296                         start = find_first_bit(&field_mask, f->field_bsize);
3297
3298                         MLX5_SET(set_action_in, action, offset, first - start);
3299                         /* length is num of bits to be written, zero means length of 32 */
3300                         MLX5_SET(set_action_in, action, length, (last - first + 1));
3301                 }
3302
3303                 if (f->field_bsize == 32)
3304                         MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
3305                 else if (f->field_bsize == 16)
3306                         MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
3307                 else if (f->field_bsize == 8)
3308                         MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
3309
3310                 ++mod_acts->num_actions;
3311         }
3312
3313         return 0;
3314 }
3315
3316 static const struct pedit_headers zero_masks = {};
3317
3318 static int verify_offload_pedit_fields(struct mlx5e_priv *priv,
3319                                        struct mlx5e_tc_flow_parse_attr *parse_attr,
3320                                        struct netlink_ext_ack *extack)
3321 {
3322         struct pedit_headers *cmd_masks;
3323         u8 cmd;
3324
3325         for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
3326                 cmd_masks = &parse_attr->hdrs[cmd].masks;
3327                 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
3328                         NL_SET_ERR_MSG_MOD(extack, "attempt to offload an unsupported field");
3329                         netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
3330                         print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3331                                        16, 1, cmd_masks, sizeof(zero_masks), true);
3332                         return -EOPNOTSUPP;
3333                 }
3334         }
3335
3336         return 0;
3337 }
3338
3339 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3340                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
3341                                  u32 *action_flags,
3342                                  struct netlink_ext_ack *extack)
3343 {
3344         int err;
3345
3346         err = offload_pedit_fields(priv, namespace, parse_attr, action_flags, extack);
3347         if (err)
3348                 goto out_dealloc_parsed_actions;
3349
3350         err = verify_offload_pedit_fields(priv, parse_attr, extack);
3351         if (err)
3352                 goto out_dealloc_parsed_actions;
3353
3354         return 0;
3355
3356 out_dealloc_parsed_actions:
3357         mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
3358         return err;
3359 }
3360
3361 struct ip_ttl_word {
3362         __u8    ttl;
3363         __u8    protocol;
3364         __sum16 check;
3365 };
3366
3367 struct ipv6_hoplimit_word {
3368         __be16  payload_len;
3369         __u8    nexthdr;
3370         __u8    hop_limit;
3371 };
3372
3373 static bool
3374 is_flow_action_modify_ip_header(struct flow_action *flow_action)
3375 {
3376         const struct flow_action_entry *act;
3377         u32 mask, offset;
3378         u8 htype;
3379         int i;
3380
3381         /* For IPv4 & IPv6 header check 4 byte word,
3382          * to determine that modified fields
3383          * are NOT ttl & hop_limit only.
3384          */
3385         flow_action_for_each(i, act, flow_action) {
3386                 if (act->id != FLOW_ACTION_MANGLE &&
3387                     act->id != FLOW_ACTION_ADD)
3388                         continue;
3389
3390                 htype = act->mangle.htype;
3391                 offset = act->mangle.offset;
3392                 mask = ~act->mangle.mask;
3393
3394                 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3395                         struct ip_ttl_word *ttl_word =
3396                                 (struct ip_ttl_word *)&mask;
3397
3398                         if (offset != offsetof(struct iphdr, ttl) ||
3399                             ttl_word->protocol ||
3400                             ttl_word->check)
3401                                 return true;
3402                 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3403                         struct ipv6_hoplimit_word *hoplimit_word =
3404                                 (struct ipv6_hoplimit_word *)&mask;
3405
3406                         if (offset != offsetof(struct ipv6hdr, payload_len) ||
3407                             hoplimit_word->payload_len ||
3408                             hoplimit_word->nexthdr)
3409                                 return true;
3410                 }
3411         }
3412
3413         return false;
3414 }
3415
3416 static bool modify_header_match_supported(struct mlx5e_priv *priv,
3417                                           struct mlx5_flow_spec *spec,
3418                                           struct flow_action *flow_action,
3419                                           u32 actions,
3420                                           struct netlink_ext_ack *extack)
3421 {
3422         bool modify_ip_header;
3423         void *headers_c;
3424         void *headers_v;
3425         u16 ethertype;
3426         u8 ip_proto;
3427
3428         headers_c = mlx5e_get_match_headers_criteria(actions, spec);
3429         headers_v = mlx5e_get_match_headers_value(actions, spec);
3430         ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3431
3432         /* for non-IP we only re-write MACs, so we're okay */
3433         if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3434             ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
3435                 goto out_ok;
3436
3437         modify_ip_header = is_flow_action_modify_ip_header(flow_action);
3438         ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
3439         if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3440             ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
3441                 NL_SET_ERR_MSG_MOD(extack,
3442                                    "can't offload re-write of non TCP/UDP");
3443                 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3444                             ip_proto);
3445                 return false;
3446         }
3447
3448 out_ok:
3449         return true;
3450 }
3451
3452 static bool
3453 actions_match_supported_fdb(struct mlx5e_priv *priv,
3454                             struct mlx5e_tc_flow *flow,
3455                             struct netlink_ext_ack *extack)
3456 {
3457         struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
3458
3459         if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3460                 NL_SET_ERR_MSG_MOD(extack,
3461                                    "current firmware doesn't support split rule for port mirroring");
3462                 netdev_warn_once(priv->netdev,
3463                                  "current firmware doesn't support split rule for port mirroring\n");
3464                 return false;
3465         }
3466
3467         return true;
3468 }
3469
3470 static bool
3471 actions_match_supported(struct mlx5e_priv *priv,
3472                         struct flow_action *flow_action,
3473                         u32 actions,
3474                         struct mlx5e_tc_flow_parse_attr *parse_attr,
3475                         struct mlx5e_tc_flow *flow,
3476                         struct netlink_ext_ack *extack)
3477 {
3478         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
3479             !modify_header_match_supported(priv, &parse_attr->spec, flow_action, actions,
3480                                            extack))
3481                 return false;
3482
3483         if (mlx5e_is_eswitch_flow(flow) &&
3484             !actions_match_supported_fdb(priv, flow, extack))
3485                 return false;
3486
3487         return true;
3488 }
3489
3490 static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3491 {
3492         return priv->mdev == peer_priv->mdev;
3493 }
3494
3495 bool mlx5e_same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3496 {
3497         struct mlx5_core_dev *fmdev, *pmdev;
3498         u64 fsystem_guid, psystem_guid;
3499
3500         fmdev = priv->mdev;
3501         pmdev = peer_priv->mdev;
3502
3503         fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3504         psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
3505
3506         return (fsystem_guid == psystem_guid);
3507 }
3508
3509 static int
3510 actions_prepare_mod_hdr_actions(struct mlx5e_priv *priv,
3511                                 struct mlx5e_tc_flow *flow,
3512                                 struct mlx5_flow_attr *attr,
3513                                 struct netlink_ext_ack *extack)
3514 {
3515         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3516         struct pedit_headers_action *hdrs = parse_attr->hdrs;
3517         enum mlx5_flow_namespace_type ns_type;
3518         int err;
3519
3520         if (!hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits &&
3521             !hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits)
3522                 return 0;
3523
3524         ns_type = mlx5e_get_flow_namespace(flow);
3525
3526         err = alloc_tc_pedit_action(priv, ns_type, parse_attr, &attr->action, extack);
3527         if (err)
3528                 return err;
3529
3530         if (parse_attr->mod_hdr_acts.num_actions > 0)
3531                 return 0;
3532
3533         /* In case all pedit actions are skipped, remove the MOD_HDR flag. */
3534         attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3535         mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
3536
3537         if (ns_type != MLX5_FLOW_NAMESPACE_FDB)
3538                 return 0;
3539
3540         if (!((attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3541               (attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3542                 attr->esw_attr->split_count = 0;
3543
3544         return 0;
3545 }
3546
3547 static struct mlx5_flow_attr*
3548 mlx5e_clone_flow_attr_for_post_act(struct mlx5_flow_attr *attr,
3549                                    enum mlx5_flow_namespace_type ns_type)
3550 {
3551         struct mlx5e_tc_flow_parse_attr *parse_attr;
3552         u32 attr_sz = ns_to_attr_sz(ns_type);
3553         struct mlx5_flow_attr *attr2;
3554
3555         attr2 = mlx5_alloc_flow_attr(ns_type);
3556         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
3557         if (!attr2 || !parse_attr) {
3558                 kvfree(parse_attr);
3559                 kfree(attr2);
3560                 return NULL;
3561         }
3562
3563         memcpy(attr2, attr, attr_sz);
3564         INIT_LIST_HEAD(&attr2->list);
3565         parse_attr->filter_dev = attr->parse_attr->filter_dev;
3566         attr2->action = 0;
3567         attr2->counter = NULL;
3568         attr2->tc_act_cookies_count = 0;
3569         attr2->flags = 0;
3570         attr2->parse_attr = parse_attr;
3571         attr2->dest_chain = 0;
3572         attr2->dest_ft = NULL;
3573         attr2->act_id_restore_rule = NULL;
3574         memset(&attr2->ct_attr, 0, sizeof(attr2->ct_attr));
3575
3576         if (ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3577                 attr2->esw_attr->out_count = 0;
3578                 attr2->esw_attr->split_count = 0;
3579         }
3580
3581         attr2->branch_true = NULL;
3582         attr2->branch_false = NULL;
3583         attr2->jumping_attr = NULL;
3584         return attr2;
3585 }
3586
3587 struct mlx5_flow_attr *
3588 mlx5e_tc_get_encap_attr(struct mlx5e_tc_flow *flow)
3589 {
3590         struct mlx5_esw_flow_attr *esw_attr;
3591         struct mlx5_flow_attr *attr;
3592         int i;
3593
3594         list_for_each_entry(attr, &flow->attrs, list) {
3595                 esw_attr = attr->esw_attr;
3596                 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
3597                         if (esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP)
3598                                 return attr;
3599                 }
3600         }
3601
3602         return NULL;
3603 }
3604
3605 void
3606 mlx5e_tc_unoffload_flow_post_acts(struct mlx5e_tc_flow *flow)
3607 {
3608         struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3609         struct mlx5_flow_attr *attr;
3610
3611         list_for_each_entry(attr, &flow->attrs, list) {
3612                 if (list_is_last(&attr->list, &flow->attrs))
3613                         break;
3614
3615                 mlx5e_tc_post_act_unoffload(post_act, attr->post_act_handle);
3616         }
3617 }
3618
3619 static void
3620 free_flow_post_acts(struct mlx5e_tc_flow *flow)
3621 {
3622         struct mlx5_flow_attr *attr, *tmp;
3623
3624         list_for_each_entry_safe(attr, tmp, &flow->attrs, list) {
3625                 if (list_is_last(&attr->list, &flow->attrs))
3626                         break;
3627
3628                 mlx5_free_flow_attr_actions(flow, attr);
3629
3630                 list_del(&attr->list);
3631                 kvfree(attr->parse_attr);
3632                 kfree(attr);
3633         }
3634 }
3635
3636 int
3637 mlx5e_tc_offload_flow_post_acts(struct mlx5e_tc_flow *flow)
3638 {
3639         struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3640         struct mlx5_flow_attr *attr;
3641         int err = 0;
3642
3643         list_for_each_entry(attr, &flow->attrs, list) {
3644                 if (list_is_last(&attr->list, &flow->attrs))
3645                         break;
3646
3647                 err = mlx5e_tc_post_act_offload(post_act, attr->post_act_handle);
3648                 if (err)
3649                         break;
3650         }
3651
3652         return err;
3653 }
3654
3655 /* TC filter rule HW translation:
3656  *
3657  * +---------------------+
3658  * + ft prio (tc chain)  +
3659  * + original match      +
3660  * +---------------------+
3661  *           |
3662  *           | if multi table action
3663  *           |
3664  *           v
3665  * +---------------------+
3666  * + post act ft         |<----.
3667  * + match fte id        |     | split on multi table action
3668  * + do actions          |-----'
3669  * +---------------------+
3670  *           |
3671  *           |
3672  *           v
3673  * Do rest of the actions after last multi table action.
3674  */
3675 static int
3676 alloc_flow_post_acts(struct mlx5e_tc_flow *flow, struct netlink_ext_ack *extack)
3677 {
3678         struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3679         struct mlx5_flow_attr *attr, *next_attr = NULL;
3680         struct mlx5e_post_act_handle *handle;
3681         int err;
3682
3683         /* This is going in reverse order as needed.
3684          * The first entry is the last attribute.
3685          */
3686         list_for_each_entry(attr, &flow->attrs, list) {
3687                 if (!next_attr) {
3688                         /* Set counter action on last post act rule. */
3689                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3690                 }
3691
3692                 if (next_attr && !(attr->flags & MLX5_ATTR_FLAG_TERMINATING)) {
3693                         err = mlx5e_tc_act_set_next_post_act(flow, attr, next_attr);
3694                         if (err)
3695                                 goto out_free;
3696                 }
3697
3698                 /* Don't add post_act rule for first attr (last in the list).
3699                  * It's being handled by the caller.
3700                  */
3701                 if (list_is_last(&attr->list, &flow->attrs))
3702                         break;
3703
3704                 err = actions_prepare_mod_hdr_actions(flow->priv, flow, attr, extack);
3705                 if (err)
3706                         goto out_free;
3707
3708                 err = post_process_attr(flow, attr, extack);
3709                 if (err)
3710                         goto out_free;
3711
3712                 handle = mlx5e_tc_post_act_add(post_act, attr);
3713                 if (IS_ERR(handle)) {
3714                         err = PTR_ERR(handle);
3715                         goto out_free;
3716                 }
3717
3718                 attr->post_act_handle = handle;
3719
3720                 if (attr->jumping_attr) {
3721                         err = mlx5e_tc_act_set_next_post_act(flow, attr->jumping_attr, attr);
3722                         if (err)
3723                                 goto out_free;
3724                 }
3725
3726                 next_attr = attr;
3727         }
3728
3729         if (flow_flag_test(flow, SLOW))
3730                 goto out;
3731
3732         err = mlx5e_tc_offload_flow_post_acts(flow);
3733         if (err)
3734                 goto out_free;
3735
3736 out:
3737         return 0;
3738
3739 out_free:
3740         free_flow_post_acts(flow);
3741         return err;
3742 }
3743
3744 static int
3745 set_branch_dest_ft(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr)
3746 {
3747         struct mlx5e_post_act *post_act = get_post_action(priv);
3748
3749         if (IS_ERR(post_act))
3750                 return PTR_ERR(post_act);
3751
3752         attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3753         attr->dest_ft = mlx5e_tc_post_act_get_ft(post_act);
3754
3755         return 0;
3756 }
3757
3758 static int
3759 alloc_branch_attr(struct mlx5e_tc_flow *flow,
3760                   struct mlx5e_tc_act_branch_ctrl *cond,
3761                   struct mlx5_flow_attr **cond_attr,
3762                   u32 *jump_count,
3763                   struct netlink_ext_ack *extack)
3764 {
3765         struct mlx5_flow_attr *attr;
3766         int err = 0;
3767
3768         *cond_attr = mlx5e_clone_flow_attr_for_post_act(flow->attr,
3769                                                         mlx5e_get_flow_namespace(flow));
3770         if (!(*cond_attr))
3771                 return -ENOMEM;
3772
3773         attr = *cond_attr;
3774
3775         switch (cond->act_id) {
3776         case FLOW_ACTION_DROP:
3777                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3778                 break;
3779         case FLOW_ACTION_ACCEPT:
3780         case FLOW_ACTION_PIPE:
3781                 if (set_branch_dest_ft(flow->priv, attr))
3782                         goto out_err;
3783                 break;
3784         case FLOW_ACTION_JUMP:
3785                 if (*jump_count) {
3786                         NL_SET_ERR_MSG_MOD(extack, "Cannot offload flows with nested jumps");
3787                         err = -EOPNOTSUPP;
3788                         goto out_err;
3789                 }
3790                 *jump_count = cond->extval;
3791                 if (set_branch_dest_ft(flow->priv, attr))
3792                         goto out_err;
3793                 break;
3794         default:
3795                 err = -EOPNOTSUPP;
3796                 goto out_err;
3797         }
3798
3799         return err;
3800 out_err:
3801         kfree(*cond_attr);
3802         *cond_attr = NULL;
3803         return err;
3804 }
3805
3806 static void
3807 dec_jump_count(struct flow_action_entry *act, struct mlx5e_tc_act *tc_act,
3808                struct mlx5_flow_attr *attr, struct mlx5e_priv *priv,
3809                struct mlx5e_tc_jump_state *jump_state)
3810 {
3811         if (!jump_state->jump_count)
3812                 return;
3813
3814         /* Single tc action can instantiate multiple offload actions (e.g. pedit)
3815          * Jump only over a tc action
3816          */
3817         if (act->id == jump_state->last_id && act->hw_index == jump_state->last_index)
3818                 return;
3819
3820         jump_state->last_id = act->id;
3821         jump_state->last_index = act->hw_index;
3822
3823         /* nothing to do for intermediate actions */
3824         if (--jump_state->jump_count > 1)
3825                 return;
3826
3827         if (jump_state->jump_count == 1) { /* last action in the jump action list */
3828
3829                 /* create a new attribute after this action */
3830                 jump_state->jump_target = true;
3831
3832                 if (tc_act->is_terminating_action) { /* the branch ends here */
3833                         attr->flags |= MLX5_ATTR_FLAG_TERMINATING;
3834                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3835                 } else { /* the branch continues executing the rest of the actions */
3836                         struct mlx5e_post_act *post_act;
3837
3838                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3839                         post_act = get_post_action(priv);
3840                         attr->dest_ft = mlx5e_tc_post_act_get_ft(post_act);
3841                 }
3842         } else if (jump_state->jump_count == 0) { /* first attr after the jump action list */
3843                 /* This is the post action for the jumping attribute (either red or green)
3844                  * Use the stored jumping_attr to set the post act id on the jumping attribute
3845                  */
3846                 attr->jumping_attr = jump_state->jumping_attr;
3847         }
3848 }
3849
3850 static int
3851 parse_branch_ctrl(struct flow_action_entry *act, struct mlx5e_tc_act *tc_act,
3852                   struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr,
3853                   struct mlx5e_tc_jump_state *jump_state,
3854                   struct netlink_ext_ack *extack)
3855 {
3856         struct mlx5e_tc_act_branch_ctrl cond_true, cond_false;
3857         u32 jump_count = jump_state->jump_count;
3858         int err;
3859
3860         if (!tc_act->get_branch_ctrl)
3861                 return 0;
3862
3863         tc_act->get_branch_ctrl(act, &cond_true, &cond_false);
3864
3865         err = alloc_branch_attr(flow, &cond_true,
3866                                 &attr->branch_true, &jump_count, extack);
3867         if (err)
3868                 goto out_err;
3869
3870         if (jump_count)
3871                 jump_state->jumping_attr = attr->branch_true;
3872
3873         err = alloc_branch_attr(flow, &cond_false,
3874                                 &attr->branch_false, &jump_count, extack);
3875         if (err)
3876                 goto err_branch_false;
3877
3878         if (jump_count && !jump_state->jumping_attr)
3879                 jump_state->jumping_attr = attr->branch_false;
3880
3881         jump_state->jump_count = jump_count;
3882
3883         /* branching action requires its own counter */
3884         attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3885         flow_flag_set(flow, USE_ACT_STATS);
3886
3887         return 0;
3888
3889 err_branch_false:
3890         free_branch_attr(flow, attr->branch_true);
3891 out_err:
3892         return err;
3893 }
3894
3895 static int
3896 parse_tc_actions(struct mlx5e_tc_act_parse_state *parse_state,
3897                  struct flow_action *flow_action)
3898 {
3899         struct netlink_ext_ack *extack = parse_state->extack;
3900         struct mlx5e_tc_flow *flow = parse_state->flow;
3901         struct mlx5e_tc_jump_state jump_state = {};
3902         struct mlx5_flow_attr *attr = flow->attr;
3903         enum mlx5_flow_namespace_type ns_type;
3904         struct mlx5e_priv *priv = flow->priv;
3905         struct mlx5_flow_attr *prev_attr;
3906         struct flow_action_entry *act;
3907         struct mlx5e_tc_act *tc_act;
3908         int err, i, i_split = 0;
3909         bool is_missable;
3910
3911         ns_type = mlx5e_get_flow_namespace(flow);
3912         list_add(&attr->list, &flow->attrs);
3913
3914         flow_action_for_each(i, act, flow_action) {
3915                 jump_state.jump_target = false;
3916                 is_missable = false;
3917                 prev_attr = attr;
3918
3919                 tc_act = mlx5e_tc_act_get(act->id, ns_type);
3920                 if (!tc_act) {
3921                         NL_SET_ERR_MSG_MOD(extack, "Not implemented offload action");
3922                         err = -EOPNOTSUPP;
3923                         goto out_free_post_acts;
3924                 }
3925
3926                 if (tc_act->can_offload && !tc_act->can_offload(parse_state, act, i, attr)) {
3927                         err = -EOPNOTSUPP;
3928                         goto out_free_post_acts;
3929                 }
3930
3931                 err = tc_act->parse_action(parse_state, act, priv, attr);
3932                 if (err)
3933                         goto out_free_post_acts;
3934
3935                 dec_jump_count(act, tc_act, attr, priv, &jump_state);
3936
3937                 err = parse_branch_ctrl(act, tc_act, flow, attr, &jump_state, extack);
3938                 if (err)
3939                         goto out_free_post_acts;
3940
3941                 parse_state->actions |= attr->action;
3942
3943                 /* Split attr for multi table act if not the last act. */
3944                 if (jump_state.jump_target ||
3945                     (tc_act->is_multi_table_act &&
3946                     tc_act->is_multi_table_act(priv, act, attr) &&
3947                     i < flow_action->num_entries - 1)) {
3948                         is_missable = tc_act->is_missable ? tc_act->is_missable(act) : false;
3949
3950                         err = mlx5e_tc_act_post_parse(parse_state, flow_action, i_split, i, attr,
3951                                                       ns_type);
3952                         if (err)
3953                                 goto out_free_post_acts;
3954
3955                         attr = mlx5e_clone_flow_attr_for_post_act(flow->attr, ns_type);
3956                         if (!attr) {
3957                                 err = -ENOMEM;
3958                                 goto out_free_post_acts;
3959                         }
3960
3961                         i_split = i + 1;
3962                         parse_state->if_count = 0;
3963                         list_add(&attr->list, &flow->attrs);
3964                 }
3965
3966                 if (is_missable) {
3967                         /* Add counter to prev, and assign act to new (next) attr */
3968                         prev_attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3969                         flow_flag_set(flow, USE_ACT_STATS);
3970
3971                         attr->tc_act_cookies[attr->tc_act_cookies_count++] = act->cookie;
3972                 } else if (!tc_act->stats_action) {
3973                         prev_attr->tc_act_cookies[prev_attr->tc_act_cookies_count++] = act->cookie;
3974                 }
3975         }
3976
3977         err = mlx5e_tc_act_post_parse(parse_state, flow_action, i_split, i, attr, ns_type);
3978         if (err)
3979                 goto out_free_post_acts;
3980
3981         err = alloc_flow_post_acts(flow, extack);
3982         if (err)
3983                 goto out_free_post_acts;
3984
3985         return 0;
3986
3987 out_free_post_acts:
3988         free_flow_post_acts(flow);
3989
3990         return err;
3991 }
3992
3993 static int
3994 flow_action_supported(struct flow_action *flow_action,
3995                       struct netlink_ext_ack *extack)
3996 {
3997         if (!flow_action_has_entries(flow_action)) {
3998                 NL_SET_ERR_MSG_MOD(extack, "Flow action doesn't have any entries");
3999                 return -EINVAL;
4000         }
4001
4002         if (!flow_action_hw_stats_check(flow_action, extack,
4003                                         FLOW_ACTION_HW_STATS_DELAYED_BIT)) {
4004                 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
4005                 return -EOPNOTSUPP;
4006         }
4007
4008         return 0;
4009 }
4010
4011 static int
4012 parse_tc_nic_actions(struct mlx5e_priv *priv,
4013                      struct flow_action *flow_action,
4014                      struct mlx5e_tc_flow *flow,
4015                      struct netlink_ext_ack *extack)
4016 {
4017         struct mlx5e_tc_act_parse_state *parse_state;
4018         struct mlx5e_tc_flow_parse_attr *parse_attr;
4019         struct mlx5_flow_attr *attr = flow->attr;
4020         int err;
4021
4022         err = flow_action_supported(flow_action, extack);
4023         if (err)
4024                 return err;
4025
4026         attr->nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
4027         parse_attr = attr->parse_attr;
4028         parse_state = &parse_attr->parse_state;
4029         mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
4030         parse_state->ct_priv = get_ct_priv(priv);
4031
4032         err = parse_tc_actions(parse_state, flow_action);
4033         if (err)
4034                 return err;
4035
4036         err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
4037         if (err)
4038                 return err;
4039
4040         err = verify_attr_actions(attr->action, extack);
4041         if (err)
4042                 return err;
4043
4044         if (!actions_match_supported(priv, flow_action, parse_state->actions,
4045                                      parse_attr, flow, extack))
4046                 return -EOPNOTSUPP;
4047
4048         return 0;
4049 }
4050
4051 static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
4052                                   struct net_device *peer_netdev)
4053 {
4054         struct mlx5e_priv *peer_priv;
4055
4056         peer_priv = netdev_priv(peer_netdev);
4057
4058         return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
4059                 mlx5e_eswitch_vf_rep(priv->netdev) &&
4060                 mlx5e_eswitch_vf_rep(peer_netdev) &&
4061                 mlx5e_same_hw_devs(priv, peer_priv));
4062 }
4063
4064 static bool same_hw_reps(struct mlx5e_priv *priv,
4065                          struct net_device *peer_netdev)
4066 {
4067         struct mlx5e_priv *peer_priv;
4068
4069         peer_priv = netdev_priv(peer_netdev);
4070
4071         return mlx5e_eswitch_rep(priv->netdev) &&
4072                mlx5e_eswitch_rep(peer_netdev) &&
4073                mlx5e_same_hw_devs(priv, peer_priv);
4074 }
4075
4076 static bool is_lag_dev(struct mlx5e_priv *priv,
4077                        struct net_device *peer_netdev)
4078 {
4079         return ((mlx5_lag_is_sriov(priv->mdev) ||
4080                  mlx5_lag_is_multipath(priv->mdev)) &&
4081                  same_hw_reps(priv, peer_netdev));
4082 }
4083
4084 static bool is_multiport_eligible(struct mlx5e_priv *priv, struct net_device *out_dev)
4085 {
4086         return same_hw_reps(priv, out_dev) && mlx5_lag_is_mpesw(priv->mdev);
4087 }
4088
4089 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
4090                                     struct net_device *out_dev)
4091 {
4092         if (is_merged_eswitch_vfs(priv, out_dev))
4093                 return true;
4094
4095         if (is_multiport_eligible(priv, out_dev))
4096                 return true;
4097
4098         if (is_lag_dev(priv, out_dev))
4099                 return true;
4100
4101         return mlx5e_eswitch_rep(out_dev) &&
4102                same_port_devs(priv, netdev_priv(out_dev));
4103 }
4104
4105 int mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv *priv,
4106                                       struct mlx5_flow_attr *attr,
4107                                       int ifindex,
4108                                       enum mlx5e_tc_int_port_type type,
4109                                       u32 *action,
4110                                       int out_index)
4111 {
4112         struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4113         struct mlx5e_tc_int_port_priv *int_port_priv;
4114         struct mlx5e_tc_flow_parse_attr *parse_attr;
4115         struct mlx5e_tc_int_port *dest_int_port;
4116         int err;
4117
4118         parse_attr = attr->parse_attr;
4119         int_port_priv = mlx5e_get_int_port_priv(priv);
4120
4121         dest_int_port = mlx5e_tc_int_port_get(int_port_priv, ifindex, type);
4122         if (IS_ERR(dest_int_port))
4123                 return PTR_ERR(dest_int_port);
4124
4125         err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
4126                                         MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
4127                                         mlx5e_tc_int_port_get_metadata(dest_int_port));
4128         if (err) {
4129                 mlx5e_tc_int_port_put(int_port_priv, dest_int_port);
4130                 return err;
4131         }
4132
4133         *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
4134
4135         esw_attr->dest_int_port = dest_int_port;
4136         esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE;
4137         esw_attr->split_count = out_index;
4138
4139         /* Forward to root fdb for matching against the new source vport */
4140         attr->dest_chain = 0;
4141
4142         return 0;
4143 }
4144
4145 static int
4146 parse_tc_fdb_actions(struct mlx5e_priv *priv,
4147                      struct flow_action *flow_action,
4148                      struct mlx5e_tc_flow *flow,
4149                      struct netlink_ext_ack *extack)
4150 {
4151         struct mlx5e_tc_act_parse_state *parse_state;
4152         struct mlx5e_tc_flow_parse_attr *parse_attr;
4153         struct mlx5_flow_attr *attr = flow->attr;
4154         struct mlx5_esw_flow_attr *esw_attr;
4155         struct net_device *filter_dev;
4156         int err;
4157
4158         err = flow_action_supported(flow_action, extack);
4159         if (err)
4160                 return err;
4161
4162         esw_attr = attr->esw_attr;
4163         parse_attr = attr->parse_attr;
4164         filter_dev = parse_attr->filter_dev;
4165         parse_state = &parse_attr->parse_state;
4166         mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
4167         parse_state->ct_priv = get_ct_priv(priv);
4168
4169         err = parse_tc_actions(parse_state, flow_action);
4170         if (err)
4171                 return err;
4172
4173         /* Forward to/from internal port can only have 1 dest */
4174         if ((netif_is_ovs_master(filter_dev) || esw_attr->dest_int_port) &&
4175             esw_attr->out_count > 1) {
4176                 NL_SET_ERR_MSG_MOD(extack,
4177                                    "Rules with internal port can have only one destination");
4178                 return -EOPNOTSUPP;
4179         }
4180
4181         /* Forward from tunnel/internal port to internal port is not supported */
4182         if ((mlx5e_get_tc_tun(filter_dev) || netif_is_ovs_master(filter_dev)) &&
4183             esw_attr->dest_int_port) {
4184                 NL_SET_ERR_MSG_MOD(extack,
4185                                    "Forwarding from tunnel/internal port to internal port is not supported");
4186                 return -EOPNOTSUPP;
4187         }
4188
4189         err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
4190         if (err)
4191                 return err;
4192
4193         if (!actions_match_supported(priv, flow_action, parse_state->actions,
4194                                      parse_attr, flow, extack))
4195                 return -EOPNOTSUPP;
4196
4197         return 0;
4198 }
4199
4200 static void get_flags(int flags, unsigned long *flow_flags)
4201 {
4202         unsigned long __flow_flags = 0;
4203
4204         if (flags & MLX5_TC_FLAG(INGRESS))
4205                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4206         if (flags & MLX5_TC_FLAG(EGRESS))
4207                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
4208
4209         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4210                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4211         if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4212                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4213         if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4214                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
4215
4216         *flow_flags = __flow_flags;
4217 }
4218
4219 static const struct rhashtable_params tc_ht_params = {
4220         .head_offset = offsetof(struct mlx5e_tc_flow, node),
4221         .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4222         .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4223         .automatic_shrinking = true,
4224 };
4225
4226 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4227                                     unsigned long flags)
4228 {
4229         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
4230         struct mlx5e_rep_priv *rpriv;
4231
4232         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
4233                 rpriv = priv->ppriv;
4234                 return &rpriv->tc_ht;
4235         } else /* NIC offload */
4236                 return &tc->ht;
4237 }
4238
4239 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4240 {
4241         struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4242         struct mlx5_flow_attr *attr = flow->attr;
4243         bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
4244                 flow_flag_test(flow, INGRESS);
4245         bool act_is_encap = !!(attr->action &
4246                                MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
4247         bool esw_paired = mlx5_devcom_comp_is_ready(esw_attr->in_mdev->priv.eswitch->devcom);
4248
4249         if (!esw_paired)
4250                 return false;
4251
4252         if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4253              mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
4254             (is_rep_ingress || act_is_encap))
4255                 return true;
4256
4257         if (mlx5_lag_is_mpesw(esw_attr->in_mdev))
4258                 return true;
4259
4260         return false;
4261 }
4262
4263 struct mlx5_flow_attr *
4264 mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4265 {
4266         u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB)  ?
4267                                 sizeof(struct mlx5_esw_flow_attr) :
4268                                 sizeof(struct mlx5_nic_flow_attr);
4269         struct mlx5_flow_attr *attr;
4270
4271         attr = kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4272         if (!attr)
4273                 return attr;
4274
4275         INIT_LIST_HEAD(&attr->list);
4276         return attr;
4277 }
4278
4279 static void
4280 mlx5_free_flow_attr_actions(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
4281 {
4282         struct mlx5_core_dev *counter_dev = get_flow_counter_dev(flow);
4283         struct mlx5_esw_flow_attr *esw_attr;
4284
4285         if (!attr)
4286                 return;
4287
4288         if (attr->post_act_handle)
4289                 mlx5e_tc_post_act_del(get_post_action(flow->priv), attr->post_act_handle);
4290
4291         mlx5e_tc_tun_encap_dests_unset(flow->priv, flow, attr);
4292
4293         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
4294                 mlx5_fc_destroy(counter_dev, attr->counter);
4295
4296         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
4297                 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
4298                 mlx5e_tc_detach_mod_hdr(flow->priv, flow, attr);
4299         }
4300
4301         if (mlx5e_is_eswitch_flow(flow)) {
4302                 esw_attr = attr->esw_attr;
4303
4304                 if (esw_attr->int_port)
4305                         mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(flow->priv),
4306                                               esw_attr->int_port);
4307
4308                 if (esw_attr->dest_int_port)
4309                         mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(flow->priv),
4310                                               esw_attr->dest_int_port);
4311         }
4312
4313         mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), attr);
4314
4315         free_branch_attr(flow, attr->branch_true);
4316         free_branch_attr(flow, attr->branch_false);
4317 }
4318
4319 static int
4320 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
4321                  struct flow_cls_offload *f, unsigned long flow_flags,
4322                  struct mlx5e_tc_flow_parse_attr **__parse_attr,
4323                  struct mlx5e_tc_flow **__flow)
4324 {
4325         struct mlx5e_tc_flow_parse_attr *parse_attr;
4326         struct mlx5_flow_attr *attr;
4327         struct mlx5e_tc_flow *flow;
4328         int err = -ENOMEM;
4329         int out_index;
4330
4331         flow = kzalloc(sizeof(*flow), GFP_KERNEL);
4332         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
4333         if (!parse_attr || !flow)
4334                 goto err_free;
4335
4336         flow->flags = flow_flags;
4337         flow->cookie = f->cookie;
4338         flow->priv = priv;
4339
4340         attr = mlx5_alloc_flow_attr(mlx5e_get_flow_namespace(flow));
4341         if (!attr)
4342                 goto err_free;
4343
4344         flow->attr = attr;
4345
4346         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4347                 INIT_LIST_HEAD(&flow->encaps[out_index].list);
4348         INIT_LIST_HEAD(&flow->hairpin);
4349         INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
4350         INIT_LIST_HEAD(&flow->attrs);
4351         INIT_LIST_HEAD(&flow->peer_flows);
4352         refcount_set(&flow->refcnt, 1);
4353         init_completion(&flow->init_done);
4354         init_completion(&flow->del_hw_done);
4355
4356         *__flow = flow;
4357         *__parse_attr = parse_attr;
4358
4359         return 0;
4360
4361 err_free:
4362         kfree(flow);
4363         kvfree(parse_attr);
4364         return err;
4365 }
4366
4367 static void
4368 mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4369                      struct mlx5e_tc_flow_parse_attr *parse_attr,
4370                      struct flow_cls_offload *f)
4371 {
4372         attr->parse_attr = parse_attr;
4373         attr->chain = f->common.chain_index;
4374         attr->prio = f->common.prio;
4375 }
4376
4377 static void
4378 mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
4379                          struct mlx5e_priv *priv,
4380                          struct mlx5e_tc_flow_parse_attr *parse_attr,
4381                          struct flow_cls_offload *f,
4382                          struct mlx5_eswitch_rep *in_rep,
4383                          struct mlx5_core_dev *in_mdev)
4384 {
4385         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4386         struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4387
4388         mlx5e_flow_attr_init(attr, parse_attr, f);
4389
4390         esw_attr->in_rep = in_rep;
4391         esw_attr->in_mdev = in_mdev;
4392
4393         if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4394             MLX5_COUNTER_SOURCE_ESWITCH)
4395                 esw_attr->counter_dev = in_mdev;
4396         else
4397                 esw_attr->counter_dev = priv->mdev;
4398 }
4399
4400 static struct mlx5e_tc_flow *
4401 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4402                      struct flow_cls_offload *f,
4403                      unsigned long flow_flags,
4404                      struct net_device *filter_dev,
4405                      struct mlx5_eswitch_rep *in_rep,
4406                      struct mlx5_core_dev *in_mdev)
4407 {
4408         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4409         struct netlink_ext_ack *extack = f->common.extack;
4410         struct mlx5e_tc_flow_parse_attr *parse_attr;
4411         struct mlx5e_tc_flow *flow;
4412         int attr_size, err;
4413
4414         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4415         attr_size  = sizeof(struct mlx5_esw_flow_attr);
4416         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4417                                &parse_attr, &flow);
4418         if (err)
4419                 goto out;
4420
4421         parse_attr->filter_dev = filter_dev;
4422         mlx5e_flow_esw_attr_init(flow->attr,
4423                                  priv, parse_attr,
4424                                  f, in_rep, in_mdev);
4425
4426         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4427                                f, filter_dev);
4428         if (err)
4429                 goto err_free;
4430
4431         /* actions validation depends on parsing the ct matches first */
4432         err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4433                                    &flow->attr->ct_attr, extack);
4434         if (err)
4435                 goto err_free;
4436
4437         err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4438         if (err)
4439                 goto err_free;
4440
4441         err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
4442         complete_all(&flow->init_done);
4443         if (err) {
4444                 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4445                         goto err_free;
4446
4447                 add_unready_flow(flow);
4448         }
4449
4450         return flow;
4451
4452 err_free:
4453         mlx5e_flow_put(priv, flow);
4454 out:
4455         return ERR_PTR(err);
4456 }
4457
4458 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
4459                                       struct mlx5e_tc_flow *flow,
4460                                       unsigned long flow_flags,
4461                                       struct mlx5_eswitch *peer_esw)
4462 {
4463         struct mlx5e_priv *priv = flow->priv, *peer_priv;
4464         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4465         struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
4466         struct mlx5e_tc_flow_parse_attr *parse_attr;
4467         int i = mlx5_get_dev_index(peer_esw->dev);
4468         struct mlx5e_rep_priv *peer_urpriv;
4469         struct mlx5e_tc_flow *peer_flow;
4470         struct mlx5_core_dev *in_mdev;
4471         int err = 0;
4472
4473         peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4474         peer_priv = netdev_priv(peer_urpriv->netdev);
4475
4476         /* in_mdev is assigned of which the packet originated from.
4477          * So packets redirected to uplink use the same mdev of the
4478          * original flow and packets redirected from uplink use the
4479          * peer mdev.
4480          * In multiport eswitch it's a special case that we need to
4481          * keep the original mdev.
4482          */
4483         if (attr->in_rep->vport == MLX5_VPORT_UPLINK && !mlx5_lag_is_mpesw(priv->mdev))
4484                 in_mdev = peer_priv->mdev;
4485         else
4486                 in_mdev = priv->mdev;
4487
4488         parse_attr = flow->attr->parse_attr;
4489         peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
4490                                          parse_attr->filter_dev,
4491                                          attr->in_rep, in_mdev);
4492         if (IS_ERR(peer_flow)) {
4493                 err = PTR_ERR(peer_flow);
4494                 goto out;
4495         }
4496
4497         list_add_tail(&peer_flow->peer_flows, &flow->peer_flows);
4498         flow_flag_set(flow, DUP);
4499         mutex_lock(&esw->offloads.peer_mutex);
4500         list_add_tail(&flow->peer[i], &esw->offloads.peer_flows[i]);
4501         mutex_unlock(&esw->offloads.peer_mutex);
4502
4503 out:
4504         return err;
4505 }
4506
4507 static int
4508 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4509                    struct flow_cls_offload *f,
4510                    unsigned long flow_flags,
4511                    struct net_device *filter_dev,
4512                    struct mlx5e_tc_flow **__flow)
4513 {
4514         struct mlx5_devcom_comp_dev *devcom = priv->mdev->priv.eswitch->devcom, *pos;
4515         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4516         struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4517         struct mlx5_core_dev *in_mdev = priv->mdev;
4518         struct mlx5_eswitch *peer_esw;
4519         struct mlx5e_tc_flow *flow;
4520         int err;
4521
4522         flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4523                                     in_mdev);
4524         if (IS_ERR(flow))
4525                 return PTR_ERR(flow);
4526
4527         if (!is_peer_flow_needed(flow)) {
4528                 *__flow = flow;
4529                 return 0;
4530         }
4531
4532         if (!mlx5_devcom_for_each_peer_begin(devcom)) {
4533                 err = -ENODEV;
4534                 goto clean_flow;
4535         }
4536
4537         mlx5_devcom_for_each_peer_entry(devcom, peer_esw, pos) {
4538                 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags, peer_esw);
4539                 if (err)
4540                         goto peer_clean;
4541         }
4542
4543         mlx5_devcom_for_each_peer_end(devcom);
4544
4545         *__flow = flow;
4546         return 0;
4547
4548 peer_clean:
4549         mlx5e_tc_del_fdb_peers_flow(flow);
4550         mlx5_devcom_for_each_peer_end(devcom);
4551 clean_flow:
4552         mlx5e_tc_del_fdb_flow(priv, flow);
4553         return err;
4554 }
4555
4556 static int
4557 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
4558                    struct flow_cls_offload *f,
4559                    unsigned long flow_flags,
4560                    struct net_device *filter_dev,
4561                    struct mlx5e_tc_flow **__flow)
4562 {
4563         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4564         struct netlink_ext_ack *extack = f->common.extack;
4565         struct mlx5e_tc_flow_parse_attr *parse_attr;
4566         struct mlx5e_tc_flow *flow;
4567         int attr_size, err;
4568
4569         if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4570                 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4571                         return -EOPNOTSUPP;
4572         } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
4573                 return -EOPNOTSUPP;
4574         }
4575
4576         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4577         attr_size  = sizeof(struct mlx5_nic_flow_attr);
4578         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4579                                &parse_attr, &flow);
4580         if (err)
4581                 goto out;
4582
4583         parse_attr->filter_dev = filter_dev;
4584         mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4585
4586         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4587                                f, filter_dev);
4588         if (err)
4589                 goto err_free;
4590
4591         err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4592                                    &flow->attr->ct_attr, extack);
4593         if (err)
4594                 goto err_free;
4595
4596         err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
4597         if (err)
4598                 goto err_free;
4599
4600         err = mlx5e_tc_add_nic_flow(priv, flow, extack);
4601         if (err)
4602                 goto err_free;
4603
4604         flow_flag_set(flow, OFFLOADED);
4605         *__flow = flow;
4606
4607         return 0;
4608
4609 err_free:
4610         flow_flag_set(flow, FAILED);
4611         mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
4612         mlx5e_flow_put(priv, flow);
4613 out:
4614         return err;
4615 }
4616
4617 static int
4618 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
4619                   struct flow_cls_offload *f,
4620                   unsigned long flags,
4621                   struct net_device *filter_dev,
4622                   struct mlx5e_tc_flow **flow)
4623 {
4624         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4625         unsigned long flow_flags;
4626         int err;
4627
4628         get_flags(flags, &flow_flags);
4629
4630         if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4631                 return -EOPNOTSUPP;
4632
4633         if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
4634                 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4635                                          filter_dev, flow);
4636         else
4637                 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4638                                          filter_dev, flow);
4639
4640         return err;
4641 }
4642
4643 static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4644                                            struct mlx5e_rep_priv *rpriv)
4645 {
4646         /* Offloaded flow rule is allowed to duplicate on non-uplink representor
4647          * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4648          * function is called from NIC mode.
4649          */
4650         return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
4651 }
4652
4653 /* As IPsec and TC order is not aligned between software and hardware-offload,
4654  * either IPsec offload or TC offload, not both, is allowed for a specific interface.
4655  */
4656 static bool is_tc_ipsec_order_check_needed(struct net_device *filter, struct mlx5e_priv *priv)
4657 {
4658         if (!IS_ENABLED(CONFIG_MLX5_EN_IPSEC))
4659                 return false;
4660
4661         if (filter != priv->netdev)
4662                 return false;
4663
4664         if (mlx5e_eswitch_vf_rep(priv->netdev))
4665                 return false;
4666
4667         return true;
4668 }
4669
4670 static int mlx5e_tc_block_ipsec_offload(struct net_device *filter, struct mlx5e_priv *priv)
4671 {
4672         struct mlx5_core_dev *mdev = priv->mdev;
4673
4674         if (!is_tc_ipsec_order_check_needed(filter, priv))
4675                 return 0;
4676
4677         if (mdev->num_block_tc)
4678                 return -EBUSY;
4679
4680         mdev->num_block_ipsec++;
4681
4682         return 0;
4683 }
4684
4685 static void mlx5e_tc_unblock_ipsec_offload(struct net_device *filter, struct mlx5e_priv *priv)
4686 {
4687         if (!is_tc_ipsec_order_check_needed(filter, priv))
4688                 return;
4689
4690         priv->mdev->num_block_ipsec--;
4691 }
4692
4693 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
4694                            struct flow_cls_offload *f, unsigned long flags)
4695 {
4696         struct netlink_ext_ack *extack = f->common.extack;
4697         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4698         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4699         struct mlx5e_tc_flow *flow;
4700         int err = 0;
4701
4702         if (!mlx5_esw_hold(priv->mdev))
4703                 return -EBUSY;
4704
4705         err = mlx5e_tc_block_ipsec_offload(dev, priv);
4706         if (err)
4707                 goto esw_release;
4708
4709         mlx5_esw_get(priv->mdev);
4710
4711         rcu_read_lock();
4712         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4713         if (flow) {
4714                 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4715                  * just return 0.
4716                  */
4717                 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
4718                         goto rcu_unlock;
4719
4720                 NL_SET_ERR_MSG_MOD(extack,
4721                                    "flow cookie already exists, ignoring");
4722                 netdev_warn_once(priv->netdev,
4723                                  "flow cookie %lx already exists, ignoring\n",
4724                                  f->cookie);
4725                 err = -EEXIST;
4726                 goto rcu_unlock;
4727         }
4728 rcu_unlock:
4729         rcu_read_unlock();
4730         if (flow)
4731                 goto out;
4732
4733         trace_mlx5e_configure_flower(f);
4734         err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
4735         if (err)
4736                 goto out;
4737
4738         /* Flow rule offloaded to non-uplink representor sharing tc block,
4739          * set the flow's owner dev.
4740          */
4741         if (is_flow_rule_duplicate_allowed(dev, rpriv))
4742                 flow->orig_dev = dev;
4743
4744         err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
4745         if (err)
4746                 goto err_free;
4747
4748         mlx5_esw_release(priv->mdev);
4749         return 0;
4750
4751 err_free:
4752         mlx5e_flow_put(priv, flow);
4753 out:
4754         mlx5e_tc_unblock_ipsec_offload(dev, priv);
4755         mlx5_esw_put(priv->mdev);
4756 esw_release:
4757         mlx5_esw_release(priv->mdev);
4758         return err;
4759 }
4760
4761 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4762 {
4763         bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4764         bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
4765
4766         return flow_flag_test(flow, INGRESS) == dir_ingress &&
4767                 flow_flag_test(flow, EGRESS) == dir_egress;
4768 }
4769
4770 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
4771                         struct flow_cls_offload *f, unsigned long flags)
4772 {
4773         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4774         struct mlx5e_tc_flow *flow;
4775         int err;
4776
4777         rcu_read_lock();
4778         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4779         if (!flow || !same_flow_direction(flow, flags)) {
4780                 err = -EINVAL;
4781                 goto errout;
4782         }
4783
4784         /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4785          * set.
4786          */
4787         if (flow_flag_test_and_set(flow, DELETED)) {
4788                 err = -EINVAL;
4789                 goto errout;
4790         }
4791         rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
4792         rcu_read_unlock();
4793
4794         trace_mlx5e_delete_flower(f);
4795         mlx5e_flow_put(priv, flow);
4796
4797         mlx5e_tc_unblock_ipsec_offload(dev, priv);
4798         mlx5_esw_put(priv->mdev);
4799         return 0;
4800
4801 errout:
4802         rcu_read_unlock();
4803         return err;
4804 }
4805
4806 int mlx5e_tc_fill_action_stats(struct mlx5e_priv *priv,
4807                                struct flow_offload_action *fl_act)
4808 {
4809         return mlx5e_tc_act_stats_fill_stats(get_act_stats_handle(priv), fl_act);
4810 }
4811
4812 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
4813                        struct flow_cls_offload *f, unsigned long flags)
4814 {
4815         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4816         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4817         struct mlx5e_tc_flow *flow;
4818         struct mlx5_fc *counter;
4819         u64 lastuse = 0;
4820         u64 packets = 0;
4821         u64 bytes = 0;
4822         int err = 0;
4823
4824         rcu_read_lock();
4825         flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4826                                                 tc_ht_params));
4827         rcu_read_unlock();
4828         if (IS_ERR(flow))
4829                 return PTR_ERR(flow);
4830
4831         if (!same_flow_direction(flow, flags)) {
4832                 err = -EINVAL;
4833                 goto errout;
4834         }
4835
4836         if (mlx5e_is_offloaded_flow(flow)) {
4837                 if (flow_flag_test(flow, USE_ACT_STATS)) {
4838                         f->use_act_stats = true;
4839                 } else {
4840                         counter = mlx5e_tc_get_counter(flow);
4841                         if (!counter)
4842                                 goto errout;
4843
4844                         mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4845                 }
4846         }
4847
4848         /* Under multipath it's possible for one rule to be currently
4849          * un-offloaded while the other rule is offloaded.
4850          */
4851         if (esw && !mlx5_devcom_for_each_peer_begin(esw->devcom))
4852                 goto out;
4853
4854         if (flow_flag_test(flow, DUP)) {
4855                 struct mlx5e_tc_flow *peer_flow;
4856
4857                 list_for_each_entry(peer_flow, &flow->peer_flows, peer_flows) {
4858                         u64 packets2;
4859                         u64 lastuse2;
4860                         u64 bytes2;
4861
4862                         if (!flow_flag_test(peer_flow, OFFLOADED))
4863                                 continue;
4864                         if (flow_flag_test(flow, USE_ACT_STATS)) {
4865                                 f->use_act_stats = true;
4866                                 break;
4867                         }
4868
4869                         counter = mlx5e_tc_get_counter(peer_flow);
4870                         if (!counter)
4871                                 goto no_peer_counter;
4872                         mlx5_fc_query_cached(counter, &bytes2, &packets2,
4873                                              &lastuse2);
4874
4875                         bytes += bytes2;
4876                         packets += packets2;
4877                         lastuse = max_t(u64, lastuse, lastuse2);
4878                 }
4879         }
4880
4881 no_peer_counter:
4882         if (esw)
4883                 mlx5_devcom_for_each_peer_end(esw->devcom);
4884 out:
4885         flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
4886                           FLOW_ACTION_HW_STATS_DELAYED);
4887         trace_mlx5e_stats_flower(f);
4888 errout:
4889         mlx5e_flow_put(priv, flow);
4890         return err;
4891 }
4892
4893 static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
4894                                struct netlink_ext_ack *extack)
4895 {
4896         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4897         struct mlx5_eswitch *esw;
4898         u32 rate_mbps = 0;
4899         u16 vport_num;
4900         int err;
4901
4902         vport_num = rpriv->rep->vport;
4903         if (vport_num >= MLX5_VPORT_ECPF) {
4904                 NL_SET_ERR_MSG_MOD(extack,
4905                                    "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4906                 return -EOPNOTSUPP;
4907         }
4908
4909         esw = priv->mdev->priv.eswitch;
4910         /* rate is given in bytes/sec.
4911          * First convert to bits/sec and then round to the nearest mbit/secs.
4912          * mbit means million bits.
4913          * Moreover, if rate is non zero we choose to configure to a minimum of
4914          * 1 mbit/sec.
4915          */
4916         if (rate) {
4917                 rate = (rate * BITS_PER_BYTE) + 500000;
4918                 do_div(rate, 1000000);
4919                 rate_mbps = max_t(u32, rate, 1);
4920         }
4921
4922         err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
4923         if (err)
4924                 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4925
4926         return err;
4927 }
4928
4929 static int
4930 tc_matchall_police_validate(const struct flow_action *action,
4931                             const struct flow_action_entry *act,
4932                             struct netlink_ext_ack *extack)
4933 {
4934         if (act->police.notexceed.act_id != FLOW_ACTION_CONTINUE) {
4935                 NL_SET_ERR_MSG_MOD(extack,
4936                                    "Offload not supported when conform action is not continue");
4937                 return -EOPNOTSUPP;
4938         }
4939
4940         if (act->police.exceed.act_id != FLOW_ACTION_DROP) {
4941                 NL_SET_ERR_MSG_MOD(extack,
4942                                    "Offload not supported when exceed action is not drop");
4943                 return -EOPNOTSUPP;
4944         }
4945
4946         if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT &&
4947             !flow_action_is_last_entry(action, act)) {
4948                 NL_SET_ERR_MSG_MOD(extack,
4949                                    "Offload not supported when conform action is ok, but action is not last");
4950                 return -EOPNOTSUPP;
4951         }
4952
4953         if (act->police.peakrate_bytes_ps ||
4954             act->police.avrate || act->police.overhead) {
4955                 NL_SET_ERR_MSG_MOD(extack,
4956                                    "Offload not supported when peakrate/avrate/overhead is configured");
4957                 return -EOPNOTSUPP;
4958         }
4959
4960         return 0;
4961 }
4962
4963 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4964                                         struct flow_action *flow_action,
4965                                         struct netlink_ext_ack *extack)
4966 {
4967         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4968         const struct flow_action_entry *act;
4969         int err;
4970         int i;
4971
4972         if (!flow_action_has_entries(flow_action)) {
4973                 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4974                 return -EINVAL;
4975         }
4976
4977         if (!flow_offload_has_one_action(flow_action)) {
4978                 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4979                 return -EOPNOTSUPP;
4980         }
4981
4982         if (!flow_action_basic_hw_stats_check(flow_action, extack)) {
4983                 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
4984                 return -EOPNOTSUPP;
4985         }
4986
4987         flow_action_for_each(i, act, flow_action) {
4988                 switch (act->id) {
4989                 case FLOW_ACTION_POLICE:
4990                         err = tc_matchall_police_validate(flow_action, act, extack);
4991                         if (err)
4992                                 return err;
4993
4994                         err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4995                         if (err)
4996                                 return err;
4997
4998                         mlx5e_stats_copy_rep_stats(&rpriv->prev_vf_vport_stats,
4999                                                    &priv->stats.rep_stats);
5000                         break;
5001                 default:
5002                         NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
5003                         return -EOPNOTSUPP;
5004                 }
5005         }
5006
5007         return 0;
5008 }
5009
5010 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
5011                                 struct tc_cls_matchall_offload *ma)
5012 {
5013         struct netlink_ext_ack *extack = ma->common.extack;
5014
5015         if (ma->common.prio != 1) {
5016                 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
5017                 return -EINVAL;
5018         }
5019
5020         return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
5021 }
5022
5023 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
5024                              struct tc_cls_matchall_offload *ma)
5025 {
5026         struct netlink_ext_ack *extack = ma->common.extack;
5027
5028         return apply_police_params(priv, 0, extack);
5029 }
5030
5031 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
5032                              struct tc_cls_matchall_offload *ma)
5033 {
5034         struct mlx5e_rep_priv *rpriv = priv->ppriv;
5035         struct rtnl_link_stats64 cur_stats;
5036         u64 dbytes;
5037         u64 dpkts;
5038
5039         mlx5e_stats_copy_rep_stats(&cur_stats, &priv->stats.rep_stats);
5040         dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
5041         dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
5042         rpriv->prev_vf_vport_stats = cur_stats;
5043         flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
5044                           FLOW_ACTION_HW_STATS_DELAYED);
5045 }
5046
5047 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
5048                                               struct mlx5e_priv *peer_priv)
5049 {
5050         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5051         struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
5052         struct mlx5e_hairpin_entry *hpe, *tmp;
5053         LIST_HEAD(init_wait_list);
5054         u16 peer_vhca_id;
5055         int bkt;
5056
5057         if (!mlx5e_same_hw_devs(priv, peer_priv))
5058                 return;
5059
5060         peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
5061
5062         mutex_lock(&tc->hairpin_tbl_lock);
5063         hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
5064                 if (refcount_inc_not_zero(&hpe->refcnt))
5065                         list_add(&hpe->dead_peer_wait_list, &init_wait_list);
5066         mutex_unlock(&tc->hairpin_tbl_lock);
5067
5068         list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
5069                 wait_for_completion(&hpe->res_ready);
5070                 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
5071                         mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
5072
5073                 mlx5e_hairpin_put(priv, hpe);
5074         }
5075 }
5076
5077 static int mlx5e_tc_netdev_event(struct notifier_block *this,
5078                                  unsigned long event, void *ptr)
5079 {
5080         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
5081         struct mlx5e_priv *peer_priv;
5082         struct mlx5e_tc_table *tc;
5083         struct mlx5e_priv *priv;
5084
5085         if (ndev->netdev_ops != &mlx5e_netdev_ops ||
5086             event != NETDEV_UNREGISTER ||
5087             ndev->reg_state == NETREG_REGISTERED)
5088                 return NOTIFY_DONE;
5089
5090         tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
5091         priv = tc->priv;
5092         peer_priv = netdev_priv(ndev);
5093         if (priv == peer_priv ||
5094             !(priv->netdev->features & NETIF_F_HW_TC))
5095                 return NOTIFY_DONE;
5096
5097         mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
5098
5099         return NOTIFY_DONE;
5100 }
5101
5102 static int mlx5e_tc_nic_create_miss_table(struct mlx5e_priv *priv)
5103 {
5104         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5105         struct mlx5_flow_table **ft = &tc->miss_t;
5106         struct mlx5_flow_table_attr ft_attr = {};
5107         struct mlx5_flow_namespace *ns;
5108         int err = 0;
5109
5110         ft_attr.max_fte = 1;
5111         ft_attr.autogroup.max_num_groups = 1;
5112         ft_attr.level = MLX5E_TC_MISS_LEVEL;
5113         ft_attr.prio = 0;
5114         ns = mlx5_get_flow_namespace(priv->mdev, MLX5_FLOW_NAMESPACE_KERNEL);
5115
5116         *ft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
5117         if (IS_ERR(*ft)) {
5118                 err = PTR_ERR(*ft);
5119                 netdev_err(priv->netdev, "failed to create tc nic miss table err=%d\n", err);
5120         }
5121
5122         return err;
5123 }
5124
5125 static void mlx5e_tc_nic_destroy_miss_table(struct mlx5e_priv *priv)
5126 {
5127         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5128
5129         mlx5_destroy_flow_table(tc->miss_t);
5130 }
5131
5132 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
5133 {
5134         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5135         struct mlx5_core_dev *dev = priv->mdev;
5136         struct mapping_ctx *chains_mapping;
5137         struct mlx5_chains_attr attr = {};
5138         u64 mapping_id;
5139         int err;
5140
5141         mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
5142         mutex_init(&tc->t_lock);
5143         mutex_init(&tc->hairpin_tbl_lock);
5144         hash_init(tc->hairpin_tbl);
5145         tc->priv = priv;
5146
5147         err = rhashtable_init(&tc->ht, &tc_ht_params);
5148         if (err)
5149                 return err;
5150
5151         lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
5152         lockdep_init_map(&tc->ht.run_work.lockdep_map, "tc_ht_wq_key", &tc_ht_wq_key, 0);
5153
5154         mapping_id = mlx5_query_nic_system_image_guid(dev);
5155
5156         chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
5157                                                sizeof(struct mlx5_mapped_obj),
5158                                                MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
5159
5160         if (IS_ERR(chains_mapping)) {
5161                 err = PTR_ERR(chains_mapping);
5162                 goto err_mapping;
5163         }
5164         tc->mapping = chains_mapping;
5165
5166         err = mlx5e_tc_nic_create_miss_table(priv);
5167         if (err)
5168                 goto err_chains;
5169
5170         if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
5171                 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
5172                         MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
5173         attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
5174         attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
5175         attr.default_ft = tc->miss_t;
5176         attr.mapping = chains_mapping;
5177         attr.fs_base_prio = MLX5E_TC_PRIO;
5178
5179         tc->chains = mlx5_chains_create(dev, &attr);
5180         if (IS_ERR(tc->chains)) {
5181                 err = PTR_ERR(tc->chains);
5182                 goto err_miss;
5183         }
5184
5185         mlx5_chains_print_info(tc->chains);
5186
5187         tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
5188         tc->ct = mlx5_tc_ct_init(priv, tc->chains, &tc->mod_hdr,
5189                                  MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
5190
5191         tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
5192         err = register_netdevice_notifier_dev_net(priv->netdev,
5193                                                   &tc->netdevice_nb,
5194                                                   &tc->netdevice_nn);
5195         if (err) {
5196                 tc->netdevice_nb.notifier_call = NULL;
5197                 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
5198                 goto err_reg;
5199         }
5200
5201         mlx5e_tc_debugfs_init(tc, mlx5e_fs_get_debugfs_root(priv->fs));
5202
5203         tc->action_stats_handle = mlx5e_tc_act_stats_create();
5204         if (IS_ERR(tc->action_stats_handle)) {
5205                 err = PTR_ERR(tc->action_stats_handle);
5206                 goto err_act_stats;
5207         }
5208
5209         return 0;
5210
5211 err_act_stats:
5212         unregister_netdevice_notifier_dev_net(priv->netdev,
5213                                               &tc->netdevice_nb,
5214                                               &tc->netdevice_nn);
5215 err_reg:
5216         mlx5_tc_ct_clean(tc->ct);
5217         mlx5e_tc_post_act_destroy(tc->post_act);
5218         mlx5_chains_destroy(tc->chains);
5219 err_miss:
5220         mlx5e_tc_nic_destroy_miss_table(priv);
5221 err_chains:
5222         mapping_destroy(chains_mapping);
5223 err_mapping:
5224         rhashtable_destroy(&tc->ht);
5225         return err;
5226 }
5227
5228 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5229 {
5230         struct mlx5e_tc_flow *flow = ptr;
5231         struct mlx5e_priv *priv = flow->priv;
5232
5233         mlx5e_tc_del_flow(priv, flow);
5234         kfree(flow);
5235 }
5236
5237 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
5238 {
5239         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5240
5241         debugfs_remove_recursive(tc->dfs_root);
5242
5243         if (tc->netdevice_nb.notifier_call)
5244                 unregister_netdevice_notifier_dev_net(priv->netdev,
5245                                                       &tc->netdevice_nb,
5246                                                       &tc->netdevice_nn);
5247
5248         mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
5249         mutex_destroy(&tc->hairpin_tbl_lock);
5250
5251         rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
5252
5253         if (!IS_ERR_OR_NULL(tc->t)) {
5254                 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
5255                 tc->t = NULL;
5256         }
5257         mutex_destroy(&tc->t_lock);
5258
5259         mlx5_tc_ct_clean(tc->ct);
5260         mlx5e_tc_post_act_destroy(tc->post_act);
5261         mapping_destroy(tc->mapping);
5262         mlx5_chains_destroy(tc->chains);
5263         mlx5e_tc_nic_destroy_miss_table(priv);
5264         mlx5e_tc_act_stats_free(tc->action_stats_handle);
5265 }
5266
5267 int mlx5e_tc_ht_init(struct rhashtable *tc_ht)
5268 {
5269         int err;
5270
5271         err = rhashtable_init(tc_ht, &tc_ht_params);
5272         if (err)
5273                 return err;
5274
5275         lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5276         lockdep_init_map(&tc_ht->run_work.lockdep_map, "tc_ht_wq_key", &tc_ht_wq_key, 0);
5277
5278         return 0;
5279 }
5280
5281 void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht)
5282 {
5283         rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5284 }
5285
5286 int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *uplink_priv)
5287 {
5288         const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
5289         struct netdev_phys_item_id ppid;
5290         struct mlx5e_rep_priv *rpriv;
5291         struct mapping_ctx *mapping;
5292         struct mlx5_eswitch *esw;
5293         struct mlx5e_priv *priv;
5294         u64 mapping_id, key;
5295         int err = 0;
5296
5297         rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5298         priv = netdev_priv(rpriv->netdev);
5299         esw = priv->mdev->priv.eswitch;
5300
5301         uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
5302                                                        MLX5_FLOW_NAMESPACE_FDB);
5303         uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5304                                                esw_chains(esw),
5305                                                &esw->offloads.mod_hdr,
5306                                                MLX5_FLOW_NAMESPACE_FDB,
5307                                                uplink_priv->post_act);
5308
5309         uplink_priv->int_port_priv = mlx5e_tc_int_port_init(netdev_priv(priv->netdev));
5310
5311         uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
5312
5313         mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
5314
5315         mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
5316                                         sizeof(struct tunnel_match_key),
5317                                         TUNNEL_INFO_BITS_MASK, true);
5318
5319         if (IS_ERR(mapping)) {
5320                 err = PTR_ERR(mapping);
5321                 goto err_tun_mapping;
5322         }
5323         uplink_priv->tunnel_mapping = mapping;
5324
5325         /* Two last values are reserved for stack devices slow path table mark
5326          * and bridge ingress push mark.
5327          */
5328         mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
5329                                         sz_enc_opts, ENC_OPTS_BITS_MASK - 2, true);
5330         if (IS_ERR(mapping)) {
5331                 err = PTR_ERR(mapping);
5332                 goto err_enc_opts_mapping;
5333         }
5334         uplink_priv->tunnel_enc_opts_mapping = mapping;
5335
5336         uplink_priv->encap = mlx5e_tc_tun_init(priv);
5337         if (IS_ERR(uplink_priv->encap)) {
5338                 err = PTR_ERR(uplink_priv->encap);
5339                 goto err_register_fib_notifier;
5340         }
5341
5342         uplink_priv->action_stats_handle = mlx5e_tc_act_stats_create();
5343         if (IS_ERR(uplink_priv->action_stats_handle)) {
5344                 err = PTR_ERR(uplink_priv->action_stats_handle);
5345                 goto err_action_counter;
5346         }
5347
5348         err = dev_get_port_parent_id(priv->netdev, &ppid, false);
5349         if (!err) {
5350                 memcpy(&key, &ppid.id, sizeof(key));
5351                 mlx5_esw_offloads_devcom_init(esw, key);
5352         }
5353
5354         return 0;
5355
5356 err_action_counter:
5357         mlx5e_tc_tun_cleanup(uplink_priv->encap);
5358 err_register_fib_notifier:
5359         mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5360 err_enc_opts_mapping:
5361         mapping_destroy(uplink_priv->tunnel_mapping);
5362 err_tun_mapping:
5363         mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
5364         mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
5365         mlx5_tc_ct_clean(uplink_priv->ct_priv);
5366         netdev_warn(priv->netdev,
5367                     "Failed to initialize tc (eswitch), err: %d", err);
5368         mlx5e_tc_post_act_destroy(uplink_priv->post_act);
5369         return err;
5370 }
5371
5372 void mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv *uplink_priv)
5373 {
5374         struct mlx5e_rep_priv *rpriv;
5375         struct mlx5_eswitch *esw;
5376         struct mlx5e_priv *priv;
5377
5378         rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5379         priv = netdev_priv(rpriv->netdev);
5380         esw = priv->mdev->priv.eswitch;
5381
5382         mlx5_esw_offloads_devcom_cleanup(esw);
5383
5384         mlx5e_tc_tun_cleanup(uplink_priv->encap);
5385
5386         mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5387         mapping_destroy(uplink_priv->tunnel_mapping);
5388
5389         mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
5390         mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
5391         mlx5_tc_ct_clean(uplink_priv->ct_priv);
5392         mlx5e_flow_meters_cleanup(uplink_priv->flow_meters);
5393         mlx5e_tc_post_act_destroy(uplink_priv->post_act);
5394         mlx5e_tc_act_stats_free(uplink_priv->action_stats_handle);
5395 }
5396
5397 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
5398 {
5399         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
5400
5401         return atomic_read(&tc_ht->nelems);
5402 }
5403
5404 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5405 {
5406         struct mlx5e_tc_flow *flow, *tmp;
5407         int i;
5408
5409         for (i = 0; i < MLX5_MAX_PORTS; i++) {
5410                 if (i == mlx5_get_dev_index(esw->dev))
5411                         continue;
5412                 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows[i], peer[i])
5413                         mlx5e_tc_del_fdb_peers_flow(flow);
5414         }
5415 }
5416
5417 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5418 {
5419         struct mlx5_rep_uplink_priv *rpriv =
5420                 container_of(work, struct mlx5_rep_uplink_priv,
5421                              reoffload_flows_work);
5422         struct mlx5e_tc_flow *flow, *tmp;
5423
5424         mutex_lock(&rpriv->unready_flows_lock);
5425         list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5426                 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
5427                         unready_flow_del(flow);
5428         }
5429         mutex_unlock(&rpriv->unready_flows_lock);
5430 }
5431
5432 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5433                                      struct flow_cls_offload *cls_flower,
5434                                      unsigned long flags)
5435 {
5436         switch (cls_flower->command) {
5437         case FLOW_CLS_REPLACE:
5438                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5439                                               flags);
5440         case FLOW_CLS_DESTROY:
5441                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5442                                            flags);
5443         case FLOW_CLS_STATS:
5444                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5445                                           flags);
5446         default:
5447                 return -EOPNOTSUPP;
5448         }
5449 }
5450
5451 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5452                             void *cb_priv)
5453 {
5454         unsigned long flags = MLX5_TC_FLAG(INGRESS);
5455         struct mlx5e_priv *priv = cb_priv;
5456
5457         if (!priv->netdev || !netif_device_present(priv->netdev))
5458                 return -EOPNOTSUPP;
5459
5460         if (mlx5e_is_uplink_rep(priv))
5461                 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5462         else
5463                 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5464
5465         switch (type) {
5466         case TC_SETUP_CLSFLOWER:
5467                 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5468         default:
5469                 return -EOPNOTSUPP;
5470         }
5471 }
5472
5473 static bool mlx5e_tc_restore_tunnel(struct mlx5e_priv *priv, struct sk_buff *skb,
5474                                     struct mlx5e_tc_update_priv *tc_priv,
5475                                     u32 tunnel_id)
5476 {
5477         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5478         struct tunnel_match_enc_opts enc_opts = {};
5479         struct mlx5_rep_uplink_priv *uplink_priv;
5480         struct mlx5e_rep_priv *uplink_rpriv;
5481         struct metadata_dst *tun_dst;
5482         struct tunnel_match_key key;
5483         u32 tun_id, enc_opts_id;
5484         struct net_device *dev;
5485         int err;
5486
5487         enc_opts_id = tunnel_id & ENC_OPTS_BITS_MASK;
5488         tun_id = tunnel_id >> ENC_OPTS_BITS;
5489
5490         if (!tun_id)
5491                 return true;
5492
5493         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5494         uplink_priv = &uplink_rpriv->uplink_priv;
5495
5496         err = mapping_find(uplink_priv->tunnel_mapping, tun_id, &key);
5497         if (err) {
5498                 netdev_dbg(priv->netdev,
5499                            "Couldn't find tunnel for tun_id: %d, err: %d\n",
5500                            tun_id, err);
5501                 return false;
5502         }
5503
5504         if (enc_opts_id) {
5505                 err = mapping_find(uplink_priv->tunnel_enc_opts_mapping,
5506                                    enc_opts_id, &enc_opts);
5507                 if (err) {
5508                         netdev_dbg(priv->netdev,
5509                                    "Couldn't find tunnel (opts) for tun_id: %d, err: %d\n",
5510                                    enc_opts_id, err);
5511                         return false;
5512                 }
5513         }
5514
5515         switch (key.enc_control.addr_type) {
5516         case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
5517                 tun_dst = __ip_tun_set_dst(key.enc_ipv4.src, key.enc_ipv4.dst,
5518                                            key.enc_ip.tos, key.enc_ip.ttl,
5519                                            key.enc_tp.dst, TUNNEL_KEY,
5520                                            key32_to_tunnel_id(key.enc_key_id.keyid),
5521                                            enc_opts.key.len);
5522                 break;
5523         case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
5524                 tun_dst = __ipv6_tun_set_dst(&key.enc_ipv6.src, &key.enc_ipv6.dst,
5525                                              key.enc_ip.tos, key.enc_ip.ttl,
5526                                              key.enc_tp.dst, 0, TUNNEL_KEY,
5527                                              key32_to_tunnel_id(key.enc_key_id.keyid),
5528                                              enc_opts.key.len);
5529                 break;
5530         default:
5531                 netdev_dbg(priv->netdev,
5532                            "Couldn't restore tunnel, unsupported addr_type: %d\n",
5533                            key.enc_control.addr_type);
5534                 return false;
5535         }
5536
5537         if (!tun_dst) {
5538                 netdev_dbg(priv->netdev, "Couldn't restore tunnel, no tun_dst\n");
5539                 return false;
5540         }
5541
5542         tun_dst->u.tun_info.key.tp_src = key.enc_tp.src;
5543
5544         if (enc_opts.key.len)
5545                 ip_tunnel_info_opts_set(&tun_dst->u.tun_info,
5546                                         enc_opts.key.data,
5547                                         enc_opts.key.len,
5548                                         enc_opts.key.dst_opt_type);
5549
5550         skb_dst_set(skb, (struct dst_entry *)tun_dst);
5551         dev = dev_get_by_index(&init_net, key.filter_ifindex);
5552         if (!dev) {
5553                 netdev_dbg(priv->netdev,
5554                            "Couldn't find tunnel device with ifindex: %d\n",
5555                            key.filter_ifindex);
5556                 return false;
5557         }
5558
5559         /* Set fwd_dev so we do dev_put() after datapath */
5560         tc_priv->fwd_dev = dev;
5561
5562         skb->dev = dev;
5563
5564         return true;
5565 }
5566
5567 static bool mlx5e_tc_restore_skb_tc_meta(struct sk_buff *skb, struct mlx5_tc_ct_priv *ct_priv,
5568                                          struct mlx5_mapped_obj *mapped_obj, u32 zone_restore_id,
5569                                          u32 tunnel_id,  struct mlx5e_tc_update_priv *tc_priv)
5570 {
5571         struct mlx5e_priv *priv = netdev_priv(skb->dev);
5572         struct tc_skb_ext *tc_skb_ext;
5573         u64 act_miss_cookie;
5574         u32 chain;
5575
5576         chain = mapped_obj->type == MLX5_MAPPED_OBJ_CHAIN ? mapped_obj->chain : 0;
5577         act_miss_cookie = mapped_obj->type == MLX5_MAPPED_OBJ_ACT_MISS ?
5578                           mapped_obj->act_miss_cookie : 0;
5579         if (chain || act_miss_cookie) {
5580                 if (!mlx5e_tc_ct_restore_flow(ct_priv, skb, zone_restore_id))
5581                         return false;
5582
5583                 tc_skb_ext = tc_skb_ext_alloc(skb);
5584                 if (!tc_skb_ext) {
5585                         WARN_ON(1);
5586                         return false;
5587                 }
5588
5589                 if (act_miss_cookie) {
5590                         tc_skb_ext->act_miss_cookie = act_miss_cookie;
5591                         tc_skb_ext->act_miss = 1;
5592                 } else {
5593                         tc_skb_ext->chain = chain;
5594                 }
5595         }
5596
5597         if (tc_priv)
5598                 return mlx5e_tc_restore_tunnel(priv, skb, tc_priv, tunnel_id);
5599
5600         return true;
5601 }
5602
5603 static void mlx5e_tc_restore_skb_sample(struct mlx5e_priv *priv, struct sk_buff *skb,
5604                                         struct mlx5_mapped_obj *mapped_obj,
5605                                         struct mlx5e_tc_update_priv *tc_priv)
5606 {
5607         if (!mlx5e_tc_restore_tunnel(priv, skb, tc_priv, mapped_obj->sample.tunnel_id)) {
5608                 netdev_dbg(priv->netdev,
5609                            "Failed to restore tunnel info for sampled packet\n");
5610                 return;
5611         }
5612         mlx5e_tc_sample_skb(skb, mapped_obj);
5613 }
5614
5615 static bool mlx5e_tc_restore_skb_int_port(struct mlx5e_priv *priv, struct sk_buff *skb,
5616                                           struct mlx5_mapped_obj *mapped_obj,
5617                                           struct mlx5e_tc_update_priv *tc_priv,
5618                                           u32 tunnel_id)
5619 {
5620         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5621         struct mlx5_rep_uplink_priv *uplink_priv;
5622         struct mlx5e_rep_priv *uplink_rpriv;
5623         bool forward_tx = false;
5624
5625         /* Tunnel restore takes precedence over int port restore */
5626         if (tunnel_id)
5627                 return mlx5e_tc_restore_tunnel(priv, skb, tc_priv, tunnel_id);
5628
5629         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5630         uplink_priv = &uplink_rpriv->uplink_priv;
5631
5632         if (mlx5e_tc_int_port_dev_fwd(uplink_priv->int_port_priv, skb,
5633                                       mapped_obj->int_port_metadata, &forward_tx)) {
5634                 /* Set fwd_dev for future dev_put */
5635                 tc_priv->fwd_dev = skb->dev;
5636                 tc_priv->forward_tx = forward_tx;
5637
5638                 return true;
5639         }
5640
5641         return false;
5642 }
5643
5644 bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe, struct sk_buff *skb,
5645                          struct mapping_ctx *mapping_ctx, u32 mapped_obj_id,
5646                          struct mlx5_tc_ct_priv *ct_priv,
5647                          u32 zone_restore_id, u32 tunnel_id,
5648                          struct mlx5e_tc_update_priv *tc_priv)
5649 {
5650         struct mlx5e_priv *priv = netdev_priv(skb->dev);
5651         struct mlx5_mapped_obj mapped_obj;
5652         int err;
5653
5654         err = mapping_find(mapping_ctx, mapped_obj_id, &mapped_obj);
5655         if (err) {
5656                 netdev_dbg(skb->dev,
5657                            "Couldn't find mapped object for mapped_obj_id: %d, err: %d\n",
5658                            mapped_obj_id, err);
5659                 return false;
5660         }
5661
5662         switch (mapped_obj.type) {
5663         case MLX5_MAPPED_OBJ_CHAIN:
5664         case MLX5_MAPPED_OBJ_ACT_MISS:
5665                 return mlx5e_tc_restore_skb_tc_meta(skb, ct_priv, &mapped_obj, zone_restore_id,
5666                                                     tunnel_id, tc_priv);
5667         case MLX5_MAPPED_OBJ_SAMPLE:
5668                 mlx5e_tc_restore_skb_sample(priv, skb, &mapped_obj, tc_priv);
5669                 tc_priv->skb_done = true;
5670                 return true;
5671         case MLX5_MAPPED_OBJ_INT_PORT_METADATA:
5672                 return mlx5e_tc_restore_skb_int_port(priv, skb, &mapped_obj, tc_priv, tunnel_id);
5673         default:
5674                 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5675                 return false;
5676         }
5677
5678         return false;
5679 }
5680
5681 bool mlx5e_tc_update_skb_nic(struct mlx5_cqe64 *cqe, struct sk_buff *skb)
5682 {
5683         struct mlx5e_priv *priv = netdev_priv(skb->dev);
5684         u32 mapped_obj_id, reg_b, zone_restore_id;
5685         struct mlx5_tc_ct_priv *ct_priv;
5686         struct mapping_ctx *mapping_ctx;
5687         struct mlx5e_tc_table *tc;
5688
5689         reg_b = be32_to_cpu(cqe->ft_metadata);
5690         tc = mlx5e_fs_get_tc(priv->fs);
5691         mapped_obj_id = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5692         zone_restore_id = (reg_b >> MLX5_REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
5693                           ESW_ZONE_ID_MASK;
5694         ct_priv = tc->ct;
5695         mapping_ctx = tc->mapping;
5696
5697         return mlx5e_tc_update_skb(cqe, skb, mapping_ctx, mapped_obj_id, ct_priv, zone_restore_id,
5698                                    0, NULL);
5699 }
5700
5701 static struct mapping_ctx *
5702 mlx5e_get_priv_obj_mapping(struct mlx5e_priv *priv)
5703 {
5704         struct mlx5e_tc_table *tc;
5705         struct mlx5_eswitch *esw;
5706         struct mapping_ctx *ctx;
5707
5708         if (is_mdev_switchdev_mode(priv->mdev)) {
5709                 esw = priv->mdev->priv.eswitch;
5710                 ctx = esw->offloads.reg_c0_obj_pool;
5711         } else {
5712                 tc = mlx5e_fs_get_tc(priv->fs);
5713                 ctx = tc->mapping;
5714         }
5715
5716         return ctx;
5717 }
5718
5719 int mlx5e_tc_action_miss_mapping_get(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr,
5720                                      u64 act_miss_cookie, u32 *act_miss_mapping)
5721 {
5722         struct mlx5_mapped_obj mapped_obj = {};
5723         struct mlx5_eswitch *esw;
5724         struct mapping_ctx *ctx;
5725         int err;
5726
5727         ctx = mlx5e_get_priv_obj_mapping(priv);
5728         mapped_obj.type = MLX5_MAPPED_OBJ_ACT_MISS;
5729         mapped_obj.act_miss_cookie = act_miss_cookie;
5730         err = mapping_add(ctx, &mapped_obj, act_miss_mapping);
5731         if (err)
5732                 return err;
5733
5734         if (!is_mdev_switchdev_mode(priv->mdev))
5735                 return 0;
5736
5737         esw = priv->mdev->priv.eswitch;
5738         attr->act_id_restore_rule = esw_add_restore_rule(esw, *act_miss_mapping);
5739         if (IS_ERR(attr->act_id_restore_rule))
5740                 goto err_rule;
5741
5742         return 0;
5743
5744 err_rule:
5745         mapping_remove(ctx, *act_miss_mapping);
5746         return err;
5747 }
5748
5749 void mlx5e_tc_action_miss_mapping_put(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr,
5750                                       u32 act_miss_mapping)
5751 {
5752         struct mapping_ctx *ctx = mlx5e_get_priv_obj_mapping(priv);
5753
5754         if (is_mdev_switchdev_mode(priv->mdev))
5755                 mlx5_del_flow_rules(attr->act_id_restore_rule);
5756         mapping_remove(ctx, act_miss_mapping);
5757 }