drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

   1 /*
   2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/flow_dissector.h>
  34 #include <net/flow_offload.h>
  35 #include <net/sch_generic.h>
  36 #include <net/pkt_cls.h>
  37 #include <linux/mlx5/fs.h>
  38 #include <linux/mlx5/device.h>
  39 #include <linux/rhashtable.h>
  40 #include <linux/refcount.h>
  41 #include <linux/completion.h>
  42 #include <net/arp.h>
  43 #include <net/ipv6_stubs.h>
  44 #include <net/bareudp.h>
  45 #include <net/bonding.h>
  46 #include <net/dst_metadata.h>
  47 #include "devlink.h"
  48 #include "en.h"
  49 #include "en/tc/post_act.h"
  50 #include "en/tc/act_stats.h"
  51 #include "en_rep.h"
  52 #include "en/rep/tc.h"
  53 #include "en/rep/neigh.h"
  54 #include "en_tc.h"
  55 #include "eswitch.h"
  56 #include "fs_core.h"
  57 #include "en/port.h"
  58 #include "en/tc_tun.h"
  59 #include "en/mapping.h"
  60 #include "en/tc_ct.h"
  61 #include "en/mod_hdr.h"
  62 #include "en/tc_tun_encap.h"
  63 #include "en/tc/sample.h"
  64 #include "en/tc/act/act.h"
  65 #include "en/tc/post_meter.h"
  66 #include "lib/devcom.h"
  67 #include "lib/geneve.h"
  68 #include "lib/fs_chains.h"
  69 #include "diag/en_tc_tracepoint.h"
  70 #include <asm/div64.h>
  71 #include "lag/lag.h"
  72 #include "lag/mp.h"
  73
  74 #define MLX5E_TC_TABLE_NUM_GROUPS 4
  75 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
  76
  77 struct mlx5e_tc_table {
  78         /* Protects the dynamic assignment of the t parameter
  79          * which is the nic tc root table.
  80          */
  81         struct mutex                    t_lock;
  82         struct mlx5e_priv               *priv;
  83         struct mlx5_flow_table          *t;
  84         struct mlx5_flow_table          *miss_t;
  85         struct mlx5_fs_chains           *chains;
  86         struct mlx5e_post_act           *post_act;
  87
  88         struct rhashtable               ht;
  89
  90         struct mod_hdr_tbl mod_hdr;
  91         struct mutex hairpin_tbl_lock; /* protects hairpin_tbl */
  92         DECLARE_HASHTABLE(hairpin_tbl, 8);
  93
  94         struct notifier_block     netdevice_nb;
  95         struct netdev_net_notifier      netdevice_nn;
  96
  97         struct mlx5_tc_ct_priv         *ct;
  98         struct mapping_ctx             *mapping;
  99         struct dentry                  *dfs_root;
 100
 101         /* tc action stats */
 102         struct mlx5e_tc_act_stats_handle *action_stats_handle;
 103 };
 104
 105 struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
 106         [MAPPED_OBJ_TO_REG] = {
 107                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
 108                 .moffset = 0,
 109                 .mlen = 16,
 110         },
 111         [VPORT_TO_REG] = {
 112                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
 113                 .moffset = 16,
 114                 .mlen = 16,
 115         },
 116         [TUNNEL_TO_REG] = {
 117                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
 118                 .moffset = 8,
 119                 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
 120                 .soffset = MLX5_BYTE_OFF(fte_match_param,
 121                                          misc_parameters_2.metadata_reg_c_1),
 122         },
 123         [ZONE_TO_REG] = zone_to_reg_ct,
 124         [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
 125         [CTSTATE_TO_REG] = ctstate_to_reg_ct,
 126         [MARK_TO_REG] = mark_to_reg_ct,
 127         [LABELS_TO_REG] = labels_to_reg_ct,
 128         [FTEID_TO_REG] = fteid_to_reg_ct,
 129         /* For NIC rules we store the restore metadata directly
 130          * into reg_b that is passed to SW since we don't
 131          * jump between steering domains.
 132          */
 133         [NIC_MAPPED_OBJ_TO_REG] = {
 134                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
 135                 .moffset = 0,
 136                 .mlen = 16,
 137         },
 138         [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
 139         [PACKET_COLOR_TO_REG] = packet_color_to_reg,
 140 };
 141
 142 struct mlx5e_tc_jump_state {
 143         u32 jump_count;
 144         bool jump_target;
 145         struct mlx5_flow_attr *jumping_attr;
 146
 147         enum flow_action_id last_id;
 148         u32 last_index;
 149 };
 150
 151 struct mlx5e_tc_table *mlx5e_tc_table_alloc(void)
 152 {
 153         struct mlx5e_tc_table *tc;
 154
 155         tc = kvzalloc(sizeof(*tc), GFP_KERNEL);
 156         return tc ? tc : ERR_PTR(-ENOMEM);
 157 }
 158
 159 void mlx5e_tc_table_free(struct mlx5e_tc_table *tc)
 160 {
 161         kvfree(tc);
 162 }
 163
 164 struct mlx5_fs_chains *mlx5e_nic_chains(struct mlx5e_tc_table *tc)
 165 {
 166         return tc->chains;
 167 }
 168
 169 /* To avoid false lock dependency warning set the tc_ht lock
 170  * class different than the lock class of the ht being used when deleting
 171  * last flow from a group and then deleting a group, we get into del_sw_flow_group()
 172  * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
 173  * it's different than the ht->mutex here.
 174  */
 175 static struct lock_class_key tc_ht_lock_key;
 176 static struct lock_class_key tc_ht_wq_key;
 177
 178 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
 179 static void free_flow_post_acts(struct mlx5e_tc_flow *flow);
 180 static void mlx5_free_flow_attr_actions(struct mlx5e_tc_flow *flow,
 181                                         struct mlx5_flow_attr *attr);
 182
 183 void
 184 mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
 185                             enum mlx5e_tc_attr_to_reg type,
 186                             u32 val,
 187                             u32 mask)
 188 {
 189         void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
 190         int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
 191         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 192         int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 193         u32 max_mask = GENMASK(match_len - 1, 0);
 194         __be32 curr_mask_be, curr_val_be;
 195         u32 curr_mask, curr_val;
 196
 197         fmask = headers_c + soffset;
 198         fval = headers_v + soffset;
 199
 200         memcpy(&curr_mask_be, fmask, 4);
 201         memcpy(&curr_val_be, fval, 4);
 202
 203         curr_mask = be32_to_cpu(curr_mask_be);
 204         curr_val = be32_to_cpu(curr_val_be);
 205
 206         //move to correct offset
 207         WARN_ON(mask > max_mask);
 208         mask <<= moffset;
 209         val <<= moffset;
 210         max_mask <<= moffset;
 211
 212         //zero val and mask
 213         curr_mask &= ~max_mask;
 214         curr_val &= ~max_mask;
 215
 216         //add current to mask
 217         curr_mask |= mask;
 218         curr_val |= val;
 219
 220         //back to be32 and write
 221         curr_mask_be = cpu_to_be32(curr_mask);
 222         curr_val_be = cpu_to_be32(curr_val);
 223
 224         memcpy(fmask, &curr_mask_be, 4);
 225         memcpy(fval, &curr_val_be, 4);
 226
 227         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
 228 }
 229
 230 void
 231 mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
 232                                 enum mlx5e_tc_attr_to_reg type,
 233                                 u32 *val,
 234                                 u32 *mask)
 235 {
 236         void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
 237         int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
 238         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 239         int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 240         u32 max_mask = GENMASK(match_len - 1, 0);
 241         __be32 curr_mask_be, curr_val_be;
 242         u32 curr_mask, curr_val;
 243
 244         fmask = headers_c + soffset;
 245         fval = headers_v + soffset;
 246
 247         memcpy(&curr_mask_be, fmask, 4);
 248         memcpy(&curr_val_be, fval, 4);
 249
 250         curr_mask = be32_to_cpu(curr_mask_be);
 251         curr_val = be32_to_cpu(curr_val_be);
 252
 253         *mask = (curr_mask >> moffset) & max_mask;
 254         *val = (curr_val >> moffset) & max_mask;
 255 }
 256
 257 int
 258 mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
 259                                      struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 260                                      enum mlx5_flow_namespace_type ns,
 261                                      enum mlx5e_tc_attr_to_reg type,
 262                                      u32 data)
 263 {
 264         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 265         int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
 266         int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 267         char *modact;
 268         int err;
 269
 270         modact = mlx5e_mod_hdr_alloc(mdev, ns, mod_hdr_acts);
 271         if (IS_ERR(modact))
 272                 return PTR_ERR(modact);
 273
 274         /* Firmware has 5bit length field and 0 means 32bits */
 275         if (mlen == 32)
 276                 mlen = 0;
 277
 278         MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
 279         MLX5_SET(set_action_in, modact, field, mfield);
 280         MLX5_SET(set_action_in, modact, offset, moffset);
 281         MLX5_SET(set_action_in, modact, length, mlen);
 282         MLX5_SET(set_action_in, modact, data, data);
 283         err = mod_hdr_acts->num_actions;
 284         mod_hdr_acts->num_actions++;
 285
 286         return err;
 287 }
 288
 289 static struct mlx5e_tc_act_stats_handle  *
 290 get_act_stats_handle(struct mlx5e_priv *priv)
 291 {
 292         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 293         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 294         struct mlx5_rep_uplink_priv *uplink_priv;
 295         struct mlx5e_rep_priv *uplink_rpriv;
 296
 297         if (is_mdev_switchdev_mode(priv->mdev)) {
 298                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 299                 uplink_priv = &uplink_rpriv->uplink_priv;
 300
 301                 return uplink_priv->action_stats_handle;
 302         }
 303
 304         return tc->action_stats_handle;
 305 }
 306
 307 struct mlx5e_tc_int_port_priv *
 308 mlx5e_get_int_port_priv(struct mlx5e_priv *priv)
 309 {
 310         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 311         struct mlx5_rep_uplink_priv *uplink_priv;
 312         struct mlx5e_rep_priv *uplink_rpriv;
 313
 314         if (is_mdev_switchdev_mode(priv->mdev)) {
 315                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 316                 uplink_priv = &uplink_rpriv->uplink_priv;
 317
 318                 return uplink_priv->int_port_priv;
 319         }
 320
 321         return NULL;
 322 }
 323
 324 struct mlx5e_flow_meters *
 325 mlx5e_get_flow_meters(struct mlx5_core_dev *dev)
 326 {
 327         struct mlx5_eswitch *esw = dev->priv.eswitch;
 328         struct mlx5_rep_uplink_priv *uplink_priv;
 329         struct mlx5e_rep_priv *uplink_rpriv;
 330         struct mlx5e_priv *priv;
 331
 332         if (is_mdev_switchdev_mode(dev)) {
 333                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 334                 uplink_priv = &uplink_rpriv->uplink_priv;
 335                 priv = netdev_priv(uplink_rpriv->netdev);
 336                 if (!uplink_priv->flow_meters)
 337                         uplink_priv->flow_meters =
 338                                 mlx5e_flow_meters_init(priv,
 339                                                        MLX5_FLOW_NAMESPACE_FDB,
 340                                                        uplink_priv->post_act);
 341                 if (!IS_ERR(uplink_priv->flow_meters))
 342                         return uplink_priv->flow_meters;
 343         }
 344
 345         return NULL;
 346 }
 347
 348 static struct mlx5_tc_ct_priv *
 349 get_ct_priv(struct mlx5e_priv *priv)
 350 {
 351         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 352         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 353         struct mlx5_rep_uplink_priv *uplink_priv;
 354         struct mlx5e_rep_priv *uplink_rpriv;
 355
 356         if (is_mdev_switchdev_mode(priv->mdev)) {
 357                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 358                 uplink_priv = &uplink_rpriv->uplink_priv;
 359
 360                 return uplink_priv->ct_priv;
 361         }
 362
 363         return tc->ct;
 364 }
 365
 366 static struct mlx5e_tc_psample *
 367 get_sample_priv(struct mlx5e_priv *priv)
 368 {
 369         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 370         struct mlx5_rep_uplink_priv *uplink_priv;
 371         struct mlx5e_rep_priv *uplink_rpriv;
 372
 373         if (is_mdev_switchdev_mode(priv->mdev)) {
 374                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 375                 uplink_priv = &uplink_rpriv->uplink_priv;
 376
 377                 return uplink_priv->tc_psample;
 378         }
 379
 380         return NULL;
 381 }
 382
 383 static struct mlx5e_post_act *
 384 get_post_action(struct mlx5e_priv *priv)
 385 {
 386         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 387         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 388         struct mlx5_rep_uplink_priv *uplink_priv;
 389         struct mlx5e_rep_priv *uplink_rpriv;
 390
 391         if (is_mdev_switchdev_mode(priv->mdev)) {
 392                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 393                 uplink_priv = &uplink_rpriv->uplink_priv;
 394
 395                 return uplink_priv->post_act;
 396         }
 397
 398         return tc->post_act;
 399 }
 400
 401 struct mlx5_flow_handle *
 402 mlx5_tc_rule_insert(struct mlx5e_priv *priv,
 403                     struct mlx5_flow_spec *spec,
 404                     struct mlx5_flow_attr *attr)
 405 {
 406         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 407
 408         if (is_mdev_switchdev_mode(priv->mdev))
 409                 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
 410
 411         return  mlx5e_add_offloaded_nic_rule(priv, spec, attr);
 412 }
 413
 414 void
 415 mlx5_tc_rule_delete(struct mlx5e_priv *priv,
 416                     struct mlx5_flow_handle *rule,
 417                     struct mlx5_flow_attr *attr)
 418 {
 419         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 420
 421         if (is_mdev_switchdev_mode(priv->mdev)) {
 422                 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
 423                 return;
 424         }
 425
 426         mlx5e_del_offloaded_nic_rule(priv, rule, attr);
 427 }
 428
 429 static bool
 430 is_flow_meter_action(struct mlx5_flow_attr *attr)
 431 {
 432         return (((attr->action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
 433                  (attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)) ||
 434                 attr->flags & MLX5_ATTR_FLAG_MTU);
 435 }
 436
 437 static int
 438 mlx5e_tc_add_flow_meter(struct mlx5e_priv *priv,
 439                         struct mlx5_flow_attr *attr)
 440 {
 441         struct mlx5e_post_act *post_act = get_post_action(priv);
 442         struct mlx5e_post_meter_priv *post_meter;
 443         enum mlx5_flow_namespace_type ns_type;
 444         struct mlx5e_flow_meter_handle *meter;
 445         enum mlx5e_post_meter_type type;
 446
 447         meter = mlx5e_tc_meter_replace(priv->mdev, &attr->meter_attr.params);
 448         if (IS_ERR(meter)) {
 449                 mlx5_core_err(priv->mdev, "Failed to get flow meter\n");
 450                 return PTR_ERR(meter);
 451         }
 452
 453         ns_type = mlx5e_tc_meter_get_namespace(meter->flow_meters);
 454         type = meter->params.mtu ? MLX5E_POST_METER_MTU : MLX5E_POST_METER_RATE;
 455         post_meter = mlx5e_post_meter_init(priv, ns_type, post_act,
 456                                            type,
 457                                            meter->act_counter, meter->drop_counter,
 458                                            attr->branch_true, attr->branch_false);
 459         if (IS_ERR(post_meter)) {
 460                 mlx5_core_err(priv->mdev, "Failed to init post meter\n");
 461                 goto err_meter_init;
 462         }
 463
 464         attr->meter_attr.meter = meter;
 465         attr->meter_attr.post_meter = post_meter;
 466         attr->dest_ft = mlx5e_post_meter_get_ft(post_meter);
 467         attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
 468
 469         return 0;
 470
 471 err_meter_init:
 472         mlx5e_tc_meter_put(meter);
 473         return PTR_ERR(post_meter);
 474 }
 475
 476 static void
 477 mlx5e_tc_del_flow_meter(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
 478 {
 479         mlx5e_post_meter_cleanup(esw, attr->meter_attr.post_meter);
 480         mlx5e_tc_meter_put(attr->meter_attr.meter);
 481 }
 482
 483 struct mlx5_flow_handle *
 484 mlx5e_tc_rule_offload(struct mlx5e_priv *priv,
 485                       struct mlx5_flow_spec *spec,
 486                       struct mlx5_flow_attr *attr)
 487 {
 488         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 489         int err;
 490
 491         if (!is_mdev_switchdev_mode(priv->mdev))
 492                 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
 493
 494         if (attr->flags & MLX5_ATTR_FLAG_SAMPLE)
 495                 return mlx5e_tc_sample_offload(get_sample_priv(priv), spec, attr);
 496
 497         if (is_flow_meter_action(attr)) {
 498                 err = mlx5e_tc_add_flow_meter(priv, attr);
 499                 if (err)
 500                         return ERR_PTR(err);
 501         }
 502
 503         return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
 504 }
 505
 506 void
 507 mlx5e_tc_rule_unoffload(struct mlx5e_priv *priv,
 508                         struct mlx5_flow_handle *rule,
 509                         struct mlx5_flow_attr *attr)
 510 {
 511         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 512
 513         if (!is_mdev_switchdev_mode(priv->mdev)) {
 514                 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
 515                 return;
 516         }
 517
 518         if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
 519                 mlx5e_tc_sample_unoffload(get_sample_priv(priv), rule, attr);
 520                 return;
 521         }
 522
 523         mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
 524
 525         if (attr->meter_attr.meter)
 526                 mlx5e_tc_del_flow_meter(esw, attr);
 527 }
 528
 529 int
 530 mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
 531                           struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 532                           enum mlx5_flow_namespace_type ns,
 533                           enum mlx5e_tc_attr_to_reg type,
 534                           u32 data)
 535 {
 536         int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
 537
 538         return ret < 0 ? ret : 0;
 539 }
 540
 541 void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
 542                                           struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 543                                           enum mlx5e_tc_attr_to_reg type,
 544                                           int act_id, u32 data)
 545 {
 546         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 547         int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
 548         int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 549         char *modact;
 550
 551         modact = mlx5e_mod_hdr_get_item(mod_hdr_acts, act_id);
 552
 553         /* Firmware has 5bit length field and 0 means 32bits */
 554         if (mlen == 32)
 555                 mlen = 0;
 556
 557         MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
 558         MLX5_SET(set_action_in, modact, field, mfield);
 559         MLX5_SET(set_action_in, modact, offset, moffset);
 560         MLX5_SET(set_action_in, modact, length, mlen);
 561         MLX5_SET(set_action_in, modact, data, data);
 562 }
 563
 564 struct mlx5e_hairpin {
 565         struct mlx5_hairpin *pair;
 566
 567         struct mlx5_core_dev *func_mdev;
 568         struct mlx5e_priv *func_priv;
 569         u32 tdn;
 570         struct mlx5e_tir direct_tir;
 571
 572         int num_channels;
 573         u8 log_num_packets;
 574         struct mlx5e_rqt indir_rqt;
 575         struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
 576         struct mlx5_ttc_table *ttc;
 577 };
 578
 579 struct mlx5e_hairpin_entry {
 580         /* a node of a hash table which keeps all the  hairpin entries */
 581         struct hlist_node hairpin_hlist;
 582
 583         /* protects flows list */
 584         spinlock_t flows_lock;
 585         /* flows sharing the same hairpin */
 586         struct list_head flows;
 587         /* hpe's that were not fully initialized when dead peer update event
 588          * function traversed them.
 589          */
 590         struct list_head dead_peer_wait_list;
 591
 592         u16 peer_vhca_id;
 593         u8 prio;
 594         struct mlx5e_hairpin *hp;
 595         refcount_t refcnt;
 596         struct completion res_ready;
 597 };
 598
 599 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
 600                               struct mlx5e_tc_flow *flow);
 601
 602 struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
 603 {
 604         if (!flow || !refcount_inc_not_zero(&flow->refcnt))
 605                 return ERR_PTR(-EINVAL);
 606         return flow;
 607 }
 608
 609 void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
 610 {
 611         if (refcount_dec_and_test(&flow->refcnt)) {
 612                 mlx5e_tc_del_flow(priv, flow);
 613                 kfree_rcu(flow, rcu_head);
 614         }
 615 }
 616
 617 bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
 618 {
 619         return flow_flag_test(flow, ESWITCH);
 620 }
 621
 622 bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
 623 {
 624         return flow_flag_test(flow, FT);
 625 }
 626
 627 bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
 628 {
 629         return flow_flag_test(flow, OFFLOADED);
 630 }
 631
 632 int mlx5e_get_flow_namespace(struct mlx5e_tc_flow *flow)
 633 {
 634         return mlx5e_is_eswitch_flow(flow) ?
 635                 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
 636 }
 637
 638 static struct mlx5_core_dev *
 639 get_flow_counter_dev(struct mlx5e_tc_flow *flow)
 640 {
 641         return mlx5e_is_eswitch_flow(flow) ? flow->attr->esw_attr->counter_dev : flow->priv->mdev;
 642 }
 643
 644 static struct mod_hdr_tbl *
 645 get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
 646 {
 647         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 648         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 649
 650         return mlx5e_get_flow_namespace(flow) == MLX5_FLOW_NAMESPACE_FDB ?
 651                 &esw->offloads.mod_hdr :
 652                 &tc->mod_hdr;
 653 }
 654
 655 int mlx5e_tc_attach_mod_hdr(struct mlx5e_priv *priv,
 656                             struct mlx5e_tc_flow *flow,
 657                             struct mlx5_flow_attr *attr)
 658 {
 659         struct mlx5e_mod_hdr_handle *mh;
 660
 661         mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
 662                                   mlx5e_get_flow_namespace(flow),
 663                                   &attr->parse_attr->mod_hdr_acts);
 664         if (IS_ERR(mh))
 665                 return PTR_ERR(mh);
 666
 667         WARN_ON(attr->modify_hdr);
 668         attr->modify_hdr = mlx5e_mod_hdr_get(mh);
 669         attr->mh = mh;
 670
 671         return 0;
 672 }
 673
 674 void mlx5e_tc_detach_mod_hdr(struct mlx5e_priv *priv,
 675                              struct mlx5e_tc_flow *flow,
 676                              struct mlx5_flow_attr *attr)
 677 {
 678         /* flow wasn't fully initialized */
 679         if (!attr->mh)
 680                 return;
 681
 682         mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
 683                              attr->mh);
 684         attr->mh = NULL;
 685 }
 686
 687 static
 688 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
 689 {
 690         struct mlx5_core_dev *mdev;
 691         struct net_device *netdev;
 692         struct mlx5e_priv *priv;
 693
 694         netdev = dev_get_by_index(net, ifindex);
 695         if (!netdev)
 696                 return ERR_PTR(-ENODEV);
 697
 698         priv = netdev_priv(netdev);
 699         mdev = priv->mdev;
 700         dev_put(netdev);
 701
 702         /* Mirred tc action holds a refcount on the ifindex net_device (see
 703          * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
 704          * after dev_put(netdev), while we're in the context of adding a tc flow.
 705          *
 706          * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
 707          * stored in a hairpin object, which exists until all flows, that refer to it, get
 708          * removed.
 709          *
 710          * On the other hand, after a hairpin object has been created, the peer net_device may
 711          * be removed/unbound while there are still some hairpin flows that are using it. This
 712          * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
 713          * NETDEV_UNREGISTER event of the peer net_device.
 714          */
 715         return mdev;
 716 }
 717
 718 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
 719 {
 720         struct mlx5e_tir_builder *builder;
 721         int err;
 722
 723         builder = mlx5e_tir_builder_alloc(false);
 724         if (!builder)
 725                 return -ENOMEM;
 726
 727         err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
 728         if (err)
 729                 goto out;
 730
 731         mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
 732         err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
 733         if (err)
 734                 goto create_tir_err;
 735
 736 out:
 737         mlx5e_tir_builder_free(builder);
 738         return err;
 739
 740 create_tir_err:
 741         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 742
 743         goto out;
 744 }
 745
 746 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
 747 {
 748         mlx5e_tir_destroy(&hp->direct_tir);
 749         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 750 }
 751
 752 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
 753 {
 754         struct mlx5e_priv *priv = hp->func_priv;
 755         struct mlx5_core_dev *mdev = priv->mdev;
 756         struct mlx5e_rss_params_indir *indir;
 757         int err;
 758
 759         indir = kvmalloc(sizeof(*indir), GFP_KERNEL);
 760         if (!indir)
 761                 return -ENOMEM;
 762
 763         mlx5e_rss_params_indir_init_uniform(indir, hp->num_channels);
 764         err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
 765                                    mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
 766                                    indir);
 767
 768         kvfree(indir);
 769         return err;
 770 }
 771
 772 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
 773 {
 774         struct mlx5e_priv *priv = hp->func_priv;
 775         struct mlx5e_rss_params_hash rss_hash;
 776         enum mlx5_traffic_types tt, max_tt;
 777         struct mlx5e_tir_builder *builder;
 778         int err = 0;
 779
 780         builder = mlx5e_tir_builder_alloc(false);
 781         if (!builder)
 782                 return -ENOMEM;
 783
 784         rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
 785
 786         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
 787                 struct mlx5e_rss_params_traffic_type rss_tt;
 788
 789                 rss_tt = mlx5e_rss_get_default_tt_config(tt);
 790
 791                 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
 792                                             mlx5e_rqt_get_rqtn(&hp->indir_rqt),
 793                                             false);
 794                 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
 795
 796                 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
 797                 if (err) {
 798                         mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
 799                         goto err_destroy_tirs;
 800                 }
 801
 802                 mlx5e_tir_builder_clear(builder);
 803         }
 804
 805 out:
 806         mlx5e_tir_builder_free(builder);
 807         return err;
 808
 809 err_destroy_tirs:
 810         max_tt = tt;
 811         for (tt = 0; tt < max_tt; tt++)
 812                 mlx5e_tir_destroy(&hp->indir_tir[tt]);
 813
 814         goto out;
 815 }
 816
 817 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
 818 {
 819         int tt;
 820
 821         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 822                 mlx5e_tir_destroy(&hp->indir_tir[tt]);
 823 }
 824
 825 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
 826                                          struct ttc_params *ttc_params)
 827 {
 828         struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
 829         int tt;
 830
 831         memset(ttc_params, 0, sizeof(*ttc_params));
 832
 833         ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
 834                                                  MLX5_FLOW_NAMESPACE_KERNEL);
 835         for (tt = 0; tt < MLX5_NUM_TT; tt++) {
 836                 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
 837                 ttc_params->dests[tt].tir_num =
 838                         tt == MLX5_TT_ANY ?
 839                                 mlx5e_tir_get_tirn(&hp->direct_tir) :
 840                                 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
 841         }
 842
 843         ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
 844         ft_attr->prio = MLX5E_TC_PRIO;
 845 }
 846
 847 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
 848 {
 849         struct mlx5e_priv *priv = hp->func_priv;
 850         struct ttc_params ttc_params;
 851         struct mlx5_ttc_table *ttc;
 852         int err;
 853
 854         err = mlx5e_hairpin_create_indirect_rqt(hp);
 855         if (err)
 856                 return err;
 857
 858         err = mlx5e_hairpin_create_indirect_tirs(hp);
 859         if (err)
 860                 goto err_create_indirect_tirs;
 861
 862         mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
 863         hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
 864         if (IS_ERR(hp->ttc)) {
 865                 err = PTR_ERR(hp->ttc);
 866                 goto err_create_ttc_table;
 867         }
 868
 869         ttc = mlx5e_fs_get_ttc(priv->fs, false);
 870         netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
 871                    hp->num_channels,
 872                    mlx5_get_ttc_flow_table(ttc)->id);
 873
 874         return 0;
 875
 876 err_create_ttc_table:
 877         mlx5e_hairpin_destroy_indirect_tirs(hp);
 878 err_create_indirect_tirs:
 879         mlx5e_rqt_destroy(&hp->indir_rqt);
 880
 881         return err;
 882 }
 883
 884 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
 885 {
 886         mlx5_destroy_ttc_table(hp->ttc);
 887         mlx5e_hairpin_destroy_indirect_tirs(hp);
 888         mlx5e_rqt_destroy(&hp->indir_rqt);
 889 }
 890
 891 static struct mlx5e_hairpin *
 892 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
 893                      int peer_ifindex)
 894 {
 895         struct mlx5_core_dev *func_mdev, *peer_mdev;
 896         struct mlx5e_hairpin *hp;
 897         struct mlx5_hairpin *pair;
 898         int err;
 899
 900         hp = kzalloc(sizeof(*hp), GFP_KERNEL);
 901         if (!hp)
 902                 return ERR_PTR(-ENOMEM);
 903
 904         func_mdev = priv->mdev;
 905         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 906         if (IS_ERR(peer_mdev)) {
 907                 err = PTR_ERR(peer_mdev);
 908                 goto create_pair_err;
 909         }
 910
 911         pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
 912         if (IS_ERR(pair)) {
 913                 err = PTR_ERR(pair);
 914                 goto create_pair_err;
 915         }
 916         hp->pair = pair;
 917         hp->func_mdev = func_mdev;
 918         hp->func_priv = priv;
 919         hp->num_channels = params->num_channels;
 920         hp->log_num_packets = params->log_num_packets;
 921
 922         err = mlx5e_hairpin_create_transport(hp);
 923         if (err)
 924                 goto create_transport_err;
 925
 926         if (hp->num_channels > 1) {
 927                 err = mlx5e_hairpin_rss_init(hp);
 928                 if (err)
 929                         goto rss_init_err;
 930         }
 931
 932         return hp;
 933
 934 rss_init_err:
 935         mlx5e_hairpin_destroy_transport(hp);
 936 create_transport_err:
 937         mlx5_core_hairpin_destroy(hp->pair);
 938 create_pair_err:
 939         kfree(hp);
 940         return ERR_PTR(err);
 941 }
 942
 943 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
 944 {
 945         if (hp->num_channels > 1)
 946                 mlx5e_hairpin_rss_cleanup(hp);
 947         mlx5e_hairpin_destroy_transport(hp);
 948         mlx5_core_hairpin_destroy(hp->pair);
 949         kvfree(hp);
 950 }
 951
 952 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
 953 {
 954         return (peer_vhca_id << 16 | prio);
 955 }
 956
 957 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
 958                                                      u16 peer_vhca_id, u8 prio)
 959 {
 960         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 961         struct mlx5e_hairpin_entry *hpe;
 962         u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
 963
 964         hash_for_each_possible(tc->hairpin_tbl, hpe,
 965                                hairpin_hlist, hash_key) {
 966                 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
 967                         refcount_inc(&hpe->refcnt);
 968                         return hpe;
 969                 }
 970         }
 971
 972         return NULL;
 973 }
 974
 975 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
 976                               struct mlx5e_hairpin_entry *hpe)
 977 {
 978         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 979         /* no more hairpin flows for us, release the hairpin pair */
 980         if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &tc->hairpin_tbl_lock))
 981                 return;
 982         hash_del(&hpe->hairpin_hlist);
 983         mutex_unlock(&tc->hairpin_tbl_lock);
 984
 985         if (!IS_ERR_OR_NULL(hpe->hp)) {
 986                 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
 987                            dev_name(hpe->hp->pair->peer_mdev->device));
 988
 989                 mlx5e_hairpin_destroy(hpe->hp);
 990         }
 991
 992         WARN_ON(!list_empty(&hpe->flows));
 993         kfree(hpe);
 994 }
 995
 996 #define UNKNOWN_MATCH_PRIO 8
 997
 998 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
 999                                   struct mlx5_flow_spec *spec, u8 *match_prio,
1000                                   struct netlink_ext_ack *extack)
1001 {
1002         void *headers_c, *headers_v;
1003         u8 prio_val, prio_mask = 0;
1004         bool vlan_present;
1005
1006 #ifdef CONFIG_MLX5_CORE_EN_DCB
1007         if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
1008                 NL_SET_ERR_MSG_MOD(extack,
1009                                    "only PCP trust state supported for hairpin");
1010                 return -EOPNOTSUPP;
1011         }
1012 #endif
1013         headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
1014         headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1015
1016         vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
1017         if (vlan_present) {
1018                 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
1019                 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
1020         }
1021
1022         if (!vlan_present || !prio_mask) {
1023                 prio_val = UNKNOWN_MATCH_PRIO;
1024         } else if (prio_mask != 0x7) {
1025                 NL_SET_ERR_MSG_MOD(extack,
1026                                    "masked priority match not supported for hairpin");
1027                 return -EOPNOTSUPP;
1028         }
1029
1030         *match_prio = prio_val;
1031         return 0;
1032 }
1033
1034 static int debugfs_hairpin_num_active_get(void *data, u64 *val)
1035 {
1036         struct mlx5e_tc_table *tc = data;
1037         struct mlx5e_hairpin_entry *hpe;
1038         u32 cnt = 0;
1039         u32 bkt;
1040
1041         mutex_lock(&tc->hairpin_tbl_lock);
1042         hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
1043                 cnt++;
1044         mutex_unlock(&tc->hairpin_tbl_lock);
1045
1046         *val = cnt;
1047
1048         return 0;
1049 }
1050 DEFINE_DEBUGFS_ATTRIBUTE(fops_hairpin_num_active,
1051                          debugfs_hairpin_num_active_get, NULL, "%llu\n");
1052
1053 static int debugfs_hairpin_table_dump_show(struct seq_file *file, void *priv)
1054
1055 {
1056         struct mlx5e_tc_table *tc = file->private;
1057         struct mlx5e_hairpin_entry *hpe;
1058         u32 bkt;
1059
1060         mutex_lock(&tc->hairpin_tbl_lock);
1061         hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
1062                 seq_printf(file,
1063                            "Hairpin peer_vhca_id %u prio %u refcnt %u num_channels %u num_packets %lu\n",
1064                            hpe->peer_vhca_id, hpe->prio,
1065                            refcount_read(&hpe->refcnt), hpe->hp->num_channels,
1066                            BIT(hpe->hp->log_num_packets));
1067         mutex_unlock(&tc->hairpin_tbl_lock);
1068
1069         return 0;
1070 }
1071 DEFINE_SHOW_ATTRIBUTE(debugfs_hairpin_table_dump);
1072
1073 static void mlx5e_tc_debugfs_init(struct mlx5e_tc_table *tc,
1074                                   struct dentry *dfs_root)
1075 {
1076         if (IS_ERR_OR_NULL(dfs_root))
1077                 return;
1078
1079         tc->dfs_root = debugfs_create_dir("tc", dfs_root);
1080
1081         debugfs_create_file("hairpin_num_active", 0444, tc->dfs_root, tc,
1082                             &fops_hairpin_num_active);
1083         debugfs_create_file("hairpin_table_dump", 0444, tc->dfs_root, tc,
1084                             &debugfs_hairpin_table_dump_fops);
1085 }
1086
1087 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
1088                                   struct mlx5e_tc_flow *flow,
1089                                   struct mlx5e_tc_flow_parse_attr *parse_attr,
1090                                   struct netlink_ext_ack *extack)
1091 {
1092         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1093         struct devlink *devlink = priv_to_devlink(priv->mdev);
1094         int peer_ifindex = parse_attr->mirred_ifindex[0];
1095         union devlink_param_value val = {};
1096         struct mlx5_hairpin_params params;
1097         struct mlx5_core_dev *peer_mdev;
1098         struct mlx5e_hairpin_entry *hpe;
1099         struct mlx5e_hairpin *hp;
1100         u8 match_prio;
1101         u16 peer_id;
1102         int err;
1103
1104         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
1105         if (IS_ERR(peer_mdev)) {
1106                 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
1107                 return PTR_ERR(peer_mdev);
1108         }
1109
1110         if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
1111                 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
1112                 return -EOPNOTSUPP;
1113         }
1114
1115         peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
1116         err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
1117                                      extack);
1118         if (err)
1119                 return err;
1120
1121         mutex_lock(&tc->hairpin_tbl_lock);
1122         hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
1123         if (hpe) {
1124                 mutex_unlock(&tc->hairpin_tbl_lock);
1125                 wait_for_completion(&hpe->res_ready);
1126
1127                 if (IS_ERR(hpe->hp)) {
1128                         err = -EREMOTEIO;
1129                         goto out_err;
1130                 }
1131                 goto attach_flow;
1132         }
1133
1134         hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
1135         if (!hpe) {
1136                 mutex_unlock(&tc->hairpin_tbl_lock);
1137                 return -ENOMEM;
1138         }
1139
1140         spin_lock_init(&hpe->flows_lock);
1141         INIT_LIST_HEAD(&hpe->flows);
1142         INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
1143         hpe->peer_vhca_id = peer_id;
1144         hpe->prio = match_prio;
1145         refcount_set(&hpe->refcnt, 1);
1146         init_completion(&hpe->res_ready);
1147
1148         hash_add(tc->hairpin_tbl, &hpe->hairpin_hlist,
1149                  hash_hairpin_info(peer_id, match_prio));
1150         mutex_unlock(&tc->hairpin_tbl_lock);
1151
1152         err = devl_param_driverinit_value_get(
1153                 devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE, &val);
1154         if (err) {
1155                 err = -ENOMEM;
1156                 goto out_err;
1157         }
1158
1159         params.log_num_packets = ilog2(val.vu32);
1160         params.log_data_size =
1161                 clamp_t(u32,
1162                         params.log_num_packets +
1163                                 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev),
1164                         MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz),
1165                         MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
1166
1167         params.q_counter = priv->q_counter;
1168         err = devl_param_driverinit_value_get(
1169                 devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES, &val);
1170         if (err) {
1171                 err = -ENOMEM;
1172                 goto out_err;
1173         }
1174
1175         params.num_channels = val.vu32;
1176
1177         hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
1178         hpe->hp = hp;
1179         complete_all(&hpe->res_ready);
1180         if (IS_ERR(hp)) {
1181                 err = PTR_ERR(hp);
1182                 goto out_err;
1183         }
1184
1185         netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
1186                    mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
1187                    dev_name(hp->pair->peer_mdev->device),
1188                    hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
1189
1190 attach_flow:
1191         if (hpe->hp->num_channels > 1) {
1192                 flow_flag_set(flow, HAIRPIN_RSS);
1193                 flow->attr->nic_attr->hairpin_ft =
1194                         mlx5_get_ttc_flow_table(hpe->hp->ttc);
1195         } else {
1196                 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
1197         }
1198
1199         flow->hpe = hpe;
1200         spin_lock(&hpe->flows_lock);
1201         list_add(&flow->hairpin, &hpe->flows);
1202         spin_unlock(&hpe->flows_lock);
1203
1204         return 0;
1205
1206 out_err:
1207         mlx5e_hairpin_put(priv, hpe);
1208         return err;
1209 }
1210
1211 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
1212                                    struct mlx5e_tc_flow *flow)
1213 {
1214         /* flow wasn't fully initialized */
1215         if (!flow->hpe)
1216                 return;
1217
1218         spin_lock(&flow->hpe->flows_lock);
1219         list_del(&flow->hairpin);
1220         spin_unlock(&flow->hpe->flows_lock);
1221
1222         mlx5e_hairpin_put(priv, flow->hpe);
1223         flow->hpe = NULL;
1224 }
1225
1226 struct mlx5_flow_handle *
1227 mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
1228                              struct mlx5_flow_spec *spec,
1229                              struct mlx5_flow_attr *attr)
1230 {
1231         struct mlx5_flow_context *flow_context = &spec->flow_context;
1232         struct mlx5e_vlan_table *vlan = mlx5e_fs_get_vlan(priv->fs);
1233         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1234         struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
1235         struct mlx5_flow_destination dest[2] = {};
1236         struct mlx5_fs_chains *nic_chains;
1237         struct mlx5_flow_act flow_act = {
1238                 .action = attr->action,
1239                 .flags    = FLOW_ACT_NO_APPEND,
1240         };
1241         struct mlx5_flow_handle *rule;
1242         struct mlx5_flow_table *ft;
1243         int dest_ix = 0;
1244
1245         nic_chains = mlx5e_nic_chains(tc);
1246         flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1247         flow_context->flow_tag = nic_attr->flow_tag;
1248
1249         if (attr->dest_ft) {
1250                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1251                 dest[dest_ix].ft = attr->dest_ft;
1252                 dest_ix++;
1253         } else if (nic_attr->hairpin_ft) {
1254                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1255                 dest[dest_ix].ft = nic_attr->hairpin_ft;
1256                 dest_ix++;
1257         } else if (nic_attr->hairpin_tirn) {
1258                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1259                 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
1260                 dest_ix++;
1261         } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1262                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1263                 if (attr->dest_chain) {
1264                         dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
1265                                                                  attr->dest_chain, 1,
1266                                                                  MLX5E_TC_FT_LEVEL);
1267                         if (IS_ERR(dest[dest_ix].ft))
1268                                 return ERR_CAST(dest[dest_ix].ft);
1269                 } else {
1270                         dest[dest_ix].ft = mlx5e_vlan_get_flowtable(vlan);
1271                 }
1272                 dest_ix++;
1273         }
1274
1275         if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
1276             MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
1277                 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
1278
1279         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1280                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
1281                 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
1282                 dest_ix++;
1283         }
1284
1285         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1286                 flow_act.modify_hdr = attr->modify_hdr;
1287
1288         mutex_lock(&tc->t_lock);
1289         if (IS_ERR_OR_NULL(tc->t)) {
1290                 /* Create the root table here if doesn't exist yet */
1291                 tc->t =
1292                         mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
1293
1294                 if (IS_ERR(tc->t)) {
1295                         mutex_unlock(&tc->t_lock);
1296                         netdev_err(priv->netdev,
1297                                    "Failed to create tc offload table\n");
1298                         rule = ERR_CAST(tc->t);
1299                         goto err_ft_get;
1300                 }
1301         }
1302         mutex_unlock(&tc->t_lock);
1303
1304         if (attr->chain || attr->prio)
1305                 ft = mlx5_chains_get_table(nic_chains,
1306                                            attr->chain, attr->prio,
1307                                            MLX5E_TC_FT_LEVEL);
1308         else
1309                 ft = attr->ft;
1310
1311         if (IS_ERR(ft)) {
1312                 rule = ERR_CAST(ft);
1313                 goto err_ft_get;
1314         }
1315
1316         if (attr->outer_match_level != MLX5_MATCH_NONE)
1317                 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
1318
1319         rule = mlx5_add_flow_rules(ft, spec,
1320                                    &flow_act, dest, dest_ix);
1321         if (IS_ERR(rule))
1322                 goto err_rule;
1323
1324         return rule;
1325
1326 err_rule:
1327         if (attr->chain || attr->prio)
1328                 mlx5_chains_put_table(nic_chains,
1329                                       attr->chain, attr->prio,
1330                                       MLX5E_TC_FT_LEVEL);
1331 err_ft_get:
1332         if (attr->dest_chain)
1333                 mlx5_chains_put_table(nic_chains,
1334                                       attr->dest_chain, 1,
1335                                       MLX5E_TC_FT_LEVEL);
1336
1337         return ERR_CAST(rule);
1338 }
1339
1340 static int
1341 alloc_flow_attr_counter(struct mlx5_core_dev *counter_dev,
1342                         struct mlx5_flow_attr *attr)
1343
1344 {
1345         struct mlx5_fc *counter;
1346
1347         counter = mlx5_fc_create(counter_dev, true);
1348         if (IS_ERR(counter))
1349                 return PTR_ERR(counter);
1350
1351         attr->counter = counter;
1352         return 0;
1353 }
1354
1355 static int
1356 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1357                       struct mlx5e_tc_flow *flow,
1358                       struct netlink_ext_ack *extack)
1359 {
1360         struct mlx5e_tc_flow_parse_attr *parse_attr;
1361         struct mlx5_flow_attr *attr = flow->attr;
1362         struct mlx5_core_dev *dev = priv->mdev;
1363         int err;
1364
1365         parse_attr = attr->parse_attr;
1366
1367         if (flow_flag_test(flow, HAIRPIN)) {
1368                 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1369                 if (err)
1370                         return err;
1371         }
1372
1373         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1374                 err = alloc_flow_attr_counter(dev, attr);
1375                 if (err)
1376                         return err;
1377         }
1378
1379         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1380                 err = mlx5e_tc_attach_mod_hdr(priv, flow, attr);
1381                 if (err)
1382                         return err;
1383         }
1384
1385         flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec, attr);
1386         return PTR_ERR_OR_ZERO(flow->rule[0]);
1387 }
1388
1389 void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
1390                                   struct mlx5_flow_handle *rule,
1391                                   struct mlx5_flow_attr *attr)
1392 {
1393         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1394         struct mlx5_fs_chains *nic_chains;
1395
1396         nic_chains = mlx5e_nic_chains(tc);
1397         mlx5_del_flow_rules(rule);
1398
1399         if (attr->chain || attr->prio)
1400                 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1401                                       MLX5E_TC_FT_LEVEL);
1402
1403         if (attr->dest_chain)
1404                 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1405                                       MLX5E_TC_FT_LEVEL);
1406 }
1407
1408 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1409                                   struct mlx5e_tc_flow *flow)
1410 {
1411         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1412         struct mlx5_flow_attr *attr = flow->attr;
1413
1414         flow_flag_clear(flow, OFFLOADED);
1415
1416         if (!IS_ERR_OR_NULL(flow->rule[0]))
1417                 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1418
1419         /* Remove root table if no rules are left to avoid
1420          * extra steering hops.
1421          */
1422         mutex_lock(&tc->t_lock);
1423         if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1424             !IS_ERR_OR_NULL(tc->t)) {
1425                 mlx5_chains_put_table(mlx5e_nic_chains(tc), 0, 1, MLX5E_TC_FT_LEVEL);
1426                 tc->t = NULL;
1427         }
1428         mutex_unlock(&tc->t_lock);
1429
1430         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1431                 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
1432                 mlx5e_tc_detach_mod_hdr(priv, flow, attr);
1433         }
1434
1435         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1436                 mlx5_fc_destroy(priv->mdev, attr->counter);
1437
1438         if (flow_flag_test(flow, HAIRPIN))
1439                 mlx5e_hairpin_flow_del(priv, flow);
1440
1441         free_flow_post_acts(flow);
1442
1443         kvfree(attr->parse_attr);
1444         kfree(flow->attr);
1445 }
1446
1447 struct mlx5_flow_handle *
1448 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1449                            struct mlx5e_tc_flow *flow,
1450                            struct mlx5_flow_spec *spec,
1451                            struct mlx5_flow_attr *attr)
1452 {
1453         struct mlx5_flow_handle *rule;
1454
1455         if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
1456                 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1457
1458         rule = mlx5e_tc_rule_offload(flow->priv, spec, attr);
1459
1460         if (IS_ERR(rule))
1461                 return rule;
1462
1463         if (attr->esw_attr->split_count) {
1464                 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1465                 if (IS_ERR(flow->rule[1]))
1466                         goto err_rule1;
1467         }
1468
1469         return rule;
1470
1471 err_rule1:
1472         mlx5e_tc_rule_unoffload(flow->priv, rule, attr);
1473         return flow->rule[1];
1474 }
1475
1476 void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1477                                   struct mlx5e_tc_flow *flow,
1478                                   struct mlx5_flow_attr *attr)
1479 {
1480         flow_flag_clear(flow, OFFLOADED);
1481
1482         if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
1483                 return mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1484
1485         if (attr->esw_attr->split_count)
1486                 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1487
1488         mlx5e_tc_rule_unoffload(flow->priv, flow->rule[0], attr);
1489 }
1490
1491 struct mlx5_flow_handle *
1492 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1493                               struct mlx5e_tc_flow *flow,
1494                               struct mlx5_flow_spec *spec)
1495 {
1496         struct mlx5e_tc_mod_hdr_acts mod_acts = {};
1497         struct mlx5e_mod_hdr_handle *mh = NULL;
1498         struct mlx5_flow_attr *slow_attr;
1499         struct mlx5_flow_handle *rule;
1500         bool fwd_and_modify_cap;
1501         u32 chain_mapping = 0;
1502         int err;
1503
1504         slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1505         if (!slow_attr)
1506                 return ERR_PTR(-ENOMEM);
1507
1508         memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1509         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1510         slow_attr->esw_attr->split_count = 0;
1511         slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
1512
1513         fwd_and_modify_cap = MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table);
1514         if (!fwd_and_modify_cap)
1515                 goto skip_restore;
1516
1517         err = mlx5_chains_get_chain_mapping(esw_chains(esw), flow->attr->chain, &chain_mapping);
1518         if (err)
1519                 goto err_get_chain;
1520
1521         err = mlx5e_tc_match_to_reg_set(esw->dev, &mod_acts, MLX5_FLOW_NAMESPACE_FDB,
1522                                         MAPPED_OBJ_TO_REG, chain_mapping);
1523         if (err)
1524                 goto err_reg_set;
1525
1526         mh = mlx5e_mod_hdr_attach(esw->dev, get_mod_hdr_table(flow->priv, flow),
1527                                   MLX5_FLOW_NAMESPACE_FDB, &mod_acts);
1528         if (IS_ERR(mh)) {
1529                 err = PTR_ERR(mh);
1530                 goto err_attach;
1531         }
1532
1533         slow_attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1534         slow_attr->modify_hdr = mlx5e_mod_hdr_get(mh);
1535
1536 skip_restore:
1537         rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1538         if (IS_ERR(rule)) {
1539                 err = PTR_ERR(rule);
1540                 goto err_offload;
1541         }
1542
1543         flow->attr->slow_mh = mh;
1544         flow->chain_mapping = chain_mapping;
1545         flow_flag_set(flow, SLOW);
1546
1547         mlx5e_mod_hdr_dealloc(&mod_acts);
1548         kfree(slow_attr);
1549
1550         return rule;
1551
1552 err_offload:
1553         if (fwd_and_modify_cap)
1554                 mlx5e_mod_hdr_detach(esw->dev, get_mod_hdr_table(flow->priv, flow), mh);
1555 err_attach:
1556 err_reg_set:
1557         if (fwd_and_modify_cap)
1558                 mlx5_chains_put_chain_mapping(esw_chains(esw), chain_mapping);
1559 err_get_chain:
1560         mlx5e_mod_hdr_dealloc(&mod_acts);
1561         kfree(slow_attr);
1562         return ERR_PTR(err);
1563 }
1564
1565 void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1566                                        struct mlx5e_tc_flow *flow)
1567 {
1568         struct mlx5e_mod_hdr_handle *slow_mh = flow->attr->slow_mh;
1569         struct mlx5_flow_attr *slow_attr;
1570
1571         slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1572         if (!slow_attr) {
1573                 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1574                 return;
1575         }
1576
1577         memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1578         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1579         slow_attr->esw_attr->split_count = 0;
1580         slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
1581         if (slow_mh) {
1582                 slow_attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1583                 slow_attr->modify_hdr = mlx5e_mod_hdr_get(slow_mh);
1584         }
1585         mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
1586         if (slow_mh) {
1587                 mlx5e_mod_hdr_detach(esw->dev, get_mod_hdr_table(flow->priv, flow), slow_mh);
1588                 mlx5_chains_put_chain_mapping(esw_chains(esw), flow->chain_mapping);
1589                 flow->chain_mapping = 0;
1590                 flow->attr->slow_mh = NULL;
1591         }
1592         flow_flag_clear(flow, SLOW);
1593         kfree(slow_attr);
1594 }
1595
1596 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1597  * function.
1598  */
1599 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1600                              struct list_head *unready_flows)
1601 {
1602         flow_flag_set(flow, NOT_READY);
1603         list_add_tail(&flow->unready, unready_flows);
1604 }
1605
1606 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1607  * function.
1608  */
1609 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1610 {
1611         list_del(&flow->unready);
1612         flow_flag_clear(flow, NOT_READY);
1613 }
1614
1615 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1616 {
1617         struct mlx5_rep_uplink_priv *uplink_priv;
1618         struct mlx5e_rep_priv *rpriv;
1619         struct mlx5_eswitch *esw;
1620
1621         esw = flow->priv->mdev->priv.eswitch;
1622         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1623         uplink_priv = &rpriv->uplink_priv;
1624
1625         mutex_lock(&uplink_priv->unready_flows_lock);
1626         unready_flow_add(flow, &uplink_priv->unready_flows);
1627         mutex_unlock(&uplink_priv->unready_flows_lock);
1628 }
1629
1630 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1631 {
1632         struct mlx5_rep_uplink_priv *uplink_priv;
1633         struct mlx5e_rep_priv *rpriv;
1634         struct mlx5_eswitch *esw;
1635
1636         esw = flow->priv->mdev->priv.eswitch;
1637         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1638         uplink_priv = &rpriv->uplink_priv;
1639
1640         mutex_lock(&uplink_priv->unready_flows_lock);
1641         unready_flow_del(flow);
1642         mutex_unlock(&uplink_priv->unready_flows_lock);
1643 }
1644
1645 bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
1646 {
1647         struct mlx5_core_dev *out_mdev, *route_mdev;
1648         struct mlx5e_priv *out_priv, *route_priv;
1649
1650         out_priv = netdev_priv(out_dev);
1651         out_mdev = out_priv->mdev;
1652         route_priv = netdev_priv(route_dev);
1653         route_mdev = route_priv->mdev;
1654
1655         if (out_mdev->coredev_type != MLX5_COREDEV_PF)
1656                 return false;
1657
1658         if (route_mdev->coredev_type != MLX5_COREDEV_VF &&
1659             route_mdev->coredev_type != MLX5_COREDEV_SF)
1660                 return false;
1661
1662         return mlx5e_same_hw_devs(out_priv, route_priv);
1663 }
1664
1665 int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
1666 {
1667         struct mlx5e_priv *out_priv, *route_priv;
1668         struct mlx5_core_dev *route_mdev;
1669         struct mlx5_devcom *devcom;
1670         struct mlx5_eswitch *esw;
1671         u16 vhca_id;
1672         int err;
1673         int i;
1674
1675         out_priv = netdev_priv(out_dev);
1676         esw = out_priv->mdev->priv.eswitch;
1677         route_priv = netdev_priv(route_dev);
1678         route_mdev = route_priv->mdev;
1679
1680         vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1681         err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1682         if (!err)
1683                 return err;
1684
1685         if (!mlx5_lag_is_active(out_priv->mdev))
1686                 return err;
1687
1688         rcu_read_lock();
1689         devcom = out_priv->mdev->priv.devcom;
1690         err = -ENODEV;
1691         mlx5_devcom_for_each_peer_entry_rcu(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
1692                                             esw, i) {
1693                 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1694                 if (!err)
1695                         break;
1696         }
1697         rcu_read_unlock();
1698
1699         return err;
1700 }
1701
1702 static int
1703 verify_attr_actions(u32 actions, struct netlink_ext_ack *extack)
1704 {
1705         if (!(actions &
1706               (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
1707                 NL_SET_ERR_MSG_MOD(extack, "Rule must have at least one forward/drop action");
1708                 return -EOPNOTSUPP;
1709         }
1710
1711         if (!(~actions &
1712               (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
1713                 NL_SET_ERR_MSG_MOD(extack, "Rule cannot support forward+drop action");
1714                 return -EOPNOTSUPP;
1715         }
1716
1717         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1718             actions & MLX5_FLOW_CONTEXT_ACTION_DROP) {
1719                 NL_SET_ERR_MSG_MOD(extack, "Drop with modify header action is not supported");
1720                 return -EOPNOTSUPP;
1721         }
1722
1723         return 0;
1724 }
1725
1726 static int
1727 post_process_attr(struct mlx5e_tc_flow *flow,
1728                   struct mlx5_flow_attr *attr,
1729                   struct netlink_ext_ack *extack)
1730 {
1731         bool vf_tun;
1732         int err = 0;
1733
1734         err = verify_attr_actions(attr->action, extack);
1735         if (err)
1736                 goto err_out;
1737
1738         err = mlx5e_tc_tun_encap_dests_set(flow->priv, flow, attr, extack, &vf_tun);
1739         if (err)
1740                 goto err_out;
1741
1742         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1743                 err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr);
1744                 if (err)
1745                         goto err_out;
1746         }
1747
1748         if (attr->branch_true &&
1749             attr->branch_true->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1750                 err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr->branch_true);
1751                 if (err)
1752                         goto err_out;
1753         }
1754
1755         if (attr->branch_false &&
1756             attr->branch_false->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1757                 err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr->branch_false);
1758                 if (err)
1759                         goto err_out;
1760         }
1761
1762         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1763                 err = alloc_flow_attr_counter(get_flow_counter_dev(flow), attr);
1764                 if (err)
1765                         goto err_out;
1766         }
1767
1768 err_out:
1769         return err;
1770 }
1771
1772 static int
1773 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1774                       struct mlx5e_tc_flow *flow,
1775                       struct netlink_ext_ack *extack)
1776 {
1777         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1778         struct mlx5e_tc_flow_parse_attr *parse_attr;
1779         struct mlx5_flow_attr *attr = flow->attr;
1780         struct mlx5_esw_flow_attr *esw_attr;
1781         u32 max_prio, max_chain;
1782         int err = 0;
1783
1784         parse_attr = attr->parse_attr;
1785         esw_attr = attr->esw_attr;
1786
1787         /* We check chain range only for tc flows.
1788          * For ft flows, we checked attr->chain was originally 0 and set it to
1789          * FDB_FT_CHAIN which is outside tc range.
1790          * See mlx5e_rep_setup_ft_cb().
1791          */
1792         max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
1793         if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
1794                 NL_SET_ERR_MSG_MOD(extack,
1795                                    "Requested chain is out of supported range");
1796                 err = -EOPNOTSUPP;
1797                 goto err_out;
1798         }
1799
1800         max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
1801         if (attr->prio > max_prio) {
1802                 NL_SET_ERR_MSG_MOD(extack,
1803                                    "Requested priority is out of supported range");
1804                 err = -EOPNOTSUPP;
1805                 goto err_out;
1806         }
1807
1808         if (flow_flag_test(flow, TUN_RX)) {
1809                 err = mlx5e_attach_decap_route(priv, flow);
1810                 if (err)
1811                         goto err_out;
1812
1813                 if (!attr->chain && esw_attr->int_port &&
1814                     attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1815                         /* If decap route device is internal port, change the
1816                          * source vport value in reg_c0 back to uplink just in
1817                          * case the rule performs goto chain > 0. If we have a miss
1818                          * on chain > 0 we want the metadata regs to hold the
1819                          * chain id so SW will resume handling of this packet
1820                          * from the proper chain.
1821                          */
1822                         u32 metadata = mlx5_eswitch_get_vport_metadata_for_set(esw,
1823                                                                         esw_attr->in_rep->vport);
1824
1825                         err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
1826                                                         MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
1827                                                         metadata);
1828                         if (err)
1829                                 goto err_out;
1830
1831                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1832                 }
1833         }
1834
1835         if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1836                 err = mlx5e_attach_decap(priv, flow, extack);
1837                 if (err)
1838                         goto err_out;
1839         }
1840
1841         if (netif_is_ovs_master(parse_attr->filter_dev)) {
1842                 struct mlx5e_tc_int_port *int_port;
1843
1844                 if (attr->chain) {
1845                         NL_SET_ERR_MSG_MOD(extack,
1846                                            "Internal port rule is only supported on chain 0");
1847                         err = -EOPNOTSUPP;
1848                         goto err_out;
1849                 }
1850
1851                 if (attr->dest_chain) {
1852                         NL_SET_ERR_MSG_MOD(extack,
1853                                            "Internal port rule offload doesn't support goto action");
1854                         err = -EOPNOTSUPP;
1855                         goto err_out;
1856                 }
1857
1858                 int_port = mlx5e_tc_int_port_get(mlx5e_get_int_port_priv(priv),
1859                                                  parse_attr->filter_dev->ifindex,
1860                                                  flow_flag_test(flow, EGRESS) ?
1861                                                  MLX5E_TC_INT_PORT_EGRESS :
1862                                                  MLX5E_TC_INT_PORT_INGRESS);
1863                 if (IS_ERR(int_port)) {
1864                         err = PTR_ERR(int_port);
1865                         goto err_out;
1866                 }
1867
1868                 esw_attr->int_port = int_port;
1869         }
1870
1871         err = post_process_attr(flow, attr, extack);
1872         if (err)
1873                 goto err_out;
1874
1875         err = mlx5e_tc_act_stats_add_flow(get_act_stats_handle(priv), flow);
1876         if (err)
1877                 goto err_out;
1878
1879         /* we get here if one of the following takes place:
1880          * (1) there's no error
1881          * (2) there's an encap action and we don't have valid neigh
1882          */
1883         if (flow_flag_test(flow, SLOW))
1884                 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
1885         else
1886                 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
1887
1888         if (IS_ERR(flow->rule[0])) {
1889                 err = PTR_ERR(flow->rule[0]);
1890                 goto err_out;
1891         }
1892         flow_flag_set(flow, OFFLOADED);
1893
1894         return 0;
1895
1896 err_out:
1897         flow_flag_set(flow, FAILED);
1898         return err;
1899 }
1900
1901 static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1902 {
1903         struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
1904         void *headers_v = MLX5_ADDR_OF(fte_match_param,
1905                                        spec->match_value,
1906                                        misc_parameters_3);
1907         u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1908                                              headers_v,
1909                                              geneve_tlv_option_0_data);
1910
1911         return !!geneve_tlv_opt_0_data;
1912 }
1913
1914 static void free_branch_attr(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
1915 {
1916         if (!attr)
1917                 return;
1918
1919         mlx5_free_flow_attr_actions(flow, attr);
1920         kvfree(attr->parse_attr);
1921         kfree(attr);
1922 }
1923
1924 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1925                                   struct mlx5e_tc_flow *flow)
1926 {
1927         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1928         struct mlx5_flow_attr *attr = flow->attr;
1929         struct mlx5_esw_flow_attr *esw_attr;
1930
1931         esw_attr = attr->esw_attr;
1932         mlx5e_put_flow_tunnel_id(flow);
1933
1934         if (flow_flag_test(flow, NOT_READY))
1935                 remove_unready_flow(flow);
1936
1937         if (mlx5e_is_offloaded_flow(flow)) {
1938                 if (flow_flag_test(flow, SLOW))
1939                         mlx5e_tc_unoffload_from_slow_path(esw, flow);
1940                 else
1941                         mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1942         }
1943         complete_all(&flow->del_hw_done);
1944
1945         if (mlx5_flow_has_geneve_opt(flow))
1946                 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1947
1948         if (flow->decap_route)
1949                 mlx5e_detach_decap_route(priv, flow);
1950
1951         mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
1952
1953         if (esw_attr->int_port)
1954                 mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(priv), esw_attr->int_port);
1955
1956         if (esw_attr->dest_int_port)
1957                 mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(priv), esw_attr->dest_int_port);
1958
1959         if (flow_flag_test(flow, L3_TO_L2_DECAP))
1960                 mlx5e_detach_decap(priv, flow);
1961
1962         mlx5e_tc_act_stats_del_flow(get_act_stats_handle(priv), flow);
1963
1964         free_flow_post_acts(flow);
1965         mlx5_free_flow_attr_actions(flow, attr);
1966
1967         kvfree(attr->esw_attr->rx_tun_attr);
1968         kvfree(attr->parse_attr);
1969         kfree(flow->attr);
1970 }
1971
1972 struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1973 {
1974         struct mlx5_flow_attr *attr;
1975
1976         attr = list_first_entry(&flow->attrs, struct mlx5_flow_attr, list);
1977         return attr->counter;
1978 }
1979
1980 /* Iterate over tmp_list of flows attached to flow_list head. */
1981 void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
1982 {
1983         struct mlx5e_tc_flow *flow, *tmp;
1984
1985         list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1986                 mlx5e_flow_put(priv, flow);
1987 }
1988
1989 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow,
1990                                        int peer_index)
1991 {
1992         struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1993         struct mlx5e_tc_flow *peer_flow;
1994         struct mlx5e_tc_flow *tmp;
1995
1996         if (!flow_flag_test(flow, ESWITCH) ||
1997             !flow_flag_test(flow, DUP))
1998                 return;
1999
2000         mutex_lock(&esw->offloads.peer_mutex);
2001         list_del(&flow->peer[peer_index]);
2002         mutex_unlock(&esw->offloads.peer_mutex);
2003
2004         list_for_each_entry_safe(peer_flow, tmp, &flow->peer_flows, peer_flows) {
2005                 if (peer_index != mlx5_get_dev_index(peer_flow->priv->mdev))
2006                         continue;
2007                 if (refcount_dec_and_test(&peer_flow->refcnt)) {
2008                         mlx5e_tc_del_fdb_flow(peer_flow->priv, peer_flow);
2009                         list_del(&peer_flow->peer_flows);
2010                         kfree(peer_flow);
2011                 }
2012         }
2013
2014         if (list_empty(&flow->peer_flows))
2015                 flow_flag_clear(flow, DUP);
2016 }
2017
2018 static void mlx5e_tc_del_fdb_peers_flow(struct mlx5e_tc_flow *flow)
2019 {
2020         int i;
2021
2022         for (i = 0; i < MLX5_MAX_PORTS; i++) {
2023                 if (i == mlx5_get_dev_index(flow->priv->mdev))
2024                         continue;
2025                 mlx5e_tc_del_fdb_peer_flow(flow, i);
2026         }
2027 }
2028
2029 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
2030                               struct mlx5e_tc_flow *flow)
2031 {
2032         if (mlx5e_is_eswitch_flow(flow)) {
2033                 struct mlx5_devcom *devcom = flow->priv->mdev->priv.devcom;
2034
2035                 if (!mlx5_devcom_for_each_peer_begin(devcom, MLX5_DEVCOM_ESW_OFFLOADS)) {
2036                         mlx5e_tc_del_fdb_flow(priv, flow);
2037                         return;
2038                 }
2039
2040                 mlx5e_tc_del_fdb_peers_flow(flow);
2041                 mlx5_devcom_for_each_peer_end(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2042                 mlx5e_tc_del_fdb_flow(priv, flow);
2043         } else {
2044                 mlx5e_tc_del_nic_flow(priv, flow);
2045         }
2046 }
2047
2048 static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
2049 {
2050         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2051         struct flow_action *flow_action = &rule->action;
2052         const struct flow_action_entry *act;
2053         int i;
2054
2055         if (chain)
2056                 return false;
2057
2058         flow_action_for_each(i, act, flow_action) {
2059                 switch (act->id) {
2060                 case FLOW_ACTION_GOTO:
2061                         return true;
2062                 case FLOW_ACTION_SAMPLE:
2063                         return true;
2064                 default:
2065                         continue;
2066                 }
2067         }
2068
2069         return false;
2070 }
2071
2072 static int
2073 enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
2074                                     struct flow_dissector_key_enc_opts *opts,
2075                                     struct netlink_ext_ack *extack,
2076                                     bool *dont_care)
2077 {
2078         struct geneve_opt *opt;
2079         int off = 0;
2080
2081         *dont_care = true;
2082
2083         while (opts->len > off) {
2084                 opt = (struct geneve_opt *)&opts->data[off];
2085
2086                 if (!(*dont_care) || opt->opt_class || opt->type ||
2087                     memchr_inv(opt->opt_data, 0, opt->length * 4)) {
2088                         *dont_care = false;
2089
2090                         if (opt->opt_class != htons(U16_MAX) ||
2091                             opt->type != U8_MAX) {
2092                                 NL_SET_ERR_MSG_MOD(extack,
2093                                                    "Partial match of tunnel options in chain > 0 isn't supported");
2094                                 netdev_warn(priv->netdev,
2095                                             "Partial match of tunnel options in chain > 0 isn't supported");
2096                                 return -EOPNOTSUPP;
2097                         }
2098                 }
2099
2100                 off += sizeof(struct geneve_opt) + opt->length * 4;
2101         }
2102
2103         return 0;
2104 }
2105
2106 #define COPY_DISSECTOR(rule, diss_key, dst)\
2107 ({ \
2108         struct flow_rule *__rule = (rule);\
2109         typeof(dst) __dst = dst;\
2110 \
2111         memcpy(__dst,\
2112                skb_flow_dissector_target(__rule->match.dissector,\
2113                                          diss_key,\
2114                                          __rule->match.key),\
2115                sizeof(*__dst));\
2116 })
2117
2118 static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
2119                                     struct mlx5e_tc_flow *flow,
2120                                     struct flow_cls_offload *f,
2121                                     struct net_device *filter_dev)
2122 {
2123         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2124         struct netlink_ext_ack *extack = f->common.extack;
2125         struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
2126         struct flow_match_enc_opts enc_opts_match;
2127         struct tunnel_match_enc_opts tun_enc_opts;
2128         struct mlx5_rep_uplink_priv *uplink_priv;
2129         struct mlx5_flow_attr *attr = flow->attr;
2130         struct mlx5e_rep_priv *uplink_rpriv;
2131         struct tunnel_match_key tunnel_key;
2132         bool enc_opts_is_dont_care = true;
2133         u32 tun_id, enc_opts_id = 0;
2134         struct mlx5_eswitch *esw;
2135         u32 value, mask;
2136         int err;
2137
2138         esw = priv->mdev->priv.eswitch;
2139         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2140         uplink_priv = &uplink_rpriv->uplink_priv;
2141
2142         memset(&tunnel_key, 0, sizeof(tunnel_key));
2143         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
2144                        &tunnel_key.enc_control);
2145         if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
2146                 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
2147                                &tunnel_key.enc_ipv4);
2148         else
2149                 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
2150                                &tunnel_key.enc_ipv6);
2151         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
2152         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
2153                        &tunnel_key.enc_tp);
2154         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
2155                        &tunnel_key.enc_key_id);
2156         tunnel_key.filter_ifindex = filter_dev->ifindex;
2157
2158         err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
2159         if (err)
2160                 return err;
2161
2162         flow_rule_match_enc_opts(rule, &enc_opts_match);
2163         err = enc_opts_is_dont_care_or_full_match(priv,
2164                                                   enc_opts_match.mask,
2165                                                   extack,
2166                                                   &enc_opts_is_dont_care);
2167         if (err)
2168                 goto err_enc_opts;
2169
2170         if (!enc_opts_is_dont_care) {
2171                 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
2172                 memcpy(&tun_enc_opts.key, enc_opts_match.key,
2173                        sizeof(*enc_opts_match.key));
2174                 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
2175                        sizeof(*enc_opts_match.mask));
2176
2177                 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
2178                                   &tun_enc_opts, &enc_opts_id);
2179                 if (err)
2180                         goto err_enc_opts;
2181         }
2182
2183         value = tun_id << ENC_OPTS_BITS | enc_opts_id;
2184         mask = enc_opts_id ? TUNNEL_ID_MASK :
2185                              (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
2186
2187         if (attr->chain) {
2188                 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
2189                                             TUNNEL_TO_REG, value, mask);
2190         } else {
2191                 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
2192                 err = mlx5e_tc_match_to_reg_set(priv->mdev,
2193                                                 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
2194                                                 TUNNEL_TO_REG, value);
2195                 if (err)
2196                         goto err_set;
2197
2198                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2199         }
2200
2201         flow->attr->tunnel_id = value;
2202         return 0;
2203
2204 err_set:
2205         if (enc_opts_id)
2206                 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2207                                enc_opts_id);
2208 err_enc_opts:
2209         mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2210         return err;
2211 }
2212
2213 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
2214 {
2215         u32 enc_opts_id = flow->attr->tunnel_id & ENC_OPTS_BITS_MASK;
2216         u32 tun_id = flow->attr->tunnel_id >> ENC_OPTS_BITS;
2217         struct mlx5_rep_uplink_priv *uplink_priv;
2218         struct mlx5e_rep_priv *uplink_rpriv;
2219         struct mlx5_eswitch *esw;
2220
2221         esw = flow->priv->mdev->priv.eswitch;
2222         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2223         uplink_priv = &uplink_rpriv->uplink_priv;
2224
2225         if (tun_id)
2226                 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2227         if (enc_opts_id)
2228                 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2229                                enc_opts_id);
2230 }
2231
2232 void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
2233                             struct flow_match_basic *match, bool outer,
2234                             void *headers_c, void *headers_v)
2235 {
2236         bool ip_version_cap;
2237
2238         ip_version_cap = outer ?
2239                 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2240                                           ft_field_support.outer_ip_version) :
2241                 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2242                                           ft_field_support.inner_ip_version);
2243
2244         if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
2245             (match->key->n_proto == htons(ETH_P_IP) ||
2246              match->key->n_proto == htons(ETH_P_IPV6))) {
2247                 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
2248                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
2249                          match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
2250         } else {
2251                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
2252                          ntohs(match->mask->n_proto));
2253                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
2254                          ntohs(match->key->n_proto));
2255         }
2256 }
2257
2258 u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
2259 {
2260         void *headers_v;
2261         u16 ethertype;
2262         u8 ip_version;
2263
2264         if (outer)
2265                 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2266         else
2267                 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
2268
2269         ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
2270         /* Return ip_version converted from ethertype anyway */
2271         if (!ip_version) {
2272                 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2273                 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
2274                         ip_version = 4;
2275                 else if (ethertype == ETH_P_IPV6)
2276                         ip_version = 6;
2277         }
2278         return ip_version;
2279 }
2280
2281 /* Tunnel device follows RFC 6040, see include/net/inet_ecn.h.
2282  * And changes inner ip_ecn depending on inner and outer ip_ecn as follows:
2283  *      +---------+----------------------------------------+
2284  *      |Arriving |         Arriving Outer Header          |
2285  *      |   Inner +---------+---------+---------+----------+
2286  *      |  Header | Not-ECT | ECT(0)  | ECT(1)  |   CE     |
2287  *      +---------+---------+---------+---------+----------+
2288  *      | Not-ECT | Not-ECT | Not-ECT | Not-ECT | <drop>   |
2289  *      |  ECT(0) |  ECT(0) | ECT(0)  | ECT(1)  |   CE*    |
2290  *      |  ECT(1) |  ECT(1) | ECT(1)  | ECT(1)* |   CE*    |
2291  *      |    CE   |   CE    |  CE     | CE      |   CE     |
2292  *      +---------+---------+---------+---------+----------+
2293  *
2294  * Tc matches on inner after decapsulation on tunnel device, but hw offload matches
2295  * the inner ip_ecn value before hardware decap action.
2296  *
2297  * Cells marked are changed from original inner packet ip_ecn value during decap, and
2298  * so matching those values on inner ip_ecn before decap will fail.
2299  *
2300  * The following helper allows offload when inner ip_ecn won't be changed by outer ip_ecn,
2301  * except for the outer ip_ecn = CE, where in all cases inner ip_ecn will be changed to CE,
2302  * and such we can drop the inner ip_ecn=CE match.
2303  */
2304
2305 static int mlx5e_tc_verify_tunnel_ecn(struct mlx5e_priv *priv,
2306                                       struct flow_cls_offload *f,
2307                                       bool *match_inner_ecn)
2308 {
2309         u8 outer_ecn_mask = 0, outer_ecn_key = 0, inner_ecn_mask = 0, inner_ecn_key = 0;
2310         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2311         struct netlink_ext_ack *extack = f->common.extack;
2312         struct flow_match_ip match;
2313
2314         *match_inner_ecn = true;
2315
2316         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
2317                 flow_rule_match_enc_ip(rule, &match);
2318                 outer_ecn_key = match.key->tos & INET_ECN_MASK;
2319                 outer_ecn_mask = match.mask->tos & INET_ECN_MASK;
2320         }
2321
2322         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2323                 flow_rule_match_ip(rule, &match);
2324                 inner_ecn_key = match.key->tos & INET_ECN_MASK;
2325                 inner_ecn_mask = match.mask->tos & INET_ECN_MASK;
2326         }
2327
2328         if (outer_ecn_mask != 0 && outer_ecn_mask != INET_ECN_MASK) {
2329                 NL_SET_ERR_MSG_MOD(extack, "Partial match on enc_tos ecn bits isn't supported");
2330                 netdev_warn(priv->netdev, "Partial match on enc_tos ecn bits isn't supported");
2331                 return -EOPNOTSUPP;
2332         }
2333
2334         if (!outer_ecn_mask) {
2335                 if (!inner_ecn_mask)
2336                         return 0;
2337
2338                 NL_SET_ERR_MSG_MOD(extack,
2339                                    "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2340                 netdev_warn(priv->netdev,
2341                             "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2342                 return -EOPNOTSUPP;
2343         }
2344
2345         if (inner_ecn_mask && inner_ecn_mask != INET_ECN_MASK) {
2346                 NL_SET_ERR_MSG_MOD(extack,
2347                                    "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2348                 netdev_warn(priv->netdev,
2349                             "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2350                 return -EOPNOTSUPP;
2351         }
2352
2353         if (!inner_ecn_mask)
2354                 return 0;
2355
2356         /* Both inner and outer have full mask on ecn */
2357
2358         if (outer_ecn_key == INET_ECN_ECT_1) {
2359                 /* inner ecn might change by DECAP action */
2360
2361                 NL_SET_ERR_MSG_MOD(extack, "Match on enc_tos ecn = ECT(1) isn't supported");
2362                 netdev_warn(priv->netdev, "Match on enc_tos ecn = ECT(1) isn't supported");
2363                 return -EOPNOTSUPP;
2364         }
2365
2366         if (outer_ecn_key != INET_ECN_CE)
2367                 return 0;
2368
2369         if (inner_ecn_key != INET_ECN_CE) {
2370                 /* Can't happen in software, as packet ecn will be changed to CE after decap */
2371                 NL_SET_ERR_MSG_MOD(extack,
2372                                    "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2373                 netdev_warn(priv->netdev,
2374                             "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2375                 return -EOPNOTSUPP;
2376         }
2377
2378         /* outer ecn = CE, inner ecn = CE, as decap will change inner ecn to CE in anycase,
2379          * drop match on inner ecn
2380          */
2381         *match_inner_ecn = false;
2382
2383         return 0;
2384 }
2385
2386 static int parse_tunnel_attr(struct mlx5e_priv *priv,
2387                              struct mlx5e_tc_flow *flow,
2388                              struct mlx5_flow_spec *spec,
2389                              struct flow_cls_offload *f,
2390                              struct net_device *filter_dev,
2391                              u8 *match_level,
2392                              bool *match_inner)
2393 {
2394         struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
2395         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2396         struct netlink_ext_ack *extack = f->common.extack;
2397         bool needs_mapping, sets_mapping;
2398         int err;
2399
2400         if (!mlx5e_is_eswitch_flow(flow)) {
2401                 NL_SET_ERR_MSG_MOD(extack, "Match on tunnel is not supported");
2402                 return -EOPNOTSUPP;
2403         }
2404
2405         needs_mapping = !!flow->attr->chain;
2406         sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
2407         *match_inner = !needs_mapping;
2408
2409         if ((needs_mapping || sets_mapping) &&
2410             !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
2411                 NL_SET_ERR_MSG_MOD(extack,
2412                                    "Chains on tunnel devices isn't supported without register loopback support");
2413                 netdev_warn(priv->netdev,
2414                             "Chains on tunnel devices isn't supported without register loopback support");
2415                 return -EOPNOTSUPP;
2416         }
2417
2418         if (!flow->attr->chain) {
2419                 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2420                                          match_level);
2421                 if (err) {
2422                         NL_SET_ERR_MSG_MOD(extack,
2423                                            "Failed to parse tunnel attributes");
2424                         netdev_warn(priv->netdev,
2425                                     "Failed to parse tunnel attributes");
2426                         return err;
2427                 }
2428
2429                 /* With mpls over udp we decapsulate using packet reformat
2430                  * object
2431                  */
2432                 if (!netif_is_bareudp(filter_dev))
2433                         flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2434                 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
2435                 if (err)
2436                         return err;
2437         } else if (tunnel) {
2438                 struct mlx5_flow_spec *tmp_spec;
2439
2440                 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
2441                 if (!tmp_spec) {
2442                         NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for tunnel tmp spec");
2443                         netdev_warn(priv->netdev, "Failed to allocate memory for tunnel tmp spec");
2444                         return -ENOMEM;
2445                 }
2446                 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
2447
2448                 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
2449                 if (err) {
2450                         kvfree(tmp_spec);
2451                         NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
2452                         netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
2453                         return err;
2454                 }
2455                 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
2456                 kvfree(tmp_spec);
2457                 if (err)
2458                         return err;
2459         }
2460
2461         if (!needs_mapping && !sets_mapping)
2462                 return 0;
2463
2464         return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
2465 }
2466
2467 static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
2468 {
2469         return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2470                             inner_headers);
2471 }
2472
2473 static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
2474 {
2475         return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2476                             inner_headers);
2477 }
2478
2479 static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2480 {
2481         return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2482                             outer_headers);
2483 }
2484
2485 static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2486 {
2487         return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2488                             outer_headers);
2489 }
2490
2491 void *mlx5e_get_match_headers_value(u32 flags, struct mlx5_flow_spec *spec)
2492 {
2493         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2494                 get_match_inner_headers_value(spec) :
2495                 get_match_outer_headers_value(spec);
2496 }
2497
2498 void *mlx5e_get_match_headers_criteria(u32 flags, struct mlx5_flow_spec *spec)
2499 {
2500         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2501                 get_match_inner_headers_criteria(spec) :
2502                 get_match_outer_headers_criteria(spec);
2503 }
2504
2505 static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2506                                    struct flow_cls_offload *f)
2507 {
2508         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2509         struct netlink_ext_ack *extack = f->common.extack;
2510         struct net_device *ingress_dev;
2511         struct flow_match_meta match;
2512
2513         if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2514                 return 0;
2515
2516         flow_rule_match_meta(rule, &match);
2517
2518         if (match.mask->l2_miss) {
2519                 NL_SET_ERR_MSG_MOD(f->common.extack, "Can't match on \"l2_miss\"");
2520                 return -EOPNOTSUPP;
2521         }
2522
2523         if (!match.mask->ingress_ifindex)
2524                 return 0;
2525
2526         if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2527                 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
2528                 return -EOPNOTSUPP;
2529         }
2530
2531         ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2532                                          match.key->ingress_ifindex);
2533         if (!ingress_dev) {
2534                 NL_SET_ERR_MSG_MOD(extack,
2535                                    "Can't find the ingress port to match on");
2536                 return -ENOENT;
2537         }
2538
2539         if (ingress_dev != filter_dev) {
2540                 NL_SET_ERR_MSG_MOD(extack,
2541                                    "Can't match on the ingress filter port");
2542                 return -EOPNOTSUPP;
2543         }
2544
2545         return 0;
2546 }
2547
2548 static bool skip_key_basic(struct net_device *filter_dev,
2549                            struct flow_cls_offload *f)
2550 {
2551         /* When doing mpls over udp decap, the user needs to provide
2552          * MPLS_UC as the protocol in order to be able to match on mpls
2553          * label fields.  However, the actual ethertype is IP so we want to
2554          * avoid matching on this, otherwise we'll fail the match.
2555          */
2556         if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2557                 return true;
2558
2559         return false;
2560 }
2561
2562 static int __parse_cls_flower(struct mlx5e_priv *priv,
2563                               struct mlx5e_tc_flow *flow,
2564                               struct mlx5_flow_spec *spec,
2565                               struct flow_cls_offload *f,
2566                               struct net_device *filter_dev,
2567                               u8 *inner_match_level, u8 *outer_match_level)
2568 {
2569         struct netlink_ext_ack *extack = f->common.extack;
2570         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2571                                        outer_headers);
2572         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2573                                        outer_headers);
2574         void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2575                                     misc_parameters);
2576         void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2577                                     misc_parameters);
2578         void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2579                                     misc_parameters_3);
2580         void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2581                                     misc_parameters_3);
2582         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2583         struct flow_dissector *dissector = rule->match.dissector;
2584         enum fs_flow_table_type fs_type;
2585         bool match_inner_ecn = true;
2586         u16 addr_type = 0;
2587         u8 ip_proto = 0;
2588         u8 *match_level;
2589         int err;
2590
2591         fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
2592         match_level = outer_match_level;
2593
2594         if (dissector->used_keys &
2595             ~(BIT(FLOW_DISSECTOR_KEY_META) |
2596               BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2597               BIT(FLOW_DISSECTOR_KEY_BASIC) |
2598               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2599               BIT(FLOW_DISSECTOR_KEY_VLAN) |
2600               BIT(FLOW_DISSECTOR_KEY_CVLAN) |
2601               BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2602               BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
2603               BIT(FLOW_DISSECTOR_KEY_PORTS) |
2604               BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2605               BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2606               BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2607               BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
2608               BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
2609               BIT(FLOW_DISSECTOR_KEY_TCP) |
2610               BIT(FLOW_DISSECTOR_KEY_IP)  |
2611               BIT(FLOW_DISSECTOR_KEY_CT) |
2612               BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
2613               BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
2614               BIT(FLOW_DISSECTOR_KEY_ICMP) |
2615               BIT(FLOW_DISSECTOR_KEY_MPLS))) {
2616                 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
2617                 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2618                            dissector->used_keys);
2619                 return -EOPNOTSUPP;
2620         }
2621
2622         if (mlx5e_get_tc_tun(filter_dev)) {
2623                 bool match_inner = false;
2624
2625                 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2626                                         outer_match_level, &match_inner);
2627                 if (err)
2628                         return err;
2629
2630                 if (match_inner) {
2631                         /* header pointers should point to the inner headers
2632                          * if the packet was decapsulated already.
2633                          * outer headers are set by parse_tunnel_attr.
2634                          */
2635                         match_level = inner_match_level;
2636                         headers_c = get_match_inner_headers_criteria(spec);
2637                         headers_v = get_match_inner_headers_value(spec);
2638                 }
2639
2640                 err = mlx5e_tc_verify_tunnel_ecn(priv, f, &match_inner_ecn);
2641                 if (err)
2642                         return err;
2643         }
2644
2645         err = mlx5e_flower_parse_meta(filter_dev, f);
2646         if (err)
2647                 return err;
2648
2649         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2650             !skip_key_basic(filter_dev, f)) {
2651                 struct flow_match_basic match;
2652
2653                 flow_rule_match_basic(rule, &match);
2654                 mlx5e_tc_set_ethertype(priv->mdev, &match,
2655                                        match_level == outer_match_level,
2656                                        headers_c, headers_v);
2657
2658                 if (match.mask->n_proto)
2659                         *match_level = MLX5_MATCH_L2;
2660         }
2661         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2662             is_vlan_dev(filter_dev)) {
2663                 struct flow_dissector_key_vlan filter_dev_mask;
2664                 struct flow_dissector_key_vlan filter_dev_key;
2665                 struct flow_match_vlan match;
2666
2667                 if (is_vlan_dev(filter_dev)) {
2668                         match.key = &filter_dev_key;
2669                         match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2670                         match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2671                         match.key->vlan_priority = 0;
2672                         match.mask = &filter_dev_mask;
2673                         memset(match.mask, 0xff, sizeof(*match.mask));
2674                         match.mask->vlan_priority = 0;
2675                 } else {
2676                         flow_rule_match_vlan(rule, &match);
2677                 }
2678                 if (match.mask->vlan_id ||
2679                     match.mask->vlan_priority ||
2680                     match.mask->vlan_tpid) {
2681                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2682                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2683                                          svlan_tag, 1);
2684                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2685                                          svlan_tag, 1);
2686                         } else {
2687                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2688                                          cvlan_tag, 1);
2689                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2690                                          cvlan_tag, 1);
2691                         }
2692
2693                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2694                                  match.mask->vlan_id);
2695                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2696                                  match.key->vlan_id);
2697
2698                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2699                                  match.mask->vlan_priority);
2700                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2701                                  match.key->vlan_priority);
2702
2703                         *match_level = MLX5_MATCH_L2;
2704
2705                         if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN) &&
2706                             match.mask->vlan_eth_type &&
2707                             MLX5_CAP_FLOWTABLE_TYPE(priv->mdev,
2708                                                     ft_field_support.outer_second_vid,
2709                                                     fs_type)) {
2710                                 MLX5_SET(fte_match_set_misc, misc_c,
2711                                          outer_second_cvlan_tag, 1);
2712                                 spec->match_criteria_enable |=
2713                                         MLX5_MATCH_MISC_PARAMETERS;
2714                         }
2715                 }
2716         } else if (*match_level != MLX5_MATCH_NONE) {
2717                 /* cvlan_tag enabled in match criteria and
2718                  * disabled in match value means both S & C tags
2719                  * don't exist (untagged of both)
2720                  */
2721                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
2722                 *match_level = MLX5_MATCH_L2;
2723         }
2724
2725         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2726                 struct flow_match_vlan match;
2727
2728                 flow_rule_match_cvlan(rule, &match);
2729                 if (match.mask->vlan_id ||
2730                     match.mask->vlan_priority ||
2731                     match.mask->vlan_tpid) {
2732                         if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2733                                                      fs_type)) {
2734                                 NL_SET_ERR_MSG_MOD(extack,
2735                                                    "Matching on CVLAN is not supported");
2736                                 return -EOPNOTSUPP;
2737                         }
2738
2739                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2740                                 MLX5_SET(fte_match_set_misc, misc_c,
2741                                          outer_second_svlan_tag, 1);
2742                                 MLX5_SET(fte_match_set_misc, misc_v,
2743                                          outer_second_svlan_tag, 1);
2744                         } else {
2745                                 MLX5_SET(fte_match_set_misc, misc_c,
2746                                          outer_second_cvlan_tag, 1);
2747                                 MLX5_SET(fte_match_set_misc, misc_v,
2748                                          outer_second_cvlan_tag, 1);
2749                         }
2750
2751                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
2752                                  match.mask->vlan_id);
2753                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
2754                                  match.key->vlan_id);
2755                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
2756                                  match.mask->vlan_priority);
2757                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
2758                                  match.key->vlan_priority);
2759
2760                         *match_level = MLX5_MATCH_L2;
2761                         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
2762                 }
2763         }
2764
2765         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2766                 struct flow_match_eth_addrs match;
2767
2768                 flow_rule_match_eth_addrs(rule, &match);
2769                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2770                                              dmac_47_16),
2771                                 match.mask->dst);
2772                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2773                                              dmac_47_16),
2774                                 match.key->dst);
2775
2776                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2777                                              smac_47_16),
2778                                 match.mask->src);
2779                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2780                                              smac_47_16),
2781                                 match.key->src);
2782
2783                 if (!is_zero_ether_addr(match.mask->src) ||
2784                     !is_zero_ether_addr(match.mask->dst))
2785                         *match_level = MLX5_MATCH_L2;
2786         }
2787
2788         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2789                 struct flow_match_control match;
2790
2791                 flow_rule_match_control(rule, &match);
2792                 addr_type = match.key->addr_type;
2793
2794                 /* the HW doesn't support frag first/later */
2795                 if (match.mask->flags & FLOW_DIS_FIRST_FRAG) {
2796                         NL_SET_ERR_MSG_MOD(extack, "Match on frag first/later is not supported");
2797                         return -EOPNOTSUPP;
2798                 }
2799
2800                 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
2801                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2802                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
2803                                  match.key->flags & FLOW_DIS_IS_FRAGMENT);
2804
2805                         /* the HW doesn't need L3 inline to match on frag=no */
2806                         if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
2807                                 *match_level = MLX5_MATCH_L2;
2808         /* ***  L2 attributes parsing up to here *** */
2809                         else
2810                                 *match_level = MLX5_MATCH_L3;
2811                 }
2812         }
2813
2814         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2815                 struct flow_match_basic match;
2816
2817                 flow_rule_match_basic(rule, &match);
2818                 ip_proto = match.key->ip_proto;
2819
2820                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2821                          match.mask->ip_proto);
2822                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2823                          match.key->ip_proto);
2824
2825                 if (match.mask->ip_proto)
2826                         *match_level = MLX5_MATCH_L3;
2827         }
2828
2829         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
2830                 struct flow_match_ipv4_addrs match;
2831
2832                 flow_rule_match_ipv4_addrs(rule, &match);
2833                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2834                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2835                        &match.mask->src, sizeof(match.mask->src));
2836                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2837                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2838                        &match.key->src, sizeof(match.key->src));
2839                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2840                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2841                        &match.mask->dst, sizeof(match.mask->dst));
2842                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2843                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2844                        &match.key->dst, sizeof(match.key->dst));
2845
2846                 if (match.mask->src || match.mask->dst)
2847                         *match_level = MLX5_MATCH_L3;
2848         }
2849
2850         if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
2851                 struct flow_match_ipv6_addrs match;
2852
2853                 flow_rule_match_ipv6_addrs(rule, &match);
2854                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2855                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2856                        &match.mask->src, sizeof(match.mask->src));
2857                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2858                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2859                        &match.key->src, sizeof(match.key->src));
2860
2861                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2862                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2863                        &match.mask->dst, sizeof(match.mask->dst));
2864                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2865                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2866                        &match.key->dst, sizeof(match.key->dst));
2867
2868                 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2869                     ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
2870                         *match_level = MLX5_MATCH_L3;
2871         }
2872
2873         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2874                 struct flow_match_ip match;
2875
2876                 flow_rule_match_ip(rule, &match);
2877                 if (match_inner_ecn) {
2878                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2879                                  match.mask->tos & 0x3);
2880                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2881                                  match.key->tos & 0x3);
2882                 }
2883
2884                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2885                          match.mask->tos >> 2);
2886                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2887                          match.key->tos  >> 2);
2888
2889                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2890                          match.mask->ttl);
2891                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2892                          match.key->ttl);
2893
2894                 if (match.mask->ttl &&
2895                     !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
2896                                                 ft_field_support.outer_ipv4_ttl)) {
2897                         NL_SET_ERR_MSG_MOD(extack,
2898                                            "Matching on TTL is not supported");
2899                         return -EOPNOTSUPP;
2900                 }
2901
2902                 if (match.mask->tos || match.mask->ttl)
2903                         *match_level = MLX5_MATCH_L3;
2904         }
2905
2906         /* ***  L3 attributes parsing up to here *** */
2907
2908         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2909                 struct flow_match_ports match;
2910
2911                 flow_rule_match_ports(rule, &match);
2912                 switch (ip_proto) {
2913                 case IPPROTO_TCP:
2914                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2915                                  tcp_sport, ntohs(match.mask->src));
2916                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2917                                  tcp_sport, ntohs(match.key->src));
2918
2919                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2920                                  tcp_dport, ntohs(match.mask->dst));
2921                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2922                                  tcp_dport, ntohs(match.key->dst));
2923                         break;
2924
2925                 case IPPROTO_UDP:
2926                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2927                                  udp_sport, ntohs(match.mask->src));
2928                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2929                                  udp_sport, ntohs(match.key->src));
2930
2931                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2932                                  udp_dport, ntohs(match.mask->dst));
2933                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2934                                  udp_dport, ntohs(match.key->dst));
2935                         break;
2936                 default:
2937                         NL_SET_ERR_MSG_MOD(extack,
2938                                            "Only UDP and TCP transports are supported for L4 matching");
2939                         netdev_err(priv->netdev,
2940                                    "Only UDP and TCP transport are supported\n");
2941                         return -EINVAL;
2942                 }
2943
2944                 if (match.mask->src || match.mask->dst)
2945                         *match_level = MLX5_MATCH_L4;
2946         }
2947
2948         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2949                 struct flow_match_tcp match;
2950
2951                 flow_rule_match_tcp(rule, &match);
2952                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
2953                          ntohs(match.mask->flags));
2954                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
2955                          ntohs(match.key->flags));
2956
2957                 if (match.mask->flags)
2958                         *match_level = MLX5_MATCH_L4;
2959         }
2960         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2961                 struct flow_match_icmp match;
2962
2963                 flow_rule_match_icmp(rule, &match);
2964                 switch (ip_proto) {
2965                 case IPPROTO_ICMP:
2966                         if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2967                               MLX5_FLEX_PROTO_ICMP)) {
2968                                 NL_SET_ERR_MSG_MOD(extack,
2969                                                    "Match on Flex protocols for ICMP is not supported");
2970                                 return -EOPNOTSUPP;
2971                         }
2972                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2973                                  match.mask->type);
2974                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2975                                  match.key->type);
2976                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2977                                  match.mask->code);
2978                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2979                                  match.key->code);
2980                         break;
2981                 case IPPROTO_ICMPV6:
2982                         if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2983                               MLX5_FLEX_PROTO_ICMPV6)) {
2984                                 NL_SET_ERR_MSG_MOD(extack,
2985                                                    "Match on Flex protocols for ICMPV6 is not supported");
2986                                 return -EOPNOTSUPP;
2987                         }
2988                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2989                                  match.mask->type);
2990                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2991                                  match.key->type);
2992                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2993                                  match.mask->code);
2994                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2995                                  match.key->code);
2996                         break;
2997                 default:
2998                         NL_SET_ERR_MSG_MOD(extack,
2999                                            "Code and type matching only with ICMP and ICMPv6");
3000                         netdev_err(priv->netdev,
3001                                    "Code and type matching only with ICMP and ICMPv6\n");
3002                         return -EINVAL;
3003                 }
3004                 if (match.mask->code || match.mask->type) {
3005                         *match_level = MLX5_MATCH_L4;
3006                         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
3007                 }
3008         }
3009         /* Currently supported only for MPLS over UDP */
3010         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
3011             !netif_is_bareudp(filter_dev)) {
3012                 NL_SET_ERR_MSG_MOD(extack,
3013                                    "Matching on MPLS is supported only for MPLS over UDP");
3014                 netdev_err(priv->netdev,
3015                            "Matching on MPLS is supported only for MPLS over UDP\n");
3016                 return -EOPNOTSUPP;
3017         }
3018
3019         return 0;
3020 }
3021
3022 static int parse_cls_flower(struct mlx5e_priv *priv,
3023                             struct mlx5e_tc_flow *flow,
3024                             struct mlx5_flow_spec *spec,
3025                             struct flow_cls_offload *f,
3026                             struct net_device *filter_dev)
3027 {
3028         u8 inner_match_level, outer_match_level, non_tunnel_match_level;
3029         struct netlink_ext_ack *extack = f->common.extack;
3030         struct mlx5_core_dev *dev = priv->mdev;
3031         struct mlx5_eswitch *esw = dev->priv.eswitch;
3032         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3033         struct mlx5_eswitch_rep *rep;
3034         bool is_eswitch_flow;
3035         int err;
3036
3037         inner_match_level = MLX5_MATCH_NONE;
3038         outer_match_level = MLX5_MATCH_NONE;
3039
3040         err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
3041                                  &inner_match_level, &outer_match_level);
3042         non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
3043                                  outer_match_level : inner_match_level;
3044
3045         is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
3046         if (!err && is_eswitch_flow) {
3047                 rep = rpriv->rep;
3048                 if (rep->vport != MLX5_VPORT_UPLINK &&
3049                     (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
3050                     esw->offloads.inline_mode < non_tunnel_match_level)) {
3051                         NL_SET_ERR_MSG_MOD(extack,
3052                                            "Flow is not offloaded due to min inline setting");
3053                         netdev_warn(priv->netdev,
3054                                     "Flow is not offloaded due to min inline setting, required %d actual %d\n",
3055                                     non_tunnel_match_level, esw->offloads.inline_mode);
3056                         return -EOPNOTSUPP;
3057                 }
3058         }
3059
3060         flow->attr->inner_match_level = inner_match_level;
3061         flow->attr->outer_match_level = outer_match_level;
3062
3063
3064         return err;
3065 }
3066
3067 struct mlx5_fields {
3068         u8  field;
3069         u8  field_bsize;
3070         u32 field_mask;
3071         u32 offset;
3072         u32 match_offset;
3073 };
3074
3075 #define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
3076                 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
3077                  offsetof(struct pedit_headers, field) + (off), \
3078                  MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
3079
3080 /* masked values are the same and there are no rewrites that do not have a
3081  * match.
3082  */
3083 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
3084         type matchmaskx = *(type *)(matchmaskp); \
3085         type matchvalx = *(type *)(matchvalp); \
3086         type maskx = *(type *)(maskp); \
3087         type valx = *(type *)(valp); \
3088         \
3089         (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
3090                                                                  matchmaskx)); \
3091 })
3092
3093 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
3094                          void *matchmaskp, u8 bsize)
3095 {
3096         bool same = false;
3097
3098         switch (bsize) {
3099         case 8:
3100                 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
3101                 break;
3102         case 16:
3103                 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
3104                 break;
3105         case 32:
3106                 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
3107                 break;
3108         }
3109
3110         return same;
3111 }
3112
3113 static struct mlx5_fields fields[] = {
3114         OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
3115         OFFLOAD(DMAC_15_0,  16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
3116         OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
3117         OFFLOAD(SMAC_15_0,  16, U16_MAX, eth.h_source[4], 0, smac_15_0),
3118         OFFLOAD(ETHERTYPE,  16, U16_MAX, eth.h_proto, 0, ethertype),
3119         OFFLOAD(FIRST_VID,  16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
3120
3121         OFFLOAD(IP_DSCP, 8,    0xfc, ip4.tos,   0, ip_dscp),
3122         OFFLOAD(IP_TTL,  8,  U8_MAX, ip4.ttl,   0, ttl_hoplimit),
3123         OFFLOAD(SIPV4,  32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
3124         OFFLOAD(DIPV4,  32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
3125
3126         OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
3127                 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
3128         OFFLOAD(SIPV6_95_64,  32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
3129                 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
3130         OFFLOAD(SIPV6_63_32,  32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
3131                 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
3132         OFFLOAD(SIPV6_31_0,   32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
3133                 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
3134         OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
3135                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
3136         OFFLOAD(DIPV6_95_64,  32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
3137                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
3138         OFFLOAD(DIPV6_63_32,  32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
3139                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
3140         OFFLOAD(DIPV6_31_0,   32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
3141                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
3142         OFFLOAD(IPV6_HOPLIMIT, 8,  U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
3143         OFFLOAD(IP_DSCP, 16,  0xc00f, ip6, 0, ip_dscp),
3144
3145         OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source,  0, tcp_sport),
3146         OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest,    0, tcp_dport),
3147         /* in linux iphdr tcp_flags is 8 bits long */
3148         OFFLOAD(TCP_FLAGS,  8,  U8_MAX, tcp.ack_seq, 5, tcp_flags),
3149
3150         OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
3151         OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest,   0, udp_dport),
3152 };
3153
3154 static unsigned long mask_to_le(unsigned long mask, int size)
3155 {
3156         __be32 mask_be32;
3157         __be16 mask_be16;
3158
3159         if (size == 32) {
3160                 mask_be32 = (__force __be32)(mask);
3161                 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
3162         } else if (size == 16) {
3163                 mask_be32 = (__force __be32)(mask);
3164                 mask_be16 = *(__be16 *)&mask_be32;
3165                 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
3166         }
3167
3168         return mask;
3169 }
3170
3171 static int offload_pedit_fields(struct mlx5e_priv *priv,
3172                                 int namespace,
3173                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
3174                                 u32 *action_flags,
3175                                 struct netlink_ext_ack *extack)
3176 {
3177         struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
3178         struct pedit_headers_action *hdrs = parse_attr->hdrs;
3179         void *headers_c, *headers_v, *action, *vals_p;
3180         u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
3181         struct mlx5e_tc_mod_hdr_acts *mod_acts;
3182         unsigned long mask, field_mask;
3183         int i, first, last, next_z;
3184         struct mlx5_fields *f;
3185         u8 cmd;
3186
3187         mod_acts = &parse_attr->mod_hdr_acts;
3188         headers_c = mlx5e_get_match_headers_criteria(*action_flags, &parse_attr->spec);
3189         headers_v = mlx5e_get_match_headers_value(*action_flags, &parse_attr->spec);
3190
3191         set_masks = &hdrs[0].masks;
3192         add_masks = &hdrs[1].masks;
3193         set_vals = &hdrs[0].vals;
3194         add_vals = &hdrs[1].vals;
3195
3196         for (i = 0; i < ARRAY_SIZE(fields); i++) {
3197                 bool skip;
3198
3199                 f = &fields[i];
3200                 /* avoid seeing bits set from previous iterations */
3201                 s_mask = 0;
3202                 a_mask = 0;
3203
3204                 s_masks_p = (void *)set_masks + f->offset;
3205                 a_masks_p = (void *)add_masks + f->offset;
3206
3207                 s_mask = *s_masks_p & f->field_mask;
3208                 a_mask = *a_masks_p & f->field_mask;
3209
3210                 if (!s_mask && !a_mask) /* nothing to offload here */
3211                         continue;
3212
3213                 if (s_mask && a_mask) {
3214                         NL_SET_ERR_MSG_MOD(extack,
3215                                            "can't set and add to the same HW field");
3216                         netdev_warn(priv->netdev,
3217                                     "mlx5: can't set and add to the same HW field (%x)\n",
3218                                     f->field);
3219                         return -EOPNOTSUPP;
3220                 }
3221
3222                 skip = false;
3223                 if (s_mask) {
3224                         void *match_mask = headers_c + f->match_offset;
3225                         void *match_val = headers_v + f->match_offset;
3226
3227                         cmd  = MLX5_ACTION_TYPE_SET;
3228                         mask = s_mask;
3229                         vals_p = (void *)set_vals + f->offset;
3230                         /* don't rewrite if we have a match on the same value */
3231                         if (cmp_val_mask(vals_p, s_masks_p, match_val,
3232                                          match_mask, f->field_bsize))
3233                                 skip = true;
3234                         /* clear to denote we consumed this field */
3235                         *s_masks_p &= ~f->field_mask;
3236                 } else {
3237                         cmd  = MLX5_ACTION_TYPE_ADD;
3238                         mask = a_mask;
3239                         vals_p = (void *)add_vals + f->offset;
3240                         /* add 0 is no change */
3241                         if ((*(u32 *)vals_p & f->field_mask) == 0)
3242                                 skip = true;
3243                         /* clear to denote we consumed this field */
3244                         *a_masks_p &= ~f->field_mask;
3245                 }
3246                 if (skip)
3247                         continue;
3248
3249                 mask = mask_to_le(mask, f->field_bsize);
3250
3251                 first = find_first_bit(&mask, f->field_bsize);
3252                 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
3253                 last  = find_last_bit(&mask, f->field_bsize);
3254                 if (first < next_z && next_z < last) {
3255                         NL_SET_ERR_MSG_MOD(extack,
3256                                            "rewrite of few sub-fields isn't supported");
3257                         netdev_warn(priv->netdev,
3258                                     "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
3259                                     mask);
3260                         return -EOPNOTSUPP;
3261                 }
3262
3263                 action = mlx5e_mod_hdr_alloc(priv->mdev, namespace, mod_acts);
3264                 if (IS_ERR(action)) {
3265                         NL_SET_ERR_MSG_MOD(extack,
3266                                            "too many pedit actions, can't offload");
3267                         mlx5_core_warn(priv->mdev,
3268                                        "mlx5: parsed %d pedit actions, can't do more\n",
3269                                        mod_acts->num_actions);
3270                         return PTR_ERR(action);
3271                 }
3272
3273                 MLX5_SET(set_action_in, action, action_type, cmd);
3274                 MLX5_SET(set_action_in, action, field, f->field);
3275
3276                 if (cmd == MLX5_ACTION_TYPE_SET) {
3277                         int start;
3278
3279                         field_mask = mask_to_le(f->field_mask, f->field_bsize);
3280
3281                         /* if field is bit sized it can start not from first bit */
3282                         start = find_first_bit(&field_mask, f->field_bsize);
3283
3284                         MLX5_SET(set_action_in, action, offset, first - start);
3285                         /* length is num of bits to be written, zero means length of 32 */
3286                         MLX5_SET(set_action_in, action, length, (last - first + 1));
3287                 }
3288
3289                 if (f->field_bsize == 32)
3290                         MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
3291                 else if (f->field_bsize == 16)
3292                         MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
3293                 else if (f->field_bsize == 8)
3294                         MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
3295
3296                 ++mod_acts->num_actions;
3297         }
3298
3299         return 0;
3300 }
3301
3302 static const struct pedit_headers zero_masks = {};
3303
3304 static int verify_offload_pedit_fields(struct mlx5e_priv *priv,
3305                                        struct mlx5e_tc_flow_parse_attr *parse_attr,
3306                                        struct netlink_ext_ack *extack)
3307 {
3308         struct pedit_headers *cmd_masks;
3309         u8 cmd;
3310
3311         for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
3312                 cmd_masks = &parse_attr->hdrs[cmd].masks;
3313                 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
3314                         NL_SET_ERR_MSG_MOD(extack, "attempt to offload an unsupported field");
3315                         netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
3316                         print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3317                                        16, 1, cmd_masks, sizeof(zero_masks), true);
3318                         return -EOPNOTSUPP;
3319                 }
3320         }
3321
3322         return 0;
3323 }
3324
3325 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3326                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
3327                                  u32 *action_flags,
3328                                  struct netlink_ext_ack *extack)
3329 {
3330         int err;
3331
3332         err = offload_pedit_fields(priv, namespace, parse_attr, action_flags, extack);
3333         if (err)
3334                 goto out_dealloc_parsed_actions;
3335
3336         err = verify_offload_pedit_fields(priv, parse_attr, extack);
3337         if (err)
3338                 goto out_dealloc_parsed_actions;
3339
3340         return 0;
3341
3342 out_dealloc_parsed_actions:
3343         mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
3344         return err;
3345 }
3346
3347 struct ip_ttl_word {
3348         __u8    ttl;
3349         __u8    protocol;
3350         __sum16 check;
3351 };
3352
3353 struct ipv6_hoplimit_word {
3354         __be16  payload_len;
3355         __u8    nexthdr;
3356         __u8    hop_limit;
3357 };
3358
3359 static bool
3360 is_flow_action_modify_ip_header(struct flow_action *flow_action)
3361 {
3362         const struct flow_action_entry *act;
3363         u32 mask, offset;
3364         u8 htype;
3365         int i;
3366
3367         /* For IPv4 & IPv6 header check 4 byte word,
3368          * to determine that modified fields
3369          * are NOT ttl & hop_limit only.
3370          */
3371         flow_action_for_each(i, act, flow_action) {
3372                 if (act->id != FLOW_ACTION_MANGLE &&
3373                     act->id != FLOW_ACTION_ADD)
3374                         continue;
3375
3376                 htype = act->mangle.htype;
3377                 offset = act->mangle.offset;
3378                 mask = ~act->mangle.mask;
3379
3380                 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3381                         struct ip_ttl_word *ttl_word =
3382                                 (struct ip_ttl_word *)&mask;
3383
3384                         if (offset != offsetof(struct iphdr, ttl) ||
3385                             ttl_word->protocol ||
3386                             ttl_word->check)
3387                                 return true;
3388                 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3389                         struct ipv6_hoplimit_word *hoplimit_word =
3390                                 (struct ipv6_hoplimit_word *)&mask;
3391
3392                         if (offset != offsetof(struct ipv6hdr, payload_len) ||
3393                             hoplimit_word->payload_len ||
3394                             hoplimit_word->nexthdr)
3395                                 return true;
3396                 }
3397         }
3398
3399         return false;
3400 }
3401
3402 static bool modify_header_match_supported(struct mlx5e_priv *priv,
3403                                           struct mlx5_flow_spec *spec,
3404                                           struct flow_action *flow_action,
3405                                           u32 actions,
3406                                           struct netlink_ext_ack *extack)
3407 {
3408         bool modify_ip_header;
3409         void *headers_c;
3410         void *headers_v;
3411         u16 ethertype;
3412         u8 ip_proto;
3413
3414         headers_c = mlx5e_get_match_headers_criteria(actions, spec);
3415         headers_v = mlx5e_get_match_headers_value(actions, spec);
3416         ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3417
3418         /* for non-IP we only re-write MACs, so we're okay */
3419         if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3420             ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
3421                 goto out_ok;
3422
3423         modify_ip_header = is_flow_action_modify_ip_header(flow_action);
3424         ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
3425         if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3426             ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
3427                 NL_SET_ERR_MSG_MOD(extack,
3428                                    "can't offload re-write of non TCP/UDP");
3429                 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3430                             ip_proto);
3431                 return false;
3432         }
3433
3434 out_ok:
3435         return true;
3436 }
3437
3438 static bool
3439 actions_match_supported_fdb(struct mlx5e_priv *priv,
3440                             struct mlx5e_tc_flow *flow,
3441                             struct netlink_ext_ack *extack)
3442 {
3443         struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
3444
3445         if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3446                 NL_SET_ERR_MSG_MOD(extack,
3447                                    "current firmware doesn't support split rule for port mirroring");
3448                 netdev_warn_once(priv->netdev,
3449                                  "current firmware doesn't support split rule for port mirroring\n");
3450                 return false;
3451         }
3452
3453         return true;
3454 }
3455
3456 static bool
3457 actions_match_supported(struct mlx5e_priv *priv,
3458                         struct flow_action *flow_action,
3459                         u32 actions,
3460                         struct mlx5e_tc_flow_parse_attr *parse_attr,
3461                         struct mlx5e_tc_flow *flow,
3462                         struct netlink_ext_ack *extack)
3463 {
3464         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
3465             !modify_header_match_supported(priv, &parse_attr->spec, flow_action, actions,
3466                                            extack))
3467                 return false;
3468
3469         if (mlx5e_is_eswitch_flow(flow) &&
3470             !actions_match_supported_fdb(priv, flow, extack))
3471                 return false;
3472
3473         return true;
3474 }
3475
3476 static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3477 {
3478         return priv->mdev == peer_priv->mdev;
3479 }
3480
3481 bool mlx5e_same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3482 {
3483         struct mlx5_core_dev *fmdev, *pmdev;
3484         u64 fsystem_guid, psystem_guid;
3485
3486         fmdev = priv->mdev;
3487         pmdev = peer_priv->mdev;
3488
3489         fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3490         psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
3491
3492         return (fsystem_guid == psystem_guid);
3493 }
3494
3495 static int
3496 actions_prepare_mod_hdr_actions(struct mlx5e_priv *priv,
3497                                 struct mlx5e_tc_flow *flow,
3498                                 struct mlx5_flow_attr *attr,
3499                                 struct netlink_ext_ack *extack)
3500 {
3501         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3502         struct pedit_headers_action *hdrs = parse_attr->hdrs;
3503         enum mlx5_flow_namespace_type ns_type;
3504         int err;
3505
3506         if (!hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits &&
3507             !hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits)
3508                 return 0;
3509
3510         ns_type = mlx5e_get_flow_namespace(flow);
3511
3512         err = alloc_tc_pedit_action(priv, ns_type, parse_attr, &attr->action, extack);
3513         if (err)
3514                 return err;
3515
3516         if (parse_attr->mod_hdr_acts.num_actions > 0)
3517                 return 0;
3518
3519         /* In case all pedit actions are skipped, remove the MOD_HDR flag. */
3520         attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3521         mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
3522
3523         if (ns_type != MLX5_FLOW_NAMESPACE_FDB)
3524                 return 0;
3525
3526         if (!((attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3527               (attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3528                 attr->esw_attr->split_count = 0;
3529
3530         return 0;
3531 }
3532
3533 static struct mlx5_flow_attr*
3534 mlx5e_clone_flow_attr_for_post_act(struct mlx5_flow_attr *attr,
3535                                    enum mlx5_flow_namespace_type ns_type)
3536 {
3537         struct mlx5e_tc_flow_parse_attr *parse_attr;
3538         u32 attr_sz = ns_to_attr_sz(ns_type);
3539         struct mlx5_flow_attr *attr2;
3540
3541         attr2 = mlx5_alloc_flow_attr(ns_type);
3542         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
3543         if (!attr2 || !parse_attr) {
3544                 kvfree(parse_attr);
3545                 kfree(attr2);
3546                 return NULL;
3547         }
3548
3549         memcpy(attr2, attr, attr_sz);
3550         INIT_LIST_HEAD(&attr2->list);
3551         parse_attr->filter_dev = attr->parse_attr->filter_dev;
3552         attr2->action = 0;
3553         attr2->counter = NULL;
3554         attr2->tc_act_cookies_count = 0;
3555         attr2->flags = 0;
3556         attr2->parse_attr = parse_attr;
3557         attr2->dest_chain = 0;
3558         attr2->dest_ft = NULL;
3559         attr2->act_id_restore_rule = NULL;
3560         memset(&attr2->ct_attr, 0, sizeof(attr2->ct_attr));
3561
3562         if (ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3563                 attr2->esw_attr->out_count = 0;
3564                 attr2->esw_attr->split_count = 0;
3565         }
3566
3567         attr2->branch_true = NULL;
3568         attr2->branch_false = NULL;
3569         attr2->jumping_attr = NULL;
3570         return attr2;
3571 }
3572
3573 struct mlx5_flow_attr *
3574 mlx5e_tc_get_encap_attr(struct mlx5e_tc_flow *flow)
3575 {
3576         struct mlx5_esw_flow_attr *esw_attr;
3577         struct mlx5_flow_attr *attr;
3578         int i;
3579
3580         list_for_each_entry(attr, &flow->attrs, list) {
3581                 esw_attr = attr->esw_attr;
3582                 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
3583                         if (esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP)
3584                                 return attr;
3585                 }
3586         }
3587
3588         return NULL;
3589 }
3590
3591 void
3592 mlx5e_tc_unoffload_flow_post_acts(struct mlx5e_tc_flow *flow)
3593 {
3594         struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3595         struct mlx5_flow_attr *attr;
3596
3597         list_for_each_entry(attr, &flow->attrs, list) {
3598                 if (list_is_last(&attr->list, &flow->attrs))
3599                         break;
3600
3601                 mlx5e_tc_post_act_unoffload(post_act, attr->post_act_handle);
3602         }
3603 }
3604
3605 static void
3606 free_flow_post_acts(struct mlx5e_tc_flow *flow)
3607 {
3608         struct mlx5_flow_attr *attr, *tmp;
3609
3610         list_for_each_entry_safe(attr, tmp, &flow->attrs, list) {
3611                 if (list_is_last(&attr->list, &flow->attrs))
3612                         break;
3613
3614                 mlx5_free_flow_attr_actions(flow, attr);
3615
3616                 list_del(&attr->list);
3617                 kvfree(attr->parse_attr);
3618                 kfree(attr);
3619         }
3620 }
3621
3622 int
3623 mlx5e_tc_offload_flow_post_acts(struct mlx5e_tc_flow *flow)
3624 {
3625         struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3626         struct mlx5_flow_attr *attr;
3627         int err = 0;
3628
3629         list_for_each_entry(attr, &flow->attrs, list) {
3630                 if (list_is_last(&attr->list, &flow->attrs))
3631                         break;
3632
3633                 err = mlx5e_tc_post_act_offload(post_act, attr->post_act_handle);
3634                 if (err)
3635                         break;
3636         }
3637
3638         return err;
3639 }
3640
3641 /* TC filter rule HW translation:
3642  *
3643  * +---------------------+
3644  * + ft prio (tc chain)  +
3645  * + original match      +
3646  * +---------------------+
3647  *           |
3648  *           | if multi table action
3649  *           |
3650  *           v
3651  * +---------------------+
3652  * + post act ft         |<----.
3653  * + match fte id        |     | split on multi table action
3654  * + do actions          |-----'
3655  * +---------------------+
3656  *           |
3657  *           |
3658  *           v
3659  * Do rest of the actions after last multi table action.
3660  */
3661 static int
3662 alloc_flow_post_acts(struct mlx5e_tc_flow *flow, struct netlink_ext_ack *extack)
3663 {
3664         struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3665         struct mlx5_flow_attr *attr, *next_attr = NULL;
3666         struct mlx5e_post_act_handle *handle;
3667         int err;
3668
3669         /* This is going in reverse order as needed.
3670          * The first entry is the last attribute.
3671          */
3672         list_for_each_entry(attr, &flow->attrs, list) {
3673                 if (!next_attr) {
3674                         /* Set counter action on last post act rule. */
3675                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3676                 }
3677
3678                 if (next_attr && !(attr->flags & MLX5_ATTR_FLAG_TERMINATING)) {
3679                         err = mlx5e_tc_act_set_next_post_act(flow, attr, next_attr);
3680                         if (err)
3681                                 goto out_free;
3682                 }
3683
3684                 /* Don't add post_act rule for first attr (last in the list).
3685                  * It's being handled by the caller.
3686                  */
3687                 if (list_is_last(&attr->list, &flow->attrs))
3688                         break;
3689
3690                 err = actions_prepare_mod_hdr_actions(flow->priv, flow, attr, extack);
3691                 if (err)
3692                         goto out_free;
3693
3694                 err = post_process_attr(flow, attr, extack);
3695                 if (err)
3696                         goto out_free;
3697
3698                 handle = mlx5e_tc_post_act_add(post_act, attr);
3699                 if (IS_ERR(handle)) {
3700                         err = PTR_ERR(handle);
3701                         goto out_free;
3702                 }
3703
3704                 attr->post_act_handle = handle;
3705
3706                 if (attr->jumping_attr) {
3707                         err = mlx5e_tc_act_set_next_post_act(flow, attr->jumping_attr, attr);
3708                         if (err)
3709                                 goto out_free;
3710                 }
3711
3712                 next_attr = attr;
3713         }
3714
3715         if (flow_flag_test(flow, SLOW))
3716                 goto out;
3717
3718         err = mlx5e_tc_offload_flow_post_acts(flow);
3719         if (err)
3720                 goto out_free;
3721
3722 out:
3723         return 0;
3724
3725 out_free:
3726         free_flow_post_acts(flow);
3727         return err;
3728 }
3729
3730 static int
3731 alloc_branch_attr(struct mlx5e_tc_flow *flow,
3732                   struct mlx5e_tc_act_branch_ctrl *cond,
3733                   struct mlx5_flow_attr **cond_attr,
3734                   u32 *jump_count,
3735                   struct netlink_ext_ack *extack)
3736 {
3737         struct mlx5_flow_attr *attr;
3738         int err = 0;
3739
3740         *cond_attr = mlx5e_clone_flow_attr_for_post_act(flow->attr,
3741                                                         mlx5e_get_flow_namespace(flow));
3742         if (!(*cond_attr))
3743                 return -ENOMEM;
3744
3745         attr = *cond_attr;
3746
3747         switch (cond->act_id) {
3748         case FLOW_ACTION_DROP:
3749                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3750                 break;
3751         case FLOW_ACTION_ACCEPT:
3752         case FLOW_ACTION_PIPE:
3753                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3754                 attr->dest_ft = mlx5e_tc_post_act_get_ft(get_post_action(flow->priv));
3755                 break;
3756         case FLOW_ACTION_JUMP:
3757                 if (*jump_count) {
3758                         NL_SET_ERR_MSG_MOD(extack, "Cannot offload flows with nested jumps");
3759                         err = -EOPNOTSUPP;
3760                         goto out_err;
3761                 }
3762                 *jump_count = cond->extval;
3763                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3764                 attr->dest_ft = mlx5e_tc_post_act_get_ft(get_post_action(flow->priv));
3765                 break;
3766         default:
3767                 err = -EOPNOTSUPP;
3768                 goto out_err;
3769         }
3770
3771         return err;
3772 out_err:
3773         kfree(*cond_attr);
3774         *cond_attr = NULL;
3775         return err;
3776 }
3777
3778 static void
3779 dec_jump_count(struct flow_action_entry *act, struct mlx5e_tc_act *tc_act,
3780                struct mlx5_flow_attr *attr, struct mlx5e_priv *priv,
3781                struct mlx5e_tc_jump_state *jump_state)
3782 {
3783         if (!jump_state->jump_count)
3784                 return;
3785
3786         /* Single tc action can instantiate multiple offload actions (e.g. pedit)
3787          * Jump only over a tc action
3788          */
3789         if (act->id == jump_state->last_id && act->hw_index == jump_state->last_index)
3790                 return;
3791
3792         jump_state->last_id = act->id;
3793         jump_state->last_index = act->hw_index;
3794
3795         /* nothing to do for intermediate actions */
3796         if (--jump_state->jump_count > 1)
3797                 return;
3798
3799         if (jump_state->jump_count == 1) { /* last action in the jump action list */
3800
3801                 /* create a new attribute after this action */
3802                 jump_state->jump_target = true;
3803
3804                 if (tc_act->is_terminating_action) { /* the branch ends here */
3805                         attr->flags |= MLX5_ATTR_FLAG_TERMINATING;
3806                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3807                 } else { /* the branch continues executing the rest of the actions */
3808                         struct mlx5e_post_act *post_act;
3809
3810                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3811                         post_act = get_post_action(priv);
3812                         attr->dest_ft = mlx5e_tc_post_act_get_ft(post_act);
3813                 }
3814         } else if (jump_state->jump_count == 0) { /* first attr after the jump action list */
3815                 /* This is the post action for the jumping attribute (either red or green)
3816                  * Use the stored jumping_attr to set the post act id on the jumping attribute
3817                  */
3818                 attr->jumping_attr = jump_state->jumping_attr;
3819         }
3820 }
3821
3822 static int
3823 parse_branch_ctrl(struct flow_action_entry *act, struct mlx5e_tc_act *tc_act,
3824                   struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr,
3825                   struct mlx5e_tc_jump_state *jump_state,
3826                   struct netlink_ext_ack *extack)
3827 {
3828         struct mlx5e_tc_act_branch_ctrl cond_true, cond_false;
3829         u32 jump_count = jump_state->jump_count;
3830         int err;
3831
3832         if (!tc_act->get_branch_ctrl)
3833                 return 0;
3834
3835         tc_act->get_branch_ctrl(act, &cond_true, &cond_false);
3836
3837         err = alloc_branch_attr(flow, &cond_true,
3838                                 &attr->branch_true, &jump_count, extack);
3839         if (err)
3840                 goto out_err;
3841
3842         if (jump_count)
3843                 jump_state->jumping_attr = attr->branch_true;
3844
3845         err = alloc_branch_attr(flow, &cond_false,
3846                                 &attr->branch_false, &jump_count, extack);
3847         if (err)
3848                 goto err_branch_false;
3849
3850         if (jump_count && !jump_state->jumping_attr)
3851                 jump_state->jumping_attr = attr->branch_false;
3852
3853         jump_state->jump_count = jump_count;
3854
3855         /* branching action requires its own counter */
3856         attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3857         flow_flag_set(flow, USE_ACT_STATS);
3858
3859         return 0;
3860
3861 err_branch_false:
3862         free_branch_attr(flow, attr->branch_true);
3863 out_err:
3864         return err;
3865 }
3866
3867 static int
3868 parse_tc_actions(struct mlx5e_tc_act_parse_state *parse_state,
3869                  struct flow_action *flow_action)
3870 {
3871         struct netlink_ext_ack *extack = parse_state->extack;
3872         struct mlx5e_tc_flow *flow = parse_state->flow;
3873         struct mlx5e_tc_jump_state jump_state = {};
3874         struct mlx5_flow_attr *attr = flow->attr;
3875         enum mlx5_flow_namespace_type ns_type;
3876         struct mlx5e_priv *priv = flow->priv;
3877         struct mlx5_flow_attr *prev_attr;
3878         struct flow_action_entry *act;
3879         struct mlx5e_tc_act *tc_act;
3880         int err, i, i_split = 0;
3881         bool is_missable;
3882
3883         ns_type = mlx5e_get_flow_namespace(flow);
3884         list_add(&attr->list, &flow->attrs);
3885
3886         flow_action_for_each(i, act, flow_action) {
3887                 jump_state.jump_target = false;
3888                 is_missable = false;
3889                 prev_attr = attr;
3890
3891                 tc_act = mlx5e_tc_act_get(act->id, ns_type);
3892                 if (!tc_act) {
3893                         NL_SET_ERR_MSG_MOD(extack, "Not implemented offload action");
3894                         err = -EOPNOTSUPP;
3895                         goto out_free_post_acts;
3896                 }
3897
3898                 if (tc_act->can_offload && !tc_act->can_offload(parse_state, act, i, attr)) {
3899                         err = -EOPNOTSUPP;
3900                         goto out_free_post_acts;
3901                 }
3902
3903                 err = tc_act->parse_action(parse_state, act, priv, attr);
3904                 if (err)
3905                         goto out_free_post_acts;
3906
3907                 dec_jump_count(act, tc_act, attr, priv, &jump_state);
3908
3909                 err = parse_branch_ctrl(act, tc_act, flow, attr, &jump_state, extack);
3910                 if (err)
3911                         goto out_free_post_acts;
3912
3913                 parse_state->actions |= attr->action;
3914
3915                 /* Split attr for multi table act if not the last act. */
3916                 if (jump_state.jump_target ||
3917                     (tc_act->is_multi_table_act &&
3918                     tc_act->is_multi_table_act(priv, act, attr) &&
3919                     i < flow_action->num_entries - 1)) {
3920                         is_missable = tc_act->is_missable ? tc_act->is_missable(act) : false;
3921
3922                         err = mlx5e_tc_act_post_parse(parse_state, flow_action, i_split, i, attr,
3923                                                       ns_type);
3924                         if (err)
3925                                 goto out_free_post_acts;
3926
3927                         attr = mlx5e_clone_flow_attr_for_post_act(flow->attr, ns_type);
3928                         if (!attr) {
3929                                 err = -ENOMEM;
3930                                 goto out_free_post_acts;
3931                         }
3932
3933                         i_split = i + 1;
3934                         list_add(&attr->list, &flow->attrs);
3935                 }
3936
3937                 if (is_missable) {
3938                         /* Add counter to prev, and assign act to new (next) attr */
3939                         prev_attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3940                         flow_flag_set(flow, USE_ACT_STATS);
3941
3942                         attr->tc_act_cookies[attr->tc_act_cookies_count++] = act->cookie;
3943                 } else if (!tc_act->stats_action) {
3944                         prev_attr->tc_act_cookies[prev_attr->tc_act_cookies_count++] = act->cookie;
3945                 }
3946         }
3947
3948         err = mlx5e_tc_act_post_parse(parse_state, flow_action, i_split, i, attr, ns_type);
3949         if (err)
3950                 goto out_free_post_acts;
3951
3952         err = alloc_flow_post_acts(flow, extack);
3953         if (err)
3954                 goto out_free_post_acts;
3955
3956         return 0;
3957
3958 out_free_post_acts:
3959         free_flow_post_acts(flow);
3960
3961         return err;
3962 }
3963
3964 static int
3965 flow_action_supported(struct flow_action *flow_action,
3966                       struct netlink_ext_ack *extack)
3967 {
3968         if (!flow_action_has_entries(flow_action)) {
3969                 NL_SET_ERR_MSG_MOD(extack, "Flow action doesn't have any entries");
3970                 return -EINVAL;
3971         }
3972
3973         if (!flow_action_hw_stats_check(flow_action, extack,
3974                                         FLOW_ACTION_HW_STATS_DELAYED_BIT)) {
3975                 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
3976                 return -EOPNOTSUPP;
3977         }
3978
3979         return 0;
3980 }
3981
3982 static int
3983 parse_tc_nic_actions(struct mlx5e_priv *priv,
3984                      struct flow_action *flow_action,
3985                      struct mlx5e_tc_flow *flow,
3986                      struct netlink_ext_ack *extack)
3987 {
3988         struct mlx5e_tc_act_parse_state *parse_state;
3989         struct mlx5e_tc_flow_parse_attr *parse_attr;
3990         struct mlx5_flow_attr *attr = flow->attr;
3991         int err;
3992
3993         err = flow_action_supported(flow_action, extack);
3994         if (err)
3995                 return err;
3996
3997         attr->nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
3998         parse_attr = attr->parse_attr;
3999         parse_state = &parse_attr->parse_state;
4000         mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
4001         parse_state->ct_priv = get_ct_priv(priv);
4002
4003         err = parse_tc_actions(parse_state, flow_action);
4004         if (err)
4005                 return err;
4006
4007         err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
4008         if (err)
4009                 return err;
4010
4011         err = verify_attr_actions(attr->action, extack);
4012         if (err)
4013                 return err;
4014
4015         if (!actions_match_supported(priv, flow_action, parse_state->actions,
4016                                      parse_attr, flow, extack))
4017                 return -EOPNOTSUPP;
4018
4019         return 0;
4020 }
4021
4022 static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
4023                                   struct net_device *peer_netdev)
4024 {
4025         struct mlx5e_priv *peer_priv;
4026
4027         peer_priv = netdev_priv(peer_netdev);
4028
4029         return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
4030                 mlx5e_eswitch_vf_rep(priv->netdev) &&
4031                 mlx5e_eswitch_vf_rep(peer_netdev) &&
4032                 mlx5e_same_hw_devs(priv, peer_priv));
4033 }
4034
4035 static bool same_hw_reps(struct mlx5e_priv *priv,
4036                          struct net_device *peer_netdev)
4037 {
4038         struct mlx5e_priv *peer_priv;
4039
4040         peer_priv = netdev_priv(peer_netdev);
4041
4042         return mlx5e_eswitch_rep(priv->netdev) &&
4043                mlx5e_eswitch_rep(peer_netdev) &&
4044                mlx5e_same_hw_devs(priv, peer_priv);
4045 }
4046
4047 static bool is_lag_dev(struct mlx5e_priv *priv,
4048                        struct net_device *peer_netdev)
4049 {
4050         return ((mlx5_lag_is_sriov(priv->mdev) ||
4051                  mlx5_lag_is_multipath(priv->mdev)) &&
4052                  same_hw_reps(priv, peer_netdev));
4053 }
4054
4055 static bool is_multiport_eligible(struct mlx5e_priv *priv, struct net_device *out_dev)
4056 {
4057         return same_hw_reps(priv, out_dev) && mlx5_lag_is_mpesw(priv->mdev);
4058 }
4059
4060 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
4061                                     struct net_device *out_dev)
4062 {
4063         if (is_merged_eswitch_vfs(priv, out_dev))
4064                 return true;
4065
4066         if (is_multiport_eligible(priv, out_dev))
4067                 return true;
4068
4069         if (is_lag_dev(priv, out_dev))
4070                 return true;
4071
4072         return mlx5e_eswitch_rep(out_dev) &&
4073                same_port_devs(priv, netdev_priv(out_dev));
4074 }
4075
4076 int mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv *priv,
4077                                       struct mlx5_flow_attr *attr,
4078                                       int ifindex,
4079                                       enum mlx5e_tc_int_port_type type,
4080                                       u32 *action,
4081                                       int out_index)
4082 {
4083         struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4084         struct mlx5e_tc_int_port_priv *int_port_priv;
4085         struct mlx5e_tc_flow_parse_attr *parse_attr;
4086         struct mlx5e_tc_int_port *dest_int_port;
4087         int err;
4088
4089         parse_attr = attr->parse_attr;
4090         int_port_priv = mlx5e_get_int_port_priv(priv);
4091
4092         dest_int_port = mlx5e_tc_int_port_get(int_port_priv, ifindex, type);
4093         if (IS_ERR(dest_int_port))
4094                 return PTR_ERR(dest_int_port);
4095
4096         err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
4097                                         MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
4098                                         mlx5e_tc_int_port_get_metadata(dest_int_port));
4099         if (err) {
4100                 mlx5e_tc_int_port_put(int_port_priv, dest_int_port);
4101                 return err;
4102         }
4103
4104         *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
4105
4106         esw_attr->dest_int_port = dest_int_port;
4107         esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE;
4108         esw_attr->split_count = out_index;
4109
4110         /* Forward to root fdb for matching against the new source vport */
4111         attr->dest_chain = 0;
4112
4113         return 0;
4114 }
4115
4116 static int
4117 parse_tc_fdb_actions(struct mlx5e_priv *priv,
4118                      struct flow_action *flow_action,
4119                      struct mlx5e_tc_flow *flow,
4120                      struct netlink_ext_ack *extack)
4121 {
4122         struct mlx5e_tc_act_parse_state *parse_state;
4123         struct mlx5e_tc_flow_parse_attr *parse_attr;
4124         struct mlx5_flow_attr *attr = flow->attr;
4125         struct mlx5_esw_flow_attr *esw_attr;
4126         struct net_device *filter_dev;
4127         int err;
4128
4129         err = flow_action_supported(flow_action, extack);
4130         if (err)
4131                 return err;
4132
4133         esw_attr = attr->esw_attr;
4134         parse_attr = attr->parse_attr;
4135         filter_dev = parse_attr->filter_dev;
4136         parse_state = &parse_attr->parse_state;
4137         mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
4138         parse_state->ct_priv = get_ct_priv(priv);
4139
4140         err = parse_tc_actions(parse_state, flow_action);
4141         if (err)
4142                 return err;
4143
4144         /* Forward to/from internal port can only have 1 dest */
4145         if ((netif_is_ovs_master(filter_dev) || esw_attr->dest_int_port) &&
4146             esw_attr->out_count > 1) {
4147                 NL_SET_ERR_MSG_MOD(extack,
4148                                    "Rules with internal port can have only one destination");
4149                 return -EOPNOTSUPP;
4150         }
4151
4152         /* Forward from tunnel/internal port to internal port is not supported */
4153         if ((mlx5e_get_tc_tun(filter_dev) || netif_is_ovs_master(filter_dev)) &&
4154             esw_attr->dest_int_port) {
4155                 NL_SET_ERR_MSG_MOD(extack,
4156                                    "Forwarding from tunnel/internal port to internal port is not supported");
4157                 return -EOPNOTSUPP;
4158         }
4159
4160         err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
4161         if (err)
4162                 return err;
4163
4164         if (!actions_match_supported(priv, flow_action, parse_state->actions,
4165                                      parse_attr, flow, extack))
4166                 return -EOPNOTSUPP;
4167
4168         return 0;
4169 }
4170
4171 static void get_flags(int flags, unsigned long *flow_flags)
4172 {
4173         unsigned long __flow_flags = 0;
4174
4175         if (flags & MLX5_TC_FLAG(INGRESS))
4176                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4177         if (flags & MLX5_TC_FLAG(EGRESS))
4178                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
4179
4180         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4181                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4182         if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4183                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4184         if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4185                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
4186
4187         *flow_flags = __flow_flags;
4188 }
4189
4190 static const struct rhashtable_params tc_ht_params = {
4191         .head_offset = offsetof(struct mlx5e_tc_flow, node),
4192         .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4193         .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4194         .automatic_shrinking = true,
4195 };
4196
4197 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4198                                     unsigned long flags)
4199 {
4200         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
4201         struct mlx5e_rep_priv *rpriv;
4202
4203         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
4204                 rpriv = priv->ppriv;
4205                 return &rpriv->tc_ht;
4206         } else /* NIC offload */
4207                 return &tc->ht;
4208 }
4209
4210 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4211 {
4212         struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4213         struct mlx5_flow_attr *attr = flow->attr;
4214         bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
4215                 flow_flag_test(flow, INGRESS);
4216         bool act_is_encap = !!(attr->action &
4217                                MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
4218         bool esw_paired = mlx5_devcom_comp_is_ready(esw_attr->in_mdev->priv.devcom,
4219                                                     MLX5_DEVCOM_ESW_OFFLOADS);
4220
4221         if (!esw_paired)
4222                 return false;
4223
4224         if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4225              mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
4226             (is_rep_ingress || act_is_encap))
4227                 return true;
4228
4229         if (mlx5_lag_is_mpesw(esw_attr->in_mdev))
4230                 return true;
4231
4232         return false;
4233 }
4234
4235 struct mlx5_flow_attr *
4236 mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4237 {
4238         u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB)  ?
4239                                 sizeof(struct mlx5_esw_flow_attr) :
4240                                 sizeof(struct mlx5_nic_flow_attr);
4241         struct mlx5_flow_attr *attr;
4242
4243         attr = kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4244         if (!attr)
4245                 return attr;
4246
4247         INIT_LIST_HEAD(&attr->list);
4248         return attr;
4249 }
4250
4251 static void
4252 mlx5_free_flow_attr_actions(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
4253 {
4254         struct mlx5_core_dev *counter_dev = get_flow_counter_dev(flow);
4255
4256         if (!attr)
4257                 return;
4258
4259         if (attr->post_act_handle)
4260                 mlx5e_tc_post_act_del(get_post_action(flow->priv), attr->post_act_handle);
4261
4262         mlx5e_tc_tun_encap_dests_unset(flow->priv, flow, attr);
4263
4264         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
4265                 mlx5_fc_destroy(counter_dev, attr->counter);
4266
4267         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
4268                 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
4269                 mlx5e_tc_detach_mod_hdr(flow->priv, flow, attr);
4270         }
4271
4272         mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), attr);
4273
4274         free_branch_attr(flow, attr->branch_true);
4275         free_branch_attr(flow, attr->branch_false);
4276 }
4277
4278 static int
4279 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
4280                  struct flow_cls_offload *f, unsigned long flow_flags,
4281                  struct mlx5e_tc_flow_parse_attr **__parse_attr,
4282                  struct mlx5e_tc_flow **__flow)
4283 {
4284         struct mlx5e_tc_flow_parse_attr *parse_attr;
4285         struct mlx5_flow_attr *attr;
4286         struct mlx5e_tc_flow *flow;
4287         int err = -ENOMEM;
4288         int out_index;
4289
4290         flow = kzalloc(sizeof(*flow), GFP_KERNEL);
4291         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
4292         if (!parse_attr || !flow)
4293                 goto err_free;
4294
4295         flow->flags = flow_flags;
4296         flow->cookie = f->cookie;
4297         flow->priv = priv;
4298
4299         attr = mlx5_alloc_flow_attr(mlx5e_get_flow_namespace(flow));
4300         if (!attr)
4301                 goto err_free;
4302
4303         flow->attr = attr;
4304
4305         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4306                 INIT_LIST_HEAD(&flow->encaps[out_index].list);
4307         INIT_LIST_HEAD(&flow->hairpin);
4308         INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
4309         INIT_LIST_HEAD(&flow->attrs);
4310         INIT_LIST_HEAD(&flow->peer_flows);
4311         refcount_set(&flow->refcnt, 1);
4312         init_completion(&flow->init_done);
4313         init_completion(&flow->del_hw_done);
4314
4315         *__flow = flow;
4316         *__parse_attr = parse_attr;
4317
4318         return 0;
4319
4320 err_free:
4321         kfree(flow);
4322         kvfree(parse_attr);
4323         return err;
4324 }
4325
4326 static void
4327 mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4328                      struct mlx5e_tc_flow_parse_attr *parse_attr,
4329                      struct flow_cls_offload *f)
4330 {
4331         attr->parse_attr = parse_attr;
4332         attr->chain = f->common.chain_index;
4333         attr->prio = f->common.prio;
4334 }
4335
4336 static void
4337 mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
4338                          struct mlx5e_priv *priv,
4339                          struct mlx5e_tc_flow_parse_attr *parse_attr,
4340                          struct flow_cls_offload *f,
4341                          struct mlx5_eswitch_rep *in_rep,
4342                          struct mlx5_core_dev *in_mdev)
4343 {
4344         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4345         struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4346
4347         mlx5e_flow_attr_init(attr, parse_attr, f);
4348
4349         esw_attr->in_rep = in_rep;
4350         esw_attr->in_mdev = in_mdev;
4351
4352         if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4353             MLX5_COUNTER_SOURCE_ESWITCH)
4354                 esw_attr->counter_dev = in_mdev;
4355         else
4356                 esw_attr->counter_dev = priv->mdev;
4357 }
4358
4359 static struct mlx5e_tc_flow *
4360 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4361                      struct flow_cls_offload *f,
4362                      unsigned long flow_flags,
4363                      struct net_device *filter_dev,
4364                      struct mlx5_eswitch_rep *in_rep,
4365                      struct mlx5_core_dev *in_mdev)
4366 {
4367         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4368         struct netlink_ext_ack *extack = f->common.extack;
4369         struct mlx5e_tc_flow_parse_attr *parse_attr;
4370         struct mlx5e_tc_flow *flow;
4371         int attr_size, err;
4372
4373         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4374         attr_size  = sizeof(struct mlx5_esw_flow_attr);
4375         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4376                                &parse_attr, &flow);
4377         if (err)
4378                 goto out;
4379
4380         parse_attr->filter_dev = filter_dev;
4381         mlx5e_flow_esw_attr_init(flow->attr,
4382                                  priv, parse_attr,
4383                                  f, in_rep, in_mdev);
4384
4385         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4386                                f, filter_dev);
4387         if (err)
4388                 goto err_free;
4389
4390         /* actions validation depends on parsing the ct matches first */
4391         err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4392                                    &flow->attr->ct_attr, extack);
4393         if (err)
4394                 goto err_free;
4395
4396         err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4397         if (err)
4398                 goto err_free;
4399
4400         err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
4401         complete_all(&flow->init_done);
4402         if (err) {
4403                 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4404                         goto err_free;
4405
4406                 add_unready_flow(flow);
4407         }
4408
4409         return flow;
4410
4411 err_free:
4412         mlx5e_flow_put(priv, flow);
4413 out:
4414         return ERR_PTR(err);
4415 }
4416
4417 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
4418                                       struct mlx5e_tc_flow *flow,
4419                                       unsigned long flow_flags,
4420                                       struct mlx5_eswitch *peer_esw)
4421 {
4422         struct mlx5e_priv *priv = flow->priv, *peer_priv;
4423         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4424         struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
4425         struct mlx5e_tc_flow_parse_attr *parse_attr;
4426         int i = mlx5_get_dev_index(peer_esw->dev);
4427         struct mlx5e_rep_priv *peer_urpriv;
4428         struct mlx5e_tc_flow *peer_flow;
4429         struct mlx5_core_dev *in_mdev;
4430         int err = 0;
4431
4432         peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4433         peer_priv = netdev_priv(peer_urpriv->netdev);
4434
4435         /* in_mdev is assigned of which the packet originated from.
4436          * So packets redirected to uplink use the same mdev of the
4437          * original flow and packets redirected from uplink use the
4438          * peer mdev.
4439          * In multiport eswitch it's a special case that we need to
4440          * keep the original mdev.
4441          */
4442         if (attr->in_rep->vport == MLX5_VPORT_UPLINK && !mlx5_lag_is_mpesw(priv->mdev))
4443                 in_mdev = peer_priv->mdev;
4444         else
4445                 in_mdev = priv->mdev;
4446
4447         parse_attr = flow->attr->parse_attr;
4448         peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
4449                                          parse_attr->filter_dev,
4450                                          attr->in_rep, in_mdev);
4451         if (IS_ERR(peer_flow)) {
4452                 err = PTR_ERR(peer_flow);
4453                 goto out;
4454         }
4455
4456         list_add_tail(&peer_flow->peer_flows, &flow->peer_flows);
4457         flow_flag_set(flow, DUP);
4458         mutex_lock(&esw->offloads.peer_mutex);
4459         list_add_tail(&flow->peer[i], &esw->offloads.peer_flows[i]);
4460         mutex_unlock(&esw->offloads.peer_mutex);
4461
4462 out:
4463         return err;
4464 }
4465
4466 static int
4467 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4468                    struct flow_cls_offload *f,
4469                    unsigned long flow_flags,
4470                    struct net_device *filter_dev,
4471                    struct mlx5e_tc_flow **__flow)
4472 {
4473         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4474         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4475         struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4476         struct mlx5_core_dev *in_mdev = priv->mdev;
4477         struct mlx5_eswitch *peer_esw;
4478         struct mlx5e_tc_flow *flow;
4479         int err;
4480         int i;
4481
4482         flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4483                                     in_mdev);
4484         if (IS_ERR(flow))
4485                 return PTR_ERR(flow);
4486
4487         if (!is_peer_flow_needed(flow)) {
4488                 *__flow = flow;
4489                 return 0;
4490         }
4491
4492         if (!mlx5_devcom_for_each_peer_begin(devcom, MLX5_DEVCOM_ESW_OFFLOADS)) {
4493                 err = -ENODEV;
4494                 goto clean_flow;
4495         }
4496
4497         mlx5_devcom_for_each_peer_entry(devcom,
4498                                         MLX5_DEVCOM_ESW_OFFLOADS,
4499                                         peer_esw, i) {
4500                 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags, peer_esw);
4501                 if (err)
4502                         goto peer_clean;
4503         }
4504
4505         mlx5_devcom_for_each_peer_end(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4506
4507         *__flow = flow;
4508         return 0;
4509
4510 peer_clean:
4511         mlx5e_tc_del_fdb_peers_flow(flow);
4512         mlx5_devcom_for_each_peer_end(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4513 clean_flow:
4514         mlx5e_tc_del_fdb_flow(priv, flow);
4515         return err;
4516 }
4517
4518 static int
4519 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
4520                    struct flow_cls_offload *f,
4521                    unsigned long flow_flags,
4522                    struct net_device *filter_dev,
4523                    struct mlx5e_tc_flow **__flow)
4524 {
4525         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4526         struct netlink_ext_ack *extack = f->common.extack;
4527         struct mlx5e_tc_flow_parse_attr *parse_attr;
4528         struct mlx5e_tc_flow *flow;
4529         int attr_size, err;
4530
4531         if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4532                 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4533                         return -EOPNOTSUPP;
4534         } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
4535                 return -EOPNOTSUPP;
4536         }
4537
4538         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4539         attr_size  = sizeof(struct mlx5_nic_flow_attr);
4540         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4541                                &parse_attr, &flow);
4542         if (err)
4543                 goto out;
4544
4545         parse_attr->filter_dev = filter_dev;
4546         mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4547
4548         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4549                                f, filter_dev);
4550         if (err)
4551                 goto err_free;
4552
4553         err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4554                                    &flow->attr->ct_attr, extack);
4555         if (err)
4556                 goto err_free;
4557
4558         err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
4559         if (err)
4560                 goto err_free;
4561
4562         err = mlx5e_tc_add_nic_flow(priv, flow, extack);
4563         if (err)
4564                 goto err_free;
4565
4566         flow_flag_set(flow, OFFLOADED);
4567         *__flow = flow;
4568
4569         return 0;
4570
4571 err_free:
4572         flow_flag_set(flow, FAILED);
4573         mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
4574         mlx5e_flow_put(priv, flow);
4575 out:
4576         return err;
4577 }
4578
4579 static int
4580 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
4581                   struct flow_cls_offload *f,
4582                   unsigned long flags,
4583                   struct net_device *filter_dev,
4584                   struct mlx5e_tc_flow **flow)
4585 {
4586         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4587         unsigned long flow_flags;
4588         int err;
4589
4590         get_flags(flags, &flow_flags);
4591
4592         if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4593                 return -EOPNOTSUPP;
4594
4595         if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
4596                 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4597                                          filter_dev, flow);
4598         else
4599                 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4600                                          filter_dev, flow);
4601
4602         return err;
4603 }
4604
4605 static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4606                                            struct mlx5e_rep_priv *rpriv)
4607 {
4608         /* Offloaded flow rule is allowed to duplicate on non-uplink representor
4609          * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4610          * function is called from NIC mode.
4611          */
4612         return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
4613 }
4614
4615 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
4616                            struct flow_cls_offload *f, unsigned long flags)
4617 {
4618         struct netlink_ext_ack *extack = f->common.extack;
4619         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4620         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4621         struct mlx5e_tc_flow *flow;
4622         int err = 0;
4623
4624         if (!mlx5_esw_hold(priv->mdev))
4625                 return -EBUSY;
4626
4627         mlx5_esw_get(priv->mdev);
4628
4629         rcu_read_lock();
4630         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4631         if (flow) {
4632                 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4633                  * just return 0.
4634                  */
4635                 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
4636                         goto rcu_unlock;
4637
4638                 NL_SET_ERR_MSG_MOD(extack,
4639                                    "flow cookie already exists, ignoring");
4640                 netdev_warn_once(priv->netdev,
4641                                  "flow cookie %lx already exists, ignoring\n",
4642                                  f->cookie);
4643                 err = -EEXIST;
4644                 goto rcu_unlock;
4645         }
4646 rcu_unlock:
4647         rcu_read_unlock();
4648         if (flow)
4649                 goto out;
4650
4651         trace_mlx5e_configure_flower(f);
4652         err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
4653         if (err)
4654                 goto out;
4655
4656         /* Flow rule offloaded to non-uplink representor sharing tc block,
4657          * set the flow's owner dev.
4658          */
4659         if (is_flow_rule_duplicate_allowed(dev, rpriv))
4660                 flow->orig_dev = dev;
4661
4662         err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
4663         if (err)
4664                 goto err_free;
4665
4666         mlx5_esw_release(priv->mdev);
4667         return 0;
4668
4669 err_free:
4670         mlx5e_flow_put(priv, flow);
4671 out:
4672         mlx5_esw_put(priv->mdev);
4673         mlx5_esw_release(priv->mdev);
4674         return err;
4675 }
4676
4677 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4678 {
4679         bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4680         bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
4681
4682         return flow_flag_test(flow, INGRESS) == dir_ingress &&
4683                 flow_flag_test(flow, EGRESS) == dir_egress;
4684 }
4685
4686 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
4687                         struct flow_cls_offload *f, unsigned long flags)
4688 {
4689         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4690         struct mlx5e_tc_flow *flow;
4691         int err;
4692
4693         rcu_read_lock();
4694         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4695         if (!flow || !same_flow_direction(flow, flags)) {
4696                 err = -EINVAL;
4697                 goto errout;
4698         }
4699
4700         /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4701          * set.
4702          */
4703         if (flow_flag_test_and_set(flow, DELETED)) {
4704                 err = -EINVAL;
4705                 goto errout;
4706         }
4707         rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
4708         rcu_read_unlock();
4709
4710         trace_mlx5e_delete_flower(f);
4711         mlx5e_flow_put(priv, flow);
4712
4713         mlx5_esw_put(priv->mdev);
4714         return 0;
4715
4716 errout:
4717         rcu_read_unlock();
4718         return err;
4719 }
4720
4721 int mlx5e_tc_fill_action_stats(struct mlx5e_priv *priv,
4722                                struct flow_offload_action *fl_act)
4723 {
4724         return mlx5e_tc_act_stats_fill_stats(get_act_stats_handle(priv), fl_act);
4725 }
4726
4727 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
4728                        struct flow_cls_offload *f, unsigned long flags)
4729 {
4730         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4731         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4732         struct mlx5e_tc_flow *flow;
4733         struct mlx5_fc *counter;
4734         u64 lastuse = 0;
4735         u64 packets = 0;
4736         u64 bytes = 0;
4737         int err = 0;
4738
4739         rcu_read_lock();
4740         flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4741                                                 tc_ht_params));
4742         rcu_read_unlock();
4743         if (IS_ERR(flow))
4744                 return PTR_ERR(flow);
4745
4746         if (!same_flow_direction(flow, flags)) {
4747                 err = -EINVAL;
4748                 goto errout;
4749         }
4750
4751         if (mlx5e_is_offloaded_flow(flow)) {
4752                 if (flow_flag_test(flow, USE_ACT_STATS)) {
4753                         f->use_act_stats = true;
4754                 } else {
4755                         counter = mlx5e_tc_get_counter(flow);
4756                         if (!counter)
4757                                 goto errout;
4758
4759                         mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4760                 }
4761         }
4762
4763         /* Under multipath it's possible for one rule to be currently
4764          * un-offloaded while the other rule is offloaded.
4765          */
4766         if (!mlx5_devcom_for_each_peer_begin(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
4767                 goto out;
4768
4769         if (flow_flag_test(flow, DUP)) {
4770                 struct mlx5e_tc_flow *peer_flow;
4771
4772                 list_for_each_entry(peer_flow, &flow->peer_flows, peer_flows) {
4773                         u64 packets2;
4774                         u64 lastuse2;
4775                         u64 bytes2;
4776
4777                         if (!flow_flag_test(peer_flow, OFFLOADED))
4778                                 continue;
4779                         if (flow_flag_test(flow, USE_ACT_STATS)) {
4780                                 f->use_act_stats = true;
4781                                 break;
4782                         }
4783
4784                         counter = mlx5e_tc_get_counter(peer_flow);
4785                         if (!counter)
4786                                 goto no_peer_counter;
4787                         mlx5_fc_query_cached(counter, &bytes2, &packets2,
4788                                              &lastuse2);
4789
4790                         bytes += bytes2;
4791                         packets += packets2;
4792                         lastuse = max_t(u64, lastuse, lastuse2);
4793                 }
4794         }
4795
4796 no_peer_counter:
4797         mlx5_devcom_for_each_peer_end(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4798 out:
4799         flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
4800                           FLOW_ACTION_HW_STATS_DELAYED);
4801         trace_mlx5e_stats_flower(f);
4802 errout:
4803         mlx5e_flow_put(priv, flow);
4804         return err;
4805 }
4806
4807 static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
4808                                struct netlink_ext_ack *extack)
4809 {
4810         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4811         struct mlx5_eswitch *esw;
4812         u32 rate_mbps = 0;
4813         u16 vport_num;
4814         int err;
4815
4816         vport_num = rpriv->rep->vport;
4817         if (vport_num >= MLX5_VPORT_ECPF) {
4818                 NL_SET_ERR_MSG_MOD(extack,
4819                                    "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4820                 return -EOPNOTSUPP;
4821         }
4822
4823         esw = priv->mdev->priv.eswitch;
4824         /* rate is given in bytes/sec.
4825          * First convert to bits/sec and then round to the nearest mbit/secs.
4826          * mbit means million bits.
4827          * Moreover, if rate is non zero we choose to configure to a minimum of
4828          * 1 mbit/sec.
4829          */
4830         if (rate) {
4831                 rate = (rate * BITS_PER_BYTE) + 500000;
4832                 do_div(rate, 1000000);
4833                 rate_mbps = max_t(u32, rate, 1);
4834         }
4835
4836         err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
4837         if (err)
4838                 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4839
4840         return err;
4841 }
4842
4843 static int
4844 tc_matchall_police_validate(const struct flow_action *action,
4845                             const struct flow_action_entry *act,
4846                             struct netlink_ext_ack *extack)
4847 {
4848         if (act->police.notexceed.act_id != FLOW_ACTION_CONTINUE) {
4849                 NL_SET_ERR_MSG_MOD(extack,
4850                                    "Offload not supported when conform action is not continue");
4851                 return -EOPNOTSUPP;
4852         }
4853
4854         if (act->police.exceed.act_id != FLOW_ACTION_DROP) {
4855                 NL_SET_ERR_MSG_MOD(extack,
4856                                    "Offload not supported when exceed action is not drop");
4857                 return -EOPNOTSUPP;
4858         }
4859
4860         if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT &&
4861             !flow_action_is_last_entry(action, act)) {
4862                 NL_SET_ERR_MSG_MOD(extack,
4863                                    "Offload not supported when conform action is ok, but action is not last");
4864                 return -EOPNOTSUPP;
4865         }
4866
4867         if (act->police.peakrate_bytes_ps ||
4868             act->police.avrate || act->police.overhead) {
4869                 NL_SET_ERR_MSG_MOD(extack,
4870                                    "Offload not supported when peakrate/avrate/overhead is configured");
4871                 return -EOPNOTSUPP;
4872         }
4873
4874         return 0;
4875 }
4876
4877 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4878                                         struct flow_action *flow_action,
4879                                         struct netlink_ext_ack *extack)
4880 {
4881         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4882         const struct flow_action_entry *act;
4883         int err;
4884         int i;
4885
4886         if (!flow_action_has_entries(flow_action)) {
4887                 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4888                 return -EINVAL;
4889         }
4890
4891         if (!flow_offload_has_one_action(flow_action)) {
4892                 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4893                 return -EOPNOTSUPP;
4894         }
4895
4896         if (!flow_action_basic_hw_stats_check(flow_action, extack)) {
4897                 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
4898                 return -EOPNOTSUPP;
4899         }
4900
4901         flow_action_for_each(i, act, flow_action) {
4902                 switch (act->id) {
4903                 case FLOW_ACTION_POLICE:
4904                         err = tc_matchall_police_validate(flow_action, act, extack);
4905                         if (err)
4906                                 return err;
4907
4908                         err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4909                         if (err)
4910                                 return err;
4911
4912                         rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4913                         break;
4914                 default:
4915                         NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4916                         return -EOPNOTSUPP;
4917                 }
4918         }
4919
4920         return 0;
4921 }
4922
4923 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4924                                 struct tc_cls_matchall_offload *ma)
4925 {
4926         struct netlink_ext_ack *extack = ma->common.extack;
4927
4928         if (ma->common.prio != 1) {
4929                 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4930                 return -EINVAL;
4931         }
4932
4933         return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4934 }
4935
4936 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4937                              struct tc_cls_matchall_offload *ma)
4938 {
4939         struct netlink_ext_ack *extack = ma->common.extack;
4940
4941         return apply_police_params(priv, 0, extack);
4942 }
4943
4944 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4945                              struct tc_cls_matchall_offload *ma)
4946 {
4947         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4948         struct rtnl_link_stats64 cur_stats;
4949         u64 dbytes;
4950         u64 dpkts;
4951
4952         cur_stats = priv->stats.vf_vport;
4953         dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4954         dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4955         rpriv->prev_vf_vport_stats = cur_stats;
4956         flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
4957                           FLOW_ACTION_HW_STATS_DELAYED);
4958 }
4959
4960 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4961                                               struct mlx5e_priv *peer_priv)
4962 {
4963         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
4964         struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
4965         struct mlx5e_hairpin_entry *hpe, *tmp;
4966         LIST_HEAD(init_wait_list);
4967         u16 peer_vhca_id;
4968         int bkt;
4969
4970         if (!mlx5e_same_hw_devs(priv, peer_priv))
4971                 return;
4972
4973         peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4974
4975         mutex_lock(&tc->hairpin_tbl_lock);
4976         hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
4977                 if (refcount_inc_not_zero(&hpe->refcnt))
4978                         list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4979         mutex_unlock(&tc->hairpin_tbl_lock);
4980
4981         list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4982                 wait_for_completion(&hpe->res_ready);
4983                 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4984                         mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
4985
4986                 mlx5e_hairpin_put(priv, hpe);
4987         }
4988 }
4989
4990 static int mlx5e_tc_netdev_event(struct notifier_block *this,
4991                                  unsigned long event, void *ptr)
4992 {
4993         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4994         struct mlx5e_priv *peer_priv;
4995         struct mlx5e_tc_table *tc;
4996         struct mlx5e_priv *priv;
4997
4998         if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4999             event != NETDEV_UNREGISTER ||
5000             ndev->reg_state == NETREG_REGISTERED)
5001                 return NOTIFY_DONE;
5002
5003         tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
5004         priv = tc->priv;
5005         peer_priv = netdev_priv(ndev);
5006         if (priv == peer_priv ||
5007             !(priv->netdev->features & NETIF_F_HW_TC))
5008                 return NOTIFY_DONE;
5009
5010         mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
5011
5012         return NOTIFY_DONE;
5013 }
5014
5015 static int mlx5e_tc_nic_create_miss_table(struct mlx5e_priv *priv)
5016 {
5017         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5018         struct mlx5_flow_table **ft = &tc->miss_t;
5019         struct mlx5_flow_table_attr ft_attr = {};
5020         struct mlx5_flow_namespace *ns;
5021         int err = 0;
5022
5023         ft_attr.max_fte = 1;
5024         ft_attr.autogroup.max_num_groups = 1;
5025         ft_attr.level = MLX5E_TC_MISS_LEVEL;
5026         ft_attr.prio = 0;
5027         ns = mlx5_get_flow_namespace(priv->mdev, MLX5_FLOW_NAMESPACE_KERNEL);
5028
5029         *ft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
5030         if (IS_ERR(*ft)) {
5031                 err = PTR_ERR(*ft);
5032                 netdev_err(priv->netdev, "failed to create tc nic miss table err=%d\n", err);
5033         }
5034
5035         return err;
5036 }
5037
5038 static void mlx5e_tc_nic_destroy_miss_table(struct mlx5e_priv *priv)
5039 {
5040         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5041
5042         mlx5_destroy_flow_table(tc->miss_t);
5043 }
5044
5045 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
5046 {
5047         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5048         struct mlx5_core_dev *dev = priv->mdev;
5049         struct mapping_ctx *chains_mapping;
5050         struct mlx5_chains_attr attr = {};
5051         u64 mapping_id;
5052         int err;
5053
5054         mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
5055         mutex_init(&tc->t_lock);
5056         mutex_init(&tc->hairpin_tbl_lock);
5057         hash_init(tc->hairpin_tbl);
5058         tc->priv = priv;
5059
5060         err = rhashtable_init(&tc->ht, &tc_ht_params);
5061         if (err)
5062                 return err;
5063
5064         lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
5065         lockdep_init_map(&tc->ht.run_work.lockdep_map, "tc_ht_wq_key", &tc_ht_wq_key, 0);
5066
5067         mapping_id = mlx5_query_nic_system_image_guid(dev);
5068
5069         chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
5070                                                sizeof(struct mlx5_mapped_obj),
5071                                                MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
5072
5073         if (IS_ERR(chains_mapping)) {
5074                 err = PTR_ERR(chains_mapping);
5075                 goto err_mapping;
5076         }
5077         tc->mapping = chains_mapping;
5078
5079         err = mlx5e_tc_nic_create_miss_table(priv);
5080         if (err)
5081                 goto err_chains;
5082
5083         if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
5084                 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
5085                         MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
5086         attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
5087         attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
5088         attr.default_ft = tc->miss_t;
5089         attr.mapping = chains_mapping;
5090         attr.fs_base_prio = MLX5E_TC_PRIO;
5091
5092         tc->chains = mlx5_chains_create(dev, &attr);
5093         if (IS_ERR(tc->chains)) {
5094                 err = PTR_ERR(tc->chains);
5095                 goto err_miss;
5096         }
5097
5098         mlx5_chains_print_info(tc->chains);
5099
5100         tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
5101         tc->ct = mlx5_tc_ct_init(priv, tc->chains, &tc->mod_hdr,
5102                                  MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
5103
5104         tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
5105         err = register_netdevice_notifier_dev_net(priv->netdev,
5106                                                   &tc->netdevice_nb,
5107                                                   &tc->netdevice_nn);
5108         if (err) {
5109                 tc->netdevice_nb.notifier_call = NULL;
5110                 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
5111                 goto err_reg;
5112         }
5113
5114         mlx5e_tc_debugfs_init(tc, mlx5e_fs_get_debugfs_root(priv->fs));
5115
5116         tc->action_stats_handle = mlx5e_tc_act_stats_create();
5117         if (IS_ERR(tc->action_stats_handle)) {
5118                 err = PTR_ERR(tc->action_stats_handle);
5119                 goto err_act_stats;
5120         }
5121
5122         return 0;
5123
5124 err_act_stats:
5125         unregister_netdevice_notifier_dev_net(priv->netdev,
5126                                               &tc->netdevice_nb,
5127                                               &tc->netdevice_nn);
5128 err_reg:
5129         mlx5_tc_ct_clean(tc->ct);
5130         mlx5e_tc_post_act_destroy(tc->post_act);
5131         mlx5_chains_destroy(tc->chains);
5132 err_miss:
5133         mlx5e_tc_nic_destroy_miss_table(priv);
5134 err_chains:
5135         mapping_destroy(chains_mapping);
5136 err_mapping:
5137         rhashtable_destroy(&tc->ht);
5138         return err;
5139 }
5140
5141 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5142 {
5143         struct mlx5e_tc_flow *flow = ptr;
5144         struct mlx5e_priv *priv = flow->priv;
5145
5146         mlx5e_tc_del_flow(priv, flow);
5147         kfree(flow);
5148 }
5149
5150 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
5151 {
5152         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5153
5154         debugfs_remove_recursive(tc->dfs_root);
5155
5156         if (tc->netdevice_nb.notifier_call)
5157                 unregister_netdevice_notifier_dev_net(priv->netdev,
5158                                                       &tc->netdevice_nb,
5159                                                       &tc->netdevice_nn);
5160
5161         mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
5162         mutex_destroy(&tc->hairpin_tbl_lock);
5163
5164         rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
5165
5166         if (!IS_ERR_OR_NULL(tc->t)) {
5167                 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
5168                 tc->t = NULL;
5169         }
5170         mutex_destroy(&tc->t_lock);
5171
5172         mlx5_tc_ct_clean(tc->ct);
5173         mlx5e_tc_post_act_destroy(tc->post_act);
5174         mapping_destroy(tc->mapping);
5175         mlx5_chains_destroy(tc->chains);
5176         mlx5e_tc_nic_destroy_miss_table(priv);
5177         mlx5e_tc_act_stats_free(tc->action_stats_handle);
5178 }
5179
5180 int mlx5e_tc_ht_init(struct rhashtable *tc_ht)
5181 {
5182         int err;
5183
5184         err = rhashtable_init(tc_ht, &tc_ht_params);
5185         if (err)
5186                 return err;
5187
5188         lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5189         lockdep_init_map(&tc_ht->run_work.lockdep_map, "tc_ht_wq_key", &tc_ht_wq_key, 0);
5190
5191         return 0;
5192 }
5193
5194 void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht)
5195 {
5196         rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5197 }
5198
5199 int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *uplink_priv)
5200 {
5201         const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
5202         struct mlx5e_rep_priv *rpriv;
5203         struct mapping_ctx *mapping;
5204         struct mlx5_eswitch *esw;
5205         struct mlx5e_priv *priv;
5206         u64 mapping_id;
5207         int err = 0;
5208
5209         rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5210         priv = netdev_priv(rpriv->netdev);
5211         esw = priv->mdev->priv.eswitch;
5212
5213         uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
5214                                                        MLX5_FLOW_NAMESPACE_FDB);
5215         uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5216                                                esw_chains(esw),
5217                                                &esw->offloads.mod_hdr,
5218                                                MLX5_FLOW_NAMESPACE_FDB,
5219                                                uplink_priv->post_act);
5220
5221         uplink_priv->int_port_priv = mlx5e_tc_int_port_init(netdev_priv(priv->netdev));
5222
5223         uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
5224
5225         mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
5226
5227         mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
5228                                         sizeof(struct tunnel_match_key),
5229                                         TUNNEL_INFO_BITS_MASK, true);
5230
5231         if (IS_ERR(mapping)) {
5232                 err = PTR_ERR(mapping);
5233                 goto err_tun_mapping;
5234         }
5235         uplink_priv->tunnel_mapping = mapping;
5236
5237         /* Two last values are reserved for stack devices slow path table mark
5238          * and bridge ingress push mark.
5239          */
5240         mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
5241                                         sz_enc_opts, ENC_OPTS_BITS_MASK - 2, true);
5242         if (IS_ERR(mapping)) {
5243                 err = PTR_ERR(mapping);
5244                 goto err_enc_opts_mapping;
5245         }
5246         uplink_priv->tunnel_enc_opts_mapping = mapping;
5247
5248         uplink_priv->encap = mlx5e_tc_tun_init(priv);
5249         if (IS_ERR(uplink_priv->encap)) {
5250                 err = PTR_ERR(uplink_priv->encap);
5251                 goto err_register_fib_notifier;
5252         }
5253
5254         uplink_priv->action_stats_handle = mlx5e_tc_act_stats_create();
5255         if (IS_ERR(uplink_priv->action_stats_handle)) {
5256                 err = PTR_ERR(uplink_priv->action_stats_handle);
5257                 goto err_action_counter;
5258         }
5259
5260         mlx5_esw_offloads_devcom_init(esw);
5261
5262         return 0;
5263
5264 err_action_counter:
5265         mlx5e_tc_tun_cleanup(uplink_priv->encap);
5266 err_register_fib_notifier:
5267         mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5268 err_enc_opts_mapping:
5269         mapping_destroy(uplink_priv->tunnel_mapping);
5270 err_tun_mapping:
5271         mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
5272         mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
5273         mlx5_tc_ct_clean(uplink_priv->ct_priv);
5274         netdev_warn(priv->netdev,
5275                     "Failed to initialize tc (eswitch), err: %d", err);
5276         mlx5e_tc_post_act_destroy(uplink_priv->post_act);
5277         return err;
5278 }
5279
5280 void mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv *uplink_priv)
5281 {
5282         struct mlx5e_rep_priv *rpriv;
5283         struct mlx5_eswitch *esw;
5284         struct mlx5e_priv *priv;
5285
5286         rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5287         priv = netdev_priv(rpriv->netdev);
5288         esw = priv->mdev->priv.eswitch;
5289
5290         mlx5_esw_offloads_devcom_cleanup(esw);
5291
5292         mlx5e_tc_tun_cleanup(uplink_priv->encap);
5293
5294         mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5295         mapping_destroy(uplink_priv->tunnel_mapping);
5296
5297         mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
5298         mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
5299         mlx5_tc_ct_clean(uplink_priv->ct_priv);
5300         mlx5e_flow_meters_cleanup(uplink_priv->flow_meters);
5301         mlx5e_tc_post_act_destroy(uplink_priv->post_act);
5302         mlx5e_tc_act_stats_free(uplink_priv->action_stats_handle);
5303 }
5304
5305 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
5306 {
5307         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
5308
5309         return atomic_read(&tc_ht->nelems);
5310 }
5311
5312 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5313 {
5314         struct mlx5e_tc_flow *flow, *tmp;
5315         int i;
5316
5317         for (i = 0; i < MLX5_MAX_PORTS; i++) {
5318                 if (i == mlx5_get_dev_index(esw->dev))
5319                         continue;
5320                 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows[i], peer[i])
5321                         mlx5e_tc_del_fdb_peers_flow(flow);
5322         }
5323 }
5324
5325 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5326 {
5327         struct mlx5_rep_uplink_priv *rpriv =
5328                 container_of(work, struct mlx5_rep_uplink_priv,
5329                              reoffload_flows_work);
5330         struct mlx5e_tc_flow *flow, *tmp;
5331
5332         mutex_lock(&rpriv->unready_flows_lock);
5333         list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5334                 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
5335                         unready_flow_del(flow);
5336         }
5337         mutex_unlock(&rpriv->unready_flows_lock);
5338 }
5339
5340 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5341                                      struct flow_cls_offload *cls_flower,
5342                                      unsigned long flags)
5343 {
5344         switch (cls_flower->command) {
5345         case FLOW_CLS_REPLACE:
5346                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5347                                               flags);
5348         case FLOW_CLS_DESTROY:
5349                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5350                                            flags);
5351         case FLOW_CLS_STATS:
5352                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5353                                           flags);
5354         default:
5355                 return -EOPNOTSUPP;
5356         }
5357 }
5358
5359 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5360                             void *cb_priv)
5361 {
5362         unsigned long flags = MLX5_TC_FLAG(INGRESS);
5363         struct mlx5e_priv *priv = cb_priv;
5364
5365         if (!priv->netdev || !netif_device_present(priv->netdev))
5366                 return -EOPNOTSUPP;
5367
5368         if (mlx5e_is_uplink_rep(priv))
5369                 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5370         else
5371                 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5372
5373         switch (type) {
5374         case TC_SETUP_CLSFLOWER:
5375                 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5376         default:
5377                 return -EOPNOTSUPP;
5378         }
5379 }
5380
5381 static bool mlx5e_tc_restore_tunnel(struct mlx5e_priv *priv, struct sk_buff *skb,
5382                                     struct mlx5e_tc_update_priv *tc_priv,
5383                                     u32 tunnel_id)
5384 {
5385         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5386         struct tunnel_match_enc_opts enc_opts = {};
5387         struct mlx5_rep_uplink_priv *uplink_priv;
5388         struct mlx5e_rep_priv *uplink_rpriv;
5389         struct metadata_dst *tun_dst;
5390         struct tunnel_match_key key;
5391         u32 tun_id, enc_opts_id;
5392         struct net_device *dev;
5393         int err;
5394
5395         enc_opts_id = tunnel_id & ENC_OPTS_BITS_MASK;
5396         tun_id = tunnel_id >> ENC_OPTS_BITS;
5397
5398         if (!tun_id)
5399                 return true;
5400
5401         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5402         uplink_priv = &uplink_rpriv->uplink_priv;
5403
5404         err = mapping_find(uplink_priv->tunnel_mapping, tun_id, &key);
5405         if (err) {
5406                 netdev_dbg(priv->netdev,
5407                            "Couldn't find tunnel for tun_id: %d, err: %d\n",
5408                            tun_id, err);
5409                 return false;
5410         }
5411
5412         if (enc_opts_id) {
5413                 err = mapping_find(uplink_priv->tunnel_enc_opts_mapping,
5414                                    enc_opts_id, &enc_opts);
5415                 if (err) {
5416                         netdev_dbg(priv->netdev,
5417                                    "Couldn't find tunnel (opts) for tun_id: %d, err: %d\n",
5418                                    enc_opts_id, err);
5419                         return false;
5420                 }
5421         }
5422
5423         switch (key.enc_control.addr_type) {
5424         case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
5425                 tun_dst = __ip_tun_set_dst(key.enc_ipv4.src, key.enc_ipv4.dst,
5426                                            key.enc_ip.tos, key.enc_ip.ttl,
5427                                            key.enc_tp.dst, TUNNEL_KEY,
5428                                            key32_to_tunnel_id(key.enc_key_id.keyid),
5429                                            enc_opts.key.len);
5430                 break;
5431         case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
5432                 tun_dst = __ipv6_tun_set_dst(&key.enc_ipv6.src, &key.enc_ipv6.dst,
5433                                              key.enc_ip.tos, key.enc_ip.ttl,
5434                                              key.enc_tp.dst, 0, TUNNEL_KEY,
5435                                              key32_to_tunnel_id(key.enc_key_id.keyid),
5436                                              enc_opts.key.len);
5437                 break;
5438         default:
5439                 netdev_dbg(priv->netdev,
5440                            "Couldn't restore tunnel, unsupported addr_type: %d\n",
5441                            key.enc_control.addr_type);
5442                 return false;
5443         }
5444
5445         if (!tun_dst) {
5446                 netdev_dbg(priv->netdev, "Couldn't restore tunnel, no tun_dst\n");
5447                 return false;
5448         }
5449
5450         tun_dst->u.tun_info.key.tp_src = key.enc_tp.src;
5451
5452         if (enc_opts.key.len)
5453                 ip_tunnel_info_opts_set(&tun_dst->u.tun_info,
5454                                         enc_opts.key.data,
5455                                         enc_opts.key.len,
5456                                         enc_opts.key.dst_opt_type);
5457
5458         skb_dst_set(skb, (struct dst_entry *)tun_dst);
5459         dev = dev_get_by_index(&init_net, key.filter_ifindex);
5460         if (!dev) {
5461                 netdev_dbg(priv->netdev,
5462                            "Couldn't find tunnel device with ifindex: %d\n",
5463                            key.filter_ifindex);
5464                 return false;
5465         }
5466
5467         /* Set fwd_dev so we do dev_put() after datapath */
5468         tc_priv->fwd_dev = dev;
5469
5470         skb->dev = dev;
5471
5472         return true;
5473 }
5474
5475 static bool mlx5e_tc_restore_skb_tc_meta(struct sk_buff *skb, struct mlx5_tc_ct_priv *ct_priv,
5476                                          struct mlx5_mapped_obj *mapped_obj, u32 zone_restore_id,
5477                                          u32 tunnel_id,  struct mlx5e_tc_update_priv *tc_priv)
5478 {
5479         struct mlx5e_priv *priv = netdev_priv(skb->dev);
5480         struct tc_skb_ext *tc_skb_ext;
5481         u64 act_miss_cookie;
5482         u32 chain;
5483
5484         chain = mapped_obj->type == MLX5_MAPPED_OBJ_CHAIN ? mapped_obj->chain : 0;
5485         act_miss_cookie = mapped_obj->type == MLX5_MAPPED_OBJ_ACT_MISS ?
5486                           mapped_obj->act_miss_cookie : 0;
5487         if (chain || act_miss_cookie) {
5488                 if (!mlx5e_tc_ct_restore_flow(ct_priv, skb, zone_restore_id))
5489                         return false;
5490
5491                 tc_skb_ext = tc_skb_ext_alloc(skb);
5492                 if (!tc_skb_ext) {
5493                         WARN_ON(1);
5494                         return false;
5495                 }
5496
5497                 if (act_miss_cookie) {
5498                         tc_skb_ext->act_miss_cookie = act_miss_cookie;
5499                         tc_skb_ext->act_miss = 1;
5500                 } else {
5501                         tc_skb_ext->chain = chain;
5502                 }
5503         }
5504
5505         if (tc_priv)
5506                 return mlx5e_tc_restore_tunnel(priv, skb, tc_priv, tunnel_id);
5507
5508         return true;
5509 }
5510
5511 static void mlx5e_tc_restore_skb_sample(struct mlx5e_priv *priv, struct sk_buff *skb,
5512                                         struct mlx5_mapped_obj *mapped_obj,
5513                                         struct mlx5e_tc_update_priv *tc_priv)
5514 {
5515         if (!mlx5e_tc_restore_tunnel(priv, skb, tc_priv, mapped_obj->sample.tunnel_id)) {
5516                 netdev_dbg(priv->netdev,
5517                            "Failed to restore tunnel info for sampled packet\n");
5518                 return;
5519         }
5520         mlx5e_tc_sample_skb(skb, mapped_obj);
5521 }
5522
5523 static bool mlx5e_tc_restore_skb_int_port(struct mlx5e_priv *priv, struct sk_buff *skb,
5524                                           struct mlx5_mapped_obj *mapped_obj,
5525                                           struct mlx5e_tc_update_priv *tc_priv,
5526                                           u32 tunnel_id)
5527 {
5528         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5529         struct mlx5_rep_uplink_priv *uplink_priv;
5530         struct mlx5e_rep_priv *uplink_rpriv;
5531         bool forward_tx = false;
5532
5533         /* Tunnel restore takes precedence over int port restore */
5534         if (tunnel_id)
5535                 return mlx5e_tc_restore_tunnel(priv, skb, tc_priv, tunnel_id);
5536
5537         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5538         uplink_priv = &uplink_rpriv->uplink_priv;
5539
5540         if (mlx5e_tc_int_port_dev_fwd(uplink_priv->int_port_priv, skb,
5541                                       mapped_obj->int_port_metadata, &forward_tx)) {
5542                 /* Set fwd_dev for future dev_put */
5543                 tc_priv->fwd_dev = skb->dev;
5544                 tc_priv->forward_tx = forward_tx;
5545
5546                 return true;
5547         }
5548
5549         return false;
5550 }
5551
5552 bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe, struct sk_buff *skb,
5553                          struct mapping_ctx *mapping_ctx, u32 mapped_obj_id,
5554                          struct mlx5_tc_ct_priv *ct_priv,
5555                          u32 zone_restore_id, u32 tunnel_id,
5556                          struct mlx5e_tc_update_priv *tc_priv)
5557 {
5558         struct mlx5e_priv *priv = netdev_priv(skb->dev);
5559         struct mlx5_mapped_obj mapped_obj;
5560         int err;
5561
5562         err = mapping_find(mapping_ctx, mapped_obj_id, &mapped_obj);
5563         if (err) {
5564                 netdev_dbg(skb->dev,
5565                            "Couldn't find mapped object for mapped_obj_id: %d, err: %d\n",
5566                            mapped_obj_id, err);
5567                 return false;
5568         }
5569
5570         switch (mapped_obj.type) {
5571         case MLX5_MAPPED_OBJ_CHAIN:
5572         case MLX5_MAPPED_OBJ_ACT_MISS:
5573                 return mlx5e_tc_restore_skb_tc_meta(skb, ct_priv, &mapped_obj, zone_restore_id,
5574                                                     tunnel_id, tc_priv);
5575         case MLX5_MAPPED_OBJ_SAMPLE:
5576                 mlx5e_tc_restore_skb_sample(priv, skb, &mapped_obj, tc_priv);
5577                 tc_priv->skb_done = true;
5578                 return true;
5579         case MLX5_MAPPED_OBJ_INT_PORT_METADATA:
5580                 return mlx5e_tc_restore_skb_int_port(priv, skb, &mapped_obj, tc_priv, tunnel_id);
5581         default:
5582                 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5583                 return false;
5584         }
5585
5586         return false;
5587 }
5588
5589 bool mlx5e_tc_update_skb_nic(struct mlx5_cqe64 *cqe, struct sk_buff *skb)
5590 {
5591         struct mlx5e_priv *priv = netdev_priv(skb->dev);
5592         u32 mapped_obj_id, reg_b, zone_restore_id;
5593         struct mlx5_tc_ct_priv *ct_priv;
5594         struct mapping_ctx *mapping_ctx;
5595         struct mlx5e_tc_table *tc;
5596
5597         reg_b = be32_to_cpu(cqe->ft_metadata);
5598         tc = mlx5e_fs_get_tc(priv->fs);
5599         mapped_obj_id = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5600         zone_restore_id = (reg_b >> MLX5_REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
5601                           ESW_ZONE_ID_MASK;
5602         ct_priv = tc->ct;
5603         mapping_ctx = tc->mapping;
5604
5605         return mlx5e_tc_update_skb(cqe, skb, mapping_ctx, mapped_obj_id, ct_priv, zone_restore_id,
5606                                    0, NULL);
5607 }
5608
5609 static struct mapping_ctx *
5610 mlx5e_get_priv_obj_mapping(struct mlx5e_priv *priv)
5611 {
5612         struct mlx5e_tc_table *tc;
5613         struct mlx5_eswitch *esw;
5614         struct mapping_ctx *ctx;
5615
5616         if (is_mdev_switchdev_mode(priv->mdev)) {
5617                 esw = priv->mdev->priv.eswitch;
5618                 ctx = esw->offloads.reg_c0_obj_pool;
5619         } else {
5620                 tc = mlx5e_fs_get_tc(priv->fs);
5621                 ctx = tc->mapping;
5622         }
5623
5624         return ctx;
5625 }
5626
5627 int mlx5e_tc_action_miss_mapping_get(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr,
5628                                      u64 act_miss_cookie, u32 *act_miss_mapping)
5629 {
5630         struct mlx5_mapped_obj mapped_obj = {};
5631         struct mlx5_eswitch *esw;
5632         struct mapping_ctx *ctx;
5633         int err;
5634
5635         ctx = mlx5e_get_priv_obj_mapping(priv);
5636         mapped_obj.type = MLX5_MAPPED_OBJ_ACT_MISS;
5637         mapped_obj.act_miss_cookie = act_miss_cookie;
5638         err = mapping_add(ctx, &mapped_obj, act_miss_mapping);
5639         if (err)
5640                 return err;
5641
5642         if (!is_mdev_switchdev_mode(priv->mdev))
5643                 return 0;
5644
5645         esw = priv->mdev->priv.eswitch;
5646         attr->act_id_restore_rule = esw_add_restore_rule(esw, *act_miss_mapping);
5647         if (IS_ERR(attr->act_id_restore_rule))
5648                 goto err_rule;
5649
5650         return 0;
5651
5652 err_rule:
5653         mapping_remove(ctx, *act_miss_mapping);
5654         return err;
5655 }
5656
5657 void mlx5e_tc_action_miss_mapping_put(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr,
5658                                       u32 act_miss_mapping)
5659 {
5660         struct mapping_ctx *ctx = mlx5e_get_priv_obj_mapping(priv);
5661
5662         if (is_mdev_switchdev_mode(priv->mdev))
5663                 mlx5_del_flow_rules(attr->act_id_restore_rule);
5664         mapping_remove(ctx, act_miss_mapping);
5665 }