2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_EN_STATS_H__
34 #define __MLX5_EN_STATS_H__
36 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
37 (*(u64 *)((char *)ptr + dsc[i].offset))
38 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
39 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
40 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
41 (*(u32 *)((char *)ptr + dsc[i].offset))
42 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
43 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
45 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
46 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
47 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
48 #define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld)
49 #define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld)
50 #define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld)
51 #define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld)
52 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)
54 #define MLX5E_DECLARE_PTP_TX_STAT(type, fld) "ptp_tx%d_"#fld, offsetof(type, fld)
55 #define MLX5E_DECLARE_PTP_CH_STAT(type, fld) "ptp_ch_"#fld, offsetof(type, fld)
56 #define MLX5E_DECLARE_PTP_CQ_STAT(type, fld) "ptp_cq%d_"#fld, offsetof(type, fld)
58 #define MLX5E_DECLARE_QOS_TX_STAT(type, fld) "qos_tx%d_"#fld, offsetof(type, fld)
61 char format[ETH_GSTRING_LEN];
62 size_t offset; /* Byte offset */
66 MLX5E_NDO_UPDATE_STATS = BIT(0x1),
70 struct mlx5e_stats_grp {
71 u16 update_stats_mask;
72 int (*get_num_stats)(struct mlx5e_priv *priv);
73 int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx);
74 int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
75 void (*update_stats)(struct mlx5e_priv *priv);
78 typedef const struct mlx5e_stats_grp *const mlx5e_stats_grp_t;
80 #define MLX5E_STATS_GRP_OP(grp, name) mlx5e_stats_grp_ ## grp ## _ ## name
82 #define MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(grp) \
83 int MLX5E_STATS_GRP_OP(grp, num_stats)(struct mlx5e_priv *priv)
85 #define MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(grp) \
86 void MLX5E_STATS_GRP_OP(grp, update_stats)(struct mlx5e_priv *priv)
88 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(grp) \
89 int MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx)
91 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(grp) \
92 int MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx)
94 #define MLX5E_STATS_GRP(grp) mlx5e_stats_grp_ ## grp
96 #define MLX5E_DECLARE_STATS_GRP(grp) \
97 const struct mlx5e_stats_grp MLX5E_STATS_GRP(grp)
99 #define MLX5E_DEFINE_STATS_GRP(grp, mask) \
100 MLX5E_DECLARE_STATS_GRP(grp) = { \
101 .get_num_stats = MLX5E_STATS_GRP_OP(grp, num_stats), \
102 .fill_stats = MLX5E_STATS_GRP_OP(grp, fill_stats), \
103 .fill_strings = MLX5E_STATS_GRP_OP(grp, fill_strings), \
104 .update_stats = MLX5E_STATS_GRP_OP(grp, update_stats), \
105 .update_stats_mask = mask, \
108 unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv);
109 void mlx5e_stats_update(struct mlx5e_priv *priv);
110 void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx);
111 void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data);
112 void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv);
114 void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
115 struct ethtool_pause_stats *pause_stats);
117 /* Concrete NIC Stats */
119 struct mlx5e_sw_stats {
126 u64 tx_tso_inner_packets;
127 u64 tx_tso_inner_bytes;
128 u64 tx_added_vlan_packets;
134 u64 rx_mcast_packets;
136 u64 rx_removed_vlan_packets;
137 u64 rx_csum_unnecessary;
139 u64 rx_csum_complete;
140 u64 rx_csum_complete_tail;
141 u64 rx_csum_complete_tail_slow;
142 u64 rx_csum_unnecessary_inner;
154 u64 tx_csum_partial_inner;
155 u64 tx_queue_stopped;
156 u64 tx_queue_dropped;
170 u64 rx_mpwqe_filler_cqes;
171 u64 rx_mpwqe_filler_strides;
172 u64 rx_oversize_pkts_sw_drop;
173 u64 rx_buff_alloc_err;
174 u64 rx_cqe_compress_blks;
175 u64 rx_cqe_compress_pkts;
191 #ifdef CONFIG_MLX5_EN_TLS
192 u64 tx_tls_encrypted_packets;
193 u64 tx_tls_encrypted_bytes;
195 u64 tx_tls_dump_packets;
196 u64 tx_tls_dump_bytes;
197 u64 tx_tls_resync_bytes;
198 u64 tx_tls_skip_no_sync_data;
199 u64 tx_tls_drop_no_sync_data;
200 u64 tx_tls_drop_bypass_req;
202 u64 rx_tls_decrypted_packets;
203 u64 rx_tls_decrypted_bytes;
204 u64 rx_tls_resync_req_pkt;
205 u64 rx_tls_resync_req_start;
206 u64 rx_tls_resync_req_end;
207 u64 rx_tls_resync_req_skip;
208 u64 rx_tls_resync_res_ok;
209 u64 rx_tls_resync_res_skip;
215 u64 rx_xsk_csum_complete;
216 u64 rx_xsk_csum_unnecessary;
217 u64 rx_xsk_csum_unnecessary_inner;
218 u64 rx_xsk_csum_none;
220 u64 rx_xsk_removed_vlan_packets;
222 u64 rx_xsk_xdp_redirect;
224 u64 rx_xsk_mpwqe_filler_cqes;
225 u64 rx_xsk_mpwqe_filler_strides;
226 u64 rx_xsk_oversize_pkts_sw_drop;
227 u64 rx_xsk_buff_alloc_err;
228 u64 rx_xsk_cqe_compress_blks;
229 u64 rx_xsk_cqe_compress_pkts;
230 u64 rx_xsk_congst_umr;
240 struct mlx5e_qcounter_stats {
241 u32 rx_out_of_buffer;
242 u32 rx_if_down_packets;
245 struct mlx5e_vnic_env_stats {
246 __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
249 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
250 vstats->query_vport_out, c)
252 struct mlx5e_vport_stats {
253 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
256 #define PPORT_802_3_GET(pstats, c) \
257 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
258 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
259 #define PPORT_2863_GET(pstats, c) \
260 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
261 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
262 #define PPORT_2819_GET(pstats, c) \
263 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
264 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
265 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \
266 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
267 counter_set.phys_layer_statistical_cntrs.c##_high)
268 #define PPORT_PER_PRIO_GET(pstats, prio, c) \
269 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
270 counter_set.eth_per_prio_grp_data_layout.c##_high)
271 #define NUM_PPORT_PRIO 8
272 #define PPORT_ETH_EXT_GET(pstats, c) \
273 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
274 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
276 struct mlx5e_pport_stats {
277 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
278 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
279 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
280 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
281 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
282 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
283 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
284 __be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
285 __be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
288 #define PCIE_PERF_GET(pcie_stats, c) \
289 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
290 counter_set.pcie_perf_cntrs_grp_data_layout.c)
292 #define PCIE_PERF_GET64(pcie_stats, c) \
293 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
294 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
296 struct mlx5e_pcie_stats {
297 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
300 struct mlx5e_rq_stats {
304 u64 csum_complete_tail;
305 u64 csum_complete_tail_slow;
306 u64 csum_unnecessary;
307 u64 csum_unnecessary_inner;
313 u64 removed_vlan_packets;
317 u64 mpwqe_filler_cqes;
318 u64 mpwqe_filler_strides;
319 u64 oversize_pkts_sw_drop;
321 u64 cqe_compress_blks;
322 u64 cqe_compress_pkts;
331 #ifdef CONFIG_MLX5_EN_TLS
332 u64 tls_decrypted_packets;
333 u64 tls_decrypted_bytes;
334 u64 tls_resync_req_pkt;
335 u64 tls_resync_req_start;
336 u64 tls_resync_req_end;
337 u64 tls_resync_req_skip;
338 u64 tls_resync_res_ok;
339 u64 tls_resync_res_skip;
344 struct mlx5e_sq_stats {
345 /* commonly accessed in data path */
351 u64 tso_inner_packets;
354 u64 csum_partial_inner;
355 u64 added_vlan_packets;
359 #ifdef CONFIG_MLX5_EN_TLS
360 u64 tls_encrypted_packets;
361 u64 tls_encrypted_bytes;
363 u64 tls_dump_packets;
365 u64 tls_resync_bytes;
366 u64 tls_skip_no_sync_data;
367 u64 tls_drop_no_sync_data;
368 u64 tls_drop_bypass_req;
370 /* less likely accessed in data path */
375 /* dirtied @completion */
376 u64 cqes ____cacheline_aligned_in_smp;
381 struct mlx5e_xdpsq_stats {
388 /* dirtied @completion */
389 u64 cqes ____cacheline_aligned_in_smp;
392 struct mlx5e_ch_stats {
401 struct mlx5e_ptp_cq_stats {
405 u64 abort_abs_diff_ns;
409 struct mlx5e_sw_stats sw;
410 struct mlx5e_qcounter_stats qcnt;
411 struct mlx5e_vnic_env_stats vnic;
412 struct mlx5e_vport_stats vport;
413 struct mlx5e_pport_stats pport;
414 struct rtnl_link_stats64 vf_vport;
415 struct mlx5e_pcie_stats pcie;
418 extern mlx5e_stats_grp_t mlx5e_nic_stats_grps[];
419 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv);
421 extern MLX5E_DECLARE_STATS_GRP(sw);
422 extern MLX5E_DECLARE_STATS_GRP(qcnt);
423 extern MLX5E_DECLARE_STATS_GRP(vnic_env);
424 extern MLX5E_DECLARE_STATS_GRP(vport);
425 extern MLX5E_DECLARE_STATS_GRP(802_3);
426 extern MLX5E_DECLARE_STATS_GRP(2863);
427 extern MLX5E_DECLARE_STATS_GRP(2819);
428 extern MLX5E_DECLARE_STATS_GRP(phy);
429 extern MLX5E_DECLARE_STATS_GRP(eth_ext);
430 extern MLX5E_DECLARE_STATS_GRP(pcie);
431 extern MLX5E_DECLARE_STATS_GRP(per_prio);
432 extern MLX5E_DECLARE_STATS_GRP(pme);
433 extern MLX5E_DECLARE_STATS_GRP(channels);
434 extern MLX5E_DECLARE_STATS_GRP(per_port_buff_congest);
435 extern MLX5E_DECLARE_STATS_GRP(ipsec_hw);
436 extern MLX5E_DECLARE_STATS_GRP(ipsec_sw);
438 #endif /* __MLX5_EN_STATS_H__ */