2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
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6 * General Public License (GPL) Version 2, available from the file
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_EN_STATS_H__
34 #define __MLX5_EN_STATS_H__
36 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
37 (*(u64 *)((char *)ptr + dsc[i].offset))
38 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
39 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
40 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
41 (*(u32 *)((char *)ptr + dsc[i].offset))
42 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
43 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
45 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
46 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
47 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
48 #define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld)
49 #define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld)
50 #define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld)
51 #define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld)
52 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)
54 #define MLX5E_DECLARE_PTP_TX_STAT(type, fld) "ptp_tx%d_"#fld, offsetof(type, fld)
55 #define MLX5E_DECLARE_PTP_CH_STAT(type, fld) "ptp_ch_"#fld, offsetof(type, fld)
56 #define MLX5E_DECLARE_PTP_CQ_STAT(type, fld) "ptp_cq%d_"#fld, offsetof(type, fld)
57 #define MLX5E_DECLARE_PTP_RQ_STAT(type, fld) "ptp_rq%d_"#fld, offsetof(type, fld)
59 #define MLX5E_DECLARE_QOS_TX_STAT(type, fld) "qos_tx%d_"#fld, offsetof(type, fld)
62 char format[ETH_GSTRING_LEN];
63 size_t offset; /* Byte offset */
67 MLX5E_NDO_UPDATE_STATS = BIT(0x1),
71 struct mlx5e_stats_grp {
72 u16 update_stats_mask;
73 int (*get_num_stats)(struct mlx5e_priv *priv);
74 int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx);
75 int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
76 void (*update_stats)(struct mlx5e_priv *priv);
79 typedef const struct mlx5e_stats_grp *const mlx5e_stats_grp_t;
81 #define MLX5E_STATS_GRP_OP(grp, name) mlx5e_stats_grp_ ## grp ## _ ## name
83 #define MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(grp) \
84 int MLX5E_STATS_GRP_OP(grp, num_stats)(struct mlx5e_priv *priv)
86 #define MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(grp) \
87 void MLX5E_STATS_GRP_OP(grp, update_stats)(struct mlx5e_priv *priv)
89 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(grp) \
90 int MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx)
92 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(grp) \
93 int MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx)
95 #define MLX5E_STATS_GRP(grp) mlx5e_stats_grp_ ## grp
97 #define MLX5E_DECLARE_STATS_GRP(grp) \
98 const struct mlx5e_stats_grp MLX5E_STATS_GRP(grp)
100 #define MLX5E_DEFINE_STATS_GRP(grp, mask) \
101 MLX5E_DECLARE_STATS_GRP(grp) = { \
102 .get_num_stats = MLX5E_STATS_GRP_OP(grp, num_stats), \
103 .fill_stats = MLX5E_STATS_GRP_OP(grp, fill_stats), \
104 .fill_strings = MLX5E_STATS_GRP_OP(grp, fill_strings), \
105 .update_stats = MLX5E_STATS_GRP_OP(grp, update_stats), \
106 .update_stats_mask = mask, \
109 unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv);
110 void mlx5e_stats_update(struct mlx5e_priv *priv);
111 void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx);
112 void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data);
113 void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv);
115 void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
116 struct ethtool_pause_stats *pause_stats);
117 void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
118 struct ethtool_fec_stats *fec_stats);
120 void mlx5e_stats_eth_phy_get(struct mlx5e_priv *priv,
121 struct ethtool_eth_phy_stats *phy_stats);
122 void mlx5e_stats_eth_mac_get(struct mlx5e_priv *priv,
123 struct ethtool_eth_mac_stats *mac_stats);
124 void mlx5e_stats_eth_ctrl_get(struct mlx5e_priv *priv,
125 struct ethtool_eth_ctrl_stats *ctrl_stats);
126 void mlx5e_stats_rmon_get(struct mlx5e_priv *priv,
127 struct ethtool_rmon_stats *rmon,
128 const struct ethtool_rmon_hist_range **ranges);
130 /* Concrete NIC Stats */
132 struct mlx5e_sw_stats {
139 u64 tx_tso_inner_packets;
140 u64 tx_tso_inner_bytes;
141 u64 tx_added_vlan_packets;
147 u64 rx_mcast_packets;
149 u64 rx_removed_vlan_packets;
150 u64 rx_csum_unnecessary;
152 u64 rx_csum_complete;
153 u64 rx_csum_complete_tail;
154 u64 rx_csum_complete_tail_slow;
155 u64 rx_csum_unnecessary_inner;
167 u64 tx_csum_partial_inner;
168 u64 tx_queue_stopped;
169 u64 tx_queue_dropped;
183 u64 rx_mpwqe_filler_cqes;
184 u64 rx_mpwqe_filler_strides;
185 u64 rx_oversize_pkts_sw_drop;
186 u64 rx_buff_alloc_err;
187 u64 rx_cqe_compress_blks;
188 u64 rx_cqe_compress_pkts;
204 #ifdef CONFIG_MLX5_EN_TLS
205 u64 tx_tls_encrypted_packets;
206 u64 tx_tls_encrypted_bytes;
208 u64 tx_tls_dump_packets;
209 u64 tx_tls_dump_bytes;
210 u64 tx_tls_resync_bytes;
211 u64 tx_tls_skip_no_sync_data;
212 u64 tx_tls_drop_no_sync_data;
213 u64 tx_tls_drop_bypass_req;
215 u64 rx_tls_decrypted_packets;
216 u64 rx_tls_decrypted_bytes;
217 u64 rx_tls_resync_req_pkt;
218 u64 rx_tls_resync_req_start;
219 u64 rx_tls_resync_req_end;
220 u64 rx_tls_resync_req_skip;
221 u64 rx_tls_resync_res_ok;
222 u64 rx_tls_resync_res_retry;
223 u64 rx_tls_resync_res_skip;
229 u64 rx_xsk_csum_complete;
230 u64 rx_xsk_csum_unnecessary;
231 u64 rx_xsk_csum_unnecessary_inner;
232 u64 rx_xsk_csum_none;
234 u64 rx_xsk_removed_vlan_packets;
236 u64 rx_xsk_xdp_redirect;
238 u64 rx_xsk_mpwqe_filler_cqes;
239 u64 rx_xsk_mpwqe_filler_strides;
240 u64 rx_xsk_oversize_pkts_sw_drop;
241 u64 rx_xsk_buff_alloc_err;
242 u64 rx_xsk_cqe_compress_blks;
243 u64 rx_xsk_cqe_compress_pkts;
244 u64 rx_xsk_congst_umr;
254 struct mlx5e_qcounter_stats {
255 u32 rx_out_of_buffer;
256 u32 rx_if_down_packets;
259 struct mlx5e_vnic_env_stats {
260 __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
263 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
264 vstats->query_vport_out, c)
266 struct mlx5e_vport_stats {
267 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
270 #define PPORT_802_3_GET(pstats, c) \
271 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
272 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
273 #define PPORT_2863_GET(pstats, c) \
274 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
275 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
276 #define PPORT_2819_GET(pstats, c) \
277 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
278 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
279 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \
280 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
281 counter_set.phys_layer_statistical_cntrs.c##_high)
282 #define PPORT_PER_PRIO_GET(pstats, prio, c) \
283 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
284 counter_set.eth_per_prio_grp_data_layout.c##_high)
285 #define NUM_PPORT_PRIO 8
286 #define PPORT_ETH_EXT_GET(pstats, c) \
287 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
288 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
290 struct mlx5e_pport_stats {
291 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
292 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
293 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
294 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
295 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
296 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
297 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
298 __be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
299 __be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
302 #define PCIE_PERF_GET(pcie_stats, c) \
303 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
304 counter_set.pcie_perf_cntrs_grp_data_layout.c)
306 #define PCIE_PERF_GET64(pcie_stats, c) \
307 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
308 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
310 struct mlx5e_pcie_stats {
311 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
314 struct mlx5e_rq_stats {
318 u64 csum_complete_tail;
319 u64 csum_complete_tail_slow;
320 u64 csum_unnecessary;
321 u64 csum_unnecessary_inner;
327 u64 removed_vlan_packets;
331 u64 mpwqe_filler_cqes;
332 u64 mpwqe_filler_strides;
333 u64 oversize_pkts_sw_drop;
335 u64 cqe_compress_blks;
336 u64 cqe_compress_pkts;
345 #ifdef CONFIG_MLX5_EN_TLS
346 u64 tls_decrypted_packets;
347 u64 tls_decrypted_bytes;
348 u64 tls_resync_req_pkt;
349 u64 tls_resync_req_start;
350 u64 tls_resync_req_end;
351 u64 tls_resync_req_skip;
352 u64 tls_resync_res_ok;
353 u64 tls_resync_res_retry;
354 u64 tls_resync_res_skip;
359 struct mlx5e_sq_stats {
360 /* commonly accessed in data path */
366 u64 tso_inner_packets;
369 u64 csum_partial_inner;
370 u64 added_vlan_packets;
374 #ifdef CONFIG_MLX5_EN_TLS
375 u64 tls_encrypted_packets;
376 u64 tls_encrypted_bytes;
378 u64 tls_dump_packets;
380 u64 tls_resync_bytes;
381 u64 tls_skip_no_sync_data;
382 u64 tls_drop_no_sync_data;
383 u64 tls_drop_bypass_req;
385 /* less likely accessed in data path */
390 /* dirtied @completion */
391 u64 cqes ____cacheline_aligned_in_smp;
396 struct mlx5e_xdpsq_stats {
403 /* dirtied @completion */
404 u64 cqes ____cacheline_aligned_in_smp;
407 struct mlx5e_ch_stats {
416 struct mlx5e_ptp_cq_stats {
420 u64 abort_abs_diff_ns;
424 struct mlx5e_sw_stats sw;
425 struct mlx5e_qcounter_stats qcnt;
426 struct mlx5e_vnic_env_stats vnic;
427 struct mlx5e_vport_stats vport;
428 struct mlx5e_pport_stats pport;
429 struct rtnl_link_stats64 vf_vport;
430 struct mlx5e_pcie_stats pcie;
433 extern mlx5e_stats_grp_t mlx5e_nic_stats_grps[];
434 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv);
436 extern MLX5E_DECLARE_STATS_GRP(sw);
437 extern MLX5E_DECLARE_STATS_GRP(qcnt);
438 extern MLX5E_DECLARE_STATS_GRP(vnic_env);
439 extern MLX5E_DECLARE_STATS_GRP(vport);
440 extern MLX5E_DECLARE_STATS_GRP(802_3);
441 extern MLX5E_DECLARE_STATS_GRP(2863);
442 extern MLX5E_DECLARE_STATS_GRP(2819);
443 extern MLX5E_DECLARE_STATS_GRP(phy);
444 extern MLX5E_DECLARE_STATS_GRP(eth_ext);
445 extern MLX5E_DECLARE_STATS_GRP(pcie);
446 extern MLX5E_DECLARE_STATS_GRP(per_prio);
447 extern MLX5E_DECLARE_STATS_GRP(pme);
448 extern MLX5E_DECLARE_STATS_GRP(channels);
449 extern MLX5E_DECLARE_STATS_GRP(per_port_buff_congest);
450 extern MLX5E_DECLARE_STATS_GRP(ipsec_hw);
451 extern MLX5E_DECLARE_STATS_GRP(ipsec_sw);
453 #endif /* __MLX5_EN_STATS_H__ */