2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
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6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_EN_STATS_H__
34 #define __MLX5_EN_STATS_H__
36 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
37 (*(u64 *)((char *)ptr + dsc[i].offset))
38 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
39 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
40 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
41 (*(u32 *)((char *)ptr + dsc[i].offset))
42 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
43 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
45 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
46 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
47 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
48 #define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld)
49 #define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld)
50 #define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld)
51 #define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld)
52 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)
55 char format[ETH_GSTRING_LEN];
56 size_t offset; /* Byte offset */
60 MLX5E_NDO_UPDATE_STATS = BIT(0x1),
64 struct mlx5e_stats_grp {
65 u16 update_stats_mask;
66 int (*get_num_stats)(struct mlx5e_priv *priv);
67 int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx);
68 int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
69 void (*update_stats)(struct mlx5e_priv *priv);
72 typedef const struct mlx5e_stats_grp *const mlx5e_stats_grp_t;
74 #define MLX5E_STATS_GRP_OP(grp, name) mlx5e_stats_grp_ ## grp ## _ ## name
76 #define MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(grp) \
77 int MLX5E_STATS_GRP_OP(grp, num_stats)(struct mlx5e_priv *priv)
79 #define MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(grp) \
80 void MLX5E_STATS_GRP_OP(grp, update_stats)(struct mlx5e_priv *priv)
82 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(grp) \
83 int MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx)
85 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(grp) \
86 int MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx)
88 #define MLX5E_STATS_GRP(grp) mlx5e_stats_grp_ ## grp
90 #define MLX5E_DECLARE_STATS_GRP(grp) \
91 const struct mlx5e_stats_grp MLX5E_STATS_GRP(grp)
93 #define MLX5E_DEFINE_STATS_GRP(grp, mask) \
94 MLX5E_DECLARE_STATS_GRP(grp) = { \
95 .get_num_stats = MLX5E_STATS_GRP_OP(grp, num_stats), \
96 .fill_stats = MLX5E_STATS_GRP_OP(grp, fill_stats), \
97 .fill_strings = MLX5E_STATS_GRP_OP(grp, fill_strings), \
98 .update_stats = MLX5E_STATS_GRP_OP(grp, update_stats), \
99 .update_stats_mask = mask, \
102 unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv);
103 void mlx5e_stats_update(struct mlx5e_priv *priv);
104 void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx);
105 void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data);
106 void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv);
108 void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
109 struct ethtool_pause_stats *pause_stats);
111 /* Concrete NIC Stats */
113 struct mlx5e_sw_stats {
120 u64 tx_tso_inner_packets;
121 u64 tx_tso_inner_bytes;
122 u64 tx_added_vlan_packets;
126 u64 rx_mcast_packets;
128 u64 rx_removed_vlan_packets;
129 u64 rx_csum_unnecessary;
131 u64 rx_csum_complete;
132 u64 rx_csum_complete_tail;
133 u64 rx_csum_complete_tail_slow;
134 u64 rx_csum_unnecessary_inner;
146 u64 tx_csum_partial_inner;
147 u64 tx_queue_stopped;
148 u64 tx_queue_dropped;
162 u64 rx_mpwqe_filler_cqes;
163 u64 rx_mpwqe_filler_strides;
164 u64 rx_oversize_pkts_sw_drop;
165 u64 rx_buff_alloc_err;
166 u64 rx_cqe_compress_blks;
167 u64 rx_cqe_compress_pkts;
183 #ifdef CONFIG_MLX5_EN_TLS
184 u64 tx_tls_encrypted_packets;
185 u64 tx_tls_encrypted_bytes;
188 u64 tx_tls_dump_packets;
189 u64 tx_tls_dump_bytes;
190 u64 tx_tls_resync_bytes;
191 u64 tx_tls_skip_no_sync_data;
192 u64 tx_tls_drop_no_sync_data;
193 u64 tx_tls_drop_bypass_req;
195 u64 rx_tls_decrypted_packets;
196 u64 rx_tls_decrypted_bytes;
199 u64 rx_tls_resync_req_pkt;
200 u64 rx_tls_resync_req_start;
201 u64 rx_tls_resync_req_end;
202 u64 rx_tls_resync_req_skip;
203 u64 rx_tls_resync_res_ok;
204 u64 rx_tls_resync_res_skip;
210 u64 rx_xsk_csum_complete;
211 u64 rx_xsk_csum_unnecessary;
212 u64 rx_xsk_csum_unnecessary_inner;
213 u64 rx_xsk_csum_none;
215 u64 rx_xsk_removed_vlan_packets;
217 u64 rx_xsk_xdp_redirect;
219 u64 rx_xsk_mpwqe_filler_cqes;
220 u64 rx_xsk_mpwqe_filler_strides;
221 u64 rx_xsk_oversize_pkts_sw_drop;
222 u64 rx_xsk_buff_alloc_err;
223 u64 rx_xsk_cqe_compress_blks;
224 u64 rx_xsk_cqe_compress_pkts;
225 u64 rx_xsk_congst_umr;
235 struct mlx5e_qcounter_stats {
236 u32 rx_out_of_buffer;
237 u32 rx_if_down_packets;
240 struct mlx5e_vnic_env_stats {
241 __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
244 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
245 vstats->query_vport_out, c)
247 struct mlx5e_vport_stats {
248 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
251 #define PPORT_802_3_GET(pstats, c) \
252 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
253 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
254 #define PPORT_2863_GET(pstats, c) \
255 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
256 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
257 #define PPORT_2819_GET(pstats, c) \
258 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
259 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
260 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \
261 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
262 counter_set.phys_layer_statistical_cntrs.c##_high)
263 #define PPORT_PER_PRIO_GET(pstats, prio, c) \
264 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
265 counter_set.eth_per_prio_grp_data_layout.c##_high)
266 #define NUM_PPORT_PRIO 8
267 #define PPORT_ETH_EXT_GET(pstats, c) \
268 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
269 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
271 struct mlx5e_pport_stats {
272 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
273 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
274 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
275 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
276 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
277 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
278 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
279 __be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
280 __be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
283 #define PCIE_PERF_GET(pcie_stats, c) \
284 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
285 counter_set.pcie_perf_cntrs_grp_data_layout.c)
287 #define PCIE_PERF_GET64(pcie_stats, c) \
288 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
289 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
291 struct mlx5e_pcie_stats {
292 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
295 struct mlx5e_rq_stats {
299 u64 csum_complete_tail;
300 u64 csum_complete_tail_slow;
301 u64 csum_unnecessary;
302 u64 csum_unnecessary_inner;
308 u64 removed_vlan_packets;
312 u64 mpwqe_filler_cqes;
313 u64 mpwqe_filler_strides;
314 u64 oversize_pkts_sw_drop;
316 u64 cqe_compress_blks;
317 u64 cqe_compress_pkts;
326 #ifdef CONFIG_MLX5_EN_TLS
327 u64 tls_decrypted_packets;
328 u64 tls_decrypted_bytes;
331 u64 tls_resync_req_pkt;
332 u64 tls_resync_req_start;
333 u64 tls_resync_req_end;
334 u64 tls_resync_req_skip;
335 u64 tls_resync_res_ok;
336 u64 tls_resync_res_skip;
341 struct mlx5e_sq_stats {
342 /* commonly accessed in data path */
348 u64 tso_inner_packets;
351 u64 csum_partial_inner;
352 u64 added_vlan_packets;
354 #ifdef CONFIG_MLX5_EN_TLS
355 u64 tls_encrypted_packets;
356 u64 tls_encrypted_bytes;
359 u64 tls_dump_packets;
361 u64 tls_resync_bytes;
362 u64 tls_skip_no_sync_data;
363 u64 tls_drop_no_sync_data;
364 u64 tls_drop_bypass_req;
366 /* less likely accessed in data path */
371 /* dirtied @completion */
372 u64 cqes ____cacheline_aligned_in_smp;
377 struct mlx5e_xdpsq_stats {
384 /* dirtied @completion */
385 u64 cqes ____cacheline_aligned_in_smp;
388 struct mlx5e_ch_stats {
398 struct mlx5e_sw_stats sw;
399 struct mlx5e_qcounter_stats qcnt;
400 struct mlx5e_vnic_env_stats vnic;
401 struct mlx5e_vport_stats vport;
402 struct mlx5e_pport_stats pport;
403 struct rtnl_link_stats64 vf_vport;
404 struct mlx5e_pcie_stats pcie;
407 extern mlx5e_stats_grp_t mlx5e_nic_stats_grps[];
408 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv);
410 extern MLX5E_DECLARE_STATS_GRP(sw);
411 extern MLX5E_DECLARE_STATS_GRP(qcnt);
412 extern MLX5E_DECLARE_STATS_GRP(vnic_env);
413 extern MLX5E_DECLARE_STATS_GRP(vport);
414 extern MLX5E_DECLARE_STATS_GRP(802_3);
415 extern MLX5E_DECLARE_STATS_GRP(2863);
416 extern MLX5E_DECLARE_STATS_GRP(2819);
417 extern MLX5E_DECLARE_STATS_GRP(phy);
418 extern MLX5E_DECLARE_STATS_GRP(eth_ext);
419 extern MLX5E_DECLARE_STATS_GRP(pcie);
420 extern MLX5E_DECLARE_STATS_GRP(per_prio);
421 extern MLX5E_DECLARE_STATS_GRP(pme);
422 extern MLX5E_DECLARE_STATS_GRP(channels);
423 extern MLX5E_DECLARE_STATS_GRP(per_port_buff_congest);
424 extern MLX5E_DECLARE_STATS_GRP(ipsec_hw);
425 extern MLX5E_DECLARE_STATS_GRP(ipsec_sw);
427 #endif /* __MLX5_EN_STATS_H__ */