2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #ifndef __MLX5_EN_STATS_H__
33 #define __MLX5_EN_STATS_H__
35 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
36 (*(u64 *)((char *)ptr + dsc[i].offset))
37 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
38 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
39 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
40 (*(u32 *)((char *)ptr + dsc[i].offset))
41 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
42 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
44 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
45 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
46 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
49 char format[ETH_GSTRING_LEN];
50 size_t offset; /* Byte offset */
53 struct mlx5e_sw_stats {
60 u64 tx_tso_inner_packets;
61 u64 tx_tso_inner_bytes;
64 u64 rx_csum_unnecessary;
67 u64 rx_csum_unnecessary_inner;
72 u64 tx_csum_partial_inner;
79 u64 rx_buff_alloc_err;
80 u64 rx_cqe_compress_blks;
81 u64 rx_cqe_compress_pkts;
88 /* Special handling counters */
89 u64 link_down_events_phy;
92 static const struct counter_desc sw_stats_desc[] = {
93 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
94 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
95 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
96 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
97 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
98 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
99 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
100 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
101 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
102 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
103 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
104 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
105 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
106 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
107 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
108 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx) },
109 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
110 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
111 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
112 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
113 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
114 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
115 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
116 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
117 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler) },
118 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
119 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
120 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
121 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) },
122 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) },
123 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) },
124 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) },
125 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) },
126 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, link_down_events_phy) },
129 struct mlx5e_qcounter_stats {
130 u32 rx_out_of_buffer;
133 static const struct counter_desc q_stats_desc[] = {
134 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
137 #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
138 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
139 vstats->query_vport_out, c)
141 struct mlx5e_vport_stats {
142 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
145 static const struct counter_desc vport_stats_desc[] = {
146 { "rx_vport_unicast_packets",
147 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
148 { "rx_vport_unicast_bytes",
149 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
150 { "tx_vport_unicast_packets",
151 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
152 { "tx_vport_unicast_bytes",
153 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
154 { "rx_vport_multicast_packets",
155 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
156 { "rx_vport_multicast_bytes",
157 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
158 { "tx_vport_multicast_packets",
159 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
160 { "tx_vport_multicast_bytes",
161 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
162 { "rx_vport_broadcast_packets",
163 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
164 { "rx_vport_broadcast_bytes",
165 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
166 { "tx_vport_broadcast_packets",
167 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
168 { "tx_vport_broadcast_bytes",
169 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
170 { "rx_vport_rdma_unicast_packets",
171 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
172 { "rx_vport_rdma_unicast_bytes",
173 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
174 { "tx_vport_rdma_unicast_packets",
175 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
176 { "tx_vport_rdma_unicast_bytes",
177 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
178 { "rx_vport_rdma_multicast_packets",
179 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
180 { "rx_vport_rdma_multicast_bytes",
181 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
182 { "tx_vport_rdma_multicast_packets",
183 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
184 { "tx_vport_rdma_multicast_bytes",
185 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
188 #define PPORT_802_3_OFF(c) \
189 MLX5_BYTE_OFF(ppcnt_reg, \
190 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
191 #define PPORT_802_3_GET(pstats, c) \
192 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
193 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
194 #define PPORT_2863_OFF(c) \
195 MLX5_BYTE_OFF(ppcnt_reg, \
196 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
197 #define PPORT_2863_GET(pstats, c) \
198 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
199 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
200 #define PPORT_2819_OFF(c) \
201 MLX5_BYTE_OFF(ppcnt_reg, \
202 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
203 #define PPORT_2819_GET(pstats, c) \
204 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
205 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
206 #define PPORT_PHY_STATISTICAL_OFF(c) \
207 MLX5_BYTE_OFF(ppcnt_reg, \
208 counter_set.phys_layer_statistical_cntrs.c##_high)
209 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \
210 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
211 counter_set.phys_layer_statistical_cntrs.c##_high)
212 #define PPORT_PER_PRIO_OFF(c) \
213 MLX5_BYTE_OFF(ppcnt_reg, \
214 counter_set.eth_per_prio_grp_data_layout.c##_high)
215 #define PPORT_PER_PRIO_GET(pstats, prio, c) \
216 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
217 counter_set.eth_per_prio_grp_data_layout.c##_high)
218 #define NUM_PPORT_PRIO 8
219 #define PPORT_ETH_EXT_OFF(c) \
220 MLX5_BYTE_OFF(ppcnt_reg, \
221 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
222 #define PPORT_ETH_EXT_GET(pstats, c) \
223 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
224 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
226 struct mlx5e_pport_stats {
227 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
228 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
229 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
230 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
231 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
232 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
233 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
236 static const struct counter_desc pport_802_3_stats_desc[] = {
237 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
238 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
239 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
240 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
241 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
242 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
243 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
244 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
245 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
246 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
247 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
248 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
249 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
250 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
251 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
252 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
253 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
254 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
257 static const struct counter_desc pport_2863_stats_desc[] = {
258 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
259 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
260 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
263 static const struct counter_desc pport_2819_stats_desc[] = {
264 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
265 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
266 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
267 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
268 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
269 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
270 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
271 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
272 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
273 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
274 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
275 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
276 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
279 static const struct counter_desc pport_phy_statistical_stats_desc[] = {
280 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
281 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
284 static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
285 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
286 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
287 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
288 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
291 static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
292 /* %s is "global" or "prio{i}" */
293 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
294 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
295 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
296 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
297 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
300 static const struct counter_desc pport_eth_ext_stats_desc[] = {
301 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
304 #define PCIE_PERF_OFF(c) \
305 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
306 #define PCIE_PERF_GET(pcie_stats, c) \
307 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
308 counter_set.pcie_perf_cntrs_grp_data_layout.c)
310 #define PCIE_PERF_OFF64(c) \
311 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
312 #define PCIE_PERF_GET64(pcie_stats, c) \
313 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
314 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
316 struct mlx5e_pcie_stats {
317 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
320 static const struct counter_desc pcie_perf_stats_desc[] = {
321 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
322 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
325 static const struct counter_desc pcie_perf_stats_desc64[] = {
326 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
329 static const struct counter_desc pcie_perf_stall_stats_desc[] = {
330 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
331 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
332 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
333 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
336 struct mlx5e_rq_stats {
340 u64 csum_unnecessary_inner;
350 u64 cqe_compress_blks;
351 u64 cqe_compress_pkts;
359 static const struct counter_desc rq_stats_desc[] = {
360 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
361 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
362 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
363 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
364 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
365 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
366 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx) },
367 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx_full) },
368 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
369 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
370 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
371 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler) },
372 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
373 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
374 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
375 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) },
376 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) },
377 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) },
378 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) },
379 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) },
382 struct mlx5e_sq_stats {
383 /* commonly accessed in data path */
389 u64 tso_inner_packets;
391 u64 csum_partial_inner;
393 /* less likely accessed in data path */
400 static const struct counter_desc sq_stats_desc[] = {
401 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
402 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
403 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
404 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
405 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
406 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
407 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
408 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
409 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
410 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
411 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
412 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
413 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
416 #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
417 #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
418 #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
419 #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
420 #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
421 #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
422 #define NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv) \
423 (ARRAY_SIZE(pport_phy_statistical_stats_desc) * \
424 MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
425 #define NUM_PCIE_PERF_COUNTERS(priv) \
426 (ARRAY_SIZE(pcie_perf_stats_desc) * \
427 MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
428 #define NUM_PCIE_PERF_COUNTERS64(priv) \
429 (ARRAY_SIZE(pcie_perf_stats_desc64) * \
430 MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
431 #define NUM_PCIE_PERF_STALL_COUNTERS(priv) \
432 (ARRAY_SIZE(pcie_perf_stall_stats_desc) * \
433 MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
434 #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS \
435 ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
436 #define NUM_PPORT_PER_PRIO_PFC_COUNTERS \
437 ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
438 #define NUM_PPORT_ETH_EXT_COUNTERS(priv) \
439 (ARRAY_SIZE(pport_eth_ext_stats_desc) * \
440 MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
441 #define NUM_PPORT_COUNTERS(priv) (NUM_PPORT_802_3_COUNTERS + \
442 NUM_PPORT_2863_COUNTERS + \
443 NUM_PPORT_2819_COUNTERS + \
444 NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv) + \
445 NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * \
447 NUM_PPORT_ETH_EXT_COUNTERS(priv))
448 #define NUM_PCIE_COUNTERS(priv) (NUM_PCIE_PERF_COUNTERS(priv) + \
449 NUM_PCIE_PERF_COUNTERS64(priv) +\
450 NUM_PCIE_PERF_STALL_COUNTERS(priv))
451 #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
452 #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
455 struct mlx5e_sw_stats sw;
456 struct mlx5e_qcounter_stats qcnt;
457 struct mlx5e_vport_stats vport;
458 struct mlx5e_pport_stats pport;
459 struct rtnl_link_stats64 vf_vport;
460 struct mlx5e_pcie_stats pcie;
463 static const struct counter_desc mlx5e_pme_status_desc[] = {
464 { "module_unplug", 8 },
467 static const struct counter_desc mlx5e_pme_error_desc[] = {
468 { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */
469 { "module_high_temp", 48 }, /* high temperature */
470 { "module_bad_shorted", 56 }, /* bad or shorted cable/module */
473 #endif /* __MLX5_EN_STATS_H__ */