2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/prefetch.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/indirect_call_wrapper.h>
38 #include <net/ip6_checksum.h>
39 #include <net/page_pool.h>
40 #include <net/inet_ecn.h>
45 #include "ipoib/ipoib.h"
46 #include "en_accel/ipsec_rxtx.h"
47 #include "en_accel/tls_rxtx.h"
48 #include "lib/clock.h"
50 #include "en/xsk/rx.h"
51 #include "en/health.h"
53 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
55 return config->rx_filter == HWTSTAMP_FILTER_ALL;
58 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq,
61 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
63 memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64));
66 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
70 struct mlx5e_cq_decomp *cqd = &rq->cqd;
71 struct mlx5_cqe64 *title = &cqd->title;
73 mlx5e_read_cqe_slot(wq, cqcc, title);
74 cqd->left = be32_to_cpu(title->byte_cnt);
75 cqd->wqe_counter = be16_to_cpu(title->wqe_counter);
76 rq->stats->cqe_compress_blks++;
79 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq,
80 struct mlx5e_cq_decomp *cqd,
83 mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr);
84 cqd->mini_arr_idx = 0;
87 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n)
90 u8 op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
91 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
92 u32 wq_sz = mlx5_cqwq_get_size(wq);
93 u32 ci_top = min_t(u32, wq_sz, ci + n);
95 for (; ci < ci_top; ci++, n--) {
96 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
101 if (unlikely(ci == wq_sz)) {
103 for (ci = 0; ci < n; ci++) {
104 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
106 cqe->op_own = op_own;
111 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
112 struct mlx5_cqwq *wq,
115 struct mlx5e_cq_decomp *cqd = &rq->cqd;
116 struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx];
117 struct mlx5_cqe64 *title = &cqd->title;
119 title->byte_cnt = mini_cqe->byte_cnt;
120 title->check_sum = mini_cqe->checksum;
121 title->op_own &= 0xf0;
122 title->op_own |= 0x01 & (cqcc >> wq->fbc.log_sz);
123 title->wqe_counter = cpu_to_be16(cqd->wqe_counter);
125 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
126 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title);
129 mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1);
132 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
133 struct mlx5_cqwq *wq,
136 struct mlx5e_cq_decomp *cqd = &rq->cqd;
138 mlx5e_decompress_cqe(rq, wq, cqcc);
139 cqd->title.rss_hash_type = 0;
140 cqd->title.rss_hash_result = 0;
143 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
144 struct mlx5_cqwq *wq,
145 int update_owner_only,
148 struct mlx5e_cq_decomp *cqd = &rq->cqd;
149 u32 cqcc = wq->cc + update_owner_only;
153 cqe_count = min_t(u32, cqd->left, budget_rem);
155 for (i = update_owner_only; i < cqe_count;
156 i++, cqd->mini_arr_idx++, cqcc++) {
157 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
158 mlx5e_read_mini_arr_slot(wq, cqd, cqcc);
160 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc);
161 rq->handle_rx_cqe(rq, &cqd->title);
163 mlx5e_cqes_update_owner(wq, cqcc - wq->cc);
165 cqd->left -= cqe_count;
166 rq->stats->cqe_compress_pkts += cqe_count;
171 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
172 struct mlx5_cqwq *wq,
175 struct mlx5e_cq_decomp *cqd = &rq->cqd;
178 mlx5e_read_title_slot(rq, wq, cc);
179 mlx5e_read_mini_arr_slot(wq, cqd, cc + 1);
180 mlx5e_decompress_cqe(rq, wq, cc);
181 rq->handle_rx_cqe(rq, &cqd->title);
184 return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem) - 1;
187 static inline bool mlx5e_page_is_reserved(struct page *page)
189 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
192 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
193 struct mlx5e_dma_info *dma_info)
195 struct mlx5e_page_cache *cache = &rq->page_cache;
196 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
197 struct mlx5e_rq_stats *stats = rq->stats;
199 if (tail_next == cache->head) {
204 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
205 stats->cache_waive++;
209 cache->page_cache[cache->tail] = *dma_info;
210 cache->tail = tail_next;
214 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
215 struct mlx5e_dma_info *dma_info)
217 struct mlx5e_page_cache *cache = &rq->page_cache;
218 struct mlx5e_rq_stats *stats = rq->stats;
220 if (unlikely(cache->head == cache->tail)) {
221 stats->cache_empty++;
225 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
230 *dma_info = cache->page_cache[cache->head];
231 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
232 stats->cache_reuse++;
234 dma_sync_single_for_device(rq->pdev, dma_info->addr,
240 static inline int mlx5e_page_alloc_pool(struct mlx5e_rq *rq,
241 struct mlx5e_dma_info *dma_info)
243 if (mlx5e_rx_cache_get(rq, dma_info))
246 dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
247 if (unlikely(!dma_info->page))
250 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
251 PAGE_SIZE, rq->buff.map_dir);
252 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
253 page_pool_recycle_direct(rq->page_pool, dma_info->page);
254 dma_info->page = NULL;
261 static inline int mlx5e_page_alloc(struct mlx5e_rq *rq,
262 struct mlx5e_dma_info *dma_info)
265 return mlx5e_xsk_page_alloc_umem(rq, dma_info);
267 return mlx5e_page_alloc_pool(rq, dma_info);
270 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
272 dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
275 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
276 struct mlx5e_dma_info *dma_info,
279 if (likely(recycle)) {
280 if (mlx5e_rx_cache_put(rq, dma_info))
283 mlx5e_page_dma_unmap(rq, dma_info);
284 page_pool_recycle_direct(rq->page_pool, dma_info->page);
286 mlx5e_page_dma_unmap(rq, dma_info);
287 page_pool_release_page(rq->page_pool, dma_info->page);
288 put_page(dma_info->page);
292 static inline void mlx5e_page_release(struct mlx5e_rq *rq,
293 struct mlx5e_dma_info *dma_info,
297 /* The `recycle` parameter is ignored, and the page is always
298 * put into the Reuse Ring, because there is no way to return
299 * the page to the userspace when the interface goes down.
301 mlx5e_xsk_page_release(rq, dma_info);
303 mlx5e_page_release_dynamic(rq, dma_info, recycle);
306 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
307 struct mlx5e_wqe_frag_info *frag)
312 /* On first frag (offset == 0), replenish page (dma_info actually).
313 * Other frags that point to the same dma_info (with a different
314 * offset) should just use the new one without replenishing again
317 err = mlx5e_page_alloc(rq, frag->di);
322 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
323 struct mlx5e_wqe_frag_info *frag,
326 if (frag->last_in_page)
327 mlx5e_page_release(rq, frag->di, recycle);
330 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
332 return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
335 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
338 struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
342 for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
343 err = mlx5e_get_rx_frag(rq, frag);
347 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
348 frag->offset + rq->buff.headroom);
355 mlx5e_put_rx_frag(rq, --frag, true);
360 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
361 struct mlx5e_wqe_frag_info *wi,
366 for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
367 mlx5e_put_rx_frag(rq, wi, recycle);
370 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
372 struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
374 mlx5e_free_rx_wqe(rq, wi, false);
377 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
379 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
384 int pages_desired = wqe_bulk << rq->wqe.info.log_num_frags;
386 if (unlikely(!mlx5e_xsk_pages_enough_umem(rq, pages_desired)))
390 for (i = 0; i < wqe_bulk; i++) {
391 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
393 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
402 mlx5e_dealloc_rx_wqe(rq, ix + i);
408 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
409 struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
410 unsigned int truesize)
412 dma_sync_single_for_cpu(rq->pdev,
413 di->addr + frag_offset,
414 len, DMA_FROM_DEVICE);
415 page_ref_inc(di->page);
416 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
417 di->page, frag_offset, len, truesize);
421 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
422 struct mlx5e_dma_info *dma_info,
423 int offset_from, u32 headlen)
425 const void *from = page_address(dma_info->page) + offset_from;
426 /* Aligning len to sizeof(long) optimizes memcpy performance */
427 unsigned int len = ALIGN(headlen, sizeof(long));
429 dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
431 skb_copy_to_linear_data(skb, from, len);
435 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
438 struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
441 /* A common case for AF_XDP. */
442 if (bitmap_full(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE))
445 no_xdp_xmit = bitmap_empty(wi->xdp_xmit_bitmap,
446 MLX5_MPWRQ_PAGES_PER_WQE);
448 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
449 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
450 mlx5e_page_release(rq, &dma_info[i], recycle);
453 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n)
455 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
458 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head);
460 mlx5_wq_ll_push(wq, next_wqe_index);
463 /* ensure wqes are visible to device before updating doorbell record */
466 mlx5_wq_ll_update_db_record(wq);
469 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
470 struct mlx5_wq_cyc *wq,
473 struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
475 edge_wi = wi + nnops;
477 /* fill sq frag edge with nops to avoid wqe wrapping two pages */
478 for (; wi < edge_wi; wi++) {
479 wi->opcode = MLX5_OPCODE_NOP;
480 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
484 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
486 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
487 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
488 struct mlx5e_icosq *sq = &rq->channel->icosq;
489 struct mlx5_wq_cyc *wq = &sq->wq;
490 struct mlx5e_umr_wqe *umr_wqe;
491 u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
492 u16 pi, contig_wqebbs_room;
497 unlikely(!mlx5e_xsk_pages_enough_umem(rq, MLX5_MPWRQ_PAGES_PER_WQE))) {
502 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
503 contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
504 if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) {
505 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room);
506 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
509 umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
510 memcpy(umr_wqe, &rq->mpwqe.umr_wqe, offsetof(struct mlx5e_umr_wqe, inline_mtts));
512 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
513 err = mlx5e_page_alloc(rq, dma_info);
516 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
519 bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
520 wi->consumed_strides = 0;
522 umr_wqe->ctrl.opmod_idx_opcode =
523 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
525 umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
527 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
528 sq->db.ico_wqe[pi].umr.rq = rq;
529 sq->pc += MLX5E_UMR_WQEBBS;
531 sq->doorbell_cseg = &umr_wqe->ctrl;
538 mlx5e_page_release(rq, dma_info, true);
542 rq->stats->buff_alloc_err++;
547 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
549 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
550 /* Don't recycle, this function is called on rq/netdev close */
551 mlx5e_free_rx_mpwqe(rq, wi, false);
554 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
556 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
560 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
563 wqe_bulk = rq->wqe.info.wqe_bulk;
565 if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
569 u16 head = mlx5_wq_cyc_get_head(wq);
571 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
573 rq->stats->buff_alloc_err++;
577 mlx5_wq_cyc_push_n(wq, wqe_bulk);
578 } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
580 /* ensure wqes are visible to device before updating doorbell record */
583 mlx5_wq_cyc_update_db_record(wq);
588 void mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
590 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
591 struct mlx5_cqe64 *cqe;
595 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
598 cqe = mlx5_cqwq_get_cqe(&cq->wq);
602 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
603 * otherwise a cq overrun may occur
612 mlx5_cqwq_pop(&cq->wq);
614 wqe_counter = be16_to_cpu(cqe->wqe_counter);
616 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
617 netdev_WARN_ONCE(cq->channel->netdev,
618 "Bad OP in ICOSQ CQE: 0x%x\n", get_cqe_opcode(cqe));
619 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state))
620 queue_work(cq->channel->priv->wq, &sq->recover_work);
624 struct mlx5e_sq_wqe_info *wi;
627 last_wqe = (sqcc == wqe_counter);
629 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
630 wi = &sq->db.ico_wqe[ci];
632 if (likely(wi->opcode == MLX5_OPCODE_UMR)) {
633 sqcc += MLX5E_UMR_WQEBBS;
634 wi->umr.rq->mpwqe.umr_completed++;
635 } else if (likely(wi->opcode == MLX5_OPCODE_NOP)) {
638 netdev_WARN_ONCE(cq->channel->netdev,
639 "Bad OPCODE in ICOSQ WQE info: 0x%x\n",
645 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
649 mlx5_cqwq_update_db_record(&cq->wq);
652 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
654 struct mlx5e_icosq *sq = &rq->channel->icosq;
655 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
656 u8 umr_completed = rq->mpwqe.umr_completed;
661 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
665 mlx5e_post_rx_mpwqe(rq, umr_completed);
666 rq->mpwqe.umr_in_progress -= umr_completed;
667 rq->mpwqe.umr_completed = 0;
670 missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress;
672 if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk))
673 rq->stats->congst_umr++;
675 #define UMR_WQE_BULK (2)
676 if (likely(missing < UMR_WQE_BULK))
679 head = rq->mpwqe.actual_wq_head;
682 alloc_err = mlx5e_alloc_rx_mpwqe(rq, head);
684 if (unlikely(alloc_err))
686 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
689 rq->mpwqe.umr_last_bulk = missing - i;
690 if (sq->doorbell_cseg) {
691 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg);
692 sq->doorbell_cseg = NULL;
695 rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk;
696 rq->mpwqe.actual_wq_head = head;
698 /* If XSK Fill Ring doesn't have enough frames, report the error, so
699 * that one of the actions can be performed:
700 * 1. If need_wakeup is used, signal that the application has to kick
701 * the driver when it refills the Fill Ring.
702 * 2. Otherwise, busy poll by rescheduling the NAPI poll.
704 if (unlikely(alloc_err == -ENOMEM && rq->umem))
710 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
712 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
713 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
714 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
717 tcp->psh = get_cqe_lro_tcppsh(cqe);
721 tcp->ack_seq = cqe->lro_ack_seq_num;
722 tcp->window = cqe->lro_tcp_win;
726 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
729 struct ethhdr *eth = (struct ethhdr *)(skb->data);
731 int network_depth = 0;
737 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
739 tot_len = cqe_bcnt - network_depth;
740 ip_p = skb->data + network_depth;
742 if (proto == htons(ETH_P_IP)) {
743 struct iphdr *ipv4 = ip_p;
745 tcp = ip_p + sizeof(struct iphdr);
746 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
748 ipv4->ttl = cqe->lro_min_ttl;
749 ipv4->tot_len = cpu_to_be16(tot_len);
751 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
754 mlx5e_lro_update_tcp_hdr(cqe, tcp);
755 check = csum_partial(tcp, tcp->doff * 4,
756 csum_unfold((__force __sum16)cqe->check_sum));
757 /* Almost done, don't forget the pseudo header */
758 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
759 tot_len - sizeof(struct iphdr),
762 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
763 struct ipv6hdr *ipv6 = ip_p;
765 tcp = ip_p + sizeof(struct ipv6hdr);
766 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
768 ipv6->hop_limit = cqe->lro_min_ttl;
769 ipv6->payload_len = cpu_to_be16(payload_len);
771 mlx5e_lro_update_tcp_hdr(cqe, tcp);
772 check = csum_partial(tcp, tcp->doff * 4,
773 csum_unfold((__force __sum16)cqe->check_sum));
774 /* Almost done, don't forget the pseudo header */
775 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
780 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
783 u8 cht = cqe->rss_hash_type;
784 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
785 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
787 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
790 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
793 *proto = ((struct ethhdr *)skb->data)->h_proto;
794 *proto = __vlan_get_protocol(skb, *proto, network_depth);
796 if (*proto == htons(ETH_P_IP))
797 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr));
799 if (*proto == htons(ETH_P_IPV6))
800 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr));
805 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
807 int network_depth = 0;
812 if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
815 ip = skb->data + network_depth;
816 rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
817 IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
819 rq->stats->ecn_mark += !!rc;
822 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
824 void *ip_p = skb->data + network_depth;
826 return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
827 ((struct ipv6hdr *)ip_p)->nexthdr;
830 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
832 #define MAX_PADDING 8
835 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len,
836 struct mlx5e_rq_stats *stats)
838 stats->csum_complete_tail_slow++;
839 skb->csum = csum_block_add(skb->csum,
840 skb_checksum(skb, offset, len, 0),
845 tail_padding_csum(struct sk_buff *skb, int offset,
846 struct mlx5e_rq_stats *stats)
848 u8 tail_padding[MAX_PADDING];
849 int len = skb->len - offset;
852 if (unlikely(len > MAX_PADDING)) {
853 tail_padding_csum_slow(skb, offset, len, stats);
857 tail = skb_header_pointer(skb, offset, len, tail_padding);
858 if (unlikely(!tail)) {
859 tail_padding_csum_slow(skb, offset, len, stats);
863 stats->csum_complete_tail++;
864 skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset);
868 mlx5e_skb_csum_fixup(struct sk_buff *skb, int network_depth, __be16 proto,
869 struct mlx5e_rq_stats *stats)
875 /* Fixup vlan headers, if any */
876 if (network_depth > ETH_HLEN)
877 /* CQE csum is calculated from the IP header and does
878 * not cover VLAN headers (if present). This will add
879 * the checksum manually.
881 skb->csum = csum_partial(skb->data + ETH_HLEN,
882 network_depth - ETH_HLEN,
885 /* Fixup tail padding, if any */
887 case htons(ETH_P_IP):
888 ip4 = (struct iphdr *)(skb->data + network_depth);
889 pkt_len = network_depth + ntohs(ip4->tot_len);
891 case htons(ETH_P_IPV6):
892 ip6 = (struct ipv6hdr *)(skb->data + network_depth);
893 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len);
899 if (likely(pkt_len >= skb->len))
902 tail_padding_csum(skb, pkt_len, stats);
905 static inline void mlx5e_handle_csum(struct net_device *netdev,
906 struct mlx5_cqe64 *cqe,
911 struct mlx5e_rq_stats *stats = rq->stats;
912 int network_depth = 0;
915 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
919 skb->ip_summed = CHECKSUM_UNNECESSARY;
920 stats->csum_unnecessary++;
924 /* True when explicitly set via priv flag, or XDP prog is loaded */
925 if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
926 goto csum_unnecessary;
928 /* CQE csum doesn't cover padding octets in short ethernet
929 * frames. And the pad field is appended prior to calculating
930 * and appending the FCS field.
932 * Detecting these padded frames requires to verify and parse
933 * IP headers, so we simply force all those small frames to be
934 * CHECKSUM_UNNECESSARY even if they are not padded.
936 if (short_frame(skb->len))
937 goto csum_unnecessary;
939 if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
940 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP))
941 goto csum_unnecessary;
943 stats->csum_complete++;
944 skb->ip_summed = CHECKSUM_COMPLETE;
945 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
947 if (test_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state))
948 return; /* CQE csum covers all received bytes */
950 /* csum might need some fixups ...*/
951 mlx5e_skb_csum_fixup(skb, network_depth, proto, stats);
956 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
957 (cqe->hds_ip_ext & CQE_L4_OK))) {
958 skb->ip_summed = CHECKSUM_UNNECESSARY;
959 if (cqe_is_tunneled(cqe)) {
961 skb->encapsulation = 1;
962 stats->csum_unnecessary_inner++;
965 stats->csum_unnecessary++;
969 skb->ip_summed = CHECKSUM_NONE;
973 #define MLX5E_CE_BIT_MASK 0x80
975 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
980 u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
981 struct mlx5e_rq_stats *stats = rq->stats;
982 struct net_device *netdev = rq->netdev;
984 skb->mac_len = ETH_HLEN;
986 #ifdef CONFIG_MLX5_EN_TLS
987 mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
990 if (lro_num_seg > 1) {
991 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
992 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
993 /* Subtract one since we already counted this as one
994 * "regular" packet in mlx5e_complete_rx_cqe()
996 stats->packets += lro_num_seg - 1;
997 stats->lro_packets++;
998 stats->lro_bytes += cqe_bcnt;
1001 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
1002 skb_hwtstamps(skb)->hwtstamp =
1003 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1005 skb_record_rx_queue(skb, rq->ix);
1007 if (likely(netdev->features & NETIF_F_RXHASH))
1008 mlx5e_skb_set_hash(cqe, skb);
1010 if (cqe_has_vlan(cqe)) {
1011 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1012 be16_to_cpu(cqe->vlan_info));
1013 stats->removed_vlan_packets++;
1016 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
1018 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
1019 /* checking CE bit in cqe - MSB in ml_path field */
1020 if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
1021 mlx5e_enable_ecn(rq, skb);
1023 skb->protocol = eth_type_trans(skb, netdev);
1026 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
1027 struct mlx5_cqe64 *cqe,
1029 struct sk_buff *skb)
1031 struct mlx5e_rq_stats *stats = rq->stats;
1034 stats->bytes += cqe_bcnt;
1035 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
1039 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
1040 u32 frag_size, u16 headroom,
1043 struct sk_buff *skb = build_skb(va, frag_size);
1045 if (unlikely(!skb)) {
1046 rq->stats->buff_alloc_err++;
1050 skb_reserve(skb, headroom);
1051 skb_put(skb, cqe_bcnt);
1057 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1058 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1060 struct mlx5e_dma_info *di = wi->di;
1061 u16 rx_headroom = rq->buff.headroom;
1062 struct sk_buff *skb;
1067 va = page_address(di->page) + wi->offset;
1068 data = va + rx_headroom;
1069 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1071 dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1072 frag_size, DMA_FROM_DEVICE);
1073 prefetchw(va); /* xdp_frame data area */
1077 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt, false);
1080 return NULL; /* page/packet was consumed by XDP */
1082 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1086 /* queue up for recycling/reuse */
1087 page_ref_inc(di->page);
1093 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1094 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1096 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1097 struct mlx5e_wqe_frag_info *head_wi = wi;
1098 u16 headlen = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1099 u16 frag_headlen = headlen;
1100 u16 byte_cnt = cqe_bcnt - headlen;
1101 struct sk_buff *skb;
1103 /* XDP is not supported in this configuration, as incoming packets
1104 * might spread among multiple pages.
1106 skb = napi_alloc_skb(rq->cq.napi,
1107 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1108 if (unlikely(!skb)) {
1109 rq->stats->buff_alloc_err++;
1113 prefetchw(skb->data);
1116 u16 frag_consumed_bytes =
1117 min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1119 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1120 frag_consumed_bytes, frag_info->frag_stride);
1121 byte_cnt -= frag_consumed_bytes;
1128 mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset, headlen);
1129 /* skb linear part was allocated with headlen and aligned to long */
1130 skb->tail += headlen;
1131 skb->len += headlen;
1136 static void trigger_report(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1138 struct mlx5_err_cqe *err_cqe = (struct mlx5_err_cqe *)cqe;
1140 if (cqe_syndrome_needs_recover(err_cqe->syndrome) &&
1141 !test_and_set_bit(MLX5E_RQ_STATE_RECOVERING, &rq->state))
1142 queue_work(rq->channel->priv->wq, &rq->recover_work);
1145 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1147 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1148 struct mlx5e_wqe_frag_info *wi;
1149 struct sk_buff *skb;
1153 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1154 wi = get_frag(rq, ci);
1155 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1157 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1158 trigger_report(rq, cqe);
1159 rq->stats->wqe_err++;
1163 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1164 mlx5e_skb_from_cqe_linear,
1165 mlx5e_skb_from_cqe_nonlinear,
1166 rq, cqe, wi, cqe_bcnt);
1168 /* probably for XDP */
1169 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1170 /* do not return page to cache,
1171 * it will be returned on XDP_TX completion.
1178 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1179 napi_gro_receive(rq->cq.napi, skb);
1182 mlx5e_free_rx_wqe(rq, wi, true);
1184 mlx5_wq_cyc_pop(wq);
1187 #ifdef CONFIG_MLX5_ESWITCH
1188 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1190 struct net_device *netdev = rq->netdev;
1191 struct mlx5e_priv *priv = netdev_priv(netdev);
1192 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1193 struct mlx5_eswitch_rep *rep = rpriv->rep;
1194 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1195 struct mlx5e_wqe_frag_info *wi;
1196 struct sk_buff *skb;
1200 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1201 wi = get_frag(rq, ci);
1202 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1204 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1205 rq->stats->wqe_err++;
1209 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1211 /* probably for XDP */
1212 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1213 /* do not return page to cache,
1214 * it will be returned on XDP_TX completion.
1221 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1223 if (rep->vlan && skb_vlan_tag_present(skb))
1226 napi_gro_receive(rq->cq.napi, skb);
1229 mlx5e_free_rx_wqe(rq, wi, true);
1231 mlx5_wq_cyc_pop(wq);
1236 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1237 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1239 u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1240 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1241 u32 frag_offset = head_offset + headlen;
1242 u32 byte_cnt = cqe_bcnt - headlen;
1243 struct mlx5e_dma_info *head_di = di;
1244 struct sk_buff *skb;
1246 skb = napi_alloc_skb(rq->cq.napi,
1247 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1248 if (unlikely(!skb)) {
1249 rq->stats->buff_alloc_err++;
1253 prefetchw(skb->data);
1255 if (unlikely(frag_offset >= PAGE_SIZE)) {
1257 frag_offset -= PAGE_SIZE;
1261 u32 pg_consumed_bytes =
1262 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1263 unsigned int truesize =
1264 ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1266 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1267 pg_consumed_bytes, truesize);
1268 byte_cnt -= pg_consumed_bytes;
1273 mlx5e_copy_skb_header(rq->pdev, skb, head_di, head_offset, headlen);
1274 /* skb linear part was allocated with headlen and aligned to long */
1275 skb->tail += headlen;
1276 skb->len += headlen;
1282 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1283 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1285 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1286 u16 rx_headroom = rq->buff.headroom;
1287 u32 cqe_bcnt32 = cqe_bcnt;
1288 struct sk_buff *skb;
1293 /* Check packet size. Note LRO doesn't use linear SKB */
1294 if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1295 rq->stats->oversize_pkts_sw_drop++;
1299 va = page_address(di->page) + head_offset;
1300 data = va + rx_headroom;
1301 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1303 dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1304 frag_size, DMA_FROM_DEVICE);
1305 prefetchw(va); /* xdp_frame data area */
1309 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32, false);
1312 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1313 __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1314 return NULL; /* page/packet was consumed by XDP */
1317 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1321 /* queue up for recycling/reuse */
1322 page_ref_inc(di->page);
1327 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1329 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
1330 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
1331 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1332 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
1333 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz;
1334 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
1335 u32 page_idx = wqe_offset >> PAGE_SHIFT;
1336 struct mlx5e_rx_wqe_ll *wqe;
1337 struct mlx5_wq_ll *wq;
1338 struct sk_buff *skb;
1341 wi->consumed_strides += cstrides;
1343 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1344 trigger_report(rq, cqe);
1345 rq->stats->wqe_err++;
1349 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1350 struct mlx5e_rq_stats *stats = rq->stats;
1352 stats->mpwqe_filler_cqes++;
1353 stats->mpwqe_filler_strides += cstrides;
1357 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1359 skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1360 mlx5e_skb_from_cqe_mpwrq_linear,
1361 mlx5e_skb_from_cqe_mpwrq_nonlinear,
1362 rq, wi, cqe_bcnt, head_offset, page_idx);
1366 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1367 napi_gro_receive(rq->cq.napi, skb);
1370 if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1374 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1375 mlx5e_free_rx_mpwqe(rq, wi, true);
1376 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1379 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1381 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1382 struct mlx5_cqwq *cqwq = &cq->wq;
1383 struct mlx5_cqe64 *cqe;
1386 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1390 page_pool_nid_changed(rq->page_pool, numa_mem_id());
1393 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget);
1394 if (rq->cqd.left || work_done >= budget)
1398 cqe = mlx5_cqwq_get_cqe(cqwq);
1400 if (unlikely(work_done))
1406 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1408 mlx5e_decompress_cqes_start(rq, cqwq,
1409 budget - work_done);
1413 mlx5_cqwq_pop(cqwq);
1415 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
1416 mlx5e_handle_rx_cqe, rq, cqe);
1417 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
1421 mlx5e_xdp_rx_poll_complete(rq);
1423 mlx5_cqwq_update_db_record(cqwq);
1425 /* ensure cq space is freed before enabling more cqes */
1431 #ifdef CONFIG_MLX5_CORE_IPOIB
1433 #define MLX5_IB_GRH_DGID_OFFSET 24
1434 #define MLX5_GID_SIZE 16
1436 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1437 struct mlx5_cqe64 *cqe,
1439 struct sk_buff *skb)
1441 struct hwtstamp_config *tstamp;
1442 struct mlx5e_rq_stats *stats;
1443 struct net_device *netdev;
1444 struct mlx5e_priv *priv;
1445 char *pseudo_header;
1450 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1451 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1453 /* No mapping present, cannot process SKB. This might happen if a child
1454 * interface is going down while having unprocessed CQEs on parent RQ
1456 if (unlikely(!netdev)) {
1457 /* TODO: add drop counters support */
1459 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1463 priv = mlx5i_epriv(netdev);
1464 tstamp = &priv->tstamp;
1465 stats = &priv->channel_stats[rq->ix].rq;
1467 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1468 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1469 if ((!g) || dgid[0] != 0xff)
1470 skb->pkt_type = PACKET_HOST;
1471 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1472 skb->pkt_type = PACKET_BROADCAST;
1474 skb->pkt_type = PACKET_MULTICAST;
1476 /* TODO: IB/ipoib: Allow mcast packets from other VFs
1477 * 68996a6e760e5c74654723eeb57bf65628ae87f4
1480 skb_pull(skb, MLX5_IB_GRH_BYTES);
1482 skb->protocol = *((__be16 *)(skb->data));
1484 if (netdev->features & NETIF_F_RXCSUM) {
1485 skb->ip_summed = CHECKSUM_COMPLETE;
1486 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1487 stats->csum_complete++;
1489 skb->ip_summed = CHECKSUM_NONE;
1493 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1494 skb_hwtstamps(skb)->hwtstamp =
1495 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1497 skb_record_rx_queue(skb, rq->ix);
1499 if (likely(netdev->features & NETIF_F_RXHASH))
1500 mlx5e_skb_set_hash(cqe, skb);
1502 /* 20 bytes of ipoib header and 4 for encap existing */
1503 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1504 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1505 skb_reset_mac_header(skb);
1506 skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1511 stats->bytes += cqe_bcnt;
1514 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1516 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1517 struct mlx5e_wqe_frag_info *wi;
1518 struct sk_buff *skb;
1522 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1523 wi = get_frag(rq, ci);
1524 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1526 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1527 rq->stats->wqe_err++;
1531 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1532 mlx5e_skb_from_cqe_linear,
1533 mlx5e_skb_from_cqe_nonlinear,
1534 rq, cqe, wi, cqe_bcnt);
1538 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1539 if (unlikely(!skb->dev)) {
1540 dev_kfree_skb_any(skb);
1543 napi_gro_receive(rq->cq.napi, skb);
1546 mlx5e_free_rx_wqe(rq, wi, true);
1547 mlx5_wq_cyc_pop(wq);
1550 #endif /* CONFIG_MLX5_CORE_IPOIB */
1552 #ifdef CONFIG_MLX5_EN_IPSEC
1554 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1556 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1557 struct mlx5e_wqe_frag_info *wi;
1558 struct sk_buff *skb;
1562 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1563 wi = get_frag(rq, ci);
1564 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1566 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1567 rq->stats->wqe_err++;
1571 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1572 mlx5e_skb_from_cqe_linear,
1573 mlx5e_skb_from_cqe_nonlinear,
1574 rq, cqe, wi, cqe_bcnt);
1575 if (unlikely(!skb)) /* a DROP, save the page-reuse checks */
1578 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1582 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1583 napi_gro_receive(rq->cq.napi, skb);
1586 mlx5e_free_rx_wqe(rq, wi, true);
1587 mlx5_wq_cyc_pop(wq);
1590 #endif /* CONFIG_MLX5_EN_IPSEC */