drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <linux/indirect_call_wrapper.h>
  38 #include <net/ip6_checksum.h>
  39 #include <net/page_pool.h>
  40 #include <net/inet_ecn.h>
  41 #include "en.h"
  42 #include "en_tc.h"
  43 #include "eswitch.h"
  44 #include "en_rep.h"
  45 #include "ipoib/ipoib.h"
  46 #include "en_accel/ipsec_rxtx.h"
  47 #include "en_accel/tls_rxtx.h"
  48 #include "lib/clock.h"
  49 #include "en/xdp.h"
  50 #include "en/xsk/rx.h"
  51 #include "en/health.h"
  52
  53 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  54 {
  55         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  56 }
  57
  58 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq,
  59                                        u32 cqcc, void *data)
  60 {
  61         u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
  62
  63         memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64));
  64 }
  65
  66 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  67                                          struct mlx5_cqwq *wq,
  68                                          u32 cqcc)
  69 {
  70         struct mlx5e_cq_decomp *cqd = &rq->cqd;
  71         struct mlx5_cqe64 *title = &cqd->title;
  72
  73         mlx5e_read_cqe_slot(wq, cqcc, title);
  74         cqd->left        = be32_to_cpu(title->byte_cnt);
  75         cqd->wqe_counter = be16_to_cpu(title->wqe_counter);
  76         rq->stats->cqe_compress_blks++;
  77 }
  78
  79 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq,
  80                                             struct mlx5e_cq_decomp *cqd,
  81                                             u32 cqcc)
  82 {
  83         mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr);
  84         cqd->mini_arr_idx = 0;
  85 }
  86
  87 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n)
  88 {
  89         u32 cqcc   = wq->cc;
  90         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
  91         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
  92         u32 wq_sz  = mlx5_cqwq_get_size(wq);
  93         u32 ci_top = min_t(u32, wq_sz, ci + n);
  94
  95         for (; ci < ci_top; ci++, n--) {
  96                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
  97
  98                 cqe->op_own = op_own;
  99         }
 100
 101         if (unlikely(ci == wq_sz)) {
 102                 op_own = !op_own;
 103                 for (ci = 0; ci < n; ci++) {
 104                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
 105
 106                         cqe->op_own = op_own;
 107                 }
 108         }
 109 }
 110
 111 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 112                                         struct mlx5_cqwq *wq,
 113                                         u32 cqcc)
 114 {
 115         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 116         struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx];
 117         struct mlx5_cqe64 *title = &cqd->title;
 118
 119         title->byte_cnt     = mini_cqe->byte_cnt;
 120         title->check_sum    = mini_cqe->checksum;
 121         title->op_own      &= 0xf0;
 122         title->op_own      |= 0x01 & (cqcc >> wq->fbc.log_sz);
 123         title->wqe_counter  = cpu_to_be16(cqd->wqe_counter);
 124
 125         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 126                 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title);
 127         else
 128                 cqd->wqe_counter =
 129                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1);
 130 }
 131
 132 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 133                                                 struct mlx5_cqwq *wq,
 134                                                 u32 cqcc)
 135 {
 136         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 137
 138         mlx5e_decompress_cqe(rq, wq, cqcc);
 139         cqd->title.rss_hash_type   = 0;
 140         cqd->title.rss_hash_result = 0;
 141 }
 142
 143 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 144                                              struct mlx5_cqwq *wq,
 145                                              int update_owner_only,
 146                                              int budget_rem)
 147 {
 148         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 149         u32 cqcc = wq->cc + update_owner_only;
 150         u32 cqe_count;
 151         u32 i;
 152
 153         cqe_count = min_t(u32, cqd->left, budget_rem);
 154
 155         for (i = update_owner_only; i < cqe_count;
 156              i++, cqd->mini_arr_idx++, cqcc++) {
 157                 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 158                         mlx5e_read_mini_arr_slot(wq, cqd, cqcc);
 159
 160                 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc);
 161                 rq->handle_rx_cqe(rq, &cqd->title);
 162         }
 163         mlx5e_cqes_update_owner(wq, cqcc - wq->cc);
 164         wq->cc = cqcc;
 165         cqd->left -= cqe_count;
 166         rq->stats->cqe_compress_pkts += cqe_count;
 167
 168         return cqe_count;
 169 }
 170
 171 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 172                                               struct mlx5_cqwq *wq,
 173                                               int budget_rem)
 174 {
 175         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 176         u32 cc = wq->cc;
 177
 178         mlx5e_read_title_slot(rq, wq, cc);
 179         mlx5e_read_mini_arr_slot(wq, cqd, cc + 1);
 180         mlx5e_decompress_cqe(rq, wq, cc);
 181         rq->handle_rx_cqe(rq, &cqd->title);
 182         cqd->mini_arr_idx++;
 183
 184         return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem) - 1;
 185 }
 186
 187 static inline bool mlx5e_page_is_reserved(struct page *page)
 188 {
 189         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 190 }
 191
 192 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 193                                       struct mlx5e_dma_info *dma_info)
 194 {
 195         struct mlx5e_page_cache *cache = &rq->page_cache;
 196         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 197         struct mlx5e_rq_stats *stats = rq->stats;
 198
 199         if (tail_next == cache->head) {
 200                 stats->cache_full++;
 201                 return false;
 202         }
 203
 204         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 205                 stats->cache_waive++;
 206                 return false;
 207         }
 208
 209         cache->page_cache[cache->tail] = *dma_info;
 210         cache->tail = tail_next;
 211         return true;
 212 }
 213
 214 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 215                                       struct mlx5e_dma_info *dma_info)
 216 {
 217         struct mlx5e_page_cache *cache = &rq->page_cache;
 218         struct mlx5e_rq_stats *stats = rq->stats;
 219
 220         if (unlikely(cache->head == cache->tail)) {
 221                 stats->cache_empty++;
 222                 return false;
 223         }
 224
 225         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 226                 stats->cache_busy++;
 227                 return false;
 228         }
 229
 230         *dma_info = cache->page_cache[cache->head];
 231         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 232         stats->cache_reuse++;
 233
 234         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 235                                    PAGE_SIZE,
 236                                    DMA_FROM_DEVICE);
 237         return true;
 238 }
 239
 240 static inline int mlx5e_page_alloc_pool(struct mlx5e_rq *rq,
 241                                         struct mlx5e_dma_info *dma_info)
 242 {
 243         if (mlx5e_rx_cache_get(rq, dma_info))
 244                 return 0;
 245
 246         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
 247         if (unlikely(!dma_info->page))
 248                 return -ENOMEM;
 249
 250         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 251                                       PAGE_SIZE, rq->buff.map_dir);
 252         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 253                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 254                 dma_info->page = NULL;
 255                 return -ENOMEM;
 256         }
 257
 258         return 0;
 259 }
 260
 261 static inline int mlx5e_page_alloc(struct mlx5e_rq *rq,
 262                                    struct mlx5e_dma_info *dma_info)
 263 {
 264         if (rq->umem)
 265                 return mlx5e_xsk_page_alloc_umem(rq, dma_info);
 266         else
 267                 return mlx5e_page_alloc_pool(rq, dma_info);
 268 }
 269
 270 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
 271 {
 272         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
 273 }
 274
 275 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
 276                                 struct mlx5e_dma_info *dma_info,
 277                                 bool recycle)
 278 {
 279         if (likely(recycle)) {
 280                 if (mlx5e_rx_cache_put(rq, dma_info))
 281                         return;
 282
 283                 mlx5e_page_dma_unmap(rq, dma_info);
 284                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 285         } else {
 286                 mlx5e_page_dma_unmap(rq, dma_info);
 287                 page_pool_release_page(rq->page_pool, dma_info->page);
 288                 put_page(dma_info->page);
 289         }
 290 }
 291
 292 static inline void mlx5e_page_release(struct mlx5e_rq *rq,
 293                                       struct mlx5e_dma_info *dma_info,
 294                                       bool recycle)
 295 {
 296         if (rq->umem)
 297                 /* The `recycle` parameter is ignored, and the page is always
 298                  * put into the Reuse Ring, because there is no way to return
 299                  * the page to the userspace when the interface goes down.
 300                  */
 301                 mlx5e_xsk_page_release(rq, dma_info);
 302         else
 303                 mlx5e_page_release_dynamic(rq, dma_info, recycle);
 304 }
 305
 306 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
 307                                     struct mlx5e_wqe_frag_info *frag)
 308 {
 309         int err = 0;
 310
 311         if (!frag->offset)
 312                 /* On first frag (offset == 0), replenish page (dma_info actually).
 313                  * Other frags that point to the same dma_info (with a different
 314                  * offset) should just use the new one without replenishing again
 315                  * by themselves.
 316                  */
 317                 err = mlx5e_page_alloc(rq, frag->di);
 318
 319         return err;
 320 }
 321
 322 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
 323                                      struct mlx5e_wqe_frag_info *frag,
 324                                      bool recycle)
 325 {
 326         if (frag->last_in_page)
 327                 mlx5e_page_release(rq, frag->di, recycle);
 328 }
 329
 330 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
 331 {
 332         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
 333 }
 334
 335 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
 336                               u16 ix)
 337 {
 338         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
 339         int err;
 340         int i;
 341
 342         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
 343                 err = mlx5e_get_rx_frag(rq, frag);
 344                 if (unlikely(err))
 345                         goto free_frags;
 346
 347                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
 348                                                 frag->offset + rq->buff.headroom);
 349         }
 350
 351         return 0;
 352
 353 free_frags:
 354         while (--i >= 0)
 355                 mlx5e_put_rx_frag(rq, --frag, true);
 356
 357         return err;
 358 }
 359
 360 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 361                                      struct mlx5e_wqe_frag_info *wi,
 362                                      bool recycle)
 363 {
 364         int i;
 365
 366         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
 367                 mlx5e_put_rx_frag(rq, wi, recycle);
 368 }
 369
 370 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 371 {
 372         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
 373
 374         mlx5e_free_rx_wqe(rq, wi, false);
 375 }
 376
 377 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
 378 {
 379         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 380         int err;
 381         int i;
 382
 383         if (rq->umem) {
 384                 int pages_desired = wqe_bulk << rq->wqe.info.log_num_frags;
 385
 386                 if (unlikely(!mlx5e_xsk_pages_enough_umem(rq, pages_desired)))
 387                         return -ENOMEM;
 388         }
 389
 390         for (i = 0; i < wqe_bulk; i++) {
 391                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
 392
 393                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
 394                 if (unlikely(err))
 395                         goto free_wqes;
 396         }
 397
 398         return 0;
 399
 400 free_wqes:
 401         while (--i >= 0)
 402                 mlx5e_dealloc_rx_wqe(rq, ix + i);
 403
 404         return err;
 405 }
 406
 407 static inline void
 408 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
 409                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
 410                    unsigned int truesize)
 411 {
 412         dma_sync_single_for_cpu(rq->pdev,
 413                                 di->addr + frag_offset,
 414                                 len, DMA_FROM_DEVICE);
 415         page_ref_inc(di->page);
 416         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 417                         di->page, frag_offset, len, truesize);
 418 }
 419
 420 static inline void
 421 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
 422                       struct mlx5e_dma_info *dma_info,
 423                       int offset_from, u32 headlen)
 424 {
 425         const void *from = page_address(dma_info->page) + offset_from;
 426         /* Aligning len to sizeof(long) optimizes memcpy performance */
 427         unsigned int len = ALIGN(headlen, sizeof(long));
 428
 429         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
 430                                 DMA_FROM_DEVICE);
 431         skb_copy_to_linear_data(skb, from, len);
 432 }
 433
 434 static void
 435 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
 436 {
 437         bool no_xdp_xmit;
 438         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 439         int i;
 440
 441         /* A common case for AF_XDP. */
 442         if (bitmap_full(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE))
 443                 return;
 444
 445         no_xdp_xmit = bitmap_empty(wi->xdp_xmit_bitmap,
 446                                    MLX5_MPWRQ_PAGES_PER_WQE);
 447
 448         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
 449                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 450                         mlx5e_page_release(rq, &dma_info[i], recycle);
 451 }
 452
 453 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n)
 454 {
 455         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 456
 457         do {
 458                 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head);
 459
 460                 mlx5_wq_ll_push(wq, next_wqe_index);
 461         } while (--n);
 462
 463         /* ensure wqes are visible to device before updating doorbell record */
 464         dma_wmb();
 465
 466         mlx5_wq_ll_update_db_record(wq);
 467 }
 468
 469 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
 470                                               struct mlx5_wq_cyc *wq,
 471                                               u16 pi, u16 nnops)
 472 {
 473         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
 474
 475         edge_wi = wi + nnops;
 476
 477         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
 478         for (; wi < edge_wi; wi++) {
 479                 wi->opcode = MLX5_OPCODE_NOP;
 480                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 481         }
 482 }
 483
 484 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 485 {
 486         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 487         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 488         struct mlx5e_icosq *sq = &rq->channel->icosq;
 489         struct mlx5_wq_cyc *wq = &sq->wq;
 490         struct mlx5e_umr_wqe *umr_wqe;
 491         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
 492         u16 pi, contig_wqebbs_room;
 493         int err;
 494         int i;
 495
 496         if (rq->umem &&
 497             unlikely(!mlx5e_xsk_pages_enough_umem(rq, MLX5_MPWRQ_PAGES_PER_WQE))) {
 498                 err = -ENOMEM;
 499                 goto err;
 500         }
 501
 502         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 503         contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
 504         if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) {
 505                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room);
 506                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 507         }
 508
 509         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 510         memcpy(umr_wqe, &rq->mpwqe.umr_wqe, offsetof(struct mlx5e_umr_wqe, inline_mtts));
 511
 512         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 513                 err = mlx5e_page_alloc(rq, dma_info);
 514                 if (unlikely(err))
 515                         goto err_unmap;
 516                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 517         }
 518
 519         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 520         wi->consumed_strides = 0;
 521
 522         umr_wqe->ctrl.opmod_idx_opcode =
 523                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 524                             MLX5_OPCODE_UMR);
 525         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
 526
 527         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 528         sq->db.ico_wqe[pi].umr.rq = rq;
 529         sq->pc += MLX5E_UMR_WQEBBS;
 530
 531         sq->doorbell_cseg = &umr_wqe->ctrl;
 532
 533         return 0;
 534
 535 err_unmap:
 536         while (--i >= 0) {
 537                 dma_info--;
 538                 mlx5e_page_release(rq, dma_info, true);
 539         }
 540
 541 err:
 542         rq->stats->buff_alloc_err++;
 543
 544         return err;
 545 }
 546
 547 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 548 {
 549         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 550         /* Don't recycle, this function is called on rq/netdev close */
 551         mlx5e_free_rx_mpwqe(rq, wi, false);
 552 }
 553
 554 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 555 {
 556         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 557         u8 wqe_bulk;
 558         int err;
 559
 560         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 561                 return false;
 562
 563         wqe_bulk = rq->wqe.info.wqe_bulk;
 564
 565         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
 566                 return false;
 567
 568         do {
 569                 u16 head = mlx5_wq_cyc_get_head(wq);
 570
 571                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
 572                 if (unlikely(err)) {
 573                         rq->stats->buff_alloc_err++;
 574                         break;
 575                 }
 576
 577                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
 578         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
 579
 580         /* ensure wqes are visible to device before updating doorbell record */
 581         dma_wmb();
 582
 583         mlx5_wq_cyc_update_db_record(wq);
 584
 585         return !!err;
 586 }
 587
 588 void mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
 589 {
 590         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 591         struct mlx5_cqe64 *cqe;
 592         u16 sqcc;
 593         int i;
 594
 595         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
 596                 return;
 597
 598         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 599         if (likely(!cqe))
 600                 return;
 601
 602         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
 603          * otherwise a cq overrun may occur
 604          */
 605         sqcc = sq->cc;
 606
 607         i = 0;
 608         do {
 609                 u16 wqe_counter;
 610                 bool last_wqe;
 611
 612                 mlx5_cqwq_pop(&cq->wq);
 613
 614                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
 615
 616                 do {
 617                         struct mlx5e_sq_wqe_info *wi;
 618                         u16 ci;
 619
 620                         last_wqe = (sqcc == wqe_counter);
 621
 622                         ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
 623                         wi = &sq->db.ico_wqe[ci];
 624
 625                         if (last_wqe && unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
 626                                 netdev_WARN_ONCE(cq->channel->netdev,
 627                                                  "Bad OP in ICOSQ CQE: 0x%x\n",
 628                                                  get_cqe_opcode(cqe));
 629                                 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state))
 630                                         queue_work(cq->channel->priv->wq, &sq->recover_work);
 631                                 break;
 632                         }
 633
 634                         if (likely(wi->opcode == MLX5_OPCODE_UMR)) {
 635                                 sqcc += MLX5E_UMR_WQEBBS;
 636                                 wi->umr.rq->mpwqe.umr_completed++;
 637                         } else if (likely(wi->opcode == MLX5_OPCODE_NOP)) {
 638                                 sqcc++;
 639                         } else {
 640                                 netdev_WARN_ONCE(cq->channel->netdev,
 641                                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n",
 642                                                  wi->opcode);
 643                         }
 644
 645                 } while (!last_wqe);
 646
 647         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
 648
 649         sq->cc = sqcc;
 650
 651         mlx5_cqwq_update_db_record(&cq->wq);
 652 }
 653
 654 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 655 {
 656         struct mlx5e_icosq *sq = &rq->channel->icosq;
 657         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 658         u8  umr_completed = rq->mpwqe.umr_completed;
 659         int alloc_err = 0;
 660         u8  missing, i;
 661         u16 head;
 662
 663         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 664                 return false;
 665
 666         if (umr_completed) {
 667                 mlx5e_post_rx_mpwqe(rq, umr_completed);
 668                 rq->mpwqe.umr_in_progress -= umr_completed;
 669                 rq->mpwqe.umr_completed = 0;
 670         }
 671
 672         missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress;
 673
 674         if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk))
 675                 rq->stats->congst_umr++;
 676
 677 #define UMR_WQE_BULK (2)
 678         if (likely(missing < UMR_WQE_BULK))
 679                 return false;
 680
 681         head = rq->mpwqe.actual_wq_head;
 682         i = missing;
 683         do {
 684                 alloc_err = mlx5e_alloc_rx_mpwqe(rq, head);
 685
 686                 if (unlikely(alloc_err))
 687                         break;
 688                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 689         } while (--i);
 690
 691         rq->mpwqe.umr_last_bulk    = missing - i;
 692         if (sq->doorbell_cseg) {
 693                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg);
 694                 sq->doorbell_cseg = NULL;
 695         }
 696
 697         rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk;
 698         rq->mpwqe.actual_wq_head   = head;
 699
 700         /* If XSK Fill Ring doesn't have enough frames, report the error, so
 701          * that one of the actions can be performed:
 702          * 1. If need_wakeup is used, signal that the application has to kick
 703          * the driver when it refills the Fill Ring.
 704          * 2. Otherwise, busy poll by rescheduling the NAPI poll.
 705          */
 706         if (unlikely(alloc_err == -ENOMEM && rq->umem))
 707                 return true;
 708
 709         return false;
 710 }
 711
 712 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 713 {
 714         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 715         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 716                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 717
 718         tcp->check                      = 0;
 719         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 720
 721         if (tcp_ack) {
 722                 tcp->ack                = 1;
 723                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 724                 tcp->window             = cqe->lro_tcp_win;
 725         }
 726 }
 727
 728 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 729                                  u32 cqe_bcnt)
 730 {
 731         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 732         struct tcphdr   *tcp;
 733         int network_depth = 0;
 734         __wsum check;
 735         __be16 proto;
 736         u16 tot_len;
 737         void *ip_p;
 738
 739         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 740
 741         tot_len = cqe_bcnt - network_depth;
 742         ip_p = skb->data + network_depth;
 743
 744         if (proto == htons(ETH_P_IP)) {
 745                 struct iphdr *ipv4 = ip_p;
 746
 747                 tcp = ip_p + sizeof(struct iphdr);
 748                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 749
 750                 ipv4->ttl               = cqe->lro_min_ttl;
 751                 ipv4->tot_len           = cpu_to_be16(tot_len);
 752                 ipv4->check             = 0;
 753                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 754                                                        ipv4->ihl);
 755
 756                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 757                 check = csum_partial(tcp, tcp->doff * 4,
 758                                      csum_unfold((__force __sum16)cqe->check_sum));
 759                 /* Almost done, don't forget the pseudo header */
 760                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 761                                                tot_len - sizeof(struct iphdr),
 762                                                IPPROTO_TCP, check);
 763         } else {
 764                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 765                 struct ipv6hdr *ipv6 = ip_p;
 766
 767                 tcp = ip_p + sizeof(struct ipv6hdr);
 768                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 769
 770                 ipv6->hop_limit         = cqe->lro_min_ttl;
 771                 ipv6->payload_len       = cpu_to_be16(payload_len);
 772
 773                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 774                 check = csum_partial(tcp, tcp->doff * 4,
 775                                      csum_unfold((__force __sum16)cqe->check_sum));
 776                 /* Almost done, don't forget the pseudo header */
 777                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 778                                              IPPROTO_TCP, check);
 779         }
 780 }
 781
 782 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 783                                       struct sk_buff *skb)
 784 {
 785         u8 cht = cqe->rss_hash_type;
 786         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 787                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 788                                             PKT_HASH_TYPE_NONE;
 789         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 790 }
 791
 792 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
 793                                         __be16 *proto)
 794 {
 795         *proto = ((struct ethhdr *)skb->data)->h_proto;
 796         *proto = __vlan_get_protocol(skb, *proto, network_depth);
 797
 798         if (*proto == htons(ETH_P_IP))
 799                 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr));
 800
 801         if (*proto == htons(ETH_P_IPV6))
 802                 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr));
 803
 804         return false;
 805 }
 806
 807 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
 808 {
 809         int network_depth = 0;
 810         __be16 proto;
 811         void *ip;
 812         int rc;
 813
 814         if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
 815                 return;
 816
 817         ip = skb->data + network_depth;
 818         rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
 819                                          IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
 820
 821         rq->stats->ecn_mark += !!rc;
 822 }
 823
 824 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
 825 {
 826         void *ip_p = skb->data + network_depth;
 827
 828         return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
 829                                             ((struct ipv6hdr *)ip_p)->nexthdr;
 830 }
 831
 832 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
 833
 834 #define MAX_PADDING 8
 835
 836 static void
 837 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len,
 838                        struct mlx5e_rq_stats *stats)
 839 {
 840         stats->csum_complete_tail_slow++;
 841         skb->csum = csum_block_add(skb->csum,
 842                                    skb_checksum(skb, offset, len, 0),
 843                                    offset);
 844 }
 845
 846 static void
 847 tail_padding_csum(struct sk_buff *skb, int offset,
 848                   struct mlx5e_rq_stats *stats)
 849 {
 850         u8 tail_padding[MAX_PADDING];
 851         int len = skb->len - offset;
 852         void *tail;
 853
 854         if (unlikely(len > MAX_PADDING)) {
 855                 tail_padding_csum_slow(skb, offset, len, stats);
 856                 return;
 857         }
 858
 859         tail = skb_header_pointer(skb, offset, len, tail_padding);
 860         if (unlikely(!tail)) {
 861                 tail_padding_csum_slow(skb, offset, len, stats);
 862                 return;
 863         }
 864
 865         stats->csum_complete_tail++;
 866         skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset);
 867 }
 868
 869 static void
 870 mlx5e_skb_csum_fixup(struct sk_buff *skb, int network_depth, __be16 proto,
 871                      struct mlx5e_rq_stats *stats)
 872 {
 873         struct ipv6hdr *ip6;
 874         struct iphdr   *ip4;
 875         int pkt_len;
 876
 877         /* Fixup vlan headers, if any */
 878         if (network_depth > ETH_HLEN)
 879                 /* CQE csum is calculated from the IP header and does
 880                  * not cover VLAN headers (if present). This will add
 881                  * the checksum manually.
 882                  */
 883                 skb->csum = csum_partial(skb->data + ETH_HLEN,
 884                                          network_depth - ETH_HLEN,
 885                                          skb->csum);
 886
 887         /* Fixup tail padding, if any */
 888         switch (proto) {
 889         case htons(ETH_P_IP):
 890                 ip4 = (struct iphdr *)(skb->data + network_depth);
 891                 pkt_len = network_depth + ntohs(ip4->tot_len);
 892                 break;
 893         case htons(ETH_P_IPV6):
 894                 ip6 = (struct ipv6hdr *)(skb->data + network_depth);
 895                 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len);
 896                 break;
 897         default:
 898                 return;
 899         }
 900
 901         if (likely(pkt_len >= skb->len))
 902                 return;
 903
 904         tail_padding_csum(skb, pkt_len, stats);
 905 }
 906
 907 static inline void mlx5e_handle_csum(struct net_device *netdev,
 908                                      struct mlx5_cqe64 *cqe,
 909                                      struct mlx5e_rq *rq,
 910                                      struct sk_buff *skb,
 911                                      bool   lro)
 912 {
 913         struct mlx5e_rq_stats *stats = rq->stats;
 914         int network_depth = 0;
 915         __be16 proto;
 916
 917         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 918                 goto csum_none;
 919
 920         if (lro) {
 921                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 922                 stats->csum_unnecessary++;
 923                 return;
 924         }
 925
 926         /* True when explicitly set via priv flag, or XDP prog is loaded */
 927         if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
 928                 goto csum_unnecessary;
 929
 930         /* CQE csum doesn't cover padding octets in short ethernet
 931          * frames. And the pad field is appended prior to calculating
 932          * and appending the FCS field.
 933          *
 934          * Detecting these padded frames requires to verify and parse
 935          * IP headers, so we simply force all those small frames to be
 936          * CHECKSUM_UNNECESSARY even if they are not padded.
 937          */
 938         if (short_frame(skb->len))
 939                 goto csum_unnecessary;
 940
 941         if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
 942                 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP))
 943                         goto csum_unnecessary;
 944
 945                 stats->csum_complete++;
 946                 skb->ip_summed = CHECKSUM_COMPLETE;
 947                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 948
 949                 if (test_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state))
 950                         return; /* CQE csum covers all received bytes */
 951
 952                 /* csum might need some fixups ...*/
 953                 mlx5e_skb_csum_fixup(skb, network_depth, proto, stats);
 954                 return;
 955         }
 956
 957 csum_unnecessary:
 958         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 959                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 960                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 961                 if (cqe_is_tunneled(cqe)) {
 962                         skb->csum_level = 1;
 963                         skb->encapsulation = 1;
 964                         stats->csum_unnecessary_inner++;
 965                         return;
 966                 }
 967                 stats->csum_unnecessary++;
 968                 return;
 969         }
 970 csum_none:
 971         skb->ip_summed = CHECKSUM_NONE;
 972         stats->csum_none++;
 973 }
 974
 975 #define MLX5E_CE_BIT_MASK 0x80
 976
 977 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 978                                       u32 cqe_bcnt,
 979                                       struct mlx5e_rq *rq,
 980                                       struct sk_buff *skb)
 981 {
 982         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 983         struct mlx5e_rq_stats *stats = rq->stats;
 984         struct net_device *netdev = rq->netdev;
 985
 986         skb->mac_len = ETH_HLEN;
 987
 988 #ifdef CONFIG_MLX5_EN_TLS
 989         mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
 990 #endif
 991
 992         if (lro_num_seg > 1) {
 993                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 994                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 995                 /* Subtract one since we already counted this as one
 996                  * "regular" packet in mlx5e_complete_rx_cqe()
 997                  */
 998                 stats->packets += lro_num_seg - 1;
 999                 stats->lro_packets++;
1000                 stats->lro_bytes += cqe_bcnt;
1001         }
1002
1003         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
1004                 skb_hwtstamps(skb)->hwtstamp =
1005                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1006
1007         skb_record_rx_queue(skb, rq->ix);
1008
1009         if (likely(netdev->features & NETIF_F_RXHASH))
1010                 mlx5e_skb_set_hash(cqe, skb);
1011
1012         if (cqe_has_vlan(cqe)) {
1013                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1014                                        be16_to_cpu(cqe->vlan_info));
1015                 stats->removed_vlan_packets++;
1016         }
1017
1018         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
1019
1020         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
1021         /* checking CE bit in cqe - MSB in ml_path field */
1022         if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
1023                 mlx5e_enable_ecn(rq, skb);
1024
1025         skb->protocol = eth_type_trans(skb, netdev);
1026 }
1027
1028 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
1029                                          struct mlx5_cqe64 *cqe,
1030                                          u32 cqe_bcnt,
1031                                          struct sk_buff *skb)
1032 {
1033         struct mlx5e_rq_stats *stats = rq->stats;
1034
1035         stats->packets++;
1036         stats->bytes += cqe_bcnt;
1037         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
1038 }
1039
1040 static inline
1041 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
1042                                        u32 frag_size, u16 headroom,
1043                                        u32 cqe_bcnt)
1044 {
1045         struct sk_buff *skb = build_skb(va, frag_size);
1046
1047         if (unlikely(!skb)) {
1048                 rq->stats->buff_alloc_err++;
1049                 return NULL;
1050         }
1051
1052         skb_reserve(skb, headroom);
1053         skb_put(skb, cqe_bcnt);
1054
1055         return skb;
1056 }
1057
1058 struct sk_buff *
1059 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1060                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1061 {
1062         struct mlx5e_dma_info *di = wi->di;
1063         u16 rx_headroom = rq->buff.headroom;
1064         struct sk_buff *skb;
1065         void *va, *data;
1066         bool consumed;
1067         u32 frag_size;
1068
1069         va             = page_address(di->page) + wi->offset;
1070         data           = va + rx_headroom;
1071         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1072
1073         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1074                                       frag_size, DMA_FROM_DEVICE);
1075         prefetchw(va); /* xdp_frame data area */
1076         prefetch(data);
1077
1078         rcu_read_lock();
1079         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt, false);
1080         rcu_read_unlock();
1081         if (consumed)
1082                 return NULL; /* page/packet was consumed by XDP */
1083
1084         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1085         if (unlikely(!skb))
1086                 return NULL;
1087
1088         /* queue up for recycling/reuse */
1089         page_ref_inc(di->page);
1090
1091         return skb;
1092 }
1093
1094 struct sk_buff *
1095 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1096                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1097 {
1098         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1099         struct mlx5e_wqe_frag_info *head_wi = wi;
1100         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1101         u16 frag_headlen = headlen;
1102         u16 byte_cnt     = cqe_bcnt - headlen;
1103         struct sk_buff *skb;
1104
1105         /* XDP is not supported in this configuration, as incoming packets
1106          * might spread among multiple pages.
1107          */
1108         skb = napi_alloc_skb(rq->cq.napi,
1109                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1110         if (unlikely(!skb)) {
1111                 rq->stats->buff_alloc_err++;
1112                 return NULL;
1113         }
1114
1115         prefetchw(skb->data);
1116
1117         while (byte_cnt) {
1118                 u16 frag_consumed_bytes =
1119                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1120
1121                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1122                                    frag_consumed_bytes, frag_info->frag_stride);
1123                 byte_cnt -= frag_consumed_bytes;
1124                 frag_headlen = 0;
1125                 frag_info++;
1126                 wi++;
1127         }
1128
1129         /* copy header */
1130         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset, headlen);
1131         /* skb linear part was allocated with headlen and aligned to long */
1132         skb->tail += headlen;
1133         skb->len  += headlen;
1134
1135         return skb;
1136 }
1137
1138 static void trigger_report(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1139 {
1140         struct mlx5_err_cqe *err_cqe = (struct mlx5_err_cqe *)cqe;
1141
1142         if (cqe_syndrome_needs_recover(err_cqe->syndrome) &&
1143             !test_and_set_bit(MLX5E_RQ_STATE_RECOVERING, &rq->state))
1144                 queue_work(rq->channel->priv->wq, &rq->recover_work);
1145 }
1146
1147 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1148 {
1149         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1150         struct mlx5e_wqe_frag_info *wi;
1151         struct sk_buff *skb;
1152         u32 cqe_bcnt;
1153         u16 ci;
1154
1155         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1156         wi       = get_frag(rq, ci);
1157         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1158
1159         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1160                 trigger_report(rq, cqe);
1161                 rq->stats->wqe_err++;
1162                 goto free_wqe;
1163         }
1164
1165         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1166                               mlx5e_skb_from_cqe_linear,
1167                               mlx5e_skb_from_cqe_nonlinear,
1168                               rq, cqe, wi, cqe_bcnt);
1169         if (!skb) {
1170                 /* probably for XDP */
1171                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1172                         /* do not return page to cache,
1173                          * it will be returned on XDP_TX completion.
1174                          */
1175                         goto wq_cyc_pop;
1176                 }
1177                 goto free_wqe;
1178         }
1179
1180         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1181         napi_gro_receive(rq->cq.napi, skb);
1182
1183 free_wqe:
1184         mlx5e_free_rx_wqe(rq, wi, true);
1185 wq_cyc_pop:
1186         mlx5_wq_cyc_pop(wq);
1187 }
1188
1189 #ifdef CONFIG_MLX5_ESWITCH
1190 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1191 {
1192         struct net_device *netdev = rq->netdev;
1193         struct mlx5e_priv *priv = netdev_priv(netdev);
1194         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1195         struct mlx5_eswitch_rep *rep = rpriv->rep;
1196         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1197         struct mlx5e_wqe_frag_info *wi;
1198         struct sk_buff *skb;
1199         u32 cqe_bcnt;
1200         u16 ci;
1201
1202         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1203         wi       = get_frag(rq, ci);
1204         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1205
1206         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1207                 rq->stats->wqe_err++;
1208                 goto free_wqe;
1209         }
1210
1211         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1212         if (!skb) {
1213                 /* probably for XDP */
1214                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1215                         /* do not return page to cache,
1216                          * it will be returned on XDP_TX completion.
1217                          */
1218                         goto wq_cyc_pop;
1219                 }
1220                 goto free_wqe;
1221         }
1222
1223         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1224
1225         if (rep->vlan && skb_vlan_tag_present(skb))
1226                 skb_vlan_pop(skb);
1227
1228         napi_gro_receive(rq->cq.napi, skb);
1229
1230 free_wqe:
1231         mlx5e_free_rx_wqe(rq, wi, true);
1232 wq_cyc_pop:
1233         mlx5_wq_cyc_pop(wq);
1234 }
1235 #endif
1236
1237 struct sk_buff *
1238 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1239                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1240 {
1241         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1242         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1243         u32 frag_offset    = head_offset + headlen;
1244         u32 byte_cnt       = cqe_bcnt - headlen;
1245         struct mlx5e_dma_info *head_di = di;
1246         struct sk_buff *skb;
1247
1248         skb = napi_alloc_skb(rq->cq.napi,
1249                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1250         if (unlikely(!skb)) {
1251                 rq->stats->buff_alloc_err++;
1252                 return NULL;
1253         }
1254
1255         prefetchw(skb->data);
1256
1257         if (unlikely(frag_offset >= PAGE_SIZE)) {
1258                 di++;
1259                 frag_offset -= PAGE_SIZE;
1260         }
1261
1262         while (byte_cnt) {
1263                 u32 pg_consumed_bytes =
1264                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1265                 unsigned int truesize =
1266                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1267
1268                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1269                                    pg_consumed_bytes, truesize);
1270                 byte_cnt -= pg_consumed_bytes;
1271                 frag_offset = 0;
1272                 di++;
1273         }
1274         /* copy header */
1275         mlx5e_copy_skb_header(rq->pdev, skb, head_di, head_offset, headlen);
1276         /* skb linear part was allocated with headlen and aligned to long */
1277         skb->tail += headlen;
1278         skb->len  += headlen;
1279
1280         return skb;
1281 }
1282
1283 struct sk_buff *
1284 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1285                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1286 {
1287         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1288         u16 rx_headroom = rq->buff.headroom;
1289         u32 cqe_bcnt32 = cqe_bcnt;
1290         struct sk_buff *skb;
1291         void *va, *data;
1292         u32 frag_size;
1293         bool consumed;
1294
1295         /* Check packet size. Note LRO doesn't use linear SKB */
1296         if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1297                 rq->stats->oversize_pkts_sw_drop++;
1298                 return NULL;
1299         }
1300
1301         va             = page_address(di->page) + head_offset;
1302         data           = va + rx_headroom;
1303         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1304
1305         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1306                                       frag_size, DMA_FROM_DEVICE);
1307         prefetchw(va); /* xdp_frame data area */
1308         prefetch(data);
1309
1310         rcu_read_lock();
1311         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32, false);
1312         rcu_read_unlock();
1313         if (consumed) {
1314                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1315                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1316                 return NULL; /* page/packet was consumed by XDP */
1317         }
1318
1319         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1320         if (unlikely(!skb))
1321                 return NULL;
1322
1323         /* queue up for recycling/reuse */
1324         page_ref_inc(di->page);
1325
1326         return skb;
1327 }
1328
1329 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1330 {
1331         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1332         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1333         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1334         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1335         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1336         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1337         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1338         struct mlx5e_rx_wqe_ll *wqe;
1339         struct mlx5_wq_ll *wq;
1340         struct sk_buff *skb;
1341         u16 cqe_bcnt;
1342
1343         wi->consumed_strides += cstrides;
1344
1345         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1346                 trigger_report(rq, cqe);
1347                 rq->stats->wqe_err++;
1348                 goto mpwrq_cqe_out;
1349         }
1350
1351         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1352                 struct mlx5e_rq_stats *stats = rq->stats;
1353
1354                 stats->mpwqe_filler_cqes++;
1355                 stats->mpwqe_filler_strides += cstrides;
1356                 goto mpwrq_cqe_out;
1357         }
1358
1359         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1360
1361         skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1362                               mlx5e_skb_from_cqe_mpwrq_linear,
1363                               mlx5e_skb_from_cqe_mpwrq_nonlinear,
1364                               rq, wi, cqe_bcnt, head_offset, page_idx);
1365         if (!skb)
1366                 goto mpwrq_cqe_out;
1367
1368         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1369         napi_gro_receive(rq->cq.napi, skb);
1370
1371 mpwrq_cqe_out:
1372         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1373                 return;
1374
1375         wq  = &rq->mpwqe.wq;
1376         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1377         mlx5e_free_rx_mpwqe(rq, wi, true);
1378         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1379 }
1380
1381 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1382 {
1383         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1384         struct mlx5_cqwq *cqwq = &cq->wq;
1385         struct mlx5_cqe64 *cqe;
1386         int work_done = 0;
1387
1388         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1389                 return 0;
1390
1391         if (rq->page_pool)
1392                 page_pool_nid_changed(rq->page_pool, numa_mem_id());
1393
1394         if (rq->cqd.left) {
1395                 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget);
1396                 if (rq->cqd.left || work_done >= budget)
1397                         goto out;
1398         }
1399
1400         cqe = mlx5_cqwq_get_cqe(cqwq);
1401         if (!cqe) {
1402                 if (unlikely(work_done))
1403                         goto out;
1404                 return 0;
1405         }
1406
1407         do {
1408                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1409                         work_done +=
1410                                 mlx5e_decompress_cqes_start(rq, cqwq,
1411                                                             budget - work_done);
1412                         continue;
1413                 }
1414
1415                 mlx5_cqwq_pop(cqwq);
1416
1417                 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
1418                                 mlx5e_handle_rx_cqe, rq, cqe);
1419         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
1420
1421 out:
1422         if (rq->xdp_prog)
1423                 mlx5e_xdp_rx_poll_complete(rq);
1424
1425         mlx5_cqwq_update_db_record(cqwq);
1426
1427         /* ensure cq space is freed before enabling more cqes */
1428         wmb();
1429
1430         return work_done;
1431 }
1432
1433 #ifdef CONFIG_MLX5_CORE_IPOIB
1434
1435 #define MLX5_IB_GRH_DGID_OFFSET 24
1436 #define MLX5_GID_SIZE           16
1437
1438 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1439                                          struct mlx5_cqe64 *cqe,
1440                                          u32 cqe_bcnt,
1441                                          struct sk_buff *skb)
1442 {
1443         struct hwtstamp_config *tstamp;
1444         struct mlx5e_rq_stats *stats;
1445         struct net_device *netdev;
1446         struct mlx5e_priv *priv;
1447         char *pseudo_header;
1448         u32 qpn;
1449         u8 *dgid;
1450         u8 g;
1451
1452         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1453         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1454
1455         /* No mapping present, cannot process SKB. This might happen if a child
1456          * interface is going down while having unprocessed CQEs on parent RQ
1457          */
1458         if (unlikely(!netdev)) {
1459                 /* TODO: add drop counters support */
1460                 skb->dev = NULL;
1461                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1462                 return;
1463         }
1464
1465         priv = mlx5i_epriv(netdev);
1466         tstamp = &priv->tstamp;
1467         stats = &priv->channel_stats[rq->ix].rq;
1468
1469         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1470         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1471         if ((!g) || dgid[0] != 0xff)
1472                 skb->pkt_type = PACKET_HOST;
1473         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1474                 skb->pkt_type = PACKET_BROADCAST;
1475         else
1476                 skb->pkt_type = PACKET_MULTICAST;
1477
1478         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1479          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1480          */
1481
1482         skb_pull(skb, MLX5_IB_GRH_BYTES);
1483
1484         skb->protocol = *((__be16 *)(skb->data));
1485
1486         if (netdev->features & NETIF_F_RXCSUM) {
1487                 skb->ip_summed = CHECKSUM_COMPLETE;
1488                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1489                 stats->csum_complete++;
1490         } else {
1491                 skb->ip_summed = CHECKSUM_NONE;
1492                 stats->csum_none++;
1493         }
1494
1495         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1496                 skb_hwtstamps(skb)->hwtstamp =
1497                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1498
1499         skb_record_rx_queue(skb, rq->ix);
1500
1501         if (likely(netdev->features & NETIF_F_RXHASH))
1502                 mlx5e_skb_set_hash(cqe, skb);
1503
1504         /* 20 bytes of ipoib header and 4 for encap existing */
1505         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1506         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1507         skb_reset_mac_header(skb);
1508         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1509
1510         skb->dev = netdev;
1511
1512         stats->packets++;
1513         stats->bytes += cqe_bcnt;
1514 }
1515
1516 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1517 {
1518         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1519         struct mlx5e_wqe_frag_info *wi;
1520         struct sk_buff *skb;
1521         u32 cqe_bcnt;
1522         u16 ci;
1523
1524         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1525         wi       = get_frag(rq, ci);
1526         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1527
1528         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1529                 rq->stats->wqe_err++;
1530                 goto wq_free_wqe;
1531         }
1532
1533         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1534                               mlx5e_skb_from_cqe_linear,
1535                               mlx5e_skb_from_cqe_nonlinear,
1536                               rq, cqe, wi, cqe_bcnt);
1537         if (!skb)
1538                 goto wq_free_wqe;
1539
1540         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1541         if (unlikely(!skb->dev)) {
1542                 dev_kfree_skb_any(skb);
1543                 goto wq_free_wqe;
1544         }
1545         napi_gro_receive(rq->cq.napi, skb);
1546
1547 wq_free_wqe:
1548         mlx5e_free_rx_wqe(rq, wi, true);
1549         mlx5_wq_cyc_pop(wq);
1550 }
1551
1552 #endif /* CONFIG_MLX5_CORE_IPOIB */
1553
1554 #ifdef CONFIG_MLX5_EN_IPSEC
1555
1556 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1557 {
1558         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1559         struct mlx5e_wqe_frag_info *wi;
1560         struct sk_buff *skb;
1561         u32 cqe_bcnt;
1562         u16 ci;
1563
1564         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1565         wi       = get_frag(rq, ci);
1566         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1567
1568         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1569                 rq->stats->wqe_err++;
1570                 goto wq_free_wqe;
1571         }
1572
1573         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1574                               mlx5e_skb_from_cqe_linear,
1575                               mlx5e_skb_from_cqe_nonlinear,
1576                               rq, cqe, wi, cqe_bcnt);
1577         if (unlikely(!skb)) /* a DROP, save the page-reuse checks */
1578                 goto wq_free_wqe;
1579
1580         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1581         if (unlikely(!skb))
1582                 goto wq_free_wqe;
1583
1584         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1585         napi_gro_receive(rq->cq.napi, skb);
1586
1587 wq_free_wqe:
1588         mlx5e_free_rx_wqe(rq, wi, true);
1589         mlx5_wq_cyc_pop(wq);
1590 }
1591
1592 #endif /* CONFIG_MLX5_EN_IPSEC */