2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/prefetch.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/indirect_call_wrapper.h>
38 #include <net/ip6_checksum.h>
39 #include <net/page_pool.h>
40 #include <net/inet_ecn.h>
45 #include "ipoib/ipoib.h"
46 #include "en_accel/ipsec_rxtx.h"
47 #include "en_accel/tls_rxtx.h"
48 #include "lib/clock.h"
50 #include "en/xsk/rx.h"
51 #include "en/health.h"
53 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
55 return config->rx_filter == HWTSTAMP_FILTER_ALL;
58 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq,
61 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
63 memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64));
66 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
70 struct mlx5e_cq_decomp *cqd = &rq->cqd;
71 struct mlx5_cqe64 *title = &cqd->title;
73 mlx5e_read_cqe_slot(wq, cqcc, title);
74 cqd->left = be32_to_cpu(title->byte_cnt);
75 cqd->wqe_counter = be16_to_cpu(title->wqe_counter);
76 rq->stats->cqe_compress_blks++;
79 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq,
80 struct mlx5e_cq_decomp *cqd,
83 mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr);
84 cqd->mini_arr_idx = 0;
87 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n)
90 u8 op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
91 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
92 u32 wq_sz = mlx5_cqwq_get_size(wq);
93 u32 ci_top = min_t(u32, wq_sz, ci + n);
95 for (; ci < ci_top; ci++, n--) {
96 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
101 if (unlikely(ci == wq_sz)) {
103 for (ci = 0; ci < n; ci++) {
104 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
106 cqe->op_own = op_own;
111 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
112 struct mlx5_cqwq *wq,
115 struct mlx5e_cq_decomp *cqd = &rq->cqd;
116 struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx];
117 struct mlx5_cqe64 *title = &cqd->title;
119 title->byte_cnt = mini_cqe->byte_cnt;
120 title->check_sum = mini_cqe->checksum;
121 title->op_own &= 0xf0;
122 title->op_own |= 0x01 & (cqcc >> wq->fbc.log_sz);
123 title->wqe_counter = cpu_to_be16(cqd->wqe_counter);
125 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
126 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title);
129 mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1);
132 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
133 struct mlx5_cqwq *wq,
136 struct mlx5e_cq_decomp *cqd = &rq->cqd;
138 mlx5e_decompress_cqe(rq, wq, cqcc);
139 cqd->title.rss_hash_type = 0;
140 cqd->title.rss_hash_result = 0;
143 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
144 struct mlx5_cqwq *wq,
145 int update_owner_only,
148 struct mlx5e_cq_decomp *cqd = &rq->cqd;
149 u32 cqcc = wq->cc + update_owner_only;
153 cqe_count = min_t(u32, cqd->left, budget_rem);
155 for (i = update_owner_only; i < cqe_count;
156 i++, cqd->mini_arr_idx++, cqcc++) {
157 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
158 mlx5e_read_mini_arr_slot(wq, cqd, cqcc);
160 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc);
161 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
162 mlx5e_handle_rx_cqe, rq, &cqd->title);
164 mlx5e_cqes_update_owner(wq, cqcc - wq->cc);
166 cqd->left -= cqe_count;
167 rq->stats->cqe_compress_pkts += cqe_count;
172 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
173 struct mlx5_cqwq *wq,
176 struct mlx5e_cq_decomp *cqd = &rq->cqd;
179 mlx5e_read_title_slot(rq, wq, cc);
180 mlx5e_read_mini_arr_slot(wq, cqd, cc + 1);
181 mlx5e_decompress_cqe(rq, wq, cc);
182 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
183 mlx5e_handle_rx_cqe, rq, &cqd->title);
186 return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem) - 1;
189 static inline bool mlx5e_page_is_reserved(struct page *page)
191 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
194 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
195 struct mlx5e_dma_info *dma_info)
197 struct mlx5e_page_cache *cache = &rq->page_cache;
198 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
199 struct mlx5e_rq_stats *stats = rq->stats;
201 if (tail_next == cache->head) {
206 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
207 stats->cache_waive++;
211 cache->page_cache[cache->tail] = *dma_info;
212 cache->tail = tail_next;
216 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
217 struct mlx5e_dma_info *dma_info)
219 struct mlx5e_page_cache *cache = &rq->page_cache;
220 struct mlx5e_rq_stats *stats = rq->stats;
222 if (unlikely(cache->head == cache->tail)) {
223 stats->cache_empty++;
227 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
232 *dma_info = cache->page_cache[cache->head];
233 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
234 stats->cache_reuse++;
236 dma_sync_single_for_device(rq->pdev, dma_info->addr,
242 static inline int mlx5e_page_alloc_pool(struct mlx5e_rq *rq,
243 struct mlx5e_dma_info *dma_info)
245 if (mlx5e_rx_cache_get(rq, dma_info))
248 dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
249 if (unlikely(!dma_info->page))
252 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
253 PAGE_SIZE, rq->buff.map_dir);
254 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
255 page_pool_recycle_direct(rq->page_pool, dma_info->page);
256 dma_info->page = NULL;
263 static inline int mlx5e_page_alloc(struct mlx5e_rq *rq,
264 struct mlx5e_dma_info *dma_info)
267 return mlx5e_xsk_page_alloc_umem(rq, dma_info);
269 return mlx5e_page_alloc_pool(rq, dma_info);
272 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
274 dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
277 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
278 struct mlx5e_dma_info *dma_info,
281 if (likely(recycle)) {
282 if (mlx5e_rx_cache_put(rq, dma_info))
285 mlx5e_page_dma_unmap(rq, dma_info);
286 page_pool_recycle_direct(rq->page_pool, dma_info->page);
288 mlx5e_page_dma_unmap(rq, dma_info);
289 page_pool_release_page(rq->page_pool, dma_info->page);
290 put_page(dma_info->page);
294 static inline void mlx5e_page_release(struct mlx5e_rq *rq,
295 struct mlx5e_dma_info *dma_info,
299 /* The `recycle` parameter is ignored, and the page is always
300 * put into the Reuse Ring, because there is no way to return
301 * the page to the userspace when the interface goes down.
303 xsk_buff_free(dma_info->xsk);
305 mlx5e_page_release_dynamic(rq, dma_info, recycle);
308 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
309 struct mlx5e_wqe_frag_info *frag)
314 /* On first frag (offset == 0), replenish page (dma_info actually).
315 * Other frags that point to the same dma_info (with a different
316 * offset) should just use the new one without replenishing again
319 err = mlx5e_page_alloc(rq, frag->di);
324 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
325 struct mlx5e_wqe_frag_info *frag,
328 if (frag->last_in_page)
329 mlx5e_page_release(rq, frag->di, recycle);
332 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
334 return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
337 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
340 struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
344 for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
345 err = mlx5e_get_rx_frag(rq, frag);
349 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
350 frag->offset + rq->buff.headroom);
357 mlx5e_put_rx_frag(rq, --frag, true);
362 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
363 struct mlx5e_wqe_frag_info *wi,
368 for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
369 mlx5e_put_rx_frag(rq, wi, recycle);
372 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
374 struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
376 mlx5e_free_rx_wqe(rq, wi, false);
379 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
381 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
386 int pages_desired = wqe_bulk << rq->wqe.info.log_num_frags;
388 /* Check in advance that we have enough frames, instead of
389 * allocating one-by-one, failing and moving frames to the
392 if (unlikely(!xsk_buff_can_alloc(rq->umem, pages_desired)))
396 for (i = 0; i < wqe_bulk; i++) {
397 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
399 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
408 mlx5e_dealloc_rx_wqe(rq, ix + i);
414 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
415 struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
416 unsigned int truesize)
418 dma_sync_single_for_cpu(rq->pdev,
419 di->addr + frag_offset,
420 len, DMA_FROM_DEVICE);
421 page_ref_inc(di->page);
422 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
423 di->page, frag_offset, len, truesize);
427 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
428 struct mlx5e_dma_info *dma_info,
429 int offset_from, u32 headlen)
431 const void *from = page_address(dma_info->page) + offset_from;
432 /* Aligning len to sizeof(long) optimizes memcpy performance */
433 unsigned int len = ALIGN(headlen, sizeof(long));
435 dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
437 skb_copy_to_linear_data(skb, from, len);
441 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
444 struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
447 /* A common case for AF_XDP. */
448 if (bitmap_full(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE))
451 no_xdp_xmit = bitmap_empty(wi->xdp_xmit_bitmap,
452 MLX5_MPWRQ_PAGES_PER_WQE);
454 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
455 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
456 mlx5e_page_release(rq, &dma_info[i], recycle);
459 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n)
461 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
464 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head);
466 mlx5_wq_ll_push(wq, next_wqe_index);
469 /* ensure wqes are visible to device before updating doorbell record */
472 mlx5_wq_ll_update_db_record(wq);
475 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
477 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
478 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
479 struct mlx5e_icosq *sq = &rq->channel->icosq;
480 struct mlx5_wq_cyc *wq = &sq->wq;
481 struct mlx5e_umr_wqe *umr_wqe;
482 u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
487 /* Check in advance that we have enough frames, instead of allocating
488 * one-by-one, failing and moving frames to the Reuse Ring.
491 unlikely(!xsk_buff_can_alloc(rq->umem, MLX5_MPWRQ_PAGES_PER_WQE))) {
496 pi = mlx5e_icosq_get_next_pi(sq, MLX5E_UMR_WQEBBS);
497 umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
498 memcpy(umr_wqe, &rq->mpwqe.umr_wqe, offsetof(struct mlx5e_umr_wqe, inline_mtts));
500 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
501 err = mlx5e_page_alloc(rq, dma_info);
504 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
507 bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
508 wi->consumed_strides = 0;
510 umr_wqe->ctrl.opmod_idx_opcode =
511 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
513 umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
515 sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) {
516 .wqe_type = MLX5E_ICOSQ_WQE_UMR_RX,
517 .num_wqebbs = MLX5E_UMR_WQEBBS,
521 sq->pc += MLX5E_UMR_WQEBBS;
523 sq->doorbell_cseg = &umr_wqe->ctrl;
530 mlx5e_page_release(rq, dma_info, true);
534 rq->stats->buff_alloc_err++;
539 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
541 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
542 /* Don't recycle, this function is called on rq/netdev close */
543 mlx5e_free_rx_mpwqe(rq, wi, false);
546 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
548 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
552 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
555 wqe_bulk = rq->wqe.info.wqe_bulk;
557 if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
561 u16 head = mlx5_wq_cyc_get_head(wq);
563 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
565 rq->stats->buff_alloc_err++;
569 mlx5_wq_cyc_push_n(wq, wqe_bulk);
570 } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
572 /* ensure wqes are visible to device before updating doorbell record */
575 mlx5_wq_cyc_update_db_record(wq);
580 int mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
582 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
583 struct mlx5_cqe64 *cqe;
587 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
590 cqe = mlx5_cqwq_get_cqe(&cq->wq);
594 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
595 * otherwise a cq overrun may occur
604 mlx5_cqwq_pop(&cq->wq);
606 wqe_counter = be16_to_cpu(cqe->wqe_counter);
609 struct mlx5e_icosq_wqe_info *wi;
612 last_wqe = (sqcc == wqe_counter);
614 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
615 wi = &sq->db.wqe_info[ci];
616 sqcc += wi->num_wqebbs;
618 if (last_wqe && unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
619 netdev_WARN_ONCE(cq->channel->netdev,
620 "Bad OP in ICOSQ CQE: 0x%x\n",
621 get_cqe_opcode(cqe));
622 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
623 (struct mlx5_err_cqe *)cqe);
624 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state))
625 queue_work(cq->channel->priv->wq, &sq->recover_work);
629 switch (wi->wqe_type) {
630 case MLX5E_ICOSQ_WQE_UMR_RX:
631 wi->umr.rq->mpwqe.umr_completed++;
633 case MLX5E_ICOSQ_WQE_NOP:
636 netdev_WARN_ONCE(cq->channel->netdev,
637 "Bad WQE type in ICOSQ WQE info: 0x%x\n",
641 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
645 mlx5_cqwq_update_db_record(&cq->wq);
650 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
652 struct mlx5e_icosq *sq = &rq->channel->icosq;
653 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
654 u8 umr_completed = rq->mpwqe.umr_completed;
659 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
663 mlx5e_post_rx_mpwqe(rq, umr_completed);
664 rq->mpwqe.umr_in_progress -= umr_completed;
665 rq->mpwqe.umr_completed = 0;
668 missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress;
670 if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk))
671 rq->stats->congst_umr++;
673 #define UMR_WQE_BULK (2)
674 if (likely(missing < UMR_WQE_BULK))
677 head = rq->mpwqe.actual_wq_head;
680 alloc_err = mlx5e_alloc_rx_mpwqe(rq, head);
682 if (unlikely(alloc_err))
684 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
687 rq->mpwqe.umr_last_bulk = missing - i;
688 if (sq->doorbell_cseg) {
689 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg);
690 sq->doorbell_cseg = NULL;
693 rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk;
694 rq->mpwqe.actual_wq_head = head;
696 /* If XSK Fill Ring doesn't have enough frames, report the error, so
697 * that one of the actions can be performed:
698 * 1. If need_wakeup is used, signal that the application has to kick
699 * the driver when it refills the Fill Ring.
700 * 2. Otherwise, busy poll by rescheduling the NAPI poll.
702 if (unlikely(alloc_err == -ENOMEM && rq->umem))
708 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
710 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
711 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
712 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
715 tcp->psh = get_cqe_lro_tcppsh(cqe);
719 tcp->ack_seq = cqe->lro_ack_seq_num;
720 tcp->window = cqe->lro_tcp_win;
724 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
727 struct ethhdr *eth = (struct ethhdr *)(skb->data);
729 int network_depth = 0;
735 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
737 tot_len = cqe_bcnt - network_depth;
738 ip_p = skb->data + network_depth;
740 if (proto == htons(ETH_P_IP)) {
741 struct iphdr *ipv4 = ip_p;
743 tcp = ip_p + sizeof(struct iphdr);
744 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
746 ipv4->ttl = cqe->lro_min_ttl;
747 ipv4->tot_len = cpu_to_be16(tot_len);
749 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
752 mlx5e_lro_update_tcp_hdr(cqe, tcp);
753 check = csum_partial(tcp, tcp->doff * 4,
754 csum_unfold((__force __sum16)cqe->check_sum));
755 /* Almost done, don't forget the pseudo header */
756 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
757 tot_len - sizeof(struct iphdr),
760 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
761 struct ipv6hdr *ipv6 = ip_p;
763 tcp = ip_p + sizeof(struct ipv6hdr);
764 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
766 ipv6->hop_limit = cqe->lro_min_ttl;
767 ipv6->payload_len = cpu_to_be16(payload_len);
769 mlx5e_lro_update_tcp_hdr(cqe, tcp);
770 check = csum_partial(tcp, tcp->doff * 4,
771 csum_unfold((__force __sum16)cqe->check_sum));
772 /* Almost done, don't forget the pseudo header */
773 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
778 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
781 u8 cht = cqe->rss_hash_type;
782 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
783 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
785 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
788 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
791 *proto = ((struct ethhdr *)skb->data)->h_proto;
792 *proto = __vlan_get_protocol(skb, *proto, network_depth);
794 if (*proto == htons(ETH_P_IP))
795 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr));
797 if (*proto == htons(ETH_P_IPV6))
798 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr));
803 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
805 int network_depth = 0;
810 if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
813 ip = skb->data + network_depth;
814 rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
815 IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
817 rq->stats->ecn_mark += !!rc;
820 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
822 void *ip_p = skb->data + network_depth;
824 return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
825 ((struct ipv6hdr *)ip_p)->nexthdr;
828 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
830 #define MAX_PADDING 8
833 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len,
834 struct mlx5e_rq_stats *stats)
836 stats->csum_complete_tail_slow++;
837 skb->csum = csum_block_add(skb->csum,
838 skb_checksum(skb, offset, len, 0),
843 tail_padding_csum(struct sk_buff *skb, int offset,
844 struct mlx5e_rq_stats *stats)
846 u8 tail_padding[MAX_PADDING];
847 int len = skb->len - offset;
850 if (unlikely(len > MAX_PADDING)) {
851 tail_padding_csum_slow(skb, offset, len, stats);
855 tail = skb_header_pointer(skb, offset, len, tail_padding);
856 if (unlikely(!tail)) {
857 tail_padding_csum_slow(skb, offset, len, stats);
861 stats->csum_complete_tail++;
862 skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset);
866 mlx5e_skb_csum_fixup(struct sk_buff *skb, int network_depth, __be16 proto,
867 struct mlx5e_rq_stats *stats)
873 /* Fixup vlan headers, if any */
874 if (network_depth > ETH_HLEN)
875 /* CQE csum is calculated from the IP header and does
876 * not cover VLAN headers (if present). This will add
877 * the checksum manually.
879 skb->csum = csum_partial(skb->data + ETH_HLEN,
880 network_depth - ETH_HLEN,
883 /* Fixup tail padding, if any */
885 case htons(ETH_P_IP):
886 ip4 = (struct iphdr *)(skb->data + network_depth);
887 pkt_len = network_depth + ntohs(ip4->tot_len);
889 case htons(ETH_P_IPV6):
890 ip6 = (struct ipv6hdr *)(skb->data + network_depth);
891 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len);
897 if (likely(pkt_len >= skb->len))
900 tail_padding_csum(skb, pkt_len, stats);
903 static inline void mlx5e_handle_csum(struct net_device *netdev,
904 struct mlx5_cqe64 *cqe,
909 struct mlx5e_rq_stats *stats = rq->stats;
910 int network_depth = 0;
913 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
917 skb->ip_summed = CHECKSUM_UNNECESSARY;
918 stats->csum_unnecessary++;
922 /* True when explicitly set via priv flag, or XDP prog is loaded */
923 if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
924 goto csum_unnecessary;
926 /* CQE csum doesn't cover padding octets in short ethernet
927 * frames. And the pad field is appended prior to calculating
928 * and appending the FCS field.
930 * Detecting these padded frames requires to verify and parse
931 * IP headers, so we simply force all those small frames to be
932 * CHECKSUM_UNNECESSARY even if they are not padded.
934 if (short_frame(skb->len))
935 goto csum_unnecessary;
937 if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
938 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP))
939 goto csum_unnecessary;
941 stats->csum_complete++;
942 skb->ip_summed = CHECKSUM_COMPLETE;
943 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
945 if (test_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state))
946 return; /* CQE csum covers all received bytes */
948 /* csum might need some fixups ...*/
949 mlx5e_skb_csum_fixup(skb, network_depth, proto, stats);
954 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
955 (cqe->hds_ip_ext & CQE_L4_OK))) {
956 skb->ip_summed = CHECKSUM_UNNECESSARY;
957 if (cqe_is_tunneled(cqe)) {
959 skb->encapsulation = 1;
960 stats->csum_unnecessary_inner++;
963 stats->csum_unnecessary++;
967 skb->ip_summed = CHECKSUM_NONE;
971 #define MLX5E_CE_BIT_MASK 0x80
973 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
978 u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
979 struct mlx5e_rq_stats *stats = rq->stats;
980 struct net_device *netdev = rq->netdev;
982 skb->mac_len = ETH_HLEN;
984 #ifdef CONFIG_MLX5_EN_TLS
985 mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
988 if (lro_num_seg > 1) {
989 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
990 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
991 /* Subtract one since we already counted this as one
992 * "regular" packet in mlx5e_complete_rx_cqe()
994 stats->packets += lro_num_seg - 1;
995 stats->lro_packets++;
996 stats->lro_bytes += cqe_bcnt;
999 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
1000 skb_hwtstamps(skb)->hwtstamp =
1001 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1003 skb_record_rx_queue(skb, rq->ix);
1005 if (likely(netdev->features & NETIF_F_RXHASH))
1006 mlx5e_skb_set_hash(cqe, skb);
1008 if (cqe_has_vlan(cqe)) {
1009 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1010 be16_to_cpu(cqe->vlan_info));
1011 stats->removed_vlan_packets++;
1014 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
1016 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
1017 /* checking CE bit in cqe - MSB in ml_path field */
1018 if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
1019 mlx5e_enable_ecn(rq, skb);
1021 skb->protocol = eth_type_trans(skb, netdev);
1024 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
1025 struct mlx5_cqe64 *cqe,
1027 struct sk_buff *skb)
1029 struct mlx5e_rq_stats *stats = rq->stats;
1032 stats->bytes += cqe_bcnt;
1033 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
1037 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
1038 u32 frag_size, u16 headroom,
1041 struct sk_buff *skb = build_skb(va, frag_size);
1043 if (unlikely(!skb)) {
1044 rq->stats->buff_alloc_err++;
1048 skb_reserve(skb, headroom);
1049 skb_put(skb, cqe_bcnt);
1054 static void mlx5e_fill_xdp_buff(struct mlx5e_rq *rq, void *va, u16 headroom,
1055 u32 len, struct xdp_buff *xdp)
1057 xdp->data_hard_start = va;
1058 xdp_set_data_meta_invalid(xdp);
1059 xdp->data = va + headroom;
1060 xdp->data_end = xdp->data + len;
1061 xdp->rxq = &rq->xdp_rxq;
1062 xdp->frame_sz = rq->buff.frame0_sz;
1066 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1067 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1069 struct mlx5e_dma_info *di = wi->di;
1070 u16 rx_headroom = rq->buff.headroom;
1071 struct xdp_buff xdp;
1072 struct sk_buff *skb;
1077 va = page_address(di->page) + wi->offset;
1078 data = va + rx_headroom;
1079 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1081 dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1082 frag_size, DMA_FROM_DEVICE);
1083 prefetchw(va); /* xdp_frame data area */
1087 mlx5e_fill_xdp_buff(rq, va, rx_headroom, cqe_bcnt, &xdp);
1088 consumed = mlx5e_xdp_handle(rq, di, &cqe_bcnt, &xdp);
1091 return NULL; /* page/packet was consumed by XDP */
1093 rx_headroom = xdp.data - xdp.data_hard_start;
1094 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1095 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1099 /* queue up for recycling/reuse */
1100 page_ref_inc(di->page);
1106 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1107 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1109 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1110 struct mlx5e_wqe_frag_info *head_wi = wi;
1111 u16 headlen = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1112 u16 frag_headlen = headlen;
1113 u16 byte_cnt = cqe_bcnt - headlen;
1114 struct sk_buff *skb;
1116 /* XDP is not supported in this configuration, as incoming packets
1117 * might spread among multiple pages.
1119 skb = napi_alloc_skb(rq->cq.napi,
1120 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1121 if (unlikely(!skb)) {
1122 rq->stats->buff_alloc_err++;
1126 prefetchw(skb->data);
1129 u16 frag_consumed_bytes =
1130 min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1132 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1133 frag_consumed_bytes, frag_info->frag_stride);
1134 byte_cnt -= frag_consumed_bytes;
1141 mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset, headlen);
1142 /* skb linear part was allocated with headlen and aligned to long */
1143 skb->tail += headlen;
1144 skb->len += headlen;
1149 static void trigger_report(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1151 struct mlx5_err_cqe *err_cqe = (struct mlx5_err_cqe *)cqe;
1153 if (cqe_syndrome_needs_recover(err_cqe->syndrome) &&
1154 !test_and_set_bit(MLX5E_RQ_STATE_RECOVERING, &rq->state))
1155 queue_work(rq->channel->priv->wq, &rq->recover_work);
1158 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1160 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1161 struct mlx5e_wqe_frag_info *wi;
1162 struct sk_buff *skb;
1166 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1167 wi = get_frag(rq, ci);
1168 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1170 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1171 trigger_report(rq, cqe);
1172 rq->stats->wqe_err++;
1176 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1177 mlx5e_skb_from_cqe_linear,
1178 mlx5e_skb_from_cqe_nonlinear,
1179 rq, cqe, wi, cqe_bcnt);
1181 /* probably for XDP */
1182 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1183 /* do not return page to cache,
1184 * it will be returned on XDP_TX completion.
1191 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1192 napi_gro_receive(rq->cq.napi, skb);
1195 mlx5e_free_rx_wqe(rq, wi, true);
1197 mlx5_wq_cyc_pop(wq);
1200 #ifdef CONFIG_MLX5_ESWITCH
1201 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1203 struct net_device *netdev = rq->netdev;
1204 struct mlx5e_priv *priv = netdev_priv(netdev);
1205 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1206 struct mlx5_eswitch_rep *rep = rpriv->rep;
1207 struct mlx5e_tc_update_priv tc_priv = {};
1208 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1209 struct mlx5e_wqe_frag_info *wi;
1210 struct sk_buff *skb;
1214 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1215 wi = get_frag(rq, ci);
1216 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1218 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1219 rq->stats->wqe_err++;
1223 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1225 /* probably for XDP */
1226 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1227 /* do not return page to cache,
1228 * it will be returned on XDP_TX completion.
1235 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1237 if (rep->vlan && skb_vlan_tag_present(skb))
1240 if (!mlx5e_tc_rep_update_skb(cqe, skb, &tc_priv))
1243 napi_gro_receive(rq->cq.napi, skb);
1245 mlx5_tc_rep_post_napi_receive(&tc_priv);
1248 mlx5e_free_rx_wqe(rq, wi, true);
1250 mlx5_wq_cyc_pop(wq);
1253 void mlx5e_handle_rx_cqe_mpwrq_rep(struct mlx5e_rq *rq,
1254 struct mlx5_cqe64 *cqe)
1256 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
1257 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
1258 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1259 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
1260 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz;
1261 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
1262 u32 page_idx = wqe_offset >> PAGE_SHIFT;
1263 struct mlx5e_tc_update_priv tc_priv = {};
1264 struct mlx5e_rx_wqe_ll *wqe;
1265 struct mlx5_wq_ll *wq;
1266 struct sk_buff *skb;
1269 wi->consumed_strides += cstrides;
1271 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1272 trigger_report(rq, cqe);
1273 rq->stats->wqe_err++;
1277 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1278 struct mlx5e_rq_stats *stats = rq->stats;
1280 stats->mpwqe_filler_cqes++;
1281 stats->mpwqe_filler_strides += cstrides;
1285 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1287 skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1288 mlx5e_skb_from_cqe_mpwrq_linear,
1289 mlx5e_skb_from_cqe_mpwrq_nonlinear,
1290 rq, wi, cqe_bcnt, head_offset, page_idx);
1294 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1296 if (!mlx5e_tc_rep_update_skb(cqe, skb, &tc_priv))
1299 napi_gro_receive(rq->cq.napi, skb);
1301 mlx5_tc_rep_post_napi_receive(&tc_priv);
1304 if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1308 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1309 mlx5e_free_rx_mpwqe(rq, wi, true);
1310 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1315 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1316 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1318 u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1319 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1320 u32 frag_offset = head_offset + headlen;
1321 u32 byte_cnt = cqe_bcnt - headlen;
1322 struct mlx5e_dma_info *head_di = di;
1323 struct sk_buff *skb;
1325 skb = napi_alloc_skb(rq->cq.napi,
1326 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1327 if (unlikely(!skb)) {
1328 rq->stats->buff_alloc_err++;
1332 prefetchw(skb->data);
1334 if (unlikely(frag_offset >= PAGE_SIZE)) {
1336 frag_offset -= PAGE_SIZE;
1340 u32 pg_consumed_bytes =
1341 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1342 unsigned int truesize =
1343 ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1345 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1346 pg_consumed_bytes, truesize);
1347 byte_cnt -= pg_consumed_bytes;
1352 mlx5e_copy_skb_header(rq->pdev, skb, head_di, head_offset, headlen);
1353 /* skb linear part was allocated with headlen and aligned to long */
1354 skb->tail += headlen;
1355 skb->len += headlen;
1361 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1362 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1364 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1365 u16 rx_headroom = rq->buff.headroom;
1366 u32 cqe_bcnt32 = cqe_bcnt;
1367 struct xdp_buff xdp;
1368 struct sk_buff *skb;
1373 /* Check packet size. Note LRO doesn't use linear SKB */
1374 if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1375 rq->stats->oversize_pkts_sw_drop++;
1379 va = page_address(di->page) + head_offset;
1380 data = va + rx_headroom;
1381 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1383 dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1384 frag_size, DMA_FROM_DEVICE);
1385 prefetchw(va); /* xdp_frame data area */
1389 mlx5e_fill_xdp_buff(rq, va, rx_headroom, cqe_bcnt32, &xdp);
1390 consumed = mlx5e_xdp_handle(rq, di, &cqe_bcnt32, &xdp);
1393 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1394 __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1395 return NULL; /* page/packet was consumed by XDP */
1398 rx_headroom = xdp.data - xdp.data_hard_start;
1399 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1400 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1404 /* queue up for recycling/reuse */
1405 page_ref_inc(di->page);
1410 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1412 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
1413 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
1414 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1415 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
1416 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz;
1417 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
1418 u32 page_idx = wqe_offset >> PAGE_SHIFT;
1419 struct mlx5e_rx_wqe_ll *wqe;
1420 struct mlx5_wq_ll *wq;
1421 struct sk_buff *skb;
1424 wi->consumed_strides += cstrides;
1426 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1427 trigger_report(rq, cqe);
1428 rq->stats->wqe_err++;
1432 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1433 struct mlx5e_rq_stats *stats = rq->stats;
1435 stats->mpwqe_filler_cqes++;
1436 stats->mpwqe_filler_strides += cstrides;
1440 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1442 skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1443 mlx5e_skb_from_cqe_mpwrq_linear,
1444 mlx5e_skb_from_cqe_mpwrq_nonlinear,
1445 rq, wi, cqe_bcnt, head_offset, page_idx);
1449 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1450 napi_gro_receive(rq->cq.napi, skb);
1453 if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1457 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1458 mlx5e_free_rx_mpwqe(rq, wi, true);
1459 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1462 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1464 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1465 struct mlx5_cqwq *cqwq = &cq->wq;
1466 struct mlx5_cqe64 *cqe;
1469 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1473 page_pool_nid_changed(rq->page_pool, numa_mem_id());
1476 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget);
1477 if (rq->cqd.left || work_done >= budget)
1481 cqe = mlx5_cqwq_get_cqe(cqwq);
1483 if (unlikely(work_done))
1489 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1491 mlx5e_decompress_cqes_start(rq, cqwq,
1492 budget - work_done);
1496 mlx5_cqwq_pop(cqwq);
1498 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
1499 mlx5e_handle_rx_cqe, rq, cqe);
1500 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
1504 mlx5e_xdp_rx_poll_complete(rq);
1506 mlx5_cqwq_update_db_record(cqwq);
1508 /* ensure cq space is freed before enabling more cqes */
1514 #ifdef CONFIG_MLX5_CORE_IPOIB
1516 #define MLX5_IB_GRH_DGID_OFFSET 24
1517 #define MLX5_GID_SIZE 16
1519 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1520 struct mlx5_cqe64 *cqe,
1522 struct sk_buff *skb)
1524 struct hwtstamp_config *tstamp;
1525 struct mlx5e_rq_stats *stats;
1526 struct net_device *netdev;
1527 struct mlx5e_priv *priv;
1528 char *pseudo_header;
1533 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1534 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1536 /* No mapping present, cannot process SKB. This might happen if a child
1537 * interface is going down while having unprocessed CQEs on parent RQ
1539 if (unlikely(!netdev)) {
1540 /* TODO: add drop counters support */
1542 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1546 priv = mlx5i_epriv(netdev);
1547 tstamp = &priv->tstamp;
1548 stats = &priv->channel_stats[rq->ix].rq;
1550 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1551 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1552 if ((!g) || dgid[0] != 0xff)
1553 skb->pkt_type = PACKET_HOST;
1554 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1555 skb->pkt_type = PACKET_BROADCAST;
1557 skb->pkt_type = PACKET_MULTICAST;
1559 /* TODO: IB/ipoib: Allow mcast packets from other VFs
1560 * 68996a6e760e5c74654723eeb57bf65628ae87f4
1563 skb_pull(skb, MLX5_IB_GRH_BYTES);
1565 skb->protocol = *((__be16 *)(skb->data));
1567 if (netdev->features & NETIF_F_RXCSUM) {
1568 skb->ip_summed = CHECKSUM_COMPLETE;
1569 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1570 stats->csum_complete++;
1572 skb->ip_summed = CHECKSUM_NONE;
1576 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1577 skb_hwtstamps(skb)->hwtstamp =
1578 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1580 skb_record_rx_queue(skb, rq->ix);
1582 if (likely(netdev->features & NETIF_F_RXHASH))
1583 mlx5e_skb_set_hash(cqe, skb);
1585 /* 20 bytes of ipoib header and 4 for encap existing */
1586 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1587 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1588 skb_reset_mac_header(skb);
1589 skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1594 stats->bytes += cqe_bcnt;
1597 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1599 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1600 struct mlx5e_wqe_frag_info *wi;
1601 struct sk_buff *skb;
1605 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1606 wi = get_frag(rq, ci);
1607 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1609 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1610 rq->stats->wqe_err++;
1614 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1615 mlx5e_skb_from_cqe_linear,
1616 mlx5e_skb_from_cqe_nonlinear,
1617 rq, cqe, wi, cqe_bcnt);
1621 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1622 if (unlikely(!skb->dev)) {
1623 dev_kfree_skb_any(skb);
1626 napi_gro_receive(rq->cq.napi, skb);
1629 mlx5e_free_rx_wqe(rq, wi, true);
1630 mlx5_wq_cyc_pop(wq);
1633 #endif /* CONFIG_MLX5_CORE_IPOIB */
1635 #ifdef CONFIG_MLX5_EN_IPSEC
1637 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1639 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1640 struct mlx5e_wqe_frag_info *wi;
1641 struct sk_buff *skb;
1645 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1646 wi = get_frag(rq, ci);
1647 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1649 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1650 rq->stats->wqe_err++;
1654 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1655 mlx5e_skb_from_cqe_linear,
1656 mlx5e_skb_from_cqe_nonlinear,
1657 rq, cqe, wi, cqe_bcnt);
1658 if (unlikely(!skb)) /* a DROP, save the page-reuse checks */
1661 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1665 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1666 napi_gro_receive(rq->cq.napi, skb);
1669 mlx5e_free_rx_wqe(rq, wi, true);
1670 mlx5_wq_cyc_pop(wq);
1673 #endif /* CONFIG_MLX5_EN_IPSEC */